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Differential D156591

[tests] precommit tests for D154953
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Authored by Allen on Jul 29 2023, 2:01 AM.

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goldstein.w.n
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rG44d14a13a95f: [tests] precommit tests for D154953

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Allen created this revision.Jul 29 2023, 2:01 AM
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Allen mentioned this in D154953: [InstSimplify] Remove the remainder loop if we know the mask is always true.Jul 29 2023, 2:03 AM
Allen added a child revision: D154953: [InstSimplify] Remove the remainder loop if we know the mask is always true.
Harbormaster completed remote builds in B248978: Diff 545347.Jul 29 2023, 2:39 AM
Allen updated this revision to Diff 545902.Jul 31 2023, 7:43 PM

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This revision was not accepted when it landed; it landed in state Needs Review.Jul 31 2023, 8:23 PM
This revision was landed with ongoing or failed builds.
Closed by commit rG44d14a13a95f: [tests] precommit tests for D154953 (authored by Allen). · Explain Why
This revision was automatically updated to reflect the committed changes.
Allen added a commit: rG44d14a13a95f: [tests] precommit tests for D154953.
Harbormaster completed remote builds in B249381: Diff 545902.Jul 31 2023, 8:24 PM

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
62 lines
22 lines

Diff 545907

llvm/test/Transforms/InstCombine/and-add-shl.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
declare void @llvm.assume(i1)
declare i8 @llvm.ctpop.i8(i8)
; https://alive2.llvm.org/ce/z/LV_8xy
define i8 @and_add_shl(i8 %x) {
; CHECK-LABEL: define i8 @and_add_shl
; CHECK-SAME: (i8 [[X:%.*]]) {
; CHECK-NEXT: [[OP1_P2:%.*]] = icmp ult i8 [[X]], 6
; CHECK-NEXT: call void @llvm.assume(i1 [[OP1_P2]])
; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i8 -1, [[X]]
; CHECK-NEXT: [[SUB:%.*]] = and i8 [[NOTMASK]], 32
; CHECK-NEXT: [[R:%.*]] = xor i8 [[SUB]], 32
; CHECK-NEXT: ret i8 [[R]]
;
%op1_p2 = icmp ule i8 %x, 5
call void @llvm.assume(i1 %op1_p2)
%shift = shl i8 1, %x
%sub = add i8 %shift, -1
%r = and i8 %sub, 32
ret i8 %r
}
; https://alive2.llvm.org/ce/z/YNYYdV
define i8 @and_not_shl(i8 %x) {
; CHECK-LABEL: define i8 @and_not_shl
; CHECK-SAME: (i8 [[X:%.*]]) {
; CHECK-NEXT: [[OP1_P2:%.*]] = icmp ult i8 [[X]], 6
; CHECK-NEXT: call void @llvm.assume(i1 [[OP1_P2]])
; CHECK-NEXT: [[SHIFT:%.*]] = shl i8 -1, [[X]]
; CHECK-NEXT: [[NOT:%.*]] = and i8 [[SHIFT]], 32
; CHECK-NEXT: [[R:%.*]] = xor i8 [[NOT]], 32
; CHECK-NEXT: ret i8 [[R]]
;
%op1_p2 = icmp ule i8 %x, 5
call void @llvm.assume(i1 %op1_p2)
%shift = shl i8 -1, %x
%not = xor i8 %shift, -1
%r = and i8 %not, 32
ret i8 %r
}
; Negative test: https://alive2.llvm.org/ce/z/uWzb4t
define i8 @and_add_shl_overlap(i8 %x) {
; CHECK-LABEL: define i8 @and_add_shl_overlap
; CHECK-SAME: (i8 [[X:%.*]]) {
; CHECK-NEXT: [[OP1_P2:%.*]] = icmp ult i8 [[X]], 7
; CHECK-NEXT: call void @llvm.assume(i1 [[OP1_P2]])
; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i8 -1, [[X]]
; CHECK-NEXT: [[SUB:%.*]] = and i8 [[NOTMASK]], 32
; CHECK-NEXT: [[R:%.*]] = xor i8 [[SUB]], 32
; CHECK-NEXT: ret i8 [[R]]
;
%op1_p2 = icmp ule i8 %x, 6
call void @llvm.assume(i1 %op1_p2)
%shift = shl i8 1, %x
%sub = add i8 %shift, -1
%r = and i8 %sub, 32
ret i8 %r
}

llvm/test/Transforms/InstCombine/rem-mul-shl.ll

Show First 20 Lines • Show All 852 Lines • ▼ Show 20 Lines;
%shift = shl nuw nsw i64 %vscale, 2 %shift = shl nuw nsw i64 %vscale, 2
%rem = urem i64 1024, %shift %rem = urem i64 1024, %shift
ret i64 %rem ret i64 %rem
} }
define i64 @urem_vscale_range() vscale_range(1,16) { define i64 @urem_vscale_range() vscale_range(1,16) {
; CHECK-LABEL: @urem_vscale_range( ; CHECK-LABEL: @urem_vscale_range(
; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 2 ; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 6
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[SHIFT]], 2047 ; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[SHIFT]], 2047
; CHECK-NEXT: [[REM:%.*]] = and i64 [[TMP1]], 1024 ; CHECK-NEXT: [[REM:%.*]] = and i64 [[TMP1]], 1024
; CHECK-NEXT: ret i64 [[REM]] ; CHECK-NEXT: ret i64 [[REM]]
; ;
%vscale = call i64 @llvm.vscale.i64() %vscale = call i64 @llvm.vscale.i64()
%shift = shl nuw nsw i64 %vscale, 2 %shift = shl nuw nsw i64 %vscale, 6
%rem = urem i64 1024, %shift %rem = urem i64 1024, %shift
ret i64 %rem ret i64 %rem
} }
define i64 @urem_shl_vscale_out_of_range() vscale_range(1,16) { define i64 @urem_shl_vscale_out_of_range() vscale_range(1,16) {
; CHECK-LABEL: @urem_shl_vscale_out_of_range( ; CHECK-LABEL: @urem_shl_vscale_out_of_range(
; CHECK-NEXT: ret i64 1024 ; CHECK-NEXT: ret i64 1024
; ;
%vscale = call i64 @llvm.vscale.i64() %vscale = call i64 @llvm.vscale.i64()
%shift = shl nuw nsw i64 %vscale, 20 %shift = shl nuw nsw i64 %vscale, 11
%rem = urem i64 1024, %shift %rem = urem i64 1024, %shift
ret i64 %rem ret i64 %rem
} }
; Negative test: The min value 1 << 10 is overlap to 1024
define i64 @urem_shl_vscale_overlap() vscale_range(1,16) {
; CHECK-LABEL: @urem_shl_vscale_overlap(
; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 10
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[SHIFT]], 2047
; CHECK-NEXT: [[REM:%.*]] = and i64 [[TMP1]], 1024
; CHECK-NEXT: ret i64 [[REM]]
;
%vscale = call i64 @llvm.vscale.i64()
%shift = shl nuw nsw i64 %vscale, 10
%rem = urem i64 1024, %shift
ret i64 %rem
}