This is an archive of the discontinued LLVM Phabricator instance.

[WebAssembly] Fix incorrect assertion in SIMD reduction codegen
ClosedPublic

Authored by tlively on Jun 29 2023, 11:09 AM.

Details

Summary

The codegen routine introduced in 18077e9fd688 did not account for vectors with
more than 16 lanes. Remove the incorrect assertion and bail out of the
optimization when encountering this case. Add test cases that previously
triggered the assertion. Unfortunately, these test cases now have terrible
codegen, but that is at least better than crashing.

Fixes #63500.

Diff Detail

Event Timeline

tlively created this revision.Jun 29 2023, 11:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 29 2023, 11:09 AM
Herald added subscribers: pmatos, asb, wingo and 4 others. · View Herald Transcript
tlively requested review of this revision.Jun 29 2023, 11:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 29 2023, 11:09 AM
aheejin accepted this revision.Jun 29 2023, 2:26 PM

Wow the codegen is indeed impressive... 😂

This revision is now accepted and ready to land.Jun 29 2023, 2:26 PM
This revision was landed with ongoing or failed builds.Jun 30 2023, 11:30 AM
This revision was automatically updated to reflect the committed changes.