[WIP] DAG: Implement computeKnownBits for GlobalAddress

[arsenm]

Summary

Use !absolute_symbol and alignment.

Currently requires many test updates. Many targets need to be updated
to use isBaseWithConstantOffset to undo everyone's favorite add->or
combine.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

unsigned MemBits =
         cast<AtomicSDNode>(Op)->getMemoryVT().getScalarSizeInBits();
     // If we are looking at the loaded value.
     if (Op.getResNo() == 0) {
       if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND)
         Known.Zero.setBitsFrom(MemBits);
     }
     break;
   }
+  case ISD::GlobalAddress:
+  case ISD::TargetGlobalAddress: {
+    const auto *GlobalNode = cast<GlobalAddressSDNode>(Op);
+    if (std::optional<ConstantRange> CR = GlobalNode->getGlobal()->getAbsoluteSymbolRange())
+      Known = CR->toKnownBits();
+
+    if (const auto *GO = dyn_cast<GlobalObject>(GlobalNode->getGlobal()))
+      Known.Zero.setLowBits(Log2(GO->getAlign().valueOrOne()));
+    break;
+  }
   case ISD::FrameIndex:
   case ISD::TargetFrameIndex:
     TLI->computeKnownBitsForFrameIndex(cast<FrameIndexSDNode>(Op)->getIndex(),
                                        Known, getMachineFunction());
     break;
 
   default:
     if (Opcode < ISD::BUILTIN_OP_END)

llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll

 ; RUN: llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=bonaire -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=gfx900 -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
 
 %struct.lds = type { [64 x ptr], [16 x i8] }
 @stored_lds_struct = addrspace(3) global %struct.lds addrspace(3) *undef, align 16
 @stored_lds_ptr = addrspace(3) global ptr addrspace(3) undef, align 4
 @stored_constant_ptr = addrspace(3) global ptr addrspace(4) undef, align 8
 @stored_global_ptr = addrspace(3) global ptr addrspace(1) undef, align 8
 
 ; GCN-LABEL: {{^}}no_reorder_flat_load_local_store_local_load:
 ; GCN: flat_load_dwordx4
-; GCN: ds_write_b128 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:512
+; GCN-DAG: ds_write2_b64 {{v[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:64 offset1:65
 ; GCN: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:129 offset1:130
 define amdgpu_kernel void @no_reorder_flat_load_local_store_local_load(ptr addrspace(3) %out, ptr %fptr) #0 {
   %ptr1 = getelementptr %struct.lds, ptr addrspace(3) @stored_lds_struct, i32 0, i32 1
   %ptr2 = getelementptr %struct.lds, ptr addrspace(3) @stored_lds_struct, i32 0, i32 1, i32 4
   call void @llvm.memcpy.p3.p0(ptr addrspace(3) align 16 %ptr1, ptr align 8 %fptr, i64 16, i1 false)
   %vector_load = load <2 x i32>, ptr addrspace(3) %ptr2, align 4
   store <2 x i32> %vector_load, ptr addrspace(3) %out, align 4
   ret void