[ARM] in ExpandTMOV32BitImm, CPSR register ops should be `Define`d

[stuij]

Summary

The CPSR registers ops of the instructions constructed in ExpandTMOV32BitImm
were marked as kill, instead of define. Best to use the pre-existing
t1CondCodeOp fn to construct CPSRs.

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

void ARMExpandPseudo::ExpandTMOV32BitImm(MachineBasicBlock &MBB,
   const MachineOperand &MO = MI.getOperand(1);
   MachineInstrBuilder Upper8_15, LSL_U8_15, Upper0_7, Lower8_15, Lower0_7;
   unsigned MIFlags = MI.getFlags();
 
   LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
 
   Upper8_15 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tMOVi8), DstReg)
-          .addReg(ARM::CPSR, RegState::Kill);
+          .add(t1CondCodeOp(true));
 
   LSL_U8_15 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg)
-          .addReg(ARM::CPSR, RegState::Kill)
+          .add(t1CondCodeOp(true))
           .addReg(DstReg)
           .addImm(8)
           .add(predOps(ARMCC::AL))
           .setMIFlags(MIFlags);
 
   Upper0_7 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8), DstReg)
-                 .addReg(ARM::CPSR, RegState::Kill)
+                 .add(t1CondCodeOp(true))
                  .addReg(DstReg);
 
   MachineInstr *LSL_U0_7 = MBB.getParent()->CloneMachineInstr(LSL_U8_15);
   MBB.insert(MBBI, LSL_U0_7);
 
   Lower8_15 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8), DstReg)
-          .addReg(ARM::CPSR, RegState::Kill)
+          .add(t1CondCodeOp(true))
           .addReg(DstReg);
 
   MachineInstr *LSL_L8_15 = MBB.getParent()->CloneMachineInstr(LSL_U8_15);
   MBB.insert(MBBI, LSL_L8_15);
 
   Lower0_7 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8))
                  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-                 .addReg(ARM::CPSR, RegState::Kill)
+                 .add(t1CondCodeOp(true))
                  .addReg(DstReg);
 
   Upper8_15.setMIFlags(MIFlags);
   Upper0_7.setMIFlags(MIFlags);
   Lower8_15.setMIFlags(MIFlags);
   Lower0_7.setMIFlags(MIFlags);
 
   switch (MO.getType()) {

llvm/test/CodeGen/ARM/execute-only.ll

-; UNSUPPORTED: expensive_checks
-
 ; RUN: llc -mtriple=thumbv8m.base-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
 ; RUN: llc -mtriple=thumbv8m.base-eabi -mcpu=cortex-m23 -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
 ; RUN: llc -mtriple=thumbv7m-eabi      -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
 ; RUN: llc -mtriple=thumbv8m.main-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
 ; RUN: llc -mtriple=thumbv6m-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK-T1 %s
 
 ; CHECK-NOT: {{^ *}}.text{{$}}
 ; CHECK: .section .text,"axy",%progbits,unique,0