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Differential D153540

[LoopUnroll] Fold add chains during unrolling
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Authored by nikic on Jun 22 2023, 5:51 AM.

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Reviewers
fhahn
reames
Commits
rGb9808e5660f5: [LoopUnroll] Fold add chains during unrolling
Summary

Loop unrolling tends to produce chains of %x1 = add %x0, 1; %x2 = add %x1, 1; ... with one add per unrolled iteration. This patch proposed to simplify these adds to %xN = add %x0, N directly during unrolling, rather than waiting for InstCombine to do so.

The motivation for this is that having a single add (rather than an add chain) on the induction variable makes it a simple recurrence, which we specially recognize in a number of places. This allows InstCombine to directly perform folds with that knowledge, instead of first folding the add chains, and then doing other folds in another InstCombine iteration.

Due to the reduced number of InstCombine iterations, this also results in a small compile-time improvement: http://llvm-compile-time-tracker.com/compare.php?from=4c748821cd18a13898db87cbe4925e5f26af1fab&to=e21a18f8e74a7bdb1bf98fbe1ce6accce3a10a0a&stat=instructions:u

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Event Timeline

nikic created this revision.Jun 22 2023, 5:51 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 22 2023, 5:51 AM
Herald added subscribers: luke, StephenFan, frasercrmck and 22 others. · View Herald Transcript
nikic requested review of this revision.Jun 22 2023, 5:51 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 22 2023, 5:51 AM
Herald added subscribers: llvm-commits, wangpc, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B240484: Diff 533574.Jun 22 2023, 7:57 AM
nikic edited the summary of this revision. (Show Details)Jun 29 2023, 12:03 AM

Ping

fhahn accepted this revision.Jun 30 2023, 8:57 AM

LGTM, thanks!

llvm/lib/Transforms/Utils/LoopUnroll.cpp
258

Do we have any tests where there's a signed overflow here? Would be good to make sure this is covered in the tests.

This revision is now accepted and ready to land.Jun 30 2023, 8:57 AM
nikic mentioned this in rG7905c48a845c: [LoopUnroll] Add test for early add folding (NFC).Jul 5 2023, 12:47 AM
Closed by commit rGb9808e5660f5: [LoopUnroll] Fold add chains during unrolling (authored by nikic). · Explain WhyJul 5 2023, 12:54 AM
This revision was automatically updated to reflect the committed changes.
nikic added a commit: rGb9808e5660f5: [LoopUnroll] Fold add chains during unrolling.

Revision Contents

Diff 537250

llvm/lib/Transforms/Utils/LoopUnroll.cpp

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#include "llvm/IR/DiagnosticInfo.h" #include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/Dominators.h" #include "llvm/IR/Dominators.h"
#include "llvm/IR/Function.h" #include "llvm/IR/Function.h"
#include "llvm/IR/Instruction.h" #include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h" #include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Metadata.h" #include "llvm/IR/Metadata.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/IR/Use.h" #include "llvm/IR/Use.h"
#include "llvm/IR/User.h" #include "llvm/IR/User.h"
#include "llvm/IR/ValueHandle.h" #include "llvm/IR/ValueHandle.h"
#include "llvm/IR/ValueMap.h" #include "llvm/IR/ValueMap.h"
#include "llvm/Support/Casting.h" #include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/GenericDomTree.h" #include "llvm/Support/GenericDomTree.h"
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/// Perform some cleanup and simplifications on loops after unrolling. It is /// Perform some cleanup and simplifications on loops after unrolling. It is
/// useful to simplify the IV's in the new loop, as well as do a quick /// useful to simplify the IV's in the new loop, as well as do a quick
/// simplify/dce pass of the instructions. /// simplify/dce pass of the instructions.
void llvm::simplifyLoopAfterUnroll(Loop *L, bool SimplifyIVs, LoopInfo *LI, void llvm::simplifyLoopAfterUnroll(Loop *L, bool SimplifyIVs, LoopInfo *LI,
ScalarEvolution *SE, DominatorTree *DT, ScalarEvolution *SE, DominatorTree *DT,
AssumptionCache *AC, AssumptionCache *AC,
const TargetTransformInfo *TTI) { const TargetTransformInfo *TTI) {
using namespace llvm::PatternMatch;
// Simplify any new induction variables in the partially unrolled loop. // Simplify any new induction variables in the partially unrolled loop.
if (SE && SimplifyIVs) { if (SE && SimplifyIVs) {
SmallVector<WeakTrackingVH, 16> DeadInsts; SmallVector<WeakTrackingVH, 16> DeadInsts;
simplifyLoopIVs(L, SE, DT, LI, TTI, DeadInsts); simplifyLoopIVs(L, SE, DT, LI, TTI, DeadInsts);
// Aggressively clean up dead instructions that simplifyLoopIVs already // Aggressively clean up dead instructions that simplifyLoopIVs already
// identified. Any remaining should be cleaned up below. // identified. Any remaining should be cleaned up below.
while (!DeadInsts.empty()) { while (!DeadInsts.empty()) {
Show All 9 Linesvoid llvm::simplifyLoopAfterUnroll(Loop *L, bool SimplifyIVs, LoopInfo *LI,
SmallVector<WeakTrackingVH, 16> DeadInsts; SmallVector<WeakTrackingVH, 16> DeadInsts;
for (BasicBlock *BB : L->getBlocks()) { for (BasicBlock *BB : L->getBlocks()) {
for (Instruction &Inst : llvm::make_early_inc_range(*BB)) { for (Instruction &Inst : llvm::make_early_inc_range(*BB)) {
if (Value *V = simplifyInstruction(&Inst, {DL, nullptr, DT, AC})) if (Value *V = simplifyInstruction(&Inst, {DL, nullptr, DT, AC}))
if (LI->replacementPreservesLCSSAForm(&Inst, V)) if (LI->replacementPreservesLCSSAForm(&Inst, V))
Inst.replaceAllUsesWith(V); Inst.replaceAllUsesWith(V);
if (isInstructionTriviallyDead(&Inst)) if (isInstructionTriviallyDead(&Inst))
DeadInsts.emplace_back(&Inst); DeadInsts.emplace_back(&Inst);
// Fold ((add X, C1), C2) to (add X, C1+C2). This is very common in
// unrolled loops, and handling this early allows following code to
// identify the IV as a "simple recurrence" without first folding away
// a long chain of adds.
{
Value *X;
const APInt *C1, *C2;
if (match(&Inst, m_Add(m_Add(m_Value(X), m_APInt(C1)), m_APInt(C2)))) {
auto *InnerI = dyn_cast<Instruction>(Inst.getOperand(0));
auto *InnerOBO = cast<OverflowingBinaryOperator>(Inst.getOperand(0));
bool SignedOverflow;
fhahnUnsubmitted
Not Done
ReplyInline Actions

Do we have any tests where there's a signed overflow here? Would be good to make sure this is covered in the tests.

fhahn: Do we have any tests where there's a signed overflow here? Would be good to make sure this is…
APInt NewC = C1->sadd_ov(*C2, SignedOverflow);
Inst.setOperand(0, X);
Inst.setOperand(1, ConstantInt::get(Inst.getType(), NewC));
Inst.setHasNoUnsignedWrap(Inst.hasNoUnsignedWrap() &&
InnerOBO->hasNoUnsignedWrap());
Inst.setHasNoSignedWrap(Inst.hasNoSignedWrap() &&
InnerOBO->hasNoSignedWrap() &&
!SignedOverflow);
if (InnerI && isInstructionTriviallyDead(InnerI))
DeadInsts.emplace_back(InnerI);
}
}
} }
// We can't do recursive deletion until we're done iterating, as we might // We can't do recursive deletion until we're done iterating, as we might
// have a phi which (potentially indirectly) uses instructions later in // have a phi which (potentially indirectly) uses instructions later in
// the block we're iterating through. // the block we're iterating through.
RecursivelyDeleteTriviallyDeadInstructions(DeadInsts); RecursivelyDeleteTriviallyDeadInstructions(DeadInsts);
} }
} }
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llvm/test/Analysis/ScalarEvolution/2012-05-29-MulAddRec.ll

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declare void @use(i8 %x) declare void @use(i8 %x)
; CHECK: @func ; CHECK: @func
; CHECK: for.cond: ; CHECK: for.cond:
; CHECK: %inc1 = phi i8 [ 0, %entry ], [ %0, %for.body ] ; CHECK: %inc1 = phi i8 [ 0, %entry ], [ %0, %for.body ]
; CHECK: br label %for.body ; CHECK: br label %for.body
; CHECK: for.body: ; CHECK: for.body:
; CHECK: %inc.9 = add i8 %inc.8, 1 ; CHECK: %inc.9 = add i8 %inc1, 10
; CHECK: %0 = add i8 %inc1, 10 ; CHECK: %0 = add i8 %inc1, 10
; CHECK: br label %for.cond ; CHECK: br label %for.cond
define void @func() noreturn nounwind uwtable ssp { define void @func() noreturn nounwind uwtable ssp {
entry: entry:
br label %for.cond br label %for.cond
for.cond.loopexit: ; preds = %for.body for.cond.loopexit: ; preds = %for.body
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llvm/test/DebugInfo/unrolled-loop-remainder.ll

Show All 36 Lines
; CHECK-NEXT: [[ADD_PROL:%.*]] = add nsw i32 [[DOTPR]], 2, !dbg [[DBG29:![0-9]+]] ; CHECK-NEXT: [[ADD_PROL:%.*]] = add nsw i32 [[DOTPR]], 2, !dbg [[DBG29:![0-9]+]]
; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i32 1, [[XTRAITER]], !dbg [[DBG24]] ; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i32 1, [[XTRAITER]], !dbg [[DBG24]]
; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[FOR_BODY_PROL_1:%.*]], label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !dbg [[DBG24]] ; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[FOR_BODY_PROL_1:%.*]], label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !dbg [[DBG24]]
; CHECK: for.body.prol.1: ; CHECK: for.body.prol.1:
; CHECK-NEXT: [[ARRAYIDX_PROL_1:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 1, !dbg [[DBG28]] ; CHECK-NEXT: [[ARRAYIDX_PROL_1:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 1, !dbg [[DBG28]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_PROL_1]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]] ; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_PROL_1]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
; CHECK-NEXT: [[CONV_PROL_1:%.*]] = sext i32 [[TMP7]] to i64, !dbg [[DBG28]] ; CHECK-NEXT: [[CONV_PROL_1:%.*]] = sext i32 [[TMP7]] to i64, !dbg [[DBG28]]
; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[CONV_PROL_1]] to ptr, !dbg [[DBG28]] ; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[CONV_PROL_1]] to ptr, !dbg [[DBG28]]
; CHECK-NEXT: [[ADD_PROL_1:%.*]] = add nsw i32 [[ADD_PROL]], 2, !dbg [[DBG29]] ; CHECK-NEXT: [[ADD_PROL_1:%.*]] = add nsw i32 [[DOTPR]], 4, !dbg [[DBG29]]
; CHECK-NEXT: [[PROL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]], !dbg [[DBG24]] ; CHECK-NEXT: [[PROL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]], !dbg [[DBG24]]
; CHECK-NEXT: br i1 [[PROL_ITER_CMP_1]], label [[FOR_BODY_PROL_2:%.*]], label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]], !dbg [[DBG24]] ; CHECK-NEXT: br i1 [[PROL_ITER_CMP_1]], label [[FOR_BODY_PROL_2:%.*]], label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]], !dbg [[DBG24]]
; CHECK: for.body.prol.2: ; CHECK: for.body.prol.2:
; CHECK-NEXT: [[ARRAYIDX_PROL_2:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 1, !dbg [[DBG28]] ; CHECK-NEXT: [[ARRAYIDX_PROL_2:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 1, !dbg [[DBG28]]
; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_PROL_2]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]] ; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_PROL_2]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
; CHECK-NEXT: [[CONV_PROL_2:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG28]] ; CHECK-NEXT: [[CONV_PROL_2:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG28]]
; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[CONV_PROL_2]] to ptr, !dbg [[DBG28]] ; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[CONV_PROL_2]] to ptr, !dbg [[DBG28]]
; CHECK-NEXT: [[ADD_PROL_2:%.*]] = add nsw i32 [[ADD_PROL_1]], 2, !dbg [[DBG29]] ; CHECK-NEXT: [[ADD_PROL_2:%.*]] = add nsw i32 [[DOTPR]], 6, !dbg [[DBG29]]
; CHECK-NEXT: br label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]] ; CHECK-NEXT: br label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]]
; CHECK: for.body.prol.loopexit.unr-lcssa: ; CHECK: for.body.prol.loopexit.unr-lcssa:
; CHECK-NEXT: [[DOTLCSSA_UNR_PH:%.*]] = phi ptr [ [[TMP6]], [[FOR_BODY_PROL]] ], [ [[TMP8]], [[FOR_BODY_PROL_1]] ], [ [[TMP10]], [[FOR_BODY_PROL_2]] ] ; CHECK-NEXT: [[DOTLCSSA_UNR_PH:%.*]] = phi ptr [ [[TMP6]], [[FOR_BODY_PROL]] ], [ [[TMP8]], [[FOR_BODY_PROL_1]] ], [ [[TMP10]], [[FOR_BODY_PROL_2]] ]
; CHECK-NEXT: [[DOTUNR_PH:%.*]] = phi ptr [ [[TMP6]], [[FOR_BODY_PROL]] ], [ [[TMP8]], [[FOR_BODY_PROL_1]] ], [ [[TMP10]], [[FOR_BODY_PROL_2]] ] ; CHECK-NEXT: [[DOTUNR_PH:%.*]] = phi ptr [ [[TMP6]], [[FOR_BODY_PROL]] ], [ [[TMP8]], [[FOR_BODY_PROL_1]] ], [ [[TMP10]], [[FOR_BODY_PROL_2]] ]
; CHECK-NEXT: [[DOTUNR1_PH:%.*]] = phi i32 [ [[ADD_PROL]], [[FOR_BODY_PROL]] ], [ [[ADD_PROL_1]], [[FOR_BODY_PROL_1]] ], [ [[ADD_PROL_2]], [[FOR_BODY_PROL_2]] ] ; CHECK-NEXT: [[DOTUNR1_PH:%.*]] = phi i32 [ [[ADD_PROL]], [[FOR_BODY_PROL]] ], [ [[ADD_PROL_1]], [[FOR_BODY_PROL_1]] ], [ [[ADD_PROL_2]], [[FOR_BODY_PROL_2]] ]
; CHECK-NEXT: br label [[FOR_BODY_PROL_LOOPEXIT]], !dbg [[DBG24]] ; CHECK-NEXT: br label [[FOR_BODY_PROL_LOOPEXIT]], !dbg [[DBG24]]
; CHECK: for.body.prol.loopexit: ; CHECK: for.body.prol.loopexit:
; CHECK-NEXT: [[DOTLCSSA_UNR:%.*]] = phi ptr [ undef, [[FOR_BODY_LR_PH]] ], [ [[DOTLCSSA_UNR_PH]], [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]] ] ; CHECK-NEXT: [[DOTLCSSA_UNR:%.*]] = phi ptr [ undef, [[FOR_BODY_LR_PH]] ], [ [[DOTLCSSA_UNR_PH]], [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[DOTUNR:%.*]] = phi ptr [ [[A_PROMOTED]], [[FOR_BODY_LR_PH]] ], [ [[DOTUNR_PH]], [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]] ] ; CHECK-NEXT: [[DOTUNR:%.*]] = phi ptr [ [[A_PROMOTED]], [[FOR_BODY_LR_PH]] ], [ [[DOTUNR_PH]], [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[DOTUNR1:%.*]] = phi i32 [ [[DOTPR]], [[FOR_BODY_LR_PH]] ], [ [[DOTUNR1_PH]], [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]] ] ; CHECK-NEXT: [[DOTUNR1:%.*]] = phi i32 [ [[DOTPR]], [[FOR_BODY_LR_PH]] ], [ [[DOTUNR1_PH]], [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[TMP11:%.*]] = icmp ult i32 [[TMP3]], 3, !dbg [[DBG24]] ; CHECK-NEXT: [[TMP11:%.*]] = icmp ult i32 [[TMP3]], 3, !dbg [[DBG24]]
; CHECK-NEXT: br i1 [[TMP11]], label [[FOR_COND_FOR_END_CRIT_EDGE:%.*]], label [[FOR_BODY_LR_PH_NEW:%.*]], !dbg [[DBG24]] ; CHECK-NEXT: br i1 [[TMP11]], label [[FOR_COND_FOR_END_CRIT_EDGE:%.*]], label [[FOR_BODY_LR_PH_NEW:%.*]], !dbg [[DBG24]]
; CHECK: for.body.lr.ph.new: ; CHECK: for.body.lr.ph.new:
; CHECK-NEXT: br label [[FOR_BODY:%.*]], !dbg [[DBG24]] ; CHECK-NEXT: br label [[FOR_BODY:%.*]], !dbg [[DBG24]]
; CHECK: for.body: ; CHECK: for.body:
; CHECK-NEXT: [[TMP12:%.*]] = phi ptr [ [[DOTUNR]], [[FOR_BODY_LR_PH_NEW]] ], [ [[TMP21:%.*]], [[FOR_BODY]] ], !dbg [[DBG28]] ; CHECK-NEXT: [[TMP12:%.*]] = phi ptr [ [[DOTUNR]], [[FOR_BODY_LR_PH_NEW]] ], [ [[TMP21:%.*]], [[FOR_BODY]] ], !dbg [[DBG28]]
; CHECK-NEXT: [[TMP13:%.*]] = phi i32 [ [[DOTUNR1]], [[FOR_BODY_LR_PH_NEW]] ], [ [[ADD_3:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[TMP13:%.*]] = phi i32 [ [[DOTUNR1]], [[FOR_BODY_LR_PH_NEW]] ], [ [[ADD_3:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP12]], i64 1, !dbg [[DBG28]] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP12]], i64 1, !dbg [[DBG28]]
; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]] ; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP14]] to i64, !dbg [[DBG28]] ; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP14]] to i64, !dbg [[DBG28]]
; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[CONV]] to ptr, !dbg [[DBG28]] ; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[CONV]] to ptr, !dbg [[DBG28]]
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 2, !dbg [[DBG29]]
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[TMP15]], i64 1, !dbg [[DBG28]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[TMP15]], i64 1, !dbg [[DBG28]]
; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]] ; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
; CHECK-NEXT: [[CONV_1:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG28]] ; CHECK-NEXT: [[CONV_1:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG28]]
; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[CONV_1]] to ptr, !dbg [[DBG28]] ; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[CONV_1]] to ptr, !dbg [[DBG28]]
; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i32 [[ADD]], 2, !dbg [[DBG29]]
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i64 1, !dbg [[DBG28]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i64 1, !dbg [[DBG28]]
; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]] ; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
; CHECK-NEXT: [[CONV_2:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG28]] ; CHECK-NEXT: [[CONV_2:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG28]]
; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[CONV_2]] to ptr, !dbg [[DBG28]] ; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[CONV_2]] to ptr, !dbg [[DBG28]]
; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i32 [[ADD_1]], 2, !dbg [[DBG29]]
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[TMP19]], i64 1, !dbg [[DBG28]] ; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[TMP19]], i64 1, !dbg [[DBG28]]
; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]] ; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
; CHECK-NEXT: [[CONV_3:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG28]] ; CHECK-NEXT: [[CONV_3:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG28]]
; CHECK-NEXT: [[TMP21]] = inttoptr i64 [[CONV_3]] to ptr, !dbg [[DBG28]] ; CHECK-NEXT: [[TMP21]] = inttoptr i64 [[CONV_3]] to ptr, !dbg [[DBG28]]
; CHECK-NEXT: [[ADD_3]] = add nsw i32 [[ADD_2]], 2, !dbg [[DBG29]] ; CHECK-NEXT: [[ADD_3]] = add nsw i32 [[TMP13]], 8, !dbg [[DBG29]]
; CHECK-NEXT: [[TOBOOL_3:%.*]] = icmp eq i32 [[ADD_3]], 0, !dbg [[DBG24]] ; CHECK-NEXT: [[TOBOOL_3:%.*]] = icmp eq i32 [[ADD_3]], 0, !dbg [[DBG24]]
; CHECK-NEXT: br i1 [[TOBOOL_3]], label [[FOR_COND_FOR_END_CRIT_EDGE_UNR_LCSSA:%.*]], label [[FOR_BODY]], !dbg [[DBG24]], !llvm.loop [[LOOP30:![0-9]+]] ; CHECK-NEXT: br i1 [[TOBOOL_3]], label [[FOR_COND_FOR_END_CRIT_EDGE_UNR_LCSSA:%.*]], label [[FOR_BODY]], !dbg [[DBG24]], !llvm.loop [[LOOP30:![0-9]+]]
; CHECK: for.cond.for.end_crit_edge.unr-lcssa: ; CHECK: for.cond.for.end_crit_edge.unr-lcssa:
; CHECK-NEXT: [[DOTLCSSA_PH:%.*]] = phi ptr [ [[TMP21]], [[FOR_BODY]] ] ; CHECK-NEXT: [[DOTLCSSA_PH:%.*]] = phi ptr [ [[TMP21]], [[FOR_BODY]] ]
; CHECK-NEXT: br label [[FOR_COND_FOR_END_CRIT_EDGE]], !dbg [[DBG24]] ; CHECK-NEXT: br label [[FOR_COND_FOR_END_CRIT_EDGE]], !dbg [[DBG24]]
; CHECK: for.cond.for.end_crit_edge: ; CHECK: for.cond.for.end_crit_edge:
; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi ptr [ [[DOTLCSSA_UNR]], [[FOR_BODY_PROL_LOOPEXIT]] ], [ [[DOTLCSSA_PH]], [[FOR_COND_FOR_END_CRIT_EDGE_UNR_LCSSA]] ], !dbg [[DBG28]] ; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi ptr [ [[DOTLCSSA_UNR]], [[FOR_BODY_PROL_LOOPEXIT]] ], [ [[DOTLCSSA_PH]], [[FOR_COND_FOR_END_CRIT_EDGE_UNR_LCSSA]] ], !dbg [[DBG28]]
; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP2]], 2, !dbg [[DBG24]] ; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP2]], 2, !dbg [[DBG24]]
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llvm/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll

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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVAR_NEXT]], [[TMP]] ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVAR_NEXT]], [[TMP]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[BB_1:%.*]], label [[BB1_BB2_CRIT_EDGE:%.*]] ; CHECK-NEXT: br i1 [[EXITCOND]], label [[BB_1:%.*]], label [[BB1_BB2_CRIT_EDGE:%.*]]
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK-NEXT: [[SCEVGEP_1:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDVAR_NEXT]] ; CHECK-NEXT: [[SCEVGEP_1:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDVAR_NEXT]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[SCEVGEP_1]], align 1 ; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[SCEVGEP_1]], align 1
; CHECK-NEXT: [[TMP4:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = add nsw i32 [[TMP3]], [[TMP2]]
; CHECK-NEXT: br label [[BB1_1:%.*]] ; CHECK-NEXT: br label [[BB1_1:%.*]]
; CHECK: bb1.1: ; CHECK: bb1.1:
; CHECK-NEXT: [[INDVAR_NEXT_1:%.*]] = add nuw nsw i64 [[INDVAR_NEXT]], 1 ; CHECK-NEXT: [[INDVAR_NEXT_1:%.*]] = add nuw nsw i64 [[INDVAR]], 2
; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp ne i64 [[INDVAR_NEXT_1]], [[TMP]] ; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp ne i64 [[INDVAR_NEXT_1]], [[TMP]]
; CHECK-NEXT: br i1 [[EXITCOND_1]], label [[BB_2:%.*]], label [[BB1_BB2_CRIT_EDGE]] ; CHECK-NEXT: br i1 [[EXITCOND_1]], label [[BB_2:%.*]], label [[BB1_BB2_CRIT_EDGE]]
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK-NEXT: [[SCEVGEP_2:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDVAR_NEXT_1]] ; CHECK-NEXT: [[SCEVGEP_2:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDVAR_NEXT_1]]
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[SCEVGEP_2]], align 1 ; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[SCEVGEP_2]], align 1
; CHECK-NEXT: [[TMP6:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
; CHECK-NEXT: br label [[BB1_2:%.*]] ; CHECK-NEXT: br label [[BB1_2:%.*]]
; CHECK: bb1.2: ; CHECK: bb1.2:
; CHECK-NEXT: [[INDVAR_NEXT_2:%.*]] = add nuw nsw i64 [[INDVAR_NEXT_1]], 1 ; CHECK-NEXT: [[INDVAR_NEXT_2:%.*]] = add nuw nsw i64 [[INDVAR]], 3
; CHECK-NEXT: [[EXITCOND_2:%.*]] = icmp ne i64 [[INDVAR_NEXT_2]], [[TMP]] ; CHECK-NEXT: [[EXITCOND_2:%.*]] = icmp ne i64 [[INDVAR_NEXT_2]], [[TMP]]
; CHECK-NEXT: br i1 [[EXITCOND_2]], label [[BB_3:%.*]], label [[BB1_BB2_CRIT_EDGE]] ; CHECK-NEXT: br i1 [[EXITCOND_2]], label [[BB_3:%.*]], label [[BB1_BB2_CRIT_EDGE]]
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK-NEXT: [[SCEVGEP_3:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDVAR_NEXT_2]] ; CHECK-NEXT: [[SCEVGEP_3:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDVAR_NEXT_2]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[SCEVGEP_3]], align 1 ; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[SCEVGEP_3]], align 1
; CHECK-NEXT: [[TMP8]] = add nsw i32 [[TMP7]], [[TMP6]] ; CHECK-NEXT: [[TMP8]] = add nsw i32 [[TMP7]], [[TMP6]]
; CHECK-NEXT: br label [[BB1_3]] ; CHECK-NEXT: br label [[BB1_3]]
; CHECK: bb1.3: ; CHECK: bb1.3:
; CHECK-NEXT: [[INDVAR_NEXT_3]] = add i64 [[INDVAR_NEXT_2]], 1 ; CHECK-NEXT: [[INDVAR_NEXT_3]] = add i64 [[INDVAR]], 4
; CHECK-NEXT: [[EXITCOND_3:%.*]] = icmp ne i64 [[INDVAR_NEXT_3]], [[TMP]] ; CHECK-NEXT: [[EXITCOND_3:%.*]] = icmp ne i64 [[INDVAR_NEXT_3]], [[TMP]]
; CHECK-NEXT: br i1 [[EXITCOND_3]], label [[BB]], label [[BB1_BB2_CRIT_EDGE]], !llvm.loop [[LOOP2:![0-9]+]] ; CHECK-NEXT: br i1 [[EXITCOND_3]], label [[BB]], label [[BB1_BB2_CRIT_EDGE]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: bb1.bb2_crit_edge: ; CHECK: bb1.bb2_crit_edge:
; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i32 [ [[TMP2]], [[BB1]] ], [ [[TMP4]], [[BB1_1]] ], [ [[TMP6]], [[BB1_2]] ], [ [[TMP8]], [[BB1_3]] ] ; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i32 [ [[TMP2]], [[BB1]] ], [ [[TMP4]], [[BB1_1]] ], [ [[TMP6]], [[BB1_2]] ], [ [[TMP8]], [[BB1_3]] ]
; CHECK-NEXT: br label [[BB2]] ; CHECK-NEXT: br label [[BB2]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: [[S_0_LCSSA:%.*]] = phi i32 [ [[DOTLCSSA]], [[BB1_BB2_CRIT_EDGE]] ], [ 0, [[ENTRY:%.*]] ] ; CHECK-NEXT: [[S_0_LCSSA:%.*]] = phi i32 [ [[DOTLCSSA]], [[BB1_BB2_CRIT_EDGE]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i32 [[S_0_LCSSA]] ; CHECK-NEXT: ret i32 [[S_0_LCSSA]]
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

llvm/test/Transforms/LoopUnroll/AArch64/partial.ll

Show All 9 Linesloop:
%inc = add i32 %iv, 1 %inc = add i32 %iv, 1
%exitcnd = icmp uge i32 %inc, 1024 %exitcnd = icmp uge i32 %inc, 1024
br i1 %exitcnd, label %exit, label %loop br i1 %exitcnd, label %exit, label %loop
exit: exit:
ret void ret void
} }
; CHECK: add ; CHECK: add{{.*}}, 8
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: icmp ; CHECK-NEXT: icmp
; Partial unroll 16 times for this loop. ; Partial unroll 16 times for this loop.
define void @unroll2() nounwind { define void @unroll2() nounwind {
entry: entry:
br label %loop1 br label %loop1
loop1: loop1:
Show All 18 Linesloop1.latch:
br i1 %exitcnd2, label %exit, label %loop1 br i1 %exitcnd2, label %exit, label %loop1
exit: exit:
ret void ret void
} }
; CHECK: add ; CHECK: add{{.*}}, 16
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: icmp ; CHECK-NEXT: icmp

llvm/test/Transforms/LoopUnroll/ARM/instr-size-costs.ll

Show All 16 Lines
; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1 ; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1
; CHECK-V8-NEXT: [[ADDR_A_1:%.*]] = getelementptr i32, ptr [[A]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_A_1:%.*]] = getelementptr i32, ptr [[A]], i32 [[COUNT]]
; CHECK-V8-NEXT: [[ADDR_B_1:%.*]] = getelementptr i32, ptr [[B]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_B_1:%.*]] = getelementptr i32, ptr [[B]], i32 [[COUNT]]
; CHECK-V8-NEXT: [[DATA_A_1:%.*]] = load i32, ptr [[ADDR_A_1]], align 4 ; CHECK-V8-NEXT: [[DATA_A_1:%.*]] = load i32, ptr [[ADDR_A_1]], align 4
; CHECK-V8-NEXT: [[DATA_B_1:%.*]] = load i32, ptr [[ADDR_B_1]], align 4 ; CHECK-V8-NEXT: [[DATA_B_1:%.*]] = load i32, ptr [[ADDR_B_1]], align 4
; CHECK-V8-NEXT: [[RES_1:%.*]] = add i32 [[DATA_A_1]], [[DATA_B_1]] ; CHECK-V8-NEXT: [[RES_1:%.*]] = add i32 [[DATA_A_1]], [[DATA_B_1]]
; CHECK-V8-NEXT: [[ADDR_C_1:%.*]] = getelementptr i32, ptr [[C]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_C_1:%.*]] = getelementptr i32, ptr [[C]], i32 [[COUNT]]
; CHECK-V8-NEXT: store i32 [[RES_1]], ptr [[ADDR_C_1]], align 4 ; CHECK-V8-NEXT: store i32 [[RES_1]], ptr [[ADDR_C_1]], align 4
; CHECK-V8-NEXT: [[COUNT_1]] = add nuw nsw i32 [[COUNT]], 1 ; CHECK-V8-NEXT: [[COUNT_1]] = add nuw nsw i32 [[IV]], 2
; CHECK-V8-NEXT: [[END_1:%.*]] = icmp ne i32 [[COUNT_1]], 100 ; CHECK-V8-NEXT: [[END_1:%.*]] = icmp ne i32 [[COUNT_1]], 100
; CHECK-V8-NEXT: br i1 [[END_1]], label [[LOOP]], label [[EXIT:%.*]] ; CHECK-V8-NEXT: br i1 [[END_1]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8: exit: ; CHECK-V8: exit:
; CHECK-V8-NEXT: ret void ; CHECK-V8-NEXT: ret void
; ;
entry: entry:
br label %loop br label %loop
Show All 30 Lines
; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1 ; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1
; CHECK-V8-NEXT: [[ADDR_A_1:%.*]] = getelementptr i32, ptr [[A]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_A_1:%.*]] = getelementptr i32, ptr [[A]], i32 [[COUNT]]
; CHECK-V8-NEXT: [[ADDR_B_1:%.*]] = getelementptr i32, ptr [[B]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_B_1:%.*]] = getelementptr i32, ptr [[B]], i32 [[COUNT]]
; CHECK-V8-NEXT: [[DATA_A_1:%.*]] = load i32, ptr [[ADDR_A_1]], align 4 ; CHECK-V8-NEXT: [[DATA_A_1:%.*]] = load i32, ptr [[ADDR_A_1]], align 4
; CHECK-V8-NEXT: [[DATA_B_1:%.*]] = load i32, ptr [[ADDR_B_1]], align 4 ; CHECK-V8-NEXT: [[DATA_B_1:%.*]] = load i32, ptr [[ADDR_B_1]], align 4
; CHECK-V8-NEXT: [[RES_1:%.*]] = add i32 [[DATA_A_1]], [[DATA_B_1]] ; CHECK-V8-NEXT: [[RES_1:%.*]] = add i32 [[DATA_A_1]], [[DATA_B_1]]
; CHECK-V8-NEXT: [[ADDR_C_1:%.*]] = getelementptr i32, ptr [[C]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_C_1:%.*]] = getelementptr i32, ptr [[C]], i32 [[COUNT]]
; CHECK-V8-NEXT: store i32 [[RES_1]], ptr [[ADDR_C_1]], align 4 ; CHECK-V8-NEXT: store i32 [[RES_1]], ptr [[ADDR_C_1]], align 4
; CHECK-V8-NEXT: [[COUNT_1]] = add nuw nsw i32 [[COUNT]], 1 ; CHECK-V8-NEXT: [[COUNT_1]] = add nuw nsw i32 [[IV]], 2
; CHECK-V8-NEXT: [[END_1:%.*]] = icmp ne i32 [[COUNT_1]], 100 ; CHECK-V8-NEXT: [[END_1:%.*]] = icmp ne i32 [[COUNT_1]], 100
; CHECK-V8-NEXT: br i1 [[END_1]], label [[LOOP]], label [[EXIT:%.*]] ; CHECK-V8-NEXT: br i1 [[END_1]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8: exit: ; CHECK-V8: exit:
; CHECK-V8-NEXT: ret void ; CHECK-V8-NEXT: ret void
; ;
entry: entry:
br label %loop br label %loop
Show All 30 Lines
; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1 ; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1
; CHECK-V8-NEXT: [[ADDR_A_1:%.*]] = getelementptr i64, ptr [[A]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_A_1:%.*]] = getelementptr i64, ptr [[A]], i32 [[COUNT]]
; CHECK-V8-NEXT: [[ADDR_B_1:%.*]] = getelementptr i64, ptr [[B]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_B_1:%.*]] = getelementptr i64, ptr [[B]], i32 [[COUNT]]
; CHECK-V8-NEXT: [[DATA_A_1:%.*]] = load i64, ptr [[ADDR_A_1]], align 4 ; CHECK-V8-NEXT: [[DATA_A_1:%.*]] = load i64, ptr [[ADDR_A_1]], align 4
; CHECK-V8-NEXT: [[DATA_B_1:%.*]] = load i64, ptr [[ADDR_B_1]], align 4 ; CHECK-V8-NEXT: [[DATA_B_1:%.*]] = load i64, ptr [[ADDR_B_1]], align 4
; CHECK-V8-NEXT: [[RES_1:%.*]] = add i64 [[DATA_A_1]], [[DATA_B_1]] ; CHECK-V8-NEXT: [[RES_1:%.*]] = add i64 [[DATA_A_1]], [[DATA_B_1]]
; CHECK-V8-NEXT: [[ADDR_C_1:%.*]] = getelementptr i64, ptr [[C]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_C_1:%.*]] = getelementptr i64, ptr [[C]], i32 [[COUNT]]
; CHECK-V8-NEXT: store i64 [[RES_1]], ptr [[ADDR_C_1]], align 4 ; CHECK-V8-NEXT: store i64 [[RES_1]], ptr [[ADDR_C_1]], align 4
; CHECK-V8-NEXT: [[COUNT_1]] = add nuw nsw i32 [[COUNT]], 1 ; CHECK-V8-NEXT: [[COUNT_1]] = add nuw nsw i32 [[IV]], 2
; CHECK-V8-NEXT: [[END_1:%.*]] = icmp ne i32 [[COUNT_1]], 100 ; CHECK-V8-NEXT: [[END_1:%.*]] = icmp ne i32 [[COUNT_1]], 100
; CHECK-V8-NEXT: br i1 [[END_1]], label [[LOOP]], label [[EXIT:%.*]] ; CHECK-V8-NEXT: br i1 [[END_1]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8: exit: ; CHECK-V8: exit:
; CHECK-V8-NEXT: ret void ; CHECK-V8-NEXT: ret void
; ;
entry: entry:
br label %loop br label %loop
Show All 30 Lines
; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1 ; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1
; CHECK-V8-NEXT: [[ADDR_A_1:%.*]] = getelementptr i64, ptr [[A]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_A_1:%.*]] = getelementptr i64, ptr [[A]], i32 [[COUNT]]
; CHECK-V8-NEXT: [[ADDR_B_1:%.*]] = getelementptr i64, ptr [[B]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_B_1:%.*]] = getelementptr i64, ptr [[B]], i32 [[COUNT]]
; CHECK-V8-NEXT: [[DATA_A_1:%.*]] = load i64, ptr [[ADDR_A_1]], align 4 ; CHECK-V8-NEXT: [[DATA_A_1:%.*]] = load i64, ptr [[ADDR_A_1]], align 4
; CHECK-V8-NEXT: [[DATA_B_1:%.*]] = load i64, ptr [[ADDR_B_1]], align 4 ; CHECK-V8-NEXT: [[DATA_B_1:%.*]] = load i64, ptr [[ADDR_B_1]], align 4
; CHECK-V8-NEXT: [[RES_1:%.*]] = add i64 [[DATA_A_1]], [[DATA_B_1]] ; CHECK-V8-NEXT: [[RES_1:%.*]] = add i64 [[DATA_A_1]], [[DATA_B_1]]
; CHECK-V8-NEXT: [[ADDR_C_1:%.*]] = getelementptr i64, ptr [[C]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_C_1:%.*]] = getelementptr i64, ptr [[C]], i32 [[COUNT]]
; CHECK-V8-NEXT: store i64 [[RES_1]], ptr [[ADDR_C_1]], align 4 ; CHECK-V8-NEXT: store i64 [[RES_1]], ptr [[ADDR_C_1]], align 4
; CHECK-V8-NEXT: [[COUNT_1]] = add nuw nsw i32 [[COUNT]], 1 ; CHECK-V8-NEXT: [[COUNT_1]] = add nuw nsw i32 [[IV]], 2
; CHECK-V8-NEXT: [[END_1:%.*]] = icmp ne i32 [[COUNT_1]], 100 ; CHECK-V8-NEXT: [[END_1:%.*]] = icmp ne i32 [[COUNT_1]], 100
; CHECK-V8-NEXT: br i1 [[END_1]], label [[LOOP]], label [[EXIT:%.*]] ; CHECK-V8-NEXT: br i1 [[END_1]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8: exit: ; CHECK-V8: exit:
; CHECK-V8-NEXT: ret void ; CHECK-V8-NEXT: ret void
; ;
entry: entry:
br label %loop br label %loop
Show All 35 Lines
; CHECK-V8-NEXT: [[ADDR_B_1:%.*]] = getelementptr i32, ptr [[B]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_B_1:%.*]] = getelementptr i32, ptr [[B]], i32 [[COUNT]]
; CHECK-V8-NEXT: [[DATA_A_1:%.*]] = load i32, ptr [[ADDR_A_1]], align 4 ; CHECK-V8-NEXT: [[DATA_A_1:%.*]] = load i32, ptr [[ADDR_A_1]], align 4
; CHECK-V8-NEXT: [[DATA_B_1:%.*]] = load i32, ptr [[ADDR_B_1]], align 4 ; CHECK-V8-NEXT: [[DATA_B_1:%.*]] = load i32, ptr [[ADDR_B_1]], align 4
; CHECK-V8-NEXT: [[UGT_1:%.*]] = icmp ugt i32 [[DATA_A_1]], [[DATA_B_1]] ; CHECK-V8-NEXT: [[UGT_1:%.*]] = icmp ugt i32 [[DATA_A_1]], [[DATA_B_1]]
; CHECK-V8-NEXT: [[UMAX_1:%.*]] = select i1 [[UGT_1]], i32 [[DATA_A_1]], i32 [[DATA_B_1]] ; CHECK-V8-NEXT: [[UMAX_1:%.*]] = select i1 [[UGT_1]], i32 [[DATA_A_1]], i32 [[DATA_B_1]]
; CHECK-V8-NEXT: [[ACC_NEXT_1]] = add i32 [[UMAX_1]], [[ACC_NEXT]] ; CHECK-V8-NEXT: [[ACC_NEXT_1]] = add i32 [[UMAX_1]], [[ACC_NEXT]]
; CHECK-V8-NEXT: [[ADDR_C_1:%.*]] = getelementptr i32, ptr [[C]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_C_1:%.*]] = getelementptr i32, ptr [[C]], i32 [[COUNT]]
; CHECK-V8-NEXT: store i32 [[UMAX_1]], ptr [[ADDR_C_1]], align 4 ; CHECK-V8-NEXT: store i32 [[UMAX_1]], ptr [[ADDR_C_1]], align 4
; CHECK-V8-NEXT: [[COUNT_1]] = add nuw nsw i32 [[COUNT]], 1 ; CHECK-V8-NEXT: [[COUNT_1]] = add nuw nsw i32 [[IV]], 2
; CHECK-V8-NEXT: [[END_1:%.*]] = icmp ne i32 [[COUNT_1]], 100 ; CHECK-V8-NEXT: [[END_1:%.*]] = icmp ne i32 [[COUNT_1]], 100
; CHECK-V8-NEXT: br i1 [[END_1]], label [[LOOP]], label [[EXIT:%.*]] ; CHECK-V8-NEXT: br i1 [[END_1]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8: exit: ; CHECK-V8: exit:
; CHECK-V8-NEXT: [[ACC_NEXT_LCSSA:%.*]] = phi i32 [ [[ACC_NEXT_1]], [[LOOP]] ] ; CHECK-V8-NEXT: [[ACC_NEXT_LCSSA:%.*]] = phi i32 [ [[ACC_NEXT_1]], [[LOOP]] ]
; CHECK-V8-NEXT: ret i32 [[ACC_NEXT_LCSSA]] ; CHECK-V8-NEXT: ret i32 [[ACC_NEXT_LCSSA]]
; ;
entry: entry:
br label %loop br label %loop
Show All 39 Lines
; CHECK-V8-NEXT: [[ADDR_B_1:%.*]] = getelementptr i32, ptr [[B]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_B_1:%.*]] = getelementptr i32, ptr [[B]], i32 [[COUNT]]
; CHECK-V8-NEXT: [[DATA_A_1:%.*]] = load i32, ptr [[ADDR_A_1]], align 4 ; CHECK-V8-NEXT: [[DATA_A_1:%.*]] = load i32, ptr [[ADDR_A_1]], align 4
; CHECK-V8-NEXT: [[DATA_B_1:%.*]] = load i32, ptr [[ADDR_B_1]], align 4 ; CHECK-V8-NEXT: [[DATA_B_1:%.*]] = load i32, ptr [[ADDR_B_1]], align 4
; CHECK-V8-NEXT: [[UGT_1:%.*]] = icmp ugt i32 [[DATA_A_1]], [[DATA_B_1]] ; CHECK-V8-NEXT: [[UGT_1:%.*]] = icmp ugt i32 [[DATA_A_1]], [[DATA_B_1]]
; CHECK-V8-NEXT: [[UMAX_1:%.*]] = select i1 [[UGT_1]], i32 [[DATA_A_1]], i32 [[DATA_B_1]] ; CHECK-V8-NEXT: [[UMAX_1:%.*]] = select i1 [[UGT_1]], i32 [[DATA_A_1]], i32 [[DATA_B_1]]
; CHECK-V8-NEXT: [[ACC_NEXT_1]] = add i32 [[UMAX_1]], [[ACC_NEXT]] ; CHECK-V8-NEXT: [[ACC_NEXT_1]] = add i32 [[UMAX_1]], [[ACC_NEXT]]
; CHECK-V8-NEXT: [[ADDR_C_1:%.*]] = getelementptr i32, ptr [[C]], i32 [[COUNT]] ; CHECK-V8-NEXT: [[ADDR_C_1:%.*]] = getelementptr i32, ptr [[C]], i32 [[COUNT]]
; CHECK-V8-NEXT: store i32 [[UMAX_1]], ptr [[ADDR_C_1]], align 4 ; CHECK-V8-NEXT: store i32 [[UMAX_1]], ptr [[ADDR_C_1]], align 4
; CHECK-V8-NEXT: [[COUNT_1]] = add nuw nsw i32 [[COUNT]], 1 ; CHECK-V8-NEXT: [[COUNT_1]] = add nuw nsw i32 [[IV]], 2
; CHECK-V8-NEXT: [[END_1:%.*]] = icmp ne i32 [[COUNT_1]], 100 ; CHECK-V8-NEXT: [[END_1:%.*]] = icmp ne i32 [[COUNT_1]], 100
; CHECK-V8-NEXT: br i1 [[END_1]], label [[LOOP]], label [[EXIT:%.*]] ; CHECK-V8-NEXT: br i1 [[END_1]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK-V8: exit: ; CHECK-V8: exit:
; CHECK-V8-NEXT: [[ACC_NEXT_LCSSA:%.*]] = phi i32 [ [[ACC_NEXT_1]], [[LOOP]] ] ; CHECK-V8-NEXT: [[ACC_NEXT_LCSSA:%.*]] = phi i32 [ [[ACC_NEXT_1]], [[LOOP]] ]
; CHECK-V8-NEXT: ret i32 [[ACC_NEXT_LCSSA]] ; CHECK-V8-NEXT: ret i32 [[ACC_NEXT_LCSSA]]
; ;
entry: entry:
br label %loop br label %loop
▲ Show 20 Lines • Show All 115 Lines • Show Last 20 Lines

llvm/test/Transforms/LoopUnroll/ARM/loop-unrolling.ll

Show All 9 Lines
entry: entry:
br label %for.body br label %for.body
; CHECK-LABEL: for.body ; CHECK-LABEL: for.body
for.body: for.body:
; CHECK-NOUNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV2:%[a-z.0-9]+]], %for.body ] ; CHECK-NOUNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV2:%[a-z.0-9]+]], %for.body ]
; CHECK-NOUNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1 ; CHECK-NOUNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
; CHECK-NOUNROLL: [[IV2]] = add nuw nsw i32 [[IV1]], 1 ; CHECK-NOUNROLL: [[IV2]] = add nuw nsw i32 [[IV0]], 2
; CHECK-NOUNROLL: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV2]], 1024 ; CHECK-NOUNROLL: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV2]], 1024
; CHECK-NOUNROLL: br i1 [[CMP]], label [[END:%[a-z.]+]], label %for.body ; CHECK-NOUNROLL: br i1 [[CMP]], label [[END:%[a-z.]+]], label %for.body
; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV16:%[a-z.0-9]+]], %for.body ] ; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV16:%[a-z.0-9]+]], %for.body ]
; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1 ; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1 ; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 2
; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1 ; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 3
; CHECK-UNROLL: [[IV4:%[a-z.0-9]+]] = add nuw nsw i32 [[IV3]], 1 ; CHECK-UNROLL: [[IV4:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 4
; CHECK-UNROLL: [[IV5:%[a-z.0-9]+]] = add nuw nsw i32 [[IV4]], 1 ; CHECK-UNROLL: [[IV5:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 5
; CHECK-UNROLL: [[IV6:%[a-z.0-9]+]] = add nuw nsw i32 [[IV5]], 1 ; CHECK-UNROLL: [[IV6:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 6
; CHECK-UNROLL: [[IV7:%[a-z.0-9]+]] = add nuw nsw i32 [[IV6]], 1 ; CHECK-UNROLL: [[IV7:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 7
; CHECK-UNROLL: [[IV8:%[a-z.0-9]+]] = add nuw nsw i32 [[IV7]], 1 ; CHECK-UNROLL: [[IV8:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 8
; CHECK-UNROLL: [[IV9:%[a-z.0-9]+]] = add nuw nsw i32 [[IV8]], 1 ; CHECK-UNROLL: [[IV9:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 9
; CHECK-UNROLL: [[IV10:%[a-z.0-9]+]] = add nuw nsw i32 [[IV9]], 1 ; CHECK-UNROLL: [[IV10:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 10
; CHECK-UNROLL: [[IV11:%[a-z.0-9]+]] = add nuw nsw i32 [[IV10]], 1 ; CHECK-UNROLL: [[IV11:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 11
; CHECK-UNROLL: [[IV12:%[a-z.0-9]+]] = add nuw nsw i32 [[IV11]], 1 ; CHECK-UNROLL: [[IV12:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 12
; CHECK-UNROLL: [[IV13:%[a-z.0-9]+]] = add nuw nsw i32 [[IV12]], 1 ; CHECK-UNROLL: [[IV13:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 13
; CHECK-UNROLL: [[IV14:%[a-z.0-9]+]] = add nuw nsw i32 [[IV13]], 1 ; CHECK-UNROLL: [[IV14:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 14
; CHECK-UNROLL: [[IV15:%[a-z.0-9]+]] = add nuw nsw i32 [[IV14]], 1 ; CHECK-UNROLL: [[IV15:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 15
; CHECK-UNROLL: [[IV16]] = add nuw nsw i32 [[IV15]], 1 ; CHECK-UNROLL: [[IV16]] = add nuw nsw i32 [[IV0]], 16
; CHECK-UNROLL: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV16]], 1024 ; CHECK-UNROLL: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV16]], 1024
; CHECK-UNROLL: br i1 [[CMP]], label [[END:%[a-z.]+]], label %for.body ; CHECK-UNROLL: br i1 [[CMP]], label [[END:%[a-z.]+]], label %for.body
%i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ] %i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %A, i32 %i.08 %arrayidx = getelementptr inbounds i32, ptr %A, i32 %i.08
%0 = load i32, ptr %arrayidx, align 4 %0 = load i32, ptr %arrayidx, align 4
%arrayidx1 = getelementptr inbounds i32, ptr %B, i32 %i.08 %arrayidx1 = getelementptr inbounds i32, ptr %B, i32 %i.08
%1 = load i32, ptr %arrayidx1, align 4 %1 = load i32, ptr %arrayidx1, align 4
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entry: entry:
%cmp8 = icmp eq i32 %N, 0 %cmp8 = icmp eq i32 %N, 0
br i1 %cmp8, label %for.cond.cleanup, label %for.body br i1 %cmp8, label %for.cond.cleanup, label %for.body
; CHECK-LABEL: for.body ; CHECK-LABEL: for.body
for.body: for.body:
; CHECK-NOUNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z.0-9]+]] ], [ [[IV2:%[a-z.0-9]+]], %for.body ] ; CHECK-NOUNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z.0-9]+]] ], [ [[IV2:%[a-z.0-9]+]], %for.body ]
; CHECK-NOUNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1 ; CHECK-NOUNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
; CHECK-NOUNROLL: [[IV2]] = add nuw i32 [[IV1]], 1 ; CHECK-NOUNROLL: [[IV2]] = add nuw i32 [[IV0]], 2
; CHECK-NOUNROLL: br ; CHECK-NOUNROLL: br
; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z.0-9]+]] ], [ [[IV4:%[a-z.0-9]+]], %for.body ] ; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z.0-9]+]] ], [ [[IV4:%[a-z.0-9]+]], %for.body ]
; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1 ; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1 ; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 2
; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1 ; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 3
; CHECK-UNROLL: [[IV4]] = add nuw i32 [[IV3]], 1 ; CHECK-UNROLL: [[IV4]] = add nuw i32 [[IV0]], 4
; CHECK-UNROLL: br ; CHECK-UNROLL: br
; CHECK-UNROLL: for.body.epil: ; CHECK-UNROLL: for.body.epil:
; CHECK-UNROLL: for.body.epil.1: ; CHECK-UNROLL: for.body.epil.1:
; CHECK-UNROLL: for.body.epil.2: ; CHECK-UNROLL: for.body.epil.2:
%i.09 = phi i32 [ %inc, %for.body ], [ 0, %entry ] %i.09 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %A, i32 %i.09 %arrayidx = getelementptr inbounds i32, ptr %A, i32 %i.09
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; CHECK-NOUNROLL: [[IV1]] = add nuw i32 [[IV0]], 1 ; CHECK-NOUNROLL: [[IV1]] = add nuw i32 [[IV0]], 1
; CHECK-NOUNROLL: br ; CHECK-NOUNROLL: br
; CHECK-UNROLL: for.body4.epil: ; CHECK-UNROLL: for.body4.epil:
; CHECK-UNROLL: for.body4.epil.1: ; CHECK-UNROLL: for.body4.epil.1:
; CHECK-UNROLL: for.body4.epil.2: ; CHECK-UNROLL: for.body4.epil.2:
; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z0-9.]+]] ], [ [[IV4:%[a-z.0-9]+]], %for.body4 ] ; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z0-9.]+]] ], [ [[IV4:%[a-z.0-9]+]], %for.body4 ]
; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1 ; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1 ; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 2
; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1 ; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 3
; CHECK-UNROLL: [[IV4]] = add nuw i32 [[IV3]], 1 ; CHECK-UNROLL: [[IV4]] = add nuw i32 [[IV0]], 4
; CHECK-UNROLL: br ; CHECK-UNROLL: br
%w.024 = phi i32 [ 0, %for.body4.lr.ph ], [ %inc, %for.body4 ] %w.024 = phi i32 [ 0, %for.body4.lr.ph ], [ %inc, %for.body4 ]
%add = add i32 %w.024, %mul %add = add i32 %w.024, %mul
%arrayidx = getelementptr inbounds i16, ptr %A, i32 %add %arrayidx = getelementptr inbounds i16, ptr %A, i32 %add
%0 = load i16, ptr %arrayidx, align 2 %0 = load i16, ptr %arrayidx, align 2
%conv = sext i16 %0 to i32 %conv = sext i16 %0 to i32
%arrayidx5 = getelementptr inbounds i16, ptr %B, i32 %w.024 %arrayidx5 = getelementptr inbounds i16, ptr %B, i32 %w.024
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llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll

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; CHECK-NEXT: br i1 [[TOBOOL_EPIL_1]], label [[FOR_INC_EPIL_1:%.*]], label [[IF_THEN_EPIL_1:%.*]] ; CHECK-NEXT: br i1 [[TOBOOL_EPIL_1]], label [[FOR_INC_EPIL_1:%.*]], label [[IF_THEN_EPIL_1:%.*]]
; CHECK: if.then.epil.1: ; CHECK: if.then.epil.1:
; CHECK-NEXT: [[ARRAYIDX1_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_EPIL]] ; CHECK-NEXT: [[ARRAYIDX1_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_EPIL]]
; CHECK-NEXT: [[I1_EPIL_1:%.*]] = load i32, ptr [[ARRAYIDX1_EPIL_1]], align 4 ; CHECK-NEXT: [[I1_EPIL_1:%.*]] = load i32, ptr [[ARRAYIDX1_EPIL_1]], align 4
; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add i32 [[I1_EPIL_1]], [[TEMP_1_EPIL]] ; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add i32 [[I1_EPIL_1]], [[TEMP_1_EPIL]]
; CHECK-NEXT: br label [[FOR_INC_EPIL_1]] ; CHECK-NEXT: br label [[FOR_INC_EPIL_1]]
; CHECK: for.inc.epil.1: ; CHECK: for.inc.epil.1:
; CHECK-NEXT: [[TEMP_1_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], [[IF_THEN_EPIL_1]] ], [ [[TEMP_1_EPIL]], [[FOR_BODY_EPIL_1]] ] ; CHECK-NEXT: [[TEMP_1_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], [[IF_THEN_EPIL_1]] ], [ [[TEMP_1_EPIL]], [[FOR_BODY_EPIL_1]] ]
; CHECK-NEXT: [[INC_EPIL_1:%.*]] = add nuw i32 [[INC_EPIL]], 1 ; CHECK-NEXT: [[INC_EPIL_1:%.*]] = add nuw i32 [[J_010_UNR]], 2
; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]] ; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]]
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_BODY_EPIL_2:%.*]], label [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]] ; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_BODY_EPIL_2:%.*]], label [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]
; CHECK: for.body.epil.2: ; CHECK: for.body.epil.2:
; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_EPIL_1]] ; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_EPIL_1]]
; CHECK-NEXT: [[I_EPIL_2:%.*]] = load i32, ptr [[ARRAYIDX_EPIL_2]], align 4 ; CHECK-NEXT: [[I_EPIL_2:%.*]] = load i32, ptr [[ARRAYIDX_EPIL_2]], align 4
; CHECK-NEXT: [[TOBOOL_EPIL_2:%.*]] = icmp eq i32 [[I_EPIL_2]], 0 ; CHECK-NEXT: [[TOBOOL_EPIL_2:%.*]] = icmp eq i32 [[I_EPIL_2]], 0
; CHECK-NEXT: br i1 [[TOBOOL_EPIL_2]], label [[FOR_INC_EPIL_2:%.*]], label [[IF_THEN_EPIL_2:%.*]] ; CHECK-NEXT: br i1 [[TOBOOL_EPIL_2]], label [[FOR_INC_EPIL_2:%.*]], label [[IF_THEN_EPIL_2:%.*]]
; CHECK: if.then.epil.2: ; CHECK: if.then.epil.2:
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; CHECK: if.then: ; CHECK: if.then:
; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[J_010]] ; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[J_010]]
; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4 ; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[I1]], [[TEMP_09]] ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[I1]], [[TEMP_09]]
; CHECK-NEXT: br label [[FOR_INC]] ; CHECK-NEXT: br label [[FOR_INC]]
; CHECK: for.inc: ; CHECK: for.inc:
; CHECK-NEXT: [[TEMP_1:%.*]] = phi i32 [ [[ADD]], [[IF_THEN]] ], [ [[TEMP_09]], [[FOR_BODY]] ] ; CHECK-NEXT: [[TEMP_1:%.*]] = phi i32 [ [[ADD]], [[IF_THEN]] ], [ [[TEMP_09]], [[FOR_BODY]] ]
; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[J_010]], 1 ; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[J_010]], 1
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i32 [[NITER]], 1
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC]]
; CHECK-NEXT: [[I_1:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4 ; CHECK-NEXT: [[I_1:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
; CHECK-NEXT: [[TOBOOL_1:%.*]] = icmp eq i32 [[I_1]], 0 ; CHECK-NEXT: [[TOBOOL_1:%.*]] = icmp eq i32 [[I_1]], 0
; CHECK-NEXT: br i1 [[TOBOOL_1]], label [[FOR_INC_1:%.*]], label [[IF_THEN_1:%.*]] ; CHECK-NEXT: br i1 [[TOBOOL_1]], label [[FOR_INC_1:%.*]], label [[IF_THEN_1:%.*]]
; CHECK: if.then.1: ; CHECK: if.then.1:
; CHECK-NEXT: [[ARRAYIDX1_1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC]] ; CHECK-NEXT: [[ARRAYIDX1_1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC]]
; CHECK-NEXT: [[I1_1:%.*]] = load i32, ptr [[ARRAYIDX1_1]], align 4 ; CHECK-NEXT: [[I1_1:%.*]] = load i32, ptr [[ARRAYIDX1_1]], align 4
; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[I1_1]], [[TEMP_1]] ; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[I1_1]], [[TEMP_1]]
; CHECK-NEXT: br label [[FOR_INC_1]] ; CHECK-NEXT: br label [[FOR_INC_1]]
; CHECK: for.inc.1: ; CHECK: for.inc.1:
; CHECK-NEXT: [[TEMP_1_1:%.*]] = phi i32 [ [[ADD_1]], [[IF_THEN_1]] ], [ [[TEMP_1]], [[FOR_INC]] ] ; CHECK-NEXT: [[TEMP_1_1:%.*]] = phi i32 [ [[ADD_1]], [[IF_THEN_1]] ], [ [[TEMP_1]], [[FOR_INC]] ]
; CHECK-NEXT: [[INC_1:%.*]] = add nuw nsw i32 [[INC]], 1 ; CHECK-NEXT: [[INC_1:%.*]] = add nuw nsw i32 [[J_010]], 2
; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i32 [[NITER_NEXT]], 1
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_1]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_1]]
; CHECK-NEXT: [[I_2:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4 ; CHECK-NEXT: [[I_2:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
; CHECK-NEXT: [[TOBOOL_2:%.*]] = icmp eq i32 [[I_2]], 0 ; CHECK-NEXT: [[TOBOOL_2:%.*]] = icmp eq i32 [[I_2]], 0
; CHECK-NEXT: br i1 [[TOBOOL_2]], label [[FOR_INC_2:%.*]], label [[IF_THEN_2:%.*]] ; CHECK-NEXT: br i1 [[TOBOOL_2]], label [[FOR_INC_2:%.*]], label [[IF_THEN_2:%.*]]
; CHECK: if.then.2: ; CHECK: if.then.2:
; CHECK-NEXT: [[ARRAYIDX1_2:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_1]] ; CHECK-NEXT: [[ARRAYIDX1_2:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_1]]
; CHECK-NEXT: [[I1_2:%.*]] = load i32, ptr [[ARRAYIDX1_2]], align 4 ; CHECK-NEXT: [[I1_2:%.*]] = load i32, ptr [[ARRAYIDX1_2]], align 4
; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[I1_2]], [[TEMP_1_1]] ; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[I1_2]], [[TEMP_1_1]]
; CHECK-NEXT: br label [[FOR_INC_2]] ; CHECK-NEXT: br label [[FOR_INC_2]]
; CHECK: for.inc.2: ; CHECK: for.inc.2:
; CHECK-NEXT: [[TEMP_1_2:%.*]] = phi i32 [ [[ADD_2]], [[IF_THEN_2]] ], [ [[TEMP_1_1]], [[FOR_INC_1]] ] ; CHECK-NEXT: [[TEMP_1_2:%.*]] = phi i32 [ [[ADD_2]], [[IF_THEN_2]] ], [ [[TEMP_1_1]], [[FOR_INC_1]] ]
; CHECK-NEXT: [[INC_2:%.*]] = add nuw nsw i32 [[INC_1]], 1 ; CHECK-NEXT: [[INC_2:%.*]] = add nuw nsw i32 [[J_010]], 3
; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i32 [[NITER_NEXT_1]], 1
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_2]] ; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_2]]
; CHECK-NEXT: [[I_3:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4 ; CHECK-NEXT: [[I_3:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
; CHECK-NEXT: [[TOBOOL_3:%.*]] = icmp eq i32 [[I_3]], 0 ; CHECK-NEXT: [[TOBOOL_3:%.*]] = icmp eq i32 [[I_3]], 0
; CHECK-NEXT: br i1 [[TOBOOL_3]], label [[FOR_INC_3]], label [[IF_THEN_3:%.*]] ; CHECK-NEXT: br i1 [[TOBOOL_3]], label [[FOR_INC_3]], label [[IF_THEN_3:%.*]]
; CHECK: if.then.3: ; CHECK: if.then.3:
; CHECK-NEXT: [[ARRAYIDX1_3:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_2]] ; CHECK-NEXT: [[ARRAYIDX1_3:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_2]]
; CHECK-NEXT: [[I1_3:%.*]] = load i32, ptr [[ARRAYIDX1_3]], align 4 ; CHECK-NEXT: [[I1_3:%.*]] = load i32, ptr [[ARRAYIDX1_3]], align 4
; CHECK-NEXT: [[ADD_3:%.*]] = add i32 [[I1_3]], [[TEMP_1_2]] ; CHECK-NEXT: [[ADD_3:%.*]] = add i32 [[I1_3]], [[TEMP_1_2]]
; CHECK-NEXT: br label [[FOR_INC_3]] ; CHECK-NEXT: br label [[FOR_INC_3]]
; CHECK: for.inc.3: ; CHECK: for.inc.3:
; CHECK-NEXT: [[TEMP_1_3]] = phi i32 [ [[ADD_3]], [[IF_THEN_3]] ], [ [[TEMP_1_2]], [[FOR_INC_2]] ] ; CHECK-NEXT: [[TEMP_1_3]] = phi i32 [ [[ADD_3]], [[IF_THEN_3]] ], [ [[TEMP_1_2]], [[FOR_INC_2]] ]
; CHECK-NEXT: [[INC_3]] = add nuw i32 [[INC_2]], 1 ; CHECK-NEXT: [[INC_3]] = add nuw i32 [[J_010]], 4
; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER_NEXT_2]], 1 ; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER]], 4
; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i32 [[NITER_NEXT_3]], [[UNROLL_ITER]] ; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i32 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA_LOOPEXIT]], label [[FOR_BODY]] ; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA_LOOPEXIT]], label [[FOR_BODY]]
; ;
entry: entry:
%cmp8 = icmp eq i32 %MaxJ, 0 %cmp8 = icmp eq i32 %MaxJ, 0
br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
for.body.preheader: ; preds = %entry for.body.preheader: ; preds = %entry
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; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ugt i32 [[I_1]], 65535 ; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ugt i32 [[I_1]], 65535
; CHECK-NEXT: br i1 [[CMP1_1]], label [[CLEANUP_LOOPEXIT]], label [[IF_END_1:%.*]] ; CHECK-NEXT: br i1 [[CMP1_1]], label [[CLEANUP_LOOPEXIT]], label [[IF_END_1:%.*]]
; CHECK: if.end.1: ; CHECK: if.end.1:
; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC]] ; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC]]
; CHECK-NEXT: [[I1_1:%.*]] = load i32, ptr [[ARRAYIDX2_1]], align 4 ; CHECK-NEXT: [[I1_1:%.*]] = load i32, ptr [[ARRAYIDX2_1]], align 4
; CHECK-NEXT: [[TOBOOL_1:%.*]] = icmp eq i32 [[I1_1]], 0 ; CHECK-NEXT: [[TOBOOL_1:%.*]] = icmp eq i32 [[I1_1]], 0
; CHECK-NEXT: [[ADD_1:%.*]] = select i1 [[TOBOOL_1]], i32 0, i32 [[I_1]] ; CHECK-NEXT: [[ADD_1:%.*]] = select i1 [[TOBOOL_1]], i32 0, i32 [[I_1]]
; CHECK-NEXT: [[TEMP_0_ADD_1:%.*]] = add i32 [[ADD_1]], [[TEMP_0_ADD]] ; CHECK-NEXT: [[TEMP_0_ADD_1:%.*]] = add i32 [[ADD_1]], [[TEMP_0_ADD]]
; CHECK-NEXT: [[INC_1:%.*]] = add nuw nsw i32 [[INC]], 1 ; CHECK-NEXT: [[INC_1:%.*]] = add nuw nsw i32 [[J_016]], 2
; CHECK-NEXT: [[CMP_1:%.*]] = icmp ult i32 [[INC_1]], [[MAXJ]] ; CHECK-NEXT: [[CMP_1:%.*]] = icmp ult i32 [[INC_1]], [[MAXJ]]
; CHECK-NEXT: br i1 [[CMP_1]], label [[FOR_BODY_2:%.*]], label [[CLEANUP_LOOPEXIT]] ; CHECK-NEXT: br i1 [[CMP_1]], label [[FOR_BODY_2:%.*]], label [[CLEANUP_LOOPEXIT]]
; CHECK: for.body.2: ; CHECK: for.body.2:
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_1]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_1]]
; CHECK-NEXT: [[I_2:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4 ; CHECK-NEXT: [[I_2:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ugt i32 [[I_2]], 65535 ; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ugt i32 [[I_2]], 65535
; CHECK-NEXT: br i1 [[CMP1_2]], label [[CLEANUP_LOOPEXIT]], label [[IF_END_2:%.*]] ; CHECK-NEXT: br i1 [[CMP1_2]], label [[CLEANUP_LOOPEXIT]], label [[IF_END_2:%.*]]
; CHECK: if.end.2: ; CHECK: if.end.2:
; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_1]] ; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_1]]
; CHECK-NEXT: [[I1_2:%.*]] = load i32, ptr [[ARRAYIDX2_2]], align 4 ; CHECK-NEXT: [[I1_2:%.*]] = load i32, ptr [[ARRAYIDX2_2]], align 4
; CHECK-NEXT: [[TOBOOL_2:%.*]] = icmp eq i32 [[I1_2]], 0 ; CHECK-NEXT: [[TOBOOL_2:%.*]] = icmp eq i32 [[I1_2]], 0
; CHECK-NEXT: [[ADD_2:%.*]] = select i1 [[TOBOOL_2]], i32 0, i32 [[I_2]] ; CHECK-NEXT: [[ADD_2:%.*]] = select i1 [[TOBOOL_2]], i32 0, i32 [[I_2]]
; CHECK-NEXT: [[TEMP_0_ADD_2:%.*]] = add i32 [[ADD_2]], [[TEMP_0_ADD_1]] ; CHECK-NEXT: [[TEMP_0_ADD_2:%.*]] = add i32 [[ADD_2]], [[TEMP_0_ADD_1]]
; CHECK-NEXT: [[INC_2:%.*]] = add nuw nsw i32 [[INC_1]], 1 ; CHECK-NEXT: [[INC_2:%.*]] = add nuw nsw i32 [[J_016]], 3
; CHECK-NEXT: [[CMP_2:%.*]] = icmp ult i32 [[INC_2]], [[MAXJ]] ; CHECK-NEXT: [[CMP_2:%.*]] = icmp ult i32 [[INC_2]], [[MAXJ]]
; CHECK-NEXT: br i1 [[CMP_2]], label [[FOR_BODY_3:%.*]], label [[CLEANUP_LOOPEXIT]] ; CHECK-NEXT: br i1 [[CMP_2]], label [[FOR_BODY_3:%.*]], label [[CLEANUP_LOOPEXIT]]
; CHECK: for.body.3: ; CHECK: for.body.3:
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_2]] ; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_2]]
; CHECK-NEXT: [[I_3:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4 ; CHECK-NEXT: [[I_3:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ugt i32 [[I_3]], 65535 ; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ugt i32 [[I_3]], 65535
; CHECK-NEXT: br i1 [[CMP1_3]], label [[CLEANUP_LOOPEXIT]], label [[IF_END_3]] ; CHECK-NEXT: br i1 [[CMP1_3]], label [[CLEANUP_LOOPEXIT]], label [[IF_END_3]]
; CHECK: if.end.3: ; CHECK: if.end.3:
; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_2]] ; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_2]]
; CHECK-NEXT: [[I1_3:%.*]] = load i32, ptr [[ARRAYIDX2_3]], align 4 ; CHECK-NEXT: [[I1_3:%.*]] = load i32, ptr [[ARRAYIDX2_3]], align 4
; CHECK-NEXT: [[TOBOOL_3:%.*]] = icmp eq i32 [[I1_3]], 0 ; CHECK-NEXT: [[TOBOOL_3:%.*]] = icmp eq i32 [[I1_3]], 0
; CHECK-NEXT: [[ADD_3:%.*]] = select i1 [[TOBOOL_3]], i32 0, i32 [[I_3]] ; CHECK-NEXT: [[ADD_3:%.*]] = select i1 [[TOBOOL_3]], i32 0, i32 [[I_3]]
; CHECK-NEXT: [[TEMP_0_ADD_3]] = add i32 [[ADD_3]], [[TEMP_0_ADD_2]] ; CHECK-NEXT: [[TEMP_0_ADD_3]] = add i32 [[ADD_3]], [[TEMP_0_ADD_2]]
; CHECK-NEXT: [[INC_3]] = add nuw i32 [[INC_2]], 1 ; CHECK-NEXT: [[INC_3]] = add nuw i32 [[J_016]], 4
; CHECK-NEXT: [[CMP_3:%.*]] = icmp ult i32 [[INC_3]], [[MAXJ]] ; CHECK-NEXT: [[CMP_3:%.*]] = icmp ult i32 [[INC_3]], [[MAXJ]]
; CHECK-NEXT: br i1 [[CMP_3]], label [[FOR_BODY]], label [[CLEANUP_LOOPEXIT]] ; CHECK-NEXT: br i1 [[CMP_3]], label [[FOR_BODY]], label [[CLEANUP_LOOPEXIT]]
; CHECK: cleanup.loopexit: ; CHECK: cleanup.loopexit:
; CHECK-NEXT: [[TEMP_0_LCSSA_PH:%.*]] = phi i32 [ [[TEMP_0_ADD]], [[IF_END]] ], [ [[TEMP_015]], [[FOR_BODY]] ], [ [[TEMP_0_ADD]], [[FOR_BODY_1]] ], [ [[TEMP_0_ADD_1]], [[IF_END_1]] ], [ [[TEMP_0_ADD_1]], [[FOR_BODY_2]] ], [ [[TEMP_0_ADD_2]], [[IF_END_2]] ], [ [[TEMP_0_ADD_2]], [[FOR_BODY_3]] ], [ [[TEMP_0_ADD_3]], [[IF_END_3]] ] ; CHECK-NEXT: [[TEMP_0_LCSSA_PH:%.*]] = phi i32 [ [[TEMP_0_ADD]], [[IF_END]] ], [ [[TEMP_015]], [[FOR_BODY]] ], [ [[TEMP_0_ADD]], [[FOR_BODY_1]] ], [ [[TEMP_0_ADD_1]], [[IF_END_1]] ], [ [[TEMP_0_ADD_1]], [[FOR_BODY_2]] ], [ [[TEMP_0_ADD_2]], [[IF_END_2]] ], [ [[TEMP_0_ADD_2]], [[FOR_BODY_3]] ], [ [[TEMP_0_ADD_3]], [[IF_END_3]] ]
; CHECK-NEXT: br label [[CLEANUP]] ; CHECK-NEXT: br label [[CLEANUP]]
; CHECK: cleanup: ; CHECK: cleanup:
; CHECK-NEXT: [[TEMP_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TEMP_0_LCSSA_PH]], [[CLEANUP_LOOPEXIT]] ] ; CHECK-NEXT: [[TEMP_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TEMP_0_LCSSA_PH]], [[CLEANUP_LOOPEXIT]] ]
; CHECK-NEXT: store i32 [[TEMP_0_LCSSA]], ptr [[OUTPUT:%.*]], align 4 ; CHECK-NEXT: store i32 [[TEMP_0_LCSSA]], ptr [[OUTPUT:%.*]], align 4
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; CHECK-NEXT: [[SUB13_EPIL_1:%.*]] = sub i32 [[TEMP_1_EPIL]], [[I3_EPIL_1]] ; CHECK-NEXT: [[SUB13_EPIL_1:%.*]] = sub i32 [[TEMP_1_EPIL]], [[I3_EPIL_1]]
; CHECK-NEXT: br label [[FOR_INC_EPIL_1:%.*]] ; CHECK-NEXT: br label [[FOR_INC_EPIL_1:%.*]]
; CHECK: if.then.epil.1: ; CHECK: if.then.epil.1:
; CHECK-NEXT: [[COND_EPIL_1:%.*]] = zext i1 [[CMP4_EPIL_1]] to i32 ; CHECK-NEXT: [[COND_EPIL_1:%.*]] = zext i1 [[CMP4_EPIL_1]] to i32
; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add i32 [[TEMP_1_EPIL]], [[COND_EPIL_1]] ; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add i32 [[TEMP_1_EPIL]], [[COND_EPIL_1]]
; CHECK-NEXT: br label [[FOR_INC_EPIL_1]] ; CHECK-NEXT: br label [[FOR_INC_EPIL_1]]
; CHECK: for.inc.epil.1: ; CHECK: for.inc.epil.1:
; CHECK-NEXT: [[TEMP_1_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], [[IF_THEN_EPIL_1]] ], [ [[SUB13_EPIL_1]], [[IF_ELSE_EPIL_1]] ] ; CHECK-NEXT: [[TEMP_1_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], [[IF_THEN_EPIL_1]] ], [ [[SUB13_EPIL_1]], [[IF_ELSE_EPIL_1]] ]
; CHECK-NEXT: [[INC_EPIL_1:%.*]] = add nuw i32 [[INC_EPIL]], 1 ; CHECK-NEXT: [[INC_EPIL_1:%.*]] = add nuw i32 [[J_027_UNR]], 2
; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]] ; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]]
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_BODY_EPIL_2:%.*]], label [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]] ; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_BODY_EPIL_2:%.*]], label [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]
; CHECK: for.body.epil.2: ; CHECK: for.body.epil.2:
; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_EPIL_1]] ; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_EPIL_1]]
; CHECK-NEXT: [[I1_EPIL_2:%.*]] = load i32, ptr [[ARRAYIDX_EPIL_2]], align 4 ; CHECK-NEXT: [[I1_EPIL_2:%.*]] = load i32, ptr [[ARRAYIDX_EPIL_2]], align 4
; CHECK-NEXT: [[CMP1_EPIL_2:%.*]] = icmp ugt i32 [[I1_EPIL_2]], 65535 ; CHECK-NEXT: [[CMP1_EPIL_2:%.*]] = icmp ugt i32 [[I1_EPIL_2]], 65535
; CHECK-NEXT: [[ARRAYIDX2_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_EPIL_1]] ; CHECK-NEXT: [[ARRAYIDX2_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_EPIL_1]]
; CHECK-NEXT: [[I2_EPIL_2:%.*]] = load i32, ptr [[ARRAYIDX2_EPIL_2]], align 4 ; CHECK-NEXT: [[I2_EPIL_2:%.*]] = load i32, ptr [[ARRAYIDX2_EPIL_2]], align 4
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; CHECK-NEXT: [[SUB10_SINK:%.*]] = add i32 [[J_027]], [[SUB]] ; CHECK-NEXT: [[SUB10_SINK:%.*]] = add i32 [[J_027]], [[SUB]]
; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[SUB10_SINK]] ; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[SUB10_SINK]]
; CHECK-NEXT: [[I3:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 ; CHECK-NEXT: [[I3:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4
; CHECK-NEXT: [[SUB13:%.*]] = sub i32 [[TEMP_026]], [[I3]] ; CHECK-NEXT: [[SUB13:%.*]] = sub i32 [[TEMP_026]], [[I3]]
; CHECK-NEXT: br label [[FOR_INC]] ; CHECK-NEXT: br label [[FOR_INC]]
; CHECK: for.inc: ; CHECK: for.inc:
; CHECK-NEXT: [[TEMP_1:%.*]] = phi i32 [ [[ADD]], [[IF_THEN]] ], [ [[SUB13]], [[IF_ELSE]] ] ; CHECK-NEXT: [[TEMP_1:%.*]] = phi i32 [ [[ADD]], [[IF_THEN]] ], [ [[SUB13]], [[IF_ELSE]] ]
; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[J_027]], 1 ; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[J_027]], 1
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i32 [[NITER]], 1
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC]]
; CHECK-NEXT: [[I1_1:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4 ; CHECK-NEXT: [[I1_1:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ugt i32 [[I1_1]], 65535 ; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ugt i32 [[I1_1]], 65535
; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC]] ; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC]]
; CHECK-NEXT: [[I2_1:%.*]] = load i32, ptr [[ARRAYIDX2_1]], align 4 ; CHECK-NEXT: [[I2_1:%.*]] = load i32, ptr [[ARRAYIDX2_1]], align 4
; CHECK-NEXT: [[CMP4_1:%.*]] = icmp ugt i32 [[I2_1]], [[I2]] ; CHECK-NEXT: [[CMP4_1:%.*]] = icmp ugt i32 [[I2_1]], [[I2]]
; CHECK-NEXT: br i1 [[CMP1_1]], label [[IF_THEN_1:%.*]], label [[IF_ELSE_1:%.*]] ; CHECK-NEXT: br i1 [[CMP1_1]], label [[IF_THEN_1:%.*]], label [[IF_ELSE_1:%.*]]
; CHECK: if.else.1: ; CHECK: if.else.1:
; CHECK-NEXT: [[NOT_CMP4_1:%.*]] = xor i1 [[CMP4_1]], true ; CHECK-NEXT: [[NOT_CMP4_1:%.*]] = xor i1 [[CMP4_1]], true
; CHECK-NEXT: [[SUB_1:%.*]] = sext i1 [[NOT_CMP4_1]] to i32 ; CHECK-NEXT: [[SUB_1:%.*]] = sext i1 [[NOT_CMP4_1]] to i32
; CHECK-NEXT: [[SUB10_SINK_1:%.*]] = add i32 [[INC]], [[SUB_1]] ; CHECK-NEXT: [[SUB10_SINK_1:%.*]] = add i32 [[INC]], [[SUB_1]]
; CHECK-NEXT: [[ARRAYIDX11_1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[SUB10_SINK_1]] ; CHECK-NEXT: [[ARRAYIDX11_1:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[SUB10_SINK_1]]
; CHECK-NEXT: [[I3_1:%.*]] = load i32, ptr [[ARRAYIDX11_1]], align 4 ; CHECK-NEXT: [[I3_1:%.*]] = load i32, ptr [[ARRAYIDX11_1]], align 4
; CHECK-NEXT: [[SUB13_1:%.*]] = sub i32 [[TEMP_1]], [[I3_1]] ; CHECK-NEXT: [[SUB13_1:%.*]] = sub i32 [[TEMP_1]], [[I3_1]]
; CHECK-NEXT: br label [[FOR_INC_1:%.*]] ; CHECK-NEXT: br label [[FOR_INC_1:%.*]]
; CHECK: if.then.1: ; CHECK: if.then.1:
; CHECK-NEXT: [[COND_1:%.*]] = zext i1 [[CMP4_1]] to i32 ; CHECK-NEXT: [[COND_1:%.*]] = zext i1 [[CMP4_1]] to i32
; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[TEMP_1]], [[COND_1]] ; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[TEMP_1]], [[COND_1]]
; CHECK-NEXT: br label [[FOR_INC_1]] ; CHECK-NEXT: br label [[FOR_INC_1]]
; CHECK: for.inc.1: ; CHECK: for.inc.1:
; CHECK-NEXT: [[TEMP_1_1:%.*]] = phi i32 [ [[ADD_1]], [[IF_THEN_1]] ], [ [[SUB13_1]], [[IF_ELSE_1]] ] ; CHECK-NEXT: [[TEMP_1_1:%.*]] = phi i32 [ [[ADD_1]], [[IF_THEN_1]] ], [ [[SUB13_1]], [[IF_ELSE_1]] ]
; CHECK-NEXT: [[INC_1:%.*]] = add nuw nsw i32 [[INC]], 1 ; CHECK-NEXT: [[INC_1:%.*]] = add nuw nsw i32 [[J_027]], 2
; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i32 [[NITER_NEXT]], 1
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_1]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_1]]
; CHECK-NEXT: [[I1_2:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4 ; CHECK-NEXT: [[I1_2:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ugt i32 [[I1_2]], 65535 ; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ugt i32 [[I1_2]], 65535
; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_1]] ; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_1]]
; CHECK-NEXT: [[I2_2:%.*]] = load i32, ptr [[ARRAYIDX2_2]], align 4 ; CHECK-NEXT: [[I2_2:%.*]] = load i32, ptr [[ARRAYIDX2_2]], align 4
; CHECK-NEXT: [[CMP4_2:%.*]] = icmp ugt i32 [[I2_2]], [[I2_1]] ; CHECK-NEXT: [[CMP4_2:%.*]] = icmp ugt i32 [[I2_2]], [[I2_1]]
; CHECK-NEXT: br i1 [[CMP1_2]], label [[IF_THEN_2:%.*]], label [[IF_ELSE_2:%.*]] ; CHECK-NEXT: br i1 [[CMP1_2]], label [[IF_THEN_2:%.*]], label [[IF_ELSE_2:%.*]]
; CHECK: if.else.2: ; CHECK: if.else.2:
; CHECK-NEXT: [[NOT_CMP4_2:%.*]] = xor i1 [[CMP4_2]], true ; CHECK-NEXT: [[NOT_CMP4_2:%.*]] = xor i1 [[CMP4_2]], true
; CHECK-NEXT: [[SUB_2:%.*]] = sext i1 [[NOT_CMP4_2]] to i32 ; CHECK-NEXT: [[SUB_2:%.*]] = sext i1 [[NOT_CMP4_2]] to i32
; CHECK-NEXT: [[SUB10_SINK_2:%.*]] = add i32 [[INC_1]], [[SUB_2]] ; CHECK-NEXT: [[SUB10_SINK_2:%.*]] = add i32 [[INC_1]], [[SUB_2]]
; CHECK-NEXT: [[ARRAYIDX11_2:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[SUB10_SINK_2]] ; CHECK-NEXT: [[ARRAYIDX11_2:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[SUB10_SINK_2]]
; CHECK-NEXT: [[I3_2:%.*]] = load i32, ptr [[ARRAYIDX11_2]], align 4 ; CHECK-NEXT: [[I3_2:%.*]] = load i32, ptr [[ARRAYIDX11_2]], align 4
; CHECK-NEXT: [[SUB13_2:%.*]] = sub i32 [[TEMP_1_1]], [[I3_2]] ; CHECK-NEXT: [[SUB13_2:%.*]] = sub i32 [[TEMP_1_1]], [[I3_2]]
; CHECK-NEXT: br label [[FOR_INC_2:%.*]] ; CHECK-NEXT: br label [[FOR_INC_2:%.*]]
; CHECK: if.then.2: ; CHECK: if.then.2:
; CHECK-NEXT: [[COND_2:%.*]] = zext i1 [[CMP4_2]] to i32 ; CHECK-NEXT: [[COND_2:%.*]] = zext i1 [[CMP4_2]] to i32
; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[TEMP_1_1]], [[COND_2]] ; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[TEMP_1_1]], [[COND_2]]
; CHECK-NEXT: br label [[FOR_INC_2]] ; CHECK-NEXT: br label [[FOR_INC_2]]
; CHECK: for.inc.2: ; CHECK: for.inc.2:
; CHECK-NEXT: [[TEMP_1_2:%.*]] = phi i32 [ [[ADD_2]], [[IF_THEN_2]] ], [ [[SUB13_2]], [[IF_ELSE_2]] ] ; CHECK-NEXT: [[TEMP_1_2:%.*]] = phi i32 [ [[ADD_2]], [[IF_THEN_2]] ], [ [[SUB13_2]], [[IF_ELSE_2]] ]
; CHECK-NEXT: [[INC_2:%.*]] = add nuw i32 [[INC_1]], 1 ; CHECK-NEXT: [[INC_2:%.*]] = add nuw i32 [[J_027]], 3
; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i32 [[NITER_NEXT_1]], 1
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_2]] ; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[CONDITION]], i32 [[INC_2]]
; CHECK-NEXT: [[I1_3:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4 ; CHECK-NEXT: [[I1_3:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ugt i32 [[I1_3]], 65535 ; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ugt i32 [[I1_3]], 65535
; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_2]] ; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[INC_2]]
; CHECK-NEXT: [[I2_3]] = load i32, ptr [[ARRAYIDX2_3]], align 4 ; CHECK-NEXT: [[I2_3]] = load i32, ptr [[ARRAYIDX2_3]], align 4
; CHECK-NEXT: [[CMP4_3:%.*]] = icmp ugt i32 [[I2_3]], [[I2_2]] ; CHECK-NEXT: [[CMP4_3:%.*]] = icmp ugt i32 [[I2_3]], [[I2_2]]
; CHECK-NEXT: br i1 [[CMP1_3]], label [[IF_THEN_3:%.*]], label [[IF_ELSE_3:%.*]] ; CHECK-NEXT: br i1 [[CMP1_3]], label [[IF_THEN_3:%.*]], label [[IF_ELSE_3:%.*]]
; CHECK: if.else.3: ; CHECK: if.else.3:
; CHECK-NEXT: [[NOT_CMP4_3:%.*]] = xor i1 [[CMP4_3]], true ; CHECK-NEXT: [[NOT_CMP4_3:%.*]] = xor i1 [[CMP4_3]], true
; CHECK-NEXT: [[SUB_3:%.*]] = sext i1 [[NOT_CMP4_3]] to i32 ; CHECK-NEXT: [[SUB_3:%.*]] = sext i1 [[NOT_CMP4_3]] to i32
; CHECK-NEXT: [[SUB10_SINK_3:%.*]] = add i32 [[INC_2]], [[SUB_3]] ; CHECK-NEXT: [[SUB10_SINK_3:%.*]] = add i32 [[INC_2]], [[SUB_3]]
; CHECK-NEXT: [[ARRAYIDX11_3:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[SUB10_SINK_3]] ; CHECK-NEXT: [[ARRAYIDX11_3:%.*]] = getelementptr inbounds i32, ptr [[INPUT]], i32 [[SUB10_SINK_3]]
; CHECK-NEXT: [[I3_3:%.*]] = load i32, ptr [[ARRAYIDX11_3]], align 4 ; CHECK-NEXT: [[I3_3:%.*]] = load i32, ptr [[ARRAYIDX11_3]], align 4
; CHECK-NEXT: [[SUB13_3:%.*]] = sub i32 [[TEMP_1_2]], [[I3_3]] ; CHECK-NEXT: [[SUB13_3:%.*]] = sub i32 [[TEMP_1_2]], [[I3_3]]
; CHECK-NEXT: br label [[FOR_INC_3]] ; CHECK-NEXT: br label [[FOR_INC_3]]
; CHECK: if.then.3: ; CHECK: if.then.3:
; CHECK-NEXT: [[COND_3:%.*]] = zext i1 [[CMP4_3]] to i32 ; CHECK-NEXT: [[COND_3:%.*]] = zext i1 [[CMP4_3]] to i32
; CHECK-NEXT: [[ADD_3:%.*]] = add i32 [[TEMP_1_2]], [[COND_3]] ; CHECK-NEXT: [[ADD_3:%.*]] = add i32 [[TEMP_1_2]], [[COND_3]]
; CHECK-NEXT: br label [[FOR_INC_3]] ; CHECK-NEXT: br label [[FOR_INC_3]]
; CHECK: for.inc.3: ; CHECK: for.inc.3:
; CHECK-NEXT: [[TEMP_1_3]] = phi i32 [ [[ADD_3]], [[IF_THEN_3]] ], [ [[SUB13_3]], [[IF_ELSE_3]] ] ; CHECK-NEXT: [[TEMP_1_3]] = phi i32 [ [[ADD_3]], [[IF_THEN_3]] ], [ [[SUB13_3]], [[IF_ELSE_3]] ]
; CHECK-NEXT: [[INC_3]] = add nuw nsw i32 [[INC_2]], 1 ; CHECK-NEXT: [[INC_3]] = add nuw i32 [[J_027]], 4
; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER_NEXT_2]], 1 ; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER]], 4
; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i32 [[NITER_NEXT_3]], [[UNROLL_ITER]] ; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i32 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA_LOOPEXIT]], label [[FOR_BODY]] ; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA_LOOPEXIT]], label [[FOR_BODY]]
; ;
entry: entry:
%cmp25 = icmp ugt i32 %MaxJ, 1 %cmp25 = icmp ugt i32 %MaxJ, 1
br i1 %cmp25, label %for.body.lr.ph, label %for.cond.cleanup br i1 %cmp25, label %for.body.lr.ph, label %for.cond.cleanup
for.body.lr.ph: ; preds = %entry for.body.lr.ph: ; preds = %entry
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llvm/test/Transforms/LoopUnroll/PowerPC/p7-unrolling.ll

; RUN: opt < %s -S -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -passes=loop-unroll | FileCheck %s ; RUN: opt < %s -S -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -passes=loop-unroll | FileCheck %s
define void @unroll_default() nounwind { define void @unroll_default() nounwind {
entry: entry:
br label %loop br label %loop
loop: loop:
%iv = phi i32 [ 0, %entry ], [ %inc, %loop ] %iv = phi i32 [ 0, %entry ], [ %inc, %loop ]
%inc = add i32 %iv, 1 %inc = add i32 %iv, 1
%exitcnd = icmp uge i32 %inc, 1024 %exitcnd = icmp uge i32 %inc, 1024
br i1 %exitcnd, label %exit, label %loop br i1 %exitcnd, label %exit, label %loop
exit: exit:
ret void ret void
} }
; CHECK-LABEL: @unroll_default ; CHECK-LABEL: @unroll_default
; CHECK: add ; CHECK: add{{.*}}, 32
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: add
; CHECK-NEXT: icmp ; CHECK-NEXT: icmp

llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll

Show All 34 Lines
; CHECK-NEXT: [[TMP4:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND12]] ; CHECK-NEXT: [[TMP4:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND12]]
; CHECK-NEXT: [[TMP5:%.*]] = and <16 x i32> [[TMP4]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[TMP5:%.*]] = and <16 x i32> [[TMP4]], [[BROADCAST_SPLAT]]
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <16 x i32> [[TMP5]], zeroinitializer ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <16 x i32> [[TMP5]], zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[TMP6]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49> ; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[TMP6]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49>
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[S:%.*]], i64 [[INDEX]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[S:%.*]], i64 [[INDEX]]
; CHECK-NEXT: store <16 x i8> [[TMP7]], ptr [[TMP8]], align 1 ; CHECK-NEXT: store <16 x i8> [[TMP7]], ptr [[TMP8]], align 1
; CHECK-NEXT: [[INDEX_NEXT:%.*]] = add nuw nsw i64 [[INDEX]], 16 ; CHECK-NEXT: [[INDEX_NEXT:%.*]] = add nuw nsw i64 [[INDEX]], 16
; CHECK-NEXT: [[VEC_IND_NEXT13:%.*]] = add <16 x i32> [[VEC_IND12]], <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> ; CHECK-NEXT: [[VEC_IND_NEXT13:%.*]] = add <16 x i32> [[VEC_IND12]], <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1
; CHECK-NEXT: [[TMP9:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND_NEXT13]] ; CHECK-NEXT: [[TMP9:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND_NEXT13]]
; CHECK-NEXT: [[TMP10:%.*]] = and <16 x i32> [[TMP9]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[TMP10:%.*]] = and <16 x i32> [[TMP9]], [[BROADCAST_SPLAT]]
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq <16 x i32> [[TMP10]], zeroinitializer ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq <16 x i32> [[TMP10]], zeroinitializer
; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49> ; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49>
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDEX_NEXT]] ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDEX_NEXT]]
; CHECK-NEXT: store <16 x i8> [[TMP12]], ptr [[TMP13]], align 1 ; CHECK-NEXT: store <16 x i8> [[TMP12]], ptr [[TMP13]], align 1
; CHECK-NEXT: [[INDEX_NEXT_1]] = add i64 [[INDEX_NEXT]], 16 ; CHECK-NEXT: [[INDEX_NEXT_1]] = add i64 [[INDEX]], 32
; CHECK-NEXT: [[VEC_IND_NEXT13_1]] = add <16 x i32> [[VEC_IND_NEXT13]], <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> ; CHECK-NEXT: [[VEC_IND_NEXT13_1]] = add <16 x i32> [[VEC_IND12]], <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER_NEXT]], 1 ; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]] ; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT:%.*]], label [[VECTOR_BODY]] ; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT:%.*]], label [[VECTOR_BODY]]
; CHECK: middle.block.unr-lcssa.loopexit: ; CHECK: middle.block.unr-lcssa.loopexit:
; CHECK-NEXT: [[INDEX_UNR_PH:%.*]] = phi i64 [ [[INDEX_NEXT_1]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[INDEX_UNR_PH:%.*]] = phi i64 [ [[INDEX_NEXT_1]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_IND12_UNR_PH:%.*]] = phi <16 x i32> [ [[VEC_IND_NEXT13_1]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND12_UNR_PH:%.*]] = phi <16 x i32> [ [[VEC_IND_NEXT13_1]], [[VECTOR_BODY]] ]
; CHECK-NEXT: br label [[MIDDLE_BLOCK_UNR_LCSSA]] ; CHECK-NEXT: br label [[MIDDLE_BLOCK_UNR_LCSSA]]
; CHECK: middle.block.unr-lcssa: ; CHECK: middle.block.unr-lcssa:
; CHECK-NEXT: [[INDEX_UNR:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_UNR_PH]], [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT]] ] ; CHECK-NEXT: [[INDEX_UNR:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_UNR_PH]], [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT]] ]
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; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[TMP25:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32 ; CHECK-NEXT: [[TMP25:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
; CHECK-NEXT: [[SHL_1:%.*]] = shl i32 1, [[TMP25]] ; CHECK-NEXT: [[SHL_1:%.*]] = shl i32 1, [[TMP25]]
; CHECK-NEXT: [[AND_1:%.*]] = and i32 [[SHL_1]], [[X]] ; CHECK-NEXT: [[AND_1:%.*]] = and i32 [[SHL_1]], [[X]]
; CHECK-NEXT: [[TOBOOL_1:%.*]] = icmp eq i32 [[AND_1]], 0 ; CHECK-NEXT: [[TOBOOL_1:%.*]] = icmp eq i32 [[AND_1]], 0
; CHECK-NEXT: [[CONV_1:%.*]] = select i1 [[TOBOOL_1]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_1:%.*]] = select i1 [[TOBOOL_1]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT]]
; CHECK-NEXT: store i8 [[CONV_1]], ptr [[ARRAYIDX_1]], align 1 ; CHECK-NEXT: store i8 [[CONV_1]], ptr [[ARRAYIDX_1]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[INDVARS_IV_NEXT_1]] to i32 ; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[INDVARS_IV_NEXT_1]] to i32
; CHECK-NEXT: [[SHL_2:%.*]] = shl i32 1, [[TMP26]] ; CHECK-NEXT: [[SHL_2:%.*]] = shl i32 1, [[TMP26]]
; CHECK-NEXT: [[AND_2:%.*]] = and i32 [[SHL_2]], [[X]] ; CHECK-NEXT: [[AND_2:%.*]] = and i32 [[SHL_2]], [[X]]
; CHECK-NEXT: [[TOBOOL_2:%.*]] = icmp eq i32 [[AND_2]], 0 ; CHECK-NEXT: [[TOBOOL_2:%.*]] = icmp eq i32 [[AND_2]], 0
; CHECK-NEXT: [[CONV_2:%.*]] = select i1 [[TOBOOL_2]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_2:%.*]] = select i1 [[TOBOOL_2]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_1]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_1]]
; CHECK-NEXT: store i8 [[CONV_2]], ptr [[ARRAYIDX_2]], align 1 ; CHECK-NEXT: store i8 [[CONV_2]], ptr [[ARRAYIDX_2]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 3
; CHECK-NEXT: [[TMP27:%.*]] = trunc i64 [[INDVARS_IV_NEXT_2]] to i32 ; CHECK-NEXT: [[TMP27:%.*]] = trunc i64 [[INDVARS_IV_NEXT_2]] to i32
; CHECK-NEXT: [[SHL_3:%.*]] = shl i32 1, [[TMP27]] ; CHECK-NEXT: [[SHL_3:%.*]] = shl i32 1, [[TMP27]]
; CHECK-NEXT: [[AND_3:%.*]] = and i32 [[SHL_3]], [[X]] ; CHECK-NEXT: [[AND_3:%.*]] = and i32 [[SHL_3]], [[X]]
; CHECK-NEXT: [[TOBOOL_3:%.*]] = icmp eq i32 [[AND_3]], 0 ; CHECK-NEXT: [[TOBOOL_3:%.*]] = icmp eq i32 [[AND_3]], 0
; CHECK-NEXT: [[CONV_3:%.*]] = select i1 [[TOBOOL_3]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_3:%.*]] = select i1 [[TOBOOL_3]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_2]] ; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_2]]
; CHECK-NEXT: store i8 [[CONV_3]], ptr [[ARRAYIDX_3]], align 1 ; CHECK-NEXT: store i8 [[CONV_3]], ptr [[ARRAYIDX_3]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 4
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[INDVARS_IV_NEXT_3]] to i32 ; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[INDVARS_IV_NEXT_3]] to i32
; CHECK-NEXT: [[SHL_4:%.*]] = shl i32 1, [[TMP28]] ; CHECK-NEXT: [[SHL_4:%.*]] = shl i32 1, [[TMP28]]
; CHECK-NEXT: [[AND_4:%.*]] = and i32 [[SHL_4]], [[X]] ; CHECK-NEXT: [[AND_4:%.*]] = and i32 [[SHL_4]], [[X]]
; CHECK-NEXT: [[TOBOOL_4:%.*]] = icmp eq i32 [[AND_4]], 0 ; CHECK-NEXT: [[TOBOOL_4:%.*]] = icmp eq i32 [[AND_4]], 0
; CHECK-NEXT: [[CONV_4:%.*]] = select i1 [[TOBOOL_4]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_4:%.*]] = select i1 [[TOBOOL_4]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_3]] ; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_3]]
; CHECK-NEXT: store i8 [[CONV_4]], ptr [[ARRAYIDX_4]], align 1 ; CHECK-NEXT: store i8 [[CONV_4]], ptr [[ARRAYIDX_4]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_3]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 5
; CHECK-NEXT: [[TMP29:%.*]] = trunc i64 [[INDVARS_IV_NEXT_4]] to i32 ; CHECK-NEXT: [[TMP29:%.*]] = trunc i64 [[INDVARS_IV_NEXT_4]] to i32
; CHECK-NEXT: [[SHL_5:%.*]] = shl i32 1, [[TMP29]] ; CHECK-NEXT: [[SHL_5:%.*]] = shl i32 1, [[TMP29]]
; CHECK-NEXT: [[AND_5:%.*]] = and i32 [[SHL_5]], [[X]] ; CHECK-NEXT: [[AND_5:%.*]] = and i32 [[SHL_5]], [[X]]
; CHECK-NEXT: [[TOBOOL_5:%.*]] = icmp eq i32 [[AND_5]], 0 ; CHECK-NEXT: [[TOBOOL_5:%.*]] = icmp eq i32 [[AND_5]], 0
; CHECK-NEXT: [[CONV_5:%.*]] = select i1 [[TOBOOL_5]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_5:%.*]] = select i1 [[TOBOOL_5]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_4]] ; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_4]]
; CHECK-NEXT: store i8 [[CONV_5]], ptr [[ARRAYIDX_5]], align 1 ; CHECK-NEXT: store i8 [[CONV_5]], ptr [[ARRAYIDX_5]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_4]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 6
; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[INDVARS_IV_NEXT_5]] to i32 ; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[INDVARS_IV_NEXT_5]] to i32
; CHECK-NEXT: [[SHL_6:%.*]] = shl i32 1, [[TMP30]] ; CHECK-NEXT: [[SHL_6:%.*]] = shl i32 1, [[TMP30]]
; CHECK-NEXT: [[AND_6:%.*]] = and i32 [[SHL_6]], [[X]] ; CHECK-NEXT: [[AND_6:%.*]] = and i32 [[SHL_6]], [[X]]
; CHECK-NEXT: [[TOBOOL_6:%.*]] = icmp eq i32 [[AND_6]], 0 ; CHECK-NEXT: [[TOBOOL_6:%.*]] = icmp eq i32 [[AND_6]], 0
; CHECK-NEXT: [[CONV_6:%.*]] = select i1 [[TOBOOL_6]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_6:%.*]] = select i1 [[TOBOOL_6]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_5]] ; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_5]]
; CHECK-NEXT: store i8 [[CONV_6]], ptr [[ARRAYIDX_6]], align 1 ; CHECK-NEXT: store i8 [[CONV_6]], ptr [[ARRAYIDX_6]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_5]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 7
; CHECK-NEXT: [[TMP31:%.*]] = trunc i64 [[INDVARS_IV_NEXT_6]] to i32 ; CHECK-NEXT: [[TMP31:%.*]] = trunc i64 [[INDVARS_IV_NEXT_6]] to i32
; CHECK-NEXT: [[SHL_7:%.*]] = shl i32 1, [[TMP31]] ; CHECK-NEXT: [[SHL_7:%.*]] = shl i32 1, [[TMP31]]
; CHECK-NEXT: [[AND_7:%.*]] = and i32 [[SHL_7]], [[X]] ; CHECK-NEXT: [[AND_7:%.*]] = and i32 [[SHL_7]], [[X]]
; CHECK-NEXT: [[TOBOOL_7:%.*]] = icmp eq i32 [[AND_7]], 0 ; CHECK-NEXT: [[TOBOOL_7:%.*]] = icmp eq i32 [[AND_7]], 0
; CHECK-NEXT: [[CONV_7:%.*]] = select i1 [[TOBOOL_7]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_7:%.*]] = select i1 [[TOBOOL_7]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_6]] ; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_6]]
; CHECK-NEXT: store i8 [[CONV_7]], ptr [[ARRAYIDX_7]], align 1 ; CHECK-NEXT: store i8 [[CONV_7]], ptr [[ARRAYIDX_7]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw nsw i64 [[INDVARS_IV_NEXT_6]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw nsw i64 [[INDVARS_IV]], 8
; CHECK-NEXT: [[EXITCOND_7:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_7]], [[WIDE_TRIP_COUNT]] ; CHECK-NEXT: [[EXITCOND_7:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_7]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND_7]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY]] ; CHECK-NEXT: br i1 [[EXITCOND_7]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY]]
; CHECK: for.end.loopexit.unr-lcssa: ; CHECK: for.end.loopexit.unr-lcssa:
; CHECK-NEXT: br label [[FOR_END_LOOPEXIT]] ; CHECK-NEXT: br label [[FOR_END_LOOPEXIT]]
; CHECK: for.end.loopexit: ; CHECK: for.end.loopexit:
; CHECK-NEXT: br label [[FOR_END]] ; CHECK-NEXT: br label [[FOR_END]]
; CHECK: for.end: ; CHECK: for.end:
; CHECK-NEXT: [[IDXPROM1:%.*]] = sext i32 [[K]] to i64 ; CHECK-NEXT: [[IDXPROM1:%.*]] = sext i32 [[K]] to i64
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llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll

Show All 34 Lines
; CHECK-NEXT: [[TMP4:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND12]] ; CHECK-NEXT: [[TMP4:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND12]]
; CHECK-NEXT: [[TMP5:%.*]] = and <16 x i32> [[TMP4]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[TMP5:%.*]] = and <16 x i32> [[TMP4]], [[BROADCAST_SPLAT]]
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <16 x i32> [[TMP5]], zeroinitializer ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <16 x i32> [[TMP5]], zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[TMP6]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49> ; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[TMP6]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49>
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[S:%.*]], i64 [[INDEX]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[S:%.*]], i64 [[INDEX]]
; CHECK-NEXT: store <16 x i8> [[TMP7]], ptr [[TMP8]], align 1 ; CHECK-NEXT: store <16 x i8> [[TMP7]], ptr [[TMP8]], align 1
; CHECK-NEXT: [[INDEX_NEXT:%.*]] = add nuw nsw i64 [[INDEX]], 16 ; CHECK-NEXT: [[INDEX_NEXT:%.*]] = add nuw nsw i64 [[INDEX]], 16
; CHECK-NEXT: [[VEC_IND_NEXT13:%.*]] = add <16 x i32> [[VEC_IND12]], <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> ; CHECK-NEXT: [[VEC_IND_NEXT13:%.*]] = add <16 x i32> [[VEC_IND12]], <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1
; CHECK-NEXT: [[TMP9:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND_NEXT13]] ; CHECK-NEXT: [[TMP9:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND_NEXT13]]
; CHECK-NEXT: [[TMP10:%.*]] = and <16 x i32> [[TMP9]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[TMP10:%.*]] = and <16 x i32> [[TMP9]], [[BROADCAST_SPLAT]]
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq <16 x i32> [[TMP10]], zeroinitializer ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq <16 x i32> [[TMP10]], zeroinitializer
; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49> ; CHECK-NEXT: [[TMP12:%.*]] = select <16 x i1> [[TMP11]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49>
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDEX_NEXT]] ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDEX_NEXT]]
; CHECK-NEXT: store <16 x i8> [[TMP12]], ptr [[TMP13]], align 1 ; CHECK-NEXT: store <16 x i8> [[TMP12]], ptr [[TMP13]], align 1
; CHECK-NEXT: [[INDEX_NEXT_1]] = add i64 [[INDEX_NEXT]], 16 ; CHECK-NEXT: [[INDEX_NEXT_1]] = add i64 [[INDEX]], 32
; CHECK-NEXT: [[VEC_IND_NEXT13_1]] = add <16 x i32> [[VEC_IND_NEXT13]], <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> ; CHECK-NEXT: [[VEC_IND_NEXT13_1]] = add <16 x i32> [[VEC_IND12]], <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER_NEXT]], 1 ; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]] ; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT:%.*]], label [[VECTOR_BODY]] ; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT:%.*]], label [[VECTOR_BODY]]
; CHECK: middle.block.unr-lcssa.loopexit: ; CHECK: middle.block.unr-lcssa.loopexit:
; CHECK-NEXT: [[INDEX_UNR_PH:%.*]] = phi i64 [ [[INDEX_NEXT_1]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[INDEX_UNR_PH:%.*]] = phi i64 [ [[INDEX_NEXT_1]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_IND12_UNR_PH:%.*]] = phi <16 x i32> [ [[VEC_IND_NEXT13_1]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND12_UNR_PH:%.*]] = phi <16 x i32> [ [[VEC_IND_NEXT13_1]], [[VECTOR_BODY]] ]
; CHECK-NEXT: br label [[MIDDLE_BLOCK_UNR_LCSSA]] ; CHECK-NEXT: br label [[MIDDLE_BLOCK_UNR_LCSSA]]
; CHECK: middle.block.unr-lcssa: ; CHECK: middle.block.unr-lcssa:
; CHECK-NEXT: [[INDEX_UNR:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_UNR_PH]], [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT]] ] ; CHECK-NEXT: [[INDEX_UNR:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_UNR_PH]], [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT]] ]
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; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[TMP25:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32 ; CHECK-NEXT: [[TMP25:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
; CHECK-NEXT: [[SHL_1:%.*]] = shl i32 1, [[TMP25]] ; CHECK-NEXT: [[SHL_1:%.*]] = shl i32 1, [[TMP25]]
; CHECK-NEXT: [[AND_1:%.*]] = and i32 [[SHL_1]], [[X]] ; CHECK-NEXT: [[AND_1:%.*]] = and i32 [[SHL_1]], [[X]]
; CHECK-NEXT: [[TOBOOL_1:%.*]] = icmp eq i32 [[AND_1]], 0 ; CHECK-NEXT: [[TOBOOL_1:%.*]] = icmp eq i32 [[AND_1]], 0
; CHECK-NEXT: [[CONV_1:%.*]] = select i1 [[TOBOOL_1]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_1:%.*]] = select i1 [[TOBOOL_1]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT]]
; CHECK-NEXT: store i8 [[CONV_1]], ptr [[ARRAYIDX_1]], align 1 ; CHECK-NEXT: store i8 [[CONV_1]], ptr [[ARRAYIDX_1]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[INDVARS_IV_NEXT_1]] to i32 ; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[INDVARS_IV_NEXT_1]] to i32
; CHECK-NEXT: [[SHL_2:%.*]] = shl i32 1, [[TMP26]] ; CHECK-NEXT: [[SHL_2:%.*]] = shl i32 1, [[TMP26]]
; CHECK-NEXT: [[AND_2:%.*]] = and i32 [[SHL_2]], [[X]] ; CHECK-NEXT: [[AND_2:%.*]] = and i32 [[SHL_2]], [[X]]
; CHECK-NEXT: [[TOBOOL_2:%.*]] = icmp eq i32 [[AND_2]], 0 ; CHECK-NEXT: [[TOBOOL_2:%.*]] = icmp eq i32 [[AND_2]], 0
; CHECK-NEXT: [[CONV_2:%.*]] = select i1 [[TOBOOL_2]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_2:%.*]] = select i1 [[TOBOOL_2]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_1]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_1]]
; CHECK-NEXT: store i8 [[CONV_2]], ptr [[ARRAYIDX_2]], align 1 ; CHECK-NEXT: store i8 [[CONV_2]], ptr [[ARRAYIDX_2]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 3
; CHECK-NEXT: [[TMP27:%.*]] = trunc i64 [[INDVARS_IV_NEXT_2]] to i32 ; CHECK-NEXT: [[TMP27:%.*]] = trunc i64 [[INDVARS_IV_NEXT_2]] to i32
; CHECK-NEXT: [[SHL_3:%.*]] = shl i32 1, [[TMP27]] ; CHECK-NEXT: [[SHL_3:%.*]] = shl i32 1, [[TMP27]]
; CHECK-NEXT: [[AND_3:%.*]] = and i32 [[SHL_3]], [[X]] ; CHECK-NEXT: [[AND_3:%.*]] = and i32 [[SHL_3]], [[X]]
; CHECK-NEXT: [[TOBOOL_3:%.*]] = icmp eq i32 [[AND_3]], 0 ; CHECK-NEXT: [[TOBOOL_3:%.*]] = icmp eq i32 [[AND_3]], 0
; CHECK-NEXT: [[CONV_3:%.*]] = select i1 [[TOBOOL_3]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_3:%.*]] = select i1 [[TOBOOL_3]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_2]] ; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_2]]
; CHECK-NEXT: store i8 [[CONV_3]], ptr [[ARRAYIDX_3]], align 1 ; CHECK-NEXT: store i8 [[CONV_3]], ptr [[ARRAYIDX_3]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 4
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[INDVARS_IV_NEXT_3]] to i32 ; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[INDVARS_IV_NEXT_3]] to i32
; CHECK-NEXT: [[SHL_4:%.*]] = shl i32 1, [[TMP28]] ; CHECK-NEXT: [[SHL_4:%.*]] = shl i32 1, [[TMP28]]
; CHECK-NEXT: [[AND_4:%.*]] = and i32 [[SHL_4]], [[X]] ; CHECK-NEXT: [[AND_4:%.*]] = and i32 [[SHL_4]], [[X]]
; CHECK-NEXT: [[TOBOOL_4:%.*]] = icmp eq i32 [[AND_4]], 0 ; CHECK-NEXT: [[TOBOOL_4:%.*]] = icmp eq i32 [[AND_4]], 0
; CHECK-NEXT: [[CONV_4:%.*]] = select i1 [[TOBOOL_4]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_4:%.*]] = select i1 [[TOBOOL_4]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_3]] ; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_3]]
; CHECK-NEXT: store i8 [[CONV_4]], ptr [[ARRAYIDX_4]], align 1 ; CHECK-NEXT: store i8 [[CONV_4]], ptr [[ARRAYIDX_4]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_3]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 5
; CHECK-NEXT: [[TMP29:%.*]] = trunc i64 [[INDVARS_IV_NEXT_4]] to i32 ; CHECK-NEXT: [[TMP29:%.*]] = trunc i64 [[INDVARS_IV_NEXT_4]] to i32
; CHECK-NEXT: [[SHL_5:%.*]] = shl i32 1, [[TMP29]] ; CHECK-NEXT: [[SHL_5:%.*]] = shl i32 1, [[TMP29]]
; CHECK-NEXT: [[AND_5:%.*]] = and i32 [[SHL_5]], [[X]] ; CHECK-NEXT: [[AND_5:%.*]] = and i32 [[SHL_5]], [[X]]
; CHECK-NEXT: [[TOBOOL_5:%.*]] = icmp eq i32 [[AND_5]], 0 ; CHECK-NEXT: [[TOBOOL_5:%.*]] = icmp eq i32 [[AND_5]], 0
; CHECK-NEXT: [[CONV_5:%.*]] = select i1 [[TOBOOL_5]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_5:%.*]] = select i1 [[TOBOOL_5]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_4]] ; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_4]]
; CHECK-NEXT: store i8 [[CONV_5]], ptr [[ARRAYIDX_5]], align 1 ; CHECK-NEXT: store i8 [[CONV_5]], ptr [[ARRAYIDX_5]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_4]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 6
; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[INDVARS_IV_NEXT_5]] to i32 ; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[INDVARS_IV_NEXT_5]] to i32
; CHECK-NEXT: [[SHL_6:%.*]] = shl i32 1, [[TMP30]] ; CHECK-NEXT: [[SHL_6:%.*]] = shl i32 1, [[TMP30]]
; CHECK-NEXT: [[AND_6:%.*]] = and i32 [[SHL_6]], [[X]] ; CHECK-NEXT: [[AND_6:%.*]] = and i32 [[SHL_6]], [[X]]
; CHECK-NEXT: [[TOBOOL_6:%.*]] = icmp eq i32 [[AND_6]], 0 ; CHECK-NEXT: [[TOBOOL_6:%.*]] = icmp eq i32 [[AND_6]], 0
; CHECK-NEXT: [[CONV_6:%.*]] = select i1 [[TOBOOL_6]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_6:%.*]] = select i1 [[TOBOOL_6]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_5]] ; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_5]]
; CHECK-NEXT: store i8 [[CONV_6]], ptr [[ARRAYIDX_6]], align 1 ; CHECK-NEXT: store i8 [[CONV_6]], ptr [[ARRAYIDX_6]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_5]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 7
; CHECK-NEXT: [[TMP31:%.*]] = trunc i64 [[INDVARS_IV_NEXT_6]] to i32 ; CHECK-NEXT: [[TMP31:%.*]] = trunc i64 [[INDVARS_IV_NEXT_6]] to i32
; CHECK-NEXT: [[SHL_7:%.*]] = shl i32 1, [[TMP31]] ; CHECK-NEXT: [[SHL_7:%.*]] = shl i32 1, [[TMP31]]
; CHECK-NEXT: [[AND_7:%.*]] = and i32 [[SHL_7]], [[X]] ; CHECK-NEXT: [[AND_7:%.*]] = and i32 [[SHL_7]], [[X]]
; CHECK-NEXT: [[TOBOOL_7:%.*]] = icmp eq i32 [[AND_7]], 0 ; CHECK-NEXT: [[TOBOOL_7:%.*]] = icmp eq i32 [[AND_7]], 0
; CHECK-NEXT: [[CONV_7:%.*]] = select i1 [[TOBOOL_7]], i8 48, i8 49 ; CHECK-NEXT: [[CONV_7:%.*]] = select i1 [[TOBOOL_7]], i8 48, i8 49
; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_6]] ; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i8, ptr [[S]], i64 [[INDVARS_IV_NEXT_6]]
; CHECK-NEXT: store i8 [[CONV_7]], ptr [[ARRAYIDX_7]], align 1 ; CHECK-NEXT: store i8 [[CONV_7]], ptr [[ARRAYIDX_7]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw nsw i64 [[INDVARS_IV_NEXT_6]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw nsw i64 [[INDVARS_IV]], 8
; CHECK-NEXT: [[EXITCOND_7:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_7]], [[WIDE_TRIP_COUNT]] ; CHECK-NEXT: [[EXITCOND_7:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_7]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND_7]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY]] ; CHECK-NEXT: br i1 [[EXITCOND_7]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY]]
; CHECK: for.end.loopexit.unr-lcssa: ; CHECK: for.end.loopexit.unr-lcssa:
; CHECK-NEXT: br label [[FOR_END_LOOPEXIT]] ; CHECK-NEXT: br label [[FOR_END_LOOPEXIT]]
; CHECK: for.end.loopexit: ; CHECK: for.end.loopexit:
; CHECK-NEXT: br label [[FOR_END]] ; CHECK-NEXT: br label [[FOR_END]]
; CHECK: for.end: ; CHECK: for.end:
; CHECK-NEXT: [[IDXPROM1:%.*]] = sext i32 [[K]] to i64 ; CHECK-NEXT: [[IDXPROM1:%.*]] = sext i32 [[K]] to i64
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llvm/test/Transforms/LoopUnroll/RISCV/unroll.ll

Show All 16 Lines
; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT]]
; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[ARRAYIDX_1]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[ARRAYIDX_1]], align 4
; CHECK-NEXT: [[MUL_1:%.*]] = fmul fast float [[TMP2]], [[A]] ; CHECK-NEXT: [[MUL_1:%.*]] = fmul fast float [[TMP2]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT]] ; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT]]
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[ARRAYIDX2_1]], align 4 ; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[ARRAYIDX2_1]], align 4
; CHECK-NEXT: [[ADD_1:%.*]] = fadd fast float [[MUL_1]], [[TMP3]] ; CHECK-NEXT: [[ADD_1:%.*]] = fadd fast float [[MUL_1]], [[TMP3]]
; CHECK-NEXT: store float [[ADD_1]], ptr [[ARRAYIDX2_1]], align 4 ; CHECK-NEXT: store float [[ADD_1]], ptr [[ARRAYIDX2_1]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_1]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_1]]
; CHECK-NEXT: [[TMP4:%.*]] = load float, ptr [[ARRAYIDX_2]], align 4 ; CHECK-NEXT: [[TMP4:%.*]] = load float, ptr [[ARRAYIDX_2]], align 4
; CHECK-NEXT: [[MUL_2:%.*]] = fmul fast float [[TMP4]], [[A]] ; CHECK-NEXT: [[MUL_2:%.*]] = fmul fast float [[TMP4]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_1]] ; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_1]]
; CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[ARRAYIDX2_2]], align 4 ; CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[ARRAYIDX2_2]], align 4
; CHECK-NEXT: [[ADD_2:%.*]] = fadd fast float [[MUL_2]], [[TMP5]] ; CHECK-NEXT: [[ADD_2:%.*]] = fadd fast float [[MUL_2]], [[TMP5]]
; CHECK-NEXT: store float [[ADD_2]], ptr [[ARRAYIDX2_2]], align 4 ; CHECK-NEXT: store float [[ADD_2]], ptr [[ARRAYIDX2_2]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 3
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_2]] ; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_2]]
; CHECK-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX_3]], align 4 ; CHECK-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX_3]], align 4
; CHECK-NEXT: [[MUL_3:%.*]] = fmul fast float [[TMP6]], [[A]] ; CHECK-NEXT: [[MUL_3:%.*]] = fmul fast float [[TMP6]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_2]] ; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_2]]
; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX2_3]], align 4 ; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX2_3]], align 4
; CHECK-NEXT: [[ADD_3:%.*]] = fadd fast float [[MUL_3]], [[TMP7]] ; CHECK-NEXT: [[ADD_3:%.*]] = fadd fast float [[MUL_3]], [[TMP7]]
; CHECK-NEXT: store float [[ADD_3]], ptr [[ARRAYIDX2_3]], align 4 ; CHECK-NEXT: store float [[ADD_3]], ptr [[ARRAYIDX2_3]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 4
; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_3]] ; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_3]]
; CHECK-NEXT: [[TMP8:%.*]] = load float, ptr [[ARRAYIDX_4]], align 4 ; CHECK-NEXT: [[TMP8:%.*]] = load float, ptr [[ARRAYIDX_4]], align 4
; CHECK-NEXT: [[MUL_4:%.*]] = fmul fast float [[TMP8]], [[A]] ; CHECK-NEXT: [[MUL_4:%.*]] = fmul fast float [[TMP8]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_4:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_3]] ; CHECK-NEXT: [[ARRAYIDX2_4:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_3]]
; CHECK-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2_4]], align 4 ; CHECK-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2_4]], align 4
; CHECK-NEXT: [[ADD_4:%.*]] = fadd fast float [[MUL_4]], [[TMP9]] ; CHECK-NEXT: [[ADD_4:%.*]] = fadd fast float [[MUL_4]], [[TMP9]]
; CHECK-NEXT: store float [[ADD_4]], ptr [[ARRAYIDX2_4]], align 4 ; CHECK-NEXT: store float [[ADD_4]], ptr [[ARRAYIDX2_4]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_3]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 5
; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_4]] ; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_4]]
; CHECK-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX_5]], align 4 ; CHECK-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX_5]], align 4
; CHECK-NEXT: [[MUL_5:%.*]] = fmul fast float [[TMP10]], [[A]] ; CHECK-NEXT: [[MUL_5:%.*]] = fmul fast float [[TMP10]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_5:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_4]] ; CHECK-NEXT: [[ARRAYIDX2_5:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_4]]
; CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2_5]], align 4 ; CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2_5]], align 4
; CHECK-NEXT: [[ADD_5:%.*]] = fadd fast float [[MUL_5]], [[TMP11]] ; CHECK-NEXT: [[ADD_5:%.*]] = fadd fast float [[MUL_5]], [[TMP11]]
; CHECK-NEXT: store float [[ADD_5]], ptr [[ARRAYIDX2_5]], align 4 ; CHECK-NEXT: store float [[ADD_5]], ptr [[ARRAYIDX2_5]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_4]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 6
; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_5]] ; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_5]]
; CHECK-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX_6]], align 4 ; CHECK-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX_6]], align 4
; CHECK-NEXT: [[MUL_6:%.*]] = fmul fast float [[TMP12]], [[A]] ; CHECK-NEXT: [[MUL_6:%.*]] = fmul fast float [[TMP12]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_6:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_5]] ; CHECK-NEXT: [[ARRAYIDX2_6:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_5]]
; CHECK-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX2_6]], align 4 ; CHECK-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX2_6]], align 4
; CHECK-NEXT: [[ADD_6:%.*]] = fadd fast float [[MUL_6]], [[TMP13]] ; CHECK-NEXT: [[ADD_6:%.*]] = fadd fast float [[MUL_6]], [[TMP13]]
; CHECK-NEXT: store float [[ADD_6]], ptr [[ARRAYIDX2_6]], align 4 ; CHECK-NEXT: store float [[ADD_6]], ptr [[ARRAYIDX2_6]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_5]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 7
; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_6]] ; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_6]]
; CHECK-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX_7]], align 4 ; CHECK-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX_7]], align 4
; CHECK-NEXT: [[MUL_7:%.*]] = fmul fast float [[TMP14]], [[A]] ; CHECK-NEXT: [[MUL_7:%.*]] = fmul fast float [[TMP14]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_7:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_6]] ; CHECK-NEXT: [[ARRAYIDX2_7:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_6]]
; CHECK-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX2_7]], align 4 ; CHECK-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX2_7]], align 4
; CHECK-NEXT: [[ADD_7:%.*]] = fadd fast float [[MUL_7]], [[TMP15]] ; CHECK-NEXT: [[ADD_7:%.*]] = fadd fast float [[MUL_7]], [[TMP15]]
; CHECK-NEXT: store float [[ADD_7]], ptr [[ARRAYIDX2_7]], align 4 ; CHECK-NEXT: store float [[ADD_7]], ptr [[ARRAYIDX2_7]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_7:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_6]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_7:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 8
; CHECK-NEXT: [[ARRAYIDX_8:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_7]] ; CHECK-NEXT: [[ARRAYIDX_8:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_7]]
; CHECK-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX_8]], align 4 ; CHECK-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX_8]], align 4
; CHECK-NEXT: [[MUL_8:%.*]] = fmul fast float [[TMP16]], [[A]] ; CHECK-NEXT: [[MUL_8:%.*]] = fmul fast float [[TMP16]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_8:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_7]] ; CHECK-NEXT: [[ARRAYIDX2_8:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_7]]
; CHECK-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2_8]], align 4 ; CHECK-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2_8]], align 4
; CHECK-NEXT: [[ADD_8:%.*]] = fadd fast float [[MUL_8]], [[TMP17]] ; CHECK-NEXT: [[ADD_8:%.*]] = fadd fast float [[MUL_8]], [[TMP17]]
; CHECK-NEXT: store float [[ADD_8]], ptr [[ARRAYIDX2_8]], align 4 ; CHECK-NEXT: store float [[ADD_8]], ptr [[ARRAYIDX2_8]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_8:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_7]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_8:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 9
; CHECK-NEXT: [[ARRAYIDX_9:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_8]] ; CHECK-NEXT: [[ARRAYIDX_9:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_8]]
; CHECK-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX_9]], align 4 ; CHECK-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX_9]], align 4
; CHECK-NEXT: [[MUL_9:%.*]] = fmul fast float [[TMP18]], [[A]] ; CHECK-NEXT: [[MUL_9:%.*]] = fmul fast float [[TMP18]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_9:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_8]] ; CHECK-NEXT: [[ARRAYIDX2_9:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_8]]
; CHECK-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX2_9]], align 4 ; CHECK-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX2_9]], align 4
; CHECK-NEXT: [[ADD_9:%.*]] = fadd fast float [[MUL_9]], [[TMP19]] ; CHECK-NEXT: [[ADD_9:%.*]] = fadd fast float [[MUL_9]], [[TMP19]]
; CHECK-NEXT: store float [[ADD_9]], ptr [[ARRAYIDX2_9]], align 4 ; CHECK-NEXT: store float [[ADD_9]], ptr [[ARRAYIDX2_9]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_9:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_8]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_9:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 10
; CHECK-NEXT: [[ARRAYIDX_10:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_9]] ; CHECK-NEXT: [[ARRAYIDX_10:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_9]]
; CHECK-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX_10]], align 4 ; CHECK-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX_10]], align 4
; CHECK-NEXT: [[MUL_10:%.*]] = fmul fast float [[TMP20]], [[A]] ; CHECK-NEXT: [[MUL_10:%.*]] = fmul fast float [[TMP20]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_10:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_9]] ; CHECK-NEXT: [[ARRAYIDX2_10:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_9]]
; CHECK-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX2_10]], align 4 ; CHECK-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX2_10]], align 4
; CHECK-NEXT: [[ADD_10:%.*]] = fadd fast float [[MUL_10]], [[TMP21]] ; CHECK-NEXT: [[ADD_10:%.*]] = fadd fast float [[MUL_10]], [[TMP21]]
; CHECK-NEXT: store float [[ADD_10]], ptr [[ARRAYIDX2_10]], align 4 ; CHECK-NEXT: store float [[ADD_10]], ptr [[ARRAYIDX2_10]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_10:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_9]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_10:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 11
; CHECK-NEXT: [[ARRAYIDX_11:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_10]] ; CHECK-NEXT: [[ARRAYIDX_11:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_10]]
; CHECK-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX_11]], align 4 ; CHECK-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX_11]], align 4
; CHECK-NEXT: [[MUL_11:%.*]] = fmul fast float [[TMP22]], [[A]] ; CHECK-NEXT: [[MUL_11:%.*]] = fmul fast float [[TMP22]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_11:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_10]] ; CHECK-NEXT: [[ARRAYIDX2_11:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_10]]
; CHECK-NEXT: [[TMP23:%.*]] = load float, ptr [[ARRAYIDX2_11]], align 4 ; CHECK-NEXT: [[TMP23:%.*]] = load float, ptr [[ARRAYIDX2_11]], align 4
; CHECK-NEXT: [[ADD_11:%.*]] = fadd fast float [[MUL_11]], [[TMP23]] ; CHECK-NEXT: [[ADD_11:%.*]] = fadd fast float [[MUL_11]], [[TMP23]]
; CHECK-NEXT: store float [[ADD_11]], ptr [[ARRAYIDX2_11]], align 4 ; CHECK-NEXT: store float [[ADD_11]], ptr [[ARRAYIDX2_11]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_11:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_10]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_11:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 12
; CHECK-NEXT: [[ARRAYIDX_12:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_11]] ; CHECK-NEXT: [[ARRAYIDX_12:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_11]]
; CHECK-NEXT: [[TMP24:%.*]] = load float, ptr [[ARRAYIDX_12]], align 4 ; CHECK-NEXT: [[TMP24:%.*]] = load float, ptr [[ARRAYIDX_12]], align 4
; CHECK-NEXT: [[MUL_12:%.*]] = fmul fast float [[TMP24]], [[A]] ; CHECK-NEXT: [[MUL_12:%.*]] = fmul fast float [[TMP24]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_12:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_11]] ; CHECK-NEXT: [[ARRAYIDX2_12:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_11]]
; CHECK-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX2_12]], align 4 ; CHECK-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX2_12]], align 4
; CHECK-NEXT: [[ADD_12:%.*]] = fadd fast float [[MUL_12]], [[TMP25]] ; CHECK-NEXT: [[ADD_12:%.*]] = fadd fast float [[MUL_12]], [[TMP25]]
; CHECK-NEXT: store float [[ADD_12]], ptr [[ARRAYIDX2_12]], align 4 ; CHECK-NEXT: store float [[ADD_12]], ptr [[ARRAYIDX2_12]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_12:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_11]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_12:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 13
; CHECK-NEXT: [[ARRAYIDX_13:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_12]] ; CHECK-NEXT: [[ARRAYIDX_13:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_12]]
; CHECK-NEXT: [[TMP26:%.*]] = load float, ptr [[ARRAYIDX_13]], align 4 ; CHECK-NEXT: [[TMP26:%.*]] = load float, ptr [[ARRAYIDX_13]], align 4
; CHECK-NEXT: [[MUL_13:%.*]] = fmul fast float [[TMP26]], [[A]] ; CHECK-NEXT: [[MUL_13:%.*]] = fmul fast float [[TMP26]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_13:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_12]] ; CHECK-NEXT: [[ARRAYIDX2_13:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_12]]
; CHECK-NEXT: [[TMP27:%.*]] = load float, ptr [[ARRAYIDX2_13]], align 4 ; CHECK-NEXT: [[TMP27:%.*]] = load float, ptr [[ARRAYIDX2_13]], align 4
; CHECK-NEXT: [[ADD_13:%.*]] = fadd fast float [[MUL_13]], [[TMP27]] ; CHECK-NEXT: [[ADD_13:%.*]] = fadd fast float [[MUL_13]], [[TMP27]]
; CHECK-NEXT: store float [[ADD_13]], ptr [[ARRAYIDX2_13]], align 4 ; CHECK-NEXT: store float [[ADD_13]], ptr [[ARRAYIDX2_13]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_13:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_12]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_13:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 14
; CHECK-NEXT: [[ARRAYIDX_14:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_13]] ; CHECK-NEXT: [[ARRAYIDX_14:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_13]]
; CHECK-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX_14]], align 4 ; CHECK-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX_14]], align 4
; CHECK-NEXT: [[MUL_14:%.*]] = fmul fast float [[TMP28]], [[A]] ; CHECK-NEXT: [[MUL_14:%.*]] = fmul fast float [[TMP28]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_14:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_13]] ; CHECK-NEXT: [[ARRAYIDX2_14:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_13]]
; CHECK-NEXT: [[TMP29:%.*]] = load float, ptr [[ARRAYIDX2_14]], align 4 ; CHECK-NEXT: [[TMP29:%.*]] = load float, ptr [[ARRAYIDX2_14]], align 4
; CHECK-NEXT: [[ADD_14:%.*]] = fadd fast float [[MUL_14]], [[TMP29]] ; CHECK-NEXT: [[ADD_14:%.*]] = fadd fast float [[MUL_14]], [[TMP29]]
; CHECK-NEXT: store float [[ADD_14]], ptr [[ARRAYIDX2_14]], align 4 ; CHECK-NEXT: store float [[ADD_14]], ptr [[ARRAYIDX2_14]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_14:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_13]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_14:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 15
; CHECK-NEXT: [[ARRAYIDX_15:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_14]] ; CHECK-NEXT: [[ARRAYIDX_15:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_14]]
; CHECK-NEXT: [[TMP30:%.*]] = load float, ptr [[ARRAYIDX_15]], align 4 ; CHECK-NEXT: [[TMP30:%.*]] = load float, ptr [[ARRAYIDX_15]], align 4
; CHECK-NEXT: [[MUL_15:%.*]] = fmul fast float [[TMP30]], [[A]] ; CHECK-NEXT: [[MUL_15:%.*]] = fmul fast float [[TMP30]], [[A]]
; CHECK-NEXT: [[ARRAYIDX2_15:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_14]] ; CHECK-NEXT: [[ARRAYIDX2_15:%.*]] = getelementptr inbounds float, ptr [[Y]], i64 [[INDVARS_IV_NEXT_14]]
; CHECK-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX2_15]], align 4 ; CHECK-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX2_15]], align 4
; CHECK-NEXT: [[ADD_15:%.*]] = fadd fast float [[MUL_15]], [[TMP31]] ; CHECK-NEXT: [[ADD_15:%.*]] = fadd fast float [[MUL_15]], [[TMP31]]
; CHECK-NEXT: store float [[ADD_15]], ptr [[ARRAYIDX2_15]], align 4 ; CHECK-NEXT: store float [[ADD_15]], ptr [[ARRAYIDX2_15]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT_15]] = add nuw nsw i64 [[INDVARS_IV_NEXT_14]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_15]] = add nuw nsw i64 [[INDVARS_IV]], 16
; CHECK-NEXT: [[EXITCOND_NOT_15:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_15]], 64 ; CHECK-NEXT: [[EXITCOND_NOT_15:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_15]], 64
; CHECK-NEXT: br i1 [[EXITCOND_NOT_15]], label [[EXIT_LOOP:%.*]], label [[FOR_BODY]] ; CHECK-NEXT: br i1 [[EXITCOND_NOT_15]], label [[EXIT_LOOP:%.*]], label [[FOR_BODY]]
; CHECK: exit_loop: ; CHECK: exit_loop:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
br label %for.body br label %for.body
Show All 17 Lines

llvm/test/Transforms/LoopUnroll/X86/mmx.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -S -passes=loop-unroll | FileCheck %s ; RUN: opt < %s -S -passes=loop-unroll | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define x86_mmx @f() #0 { define x86_mmx @f() #0 {
; CHECK-LABEL: define x86_mmx @f ; CHECK-LABEL: define x86_mmx @f
; CHECK-SAME: () #[[ATTR0:[0-9]+]] { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body: ; CHECK: for.body:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[ADD_7:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[ADD_7:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[PHI]], 1 ; CHECK-NEXT: [[ADD_6:%.*]] = add i32 [[PHI]], 7
; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[ADD]], 1 ; CHECK-NEXT: [[ADD_7]] = add i32 [[PHI]], 8
; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[ADD_1]], 1
; CHECK-NEXT: [[ADD_3:%.*]] = add nuw nsw i32 [[ADD_2]], 1
; CHECK-NEXT: [[ADD_4:%.*]] = add nuw nsw i32 [[ADD_3]], 1
; CHECK-NEXT: [[ADD_5:%.*]] = add nuw nsw i32 [[ADD_4]], 1
; CHECK-NEXT: [[ADD_6:%.*]] = add i32 [[ADD_5]], 1
; CHECK-NEXT: [[ADD_7]] = add nuw nsw i32 [[ADD_6]], 1
; CHECK-NEXT: [[CMP_7:%.*]] = icmp eq i32 [[ADD_6]], 0 ; CHECK-NEXT: [[CMP_7:%.*]] = icmp eq i32 [[ADD_6]], 0
; CHECK-NEXT: br i1 [[CMP_7]], label [[EXIT:%.*]], label [[FOR_BODY]] ; CHECK-NEXT: br i1 [[CMP_7]], label [[EXIT:%.*]], label [[FOR_BODY]]
; CHECK: exit: ; CHECK: exit:
; CHECK-NEXT: [[RET:%.*]] = phi x86_mmx [ undef, [[FOR_BODY]] ] ; CHECK-NEXT: [[RET:%.*]] = phi x86_mmx [ undef, [[FOR_BODY]] ]
; CHECK-NEXT: ret x86_mmx [[RET]] ; CHECK-NEXT: ret x86_mmx [[RET]]
; ;
entry: entry:
br label %for.body br label %for.body
Show All 13 Lines

llvm/test/Transforms/LoopUnroll/add-folding-overflow.ll

Show All 16 Lines
; CHECK-NEXT: [[IV1_NEXT:%.*]] = add i8 [[IV1]], 1 ; CHECK-NEXT: [[IV1_NEXT:%.*]] = add i8 [[IV1]], 1
; CHECK-NEXT: call void @use(i8 [[IV1_NEXT]]) ; CHECK-NEXT: call void @use(i8 [[IV1_NEXT]])
; CHECK-NEXT: [[IV2_NEXT:%.*]] = add nuw i8 [[IV2]], 1 ; CHECK-NEXT: [[IV2_NEXT:%.*]] = add nuw i8 [[IV2]], 1
; CHECK-NEXT: call void @use(i8 [[IV2_NEXT]]) ; CHECK-NEXT: call void @use(i8 [[IV2_NEXT]])
; CHECK-NEXT: [[IV3_NEXT:%.*]] = add nsw i8 [[IV3]], 1 ; CHECK-NEXT: [[IV3_NEXT:%.*]] = add nsw i8 [[IV3]], 1
; CHECK-NEXT: call void @use(i8 [[IV3_NEXT]]) ; CHECK-NEXT: call void @use(i8 [[IV3_NEXT]])
; CHECK-NEXT: [[IV4_NEXT:%.*]] = add nsw i8 [[IV4]], 127 ; CHECK-NEXT: [[IV4_NEXT:%.*]] = add nsw i8 [[IV4]], 127
; CHECK-NEXT: call void @use(i8 [[IV4_NEXT]]) ; CHECK-NEXT: call void @use(i8 [[IV4_NEXT]])
; CHECK-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i32 [[IV]], 1 ; CHECK-NEXT: [[IV1_NEXT_1:%.*]] = add i8 [[IV1]], 2
; CHECK-NEXT: [[IV1_NEXT_1:%.*]] = add i8 [[IV1_NEXT]], 1
; CHECK-NEXT: call void @use(i8 [[IV1_NEXT_1]]) ; CHECK-NEXT: call void @use(i8 [[IV1_NEXT_1]])
; CHECK-NEXT: [[IV2_NEXT_1:%.*]] = add nuw i8 [[IV2_NEXT]], 1 ; CHECK-NEXT: [[IV2_NEXT_1:%.*]] = add nuw i8 [[IV2]], 2
; CHECK-NEXT: call void @use(i8 [[IV2_NEXT_1]]) ; CHECK-NEXT: call void @use(i8 [[IV2_NEXT_1]])
; CHECK-NEXT: [[IV3_NEXT_1:%.*]] = add nsw i8 [[IV3_NEXT]], 1 ; CHECK-NEXT: [[IV3_NEXT_1:%.*]] = add nsw i8 [[IV3]], 2
; CHECK-NEXT: call void @use(i8 [[IV3_NEXT_1]]) ; CHECK-NEXT: call void @use(i8 [[IV3_NEXT_1]])
; CHECK-NEXT: [[IV4_NEXT_1:%.*]] = add nsw i8 [[IV4_NEXT]], 127 ; CHECK-NEXT: [[IV4_NEXT_1:%.*]] = add i8 [[IV4]], -2
; CHECK-NEXT: call void @use(i8 [[IV4_NEXT_1]]) ; CHECK-NEXT: call void @use(i8 [[IV4_NEXT_1]])
; CHECK-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i32 [[IV_NEXT]], 1 ; CHECK-NEXT: [[IV1_NEXT_2:%.*]] = add i8 [[IV1]], 3
; CHECK-NEXT: [[IV1_NEXT_2:%.*]] = add i8 [[IV1_NEXT_1]], 1
; CHECK-NEXT: call void @use(i8 [[IV1_NEXT_2]]) ; CHECK-NEXT: call void @use(i8 [[IV1_NEXT_2]])
; CHECK-NEXT: [[IV2_NEXT_2:%.*]] = add nuw i8 [[IV2_NEXT_1]], 1 ; CHECK-NEXT: [[IV2_NEXT_2:%.*]] = add nuw i8 [[IV2]], 3
; CHECK-NEXT: call void @use(i8 [[IV2_NEXT_2]]) ; CHECK-NEXT: call void @use(i8 [[IV2_NEXT_2]])
; CHECK-NEXT: [[IV3_NEXT_2:%.*]] = add nsw i8 [[IV3_NEXT_1]], 1 ; CHECK-NEXT: [[IV3_NEXT_2:%.*]] = add nsw i8 [[IV3]], 3
; CHECK-NEXT: call void @use(i8 [[IV3_NEXT_2]]) ; CHECK-NEXT: call void @use(i8 [[IV3_NEXT_2]])
; CHECK-NEXT: [[IV4_NEXT_2:%.*]] = add nsw i8 [[IV4_NEXT_1]], 127 ; CHECK-NEXT: [[IV4_NEXT_2:%.*]] = add i8 [[IV4]], 125
; CHECK-NEXT: call void @use(i8 [[IV4_NEXT_2]]) ; CHECK-NEXT: call void @use(i8 [[IV4_NEXT_2]])
; CHECK-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i32 [[IV_NEXT_1]], 1 ; CHECK-NEXT: [[IV1_NEXT_3:%.*]] = add i8 [[IV1]], 4
; CHECK-NEXT: [[IV1_NEXT_3:%.*]] = add i8 [[IV1_NEXT_2]], 1
; CHECK-NEXT: call void @use(i8 [[IV1_NEXT_3]]) ; CHECK-NEXT: call void @use(i8 [[IV1_NEXT_3]])
; CHECK-NEXT: [[IV2_NEXT_3:%.*]] = add nuw i8 [[IV2_NEXT_2]], 1 ; CHECK-NEXT: [[IV2_NEXT_3:%.*]] = add nuw i8 [[IV2]], 4
; CHECK-NEXT: call void @use(i8 [[IV2_NEXT_3]]) ; CHECK-NEXT: call void @use(i8 [[IV2_NEXT_3]])
; CHECK-NEXT: [[IV3_NEXT_3:%.*]] = add nsw i8 [[IV3_NEXT_2]], 1 ; CHECK-NEXT: [[IV3_NEXT_3:%.*]] = add nsw i8 [[IV3]], 4
; CHECK-NEXT: call void @use(i8 [[IV3_NEXT_3]]) ; CHECK-NEXT: call void @use(i8 [[IV3_NEXT_3]])
; CHECK-NEXT: [[IV4_NEXT_3:%.*]] = add nsw i8 [[IV4_NEXT_2]], 127 ; CHECK-NEXT: [[IV4_NEXT_3:%.*]] = add i8 [[IV4]], -4
; CHECK-NEXT: call void @use(i8 [[IV4_NEXT_3]]) ; CHECK-NEXT: call void @use(i8 [[IV4_NEXT_3]])
; CHECK-NEXT: [[IV_NEXT_3:%.*]] = add nuw nsw i32 [[IV_NEXT_2]], 1 ; CHECK-NEXT: [[IV_NEXT_3:%.*]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[IV1_NEXT_4]] = add i8 [[IV1_NEXT_3]], 1 ; CHECK-NEXT: [[IV1_NEXT_4]] = add i8 [[IV1]], 5
; CHECK-NEXT: call void @use(i8 [[IV1_NEXT_4]]) ; CHECK-NEXT: call void @use(i8 [[IV1_NEXT_4]])
; CHECK-NEXT: [[IV2_NEXT_4]] = add nuw i8 [[IV2_NEXT_3]], 1 ; CHECK-NEXT: [[IV2_NEXT_4]] = add nuw i8 [[IV2]], 5
; CHECK-NEXT: call void @use(i8 [[IV2_NEXT_4]]) ; CHECK-NEXT: call void @use(i8 [[IV2_NEXT_4]])
; CHECK-NEXT: [[IV3_NEXT_4]] = add nsw i8 [[IV3_NEXT_3]], 1 ; CHECK-NEXT: [[IV3_NEXT_4]] = add nsw i8 [[IV3]], 5
; CHECK-NEXT: call void @use(i8 [[IV3_NEXT_4]]) ; CHECK-NEXT: call void @use(i8 [[IV3_NEXT_4]])
; CHECK-NEXT: [[IV4_NEXT_4]] = add nsw i8 [[IV4_NEXT_3]], 127 ; CHECK-NEXT: [[IV4_NEXT_4]] = add i8 [[IV4]], 123
; CHECK-NEXT: call void @use(i8 [[IV4_NEXT_4]]) ; CHECK-NEXT: call void @use(i8 [[IV4_NEXT_4]])
; CHECK-NEXT: [[IV_NEXT_4]] = add nuw nsw i32 [[IV_NEXT_3]], 1 ; CHECK-NEXT: [[IV_NEXT_4]] = add nuw nsw i32 [[IV]], 5
; CHECK-NEXT: [[CMP_4:%.*]] = icmp eq i32 [[IV_NEXT_3]], 1024 ; CHECK-NEXT: [[CMP_4:%.*]] = icmp eq i32 [[IV_NEXT_3]], 1024
; CHECK-NEXT: br i1 [[CMP_4]], label [[EXIT:%.*]], label [[LOOP]] ; CHECK-NEXT: br i1 [[CMP_4]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit: ; CHECK: exit:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
br label %loop br label %loop
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llvm/test/Transforms/LoopUnroll/full-unroll-keep-first-exit.ll

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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr i32, ptr [[P:%.*]], i32 [[N]] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr i32, ptr [[P:%.*]], i32 [[N]]
; CHECK-NEXT: store i32 [[N]], ptr [[ARRAYIDX]], align 4 ; CHECK-NEXT: store i32 [[N]], ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[INC:%.*]] = add i32 [[N]], 1 ; CHECK-NEXT: [[INC:%.*]] = add i32 [[N]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[N]], [[ADD]] ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[N]], [[ADD]]
; CHECK-NEXT: br i1 [[CMP]], label [[DO_BODY_1:%.*]], label [[DO_END:%.*]] ; CHECK-NEXT: br i1 [[CMP]], label [[DO_BODY_1:%.*]], label [[DO_END:%.*]]
; CHECK: do.body.1: ; CHECK: do.body.1:
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr i32, ptr [[P]], i32 [[INC]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr i32, ptr [[P]], i32 [[INC]]
; CHECK-NEXT: store i32 [[INC]], ptr [[ARRAYIDX_1]], align 4 ; CHECK-NEXT: store i32 [[INC]], ptr [[ARRAYIDX_1]], align 4
; CHECK-NEXT: [[INC_1:%.*]] = add i32 [[INC]], 1 ; CHECK-NEXT: [[INC_1:%.*]] = add i32 [[N]], 2
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr i32, ptr [[P]], i32 [[INC_1]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr i32, ptr [[P]], i32 [[INC_1]]
; CHECK-NEXT: store i32 [[INC_1]], ptr [[ARRAYIDX_2]], align 4 ; CHECK-NEXT: store i32 [[INC_1]], ptr [[ARRAYIDX_2]], align 4
; CHECK-NEXT: br label [[DO_END]] ; CHECK-NEXT: br label [[DO_END]]
; CHECK: do.end: ; CHECK: do.end:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%add = add i32 %n, 2 %add = add i32 %n, 2
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr i32, ptr [[P:%.*]], i32 [[N]] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr i32, ptr [[P:%.*]], i32 [[N]]
; CHECK-NEXT: store i32 [[N]], ptr [[ARRAYIDX]], align 4 ; CHECK-NEXT: store i32 [[N]], ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[INC:%.*]] = add i32 [[N]], 1 ; CHECK-NEXT: [[INC:%.*]] = add i32 [[N]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[N]], [[ADD]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[N]], [[ADD]]
; CHECK-NEXT: br i1 [[CMP]], label [[DO_BODY_1:%.*]], label [[DO_END:%.*]] ; CHECK-NEXT: br i1 [[CMP]], label [[DO_BODY_1:%.*]], label [[DO_END:%.*]]
; CHECK: do.body.1: ; CHECK: do.body.1:
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr i32, ptr [[P]], i32 [[INC]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr i32, ptr [[P]], i32 [[INC]]
; CHECK-NEXT: store i32 [[INC]], ptr [[ARRAYIDX_1]], align 4 ; CHECK-NEXT: store i32 [[INC]], ptr [[ARRAYIDX_1]], align 4
; CHECK-NEXT: [[INC_1:%.*]] = add i32 [[INC]], 1 ; CHECK-NEXT: [[INC_1:%.*]] = add i32 [[N]], 2
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr i32, ptr [[P]], i32 [[INC_1]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr i32, ptr [[P]], i32 [[INC_1]]
; CHECK-NEXT: store i32 [[INC_1]], ptr [[ARRAYIDX_2]], align 4 ; CHECK-NEXT: store i32 [[INC_1]], ptr [[ARRAYIDX_2]], align 4
; CHECK-NEXT: br label [[DO_END]] ; CHECK-NEXT: br label [[DO_END]]
; CHECK: do.end: ; CHECK: do.end:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%add = add i32 %n, 2 %add = add i32 %n, 2
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llvm/test/Transforms/LoopUnroll/nonlatchcondbr.ll

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; CHECK-NEXT: br i1 true, label [[FOR_BODY:%.*]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE:%.*]] ; CHECK-NEXT: br i1 true, label [[FOR_BODY:%.*]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE:%.*]]
; CHECK: for.body: ; CHECK: for.body:
; CHECK-NEXT: [[CMP:%.*]] = call i1 @foo(i64 [[I]]) ; CHECK-NEXT: [[CMP:%.*]] = call i1 @foo(i64 [[I]])
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE]], label [[FOR_END_LOOPEXIT:%.*]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE]], label [[FOR_END_LOOPEXIT:%.*]]
; CHECK: for.body.for.body_crit_edge: ; CHECK: for.body.for.body_crit_edge:
; CHECK-NEXT: [[ARRAYIDX_PHI_TRANS_INSERT:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INC]] ; CHECK-NEXT: [[ARRAYIDX_PHI_TRANS_INSERT:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INC]]
; CHECK-NEXT: [[DOTPRE:%.*]] = load i32, ptr [[ARRAYIDX_PHI_TRANS_INSERT]], align 4 ; CHECK-NEXT: [[DOTPRE:%.*]] = load i32, ptr [[ARRAYIDX_PHI_TRANS_INSERT]], align 4
; CHECK-NEXT: call void @bar(i32 [[DOTPRE]]) ; CHECK-NEXT: call void @bar(i32 [[DOTPRE]])
; CHECK-NEXT: [[INC_1:%.*]] = add nuw nsw i64 [[INC]], 1 ; CHECK-NEXT: [[INC_1:%.*]] = add nuw nsw i64 [[I]], 2
; CHECK-NEXT: br i1 true, label [[FOR_BODY_1:%.*]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE_1:%.*]] ; CHECK-NEXT: br i1 true, label [[FOR_BODY_1:%.*]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE_1:%.*]]
; CHECK: for.body.1: ; CHECK: for.body.1:
; CHECK-NEXT: [[CMP_1:%.*]] = call i1 @foo(i64 [[INC]]) ; CHECK-NEXT: [[CMP_1:%.*]] = call i1 @foo(i64 [[INC]])
; CHECK-NEXT: br i1 [[CMP_1]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE_1]], label [[FOR_END_LOOPEXIT]] ; CHECK-NEXT: br i1 [[CMP_1]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE_1]], label [[FOR_END_LOOPEXIT]]
; CHECK: for.body.for.body_crit_edge.1: ; CHECK: for.body.for.body_crit_edge.1:
; CHECK-NEXT: [[ARRAYIDX_PHI_TRANS_INSERT_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INC_1]] ; CHECK-NEXT: [[ARRAYIDX_PHI_TRANS_INSERT_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INC_1]]
; CHECK-NEXT: [[DOTPRE_1:%.*]] = load i32, ptr [[ARRAYIDX_PHI_TRANS_INSERT_1]], align 4 ; CHECK-NEXT: [[DOTPRE_1:%.*]] = load i32, ptr [[ARRAYIDX_PHI_TRANS_INSERT_1]], align 4
; CHECK-NEXT: call void @bar(i32 [[DOTPRE_1]]) ; CHECK-NEXT: call void @bar(i32 [[DOTPRE_1]])
; CHECK-NEXT: [[INC_2:%.*]] = add nuw nsw i64 [[INC_1]], 1 ; CHECK-NEXT: [[INC_2:%.*]] = add nuw nsw i64 [[I]], 3
; CHECK-NEXT: br i1 true, label [[FOR_BODY_2:%.*]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE_2:%.*]] ; CHECK-NEXT: br i1 true, label [[FOR_BODY_2:%.*]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE_2:%.*]]
; CHECK: for.body.2: ; CHECK: for.body.2:
; CHECK-NEXT: [[CMP_2:%.*]] = call i1 @foo(i64 [[INC_1]]) ; CHECK-NEXT: [[CMP_2:%.*]] = call i1 @foo(i64 [[INC_1]])
; CHECK-NEXT: br i1 [[CMP_2]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE_2]], label [[FOR_END_LOOPEXIT]] ; CHECK-NEXT: br i1 [[CMP_2]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE_2]], label [[FOR_END_LOOPEXIT]]
; CHECK: for.body.for.body_crit_edge.2: ; CHECK: for.body.for.body_crit_edge.2:
; CHECK-NEXT: [[ARRAYIDX_PHI_TRANS_INSERT_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INC_2]] ; CHECK-NEXT: [[ARRAYIDX_PHI_TRANS_INSERT_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INC_2]]
; CHECK-NEXT: [[DOTPRE_2:%.*]] = load i32, ptr [[ARRAYIDX_PHI_TRANS_INSERT_2]], align 4 ; CHECK-NEXT: [[DOTPRE_2:%.*]] = load i32, ptr [[ARRAYIDX_PHI_TRANS_INSERT_2]], align 4
; CHECK-NEXT: call void @bar(i32 [[DOTPRE_2]]) ; CHECK-NEXT: call void @bar(i32 [[DOTPRE_2]])
; CHECK-NEXT: [[INC_3]] = add nsw i64 [[INC_2]], 1 ; CHECK-NEXT: [[INC_3]] = add nsw i64 [[I]], 4
; CHECK-NEXT: br i1 true, label [[FOR_BODY_3:%.*]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE_3]] ; CHECK-NEXT: br i1 true, label [[FOR_BODY_3:%.*]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE_3]]
; CHECK: for.body.3: ; CHECK: for.body.3:
; CHECK-NEXT: [[CMP_3:%.*]] = call i1 @foo(i64 [[INC_2]]) ; CHECK-NEXT: [[CMP_3:%.*]] = call i1 @foo(i64 [[INC_2]])
; CHECK-NEXT: br i1 [[CMP_3]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE_3]], label [[FOR_END_LOOPEXIT]] ; CHECK-NEXT: br i1 [[CMP_3]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE_3]], label [[FOR_END_LOOPEXIT]]
; CHECK: for.body.for.body_crit_edge.3: ; CHECK: for.body.for.body_crit_edge.3:
; CHECK-NEXT: [[ARRAYIDX_PHI_TRANS_INSERT_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INC_3]] ; CHECK-NEXT: [[ARRAYIDX_PHI_TRANS_INSERT_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INC_3]]
; CHECK-NEXT: [[DOTPRE_3]] = load i32, ptr [[ARRAYIDX_PHI_TRANS_INSERT_3]], align 4 ; CHECK-NEXT: [[DOTPRE_3]] = load i32, ptr [[ARRAYIDX_PHI_TRANS_INSERT_3]], align 4
; CHECK-NEXT: br label [[FOR_HEADER]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK-NEXT: br label [[FOR_HEADER]], !llvm.loop [[LOOP0:![0-9]+]]
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llvm/test/Transforms/LoopUnroll/partial-unroll-non-latch-exit.ll

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; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i64, ptr [[A2:%.*]], i64 [[IV]] ; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i64, ptr [[A2:%.*]], i64 [[IV]]
; CHECK-NEXT: [[LOAD1:%.*]] = load i64, ptr [[GEP1]], align 8 ; CHECK-NEXT: [[LOAD1:%.*]] = load i64, ptr [[GEP1]], align 8
; CHECK-NEXT: [[LOAD2:%.*]] = load i64, ptr [[GEP2]], align 8 ; CHECK-NEXT: [[LOAD2:%.*]] = load i64, ptr [[GEP2]], align 8
; CHECK-NEXT: [[EXITCOND2:%.*]] = icmp eq i64 [[LOAD1]], [[LOAD2]] ; CHECK-NEXT: [[EXITCOND2:%.*]] = icmp eq i64 [[LOAD1]], [[LOAD2]]
; CHECK-NEXT: br i1 [[EXITCOND2]], label [[LOOP_1:%.*]], label [[EXIT:%.*]] ; CHECK-NEXT: br i1 [[EXITCOND2]], label [[LOOP_1:%.*]], label [[EXIT:%.*]]
; CHECK: loop.1: ; CHECK: loop.1:
; CHECK-NEXT: br label [[LATCH_1:%.*]] ; CHECK-NEXT: br label [[LATCH_1:%.*]]
; CHECK: latch.1: ; CHECK: latch.1:
; CHECK-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV_NEXT]], 1 ; CHECK-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV]], 2
; CHECK-NEXT: [[GEP1_1:%.*]] = getelementptr inbounds i64, ptr [[A1]], i64 [[IV_NEXT]] ; CHECK-NEXT: [[GEP1_1:%.*]] = getelementptr inbounds i64, ptr [[A1]], i64 [[IV_NEXT]]
; CHECK-NEXT: [[GEP2_1:%.*]] = getelementptr inbounds i64, ptr [[A2]], i64 [[IV_NEXT]] ; CHECK-NEXT: [[GEP2_1:%.*]] = getelementptr inbounds i64, ptr [[A2]], i64 [[IV_NEXT]]
; CHECK-NEXT: [[LOAD1_1:%.*]] = load i64, ptr [[GEP1_1]], align 8 ; CHECK-NEXT: [[LOAD1_1:%.*]] = load i64, ptr [[GEP1_1]], align 8
; CHECK-NEXT: [[LOAD2_1:%.*]] = load i64, ptr [[GEP2_1]], align 8 ; CHECK-NEXT: [[LOAD2_1:%.*]] = load i64, ptr [[GEP2_1]], align 8
; CHECK-NEXT: [[EXITCOND2_1:%.*]] = icmp eq i64 [[LOAD1_1]], [[LOAD2_1]] ; CHECK-NEXT: [[EXITCOND2_1:%.*]] = icmp eq i64 [[LOAD1_1]], [[LOAD2_1]]
; CHECK-NEXT: br i1 [[EXITCOND2_1]], label [[LOOP_2:%.*]], label [[EXIT]] ; CHECK-NEXT: br i1 [[EXITCOND2_1]], label [[LOOP_2:%.*]], label [[EXIT]]
; CHECK: loop.2: ; CHECK: loop.2:
; CHECK-NEXT: br label [[LATCH_2:%.*]] ; CHECK-NEXT: br label [[LATCH_2:%.*]]
; CHECK: latch.2: ; CHECK: latch.2:
; CHECK-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV_NEXT_1]], 1 ; CHECK-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV]], 3
; CHECK-NEXT: [[GEP1_2:%.*]] = getelementptr inbounds i64, ptr [[A1]], i64 [[IV_NEXT_1]] ; CHECK-NEXT: [[GEP1_2:%.*]] = getelementptr inbounds i64, ptr [[A1]], i64 [[IV_NEXT_1]]
; CHECK-NEXT: [[GEP2_2:%.*]] = getelementptr inbounds i64, ptr [[A2]], i64 [[IV_NEXT_1]] ; CHECK-NEXT: [[GEP2_2:%.*]] = getelementptr inbounds i64, ptr [[A2]], i64 [[IV_NEXT_1]]
; CHECK-NEXT: [[LOAD1_2:%.*]] = load i64, ptr [[GEP1_2]], align 8 ; CHECK-NEXT: [[LOAD1_2:%.*]] = load i64, ptr [[GEP1_2]], align 8
; CHECK-NEXT: [[LOAD2_2:%.*]] = load i64, ptr [[GEP2_2]], align 8 ; CHECK-NEXT: [[LOAD2_2:%.*]] = load i64, ptr [[GEP2_2]], align 8
; CHECK-NEXT: [[EXITCOND2_2:%.*]] = icmp eq i64 [[LOAD1_2]], [[LOAD2_2]] ; CHECK-NEXT: [[EXITCOND2_2:%.*]] = icmp eq i64 [[LOAD1_2]], [[LOAD2_2]]
; CHECK-NEXT: br i1 [[EXITCOND2_2]], label [[LOOP_3:%.*]], label [[EXIT]] ; CHECK-NEXT: br i1 [[EXITCOND2_2]], label [[LOOP_3:%.*]], label [[EXIT]]
; CHECK: loop.3: ; CHECK: loop.3:
; CHECK-NEXT: br label [[LATCH_3:%.*]] ; CHECK-NEXT: br label [[LATCH_3:%.*]]
; CHECK: latch.3: ; CHECK: latch.3:
; CHECK-NEXT: [[IV_NEXT_3:%.*]] = add nuw nsw i64 [[IV_NEXT_2]], 1 ; CHECK-NEXT: [[IV_NEXT_3:%.*]] = add nuw nsw i64 [[IV]], 4
; CHECK-NEXT: [[GEP1_3:%.*]] = getelementptr inbounds i64, ptr [[A1]], i64 [[IV_NEXT_2]] ; CHECK-NEXT: [[GEP1_3:%.*]] = getelementptr inbounds i64, ptr [[A1]], i64 [[IV_NEXT_2]]
; CHECK-NEXT: [[GEP2_3:%.*]] = getelementptr inbounds i64, ptr [[A2]], i64 [[IV_NEXT_2]] ; CHECK-NEXT: [[GEP2_3:%.*]] = getelementptr inbounds i64, ptr [[A2]], i64 [[IV_NEXT_2]]
; CHECK-NEXT: [[LOAD1_3:%.*]] = load i64, ptr [[GEP1_3]], align 8 ; CHECK-NEXT: [[LOAD1_3:%.*]] = load i64, ptr [[GEP1_3]], align 8
; CHECK-NEXT: [[LOAD2_3:%.*]] = load i64, ptr [[GEP2_3]], align 8 ; CHECK-NEXT: [[LOAD2_3:%.*]] = load i64, ptr [[GEP2_3]], align 8
; CHECK-NEXT: [[EXITCOND2_3:%.*]] = icmp eq i64 [[LOAD1_3]], [[LOAD2_3]] ; CHECK-NEXT: [[EXITCOND2_3:%.*]] = icmp eq i64 [[LOAD1_3]], [[LOAD2_3]]
; CHECK-NEXT: br i1 [[EXITCOND2_3]], label [[LOOP_4:%.*]], label [[EXIT]] ; CHECK-NEXT: br i1 [[EXITCOND2_3]], label [[LOOP_4:%.*]], label [[EXIT]]
; CHECK: loop.4: ; CHECK: loop.4:
; CHECK-NEXT: [[EXITCOND_4:%.*]] = icmp eq i64 [[IV_NEXT_3]], 24 ; CHECK-NEXT: [[EXITCOND_4:%.*]] = icmp eq i64 [[IV_NEXT_3]], 24
; CHECK-NEXT: br i1 [[EXITCOND_4]], label [[EXIT]], label [[LATCH_4]] ; CHECK-NEXT: br i1 [[EXITCOND_4]], label [[EXIT]], label [[LATCH_4]]
; CHECK: latch.4: ; CHECK: latch.4:
; CHECK-NEXT: [[IV_NEXT_4]] = add nuw nsw i64 [[IV_NEXT_3]], 1 ; CHECK-NEXT: [[IV_NEXT_4]] = add nuw nsw i64 [[IV]], 5
; CHECK-NEXT: [[GEP1_4:%.*]] = getelementptr inbounds i64, ptr [[A1]], i64 [[IV_NEXT_3]] ; CHECK-NEXT: [[GEP1_4:%.*]] = getelementptr inbounds i64, ptr [[A1]], i64 [[IV_NEXT_3]]
; CHECK-NEXT: [[GEP2_4:%.*]] = getelementptr inbounds i64, ptr [[A2]], i64 [[IV_NEXT_3]] ; CHECK-NEXT: [[GEP2_4:%.*]] = getelementptr inbounds i64, ptr [[A2]], i64 [[IV_NEXT_3]]
; CHECK-NEXT: [[LOAD1_4:%.*]] = load i64, ptr [[GEP1_4]], align 8 ; CHECK-NEXT: [[LOAD1_4:%.*]] = load i64, ptr [[GEP1_4]], align 8
; CHECK-NEXT: [[LOAD2_4:%.*]] = load i64, ptr [[GEP2_4]], align 8 ; CHECK-NEXT: [[LOAD2_4:%.*]] = load i64, ptr [[GEP2_4]], align 8
; CHECK-NEXT: [[EXITCOND2_4:%.*]] = icmp eq i64 [[LOAD1_4]], [[LOAD2_4]] ; CHECK-NEXT: [[EXITCOND2_4:%.*]] = icmp eq i64 [[LOAD1_4]], [[LOAD2_4]]
; CHECK-NEXT: br i1 [[EXITCOND2_4]], label [[LOOP]], label [[EXIT]] ; CHECK-NEXT: br i1 [[EXITCOND2_4]], label [[LOOP]], label [[EXIT]]
; CHECK: exit: ; CHECK: exit:
; CHECK-NEXT: [[EXIT_VAL:%.*]] = phi i1 [ false, [[LATCH]] ], [ false, [[LATCH_1]] ], [ false, [[LATCH_2]] ], [ false, [[LATCH_3]] ], [ true, [[LOOP_4]] ], [ false, [[LATCH_4]] ] ; CHECK-NEXT: [[EXIT_VAL:%.*]] = phi i1 [ false, [[LATCH]] ], [ false, [[LATCH_1]] ], [ false, [[LATCH_2]] ], [ false, [[LATCH_3]] ], [ true, [[LOOP_4]] ], [ false, [[LATCH_4]] ]
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llvm/test/Transforms/LoopUnroll/partially-unroll-unconditional-latch.ll

Show All 13 Lines
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_NEXT_3:%.*]], [[FOR_LATCH_3]] ] ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_NEXT_3:%.*]], [[FOR_LATCH_3]] ]
; CHECK-NEXT: [[RED_NEXT:%.*]] = add nuw nsw i32 10, [[RED]] ; CHECK-NEXT: [[RED_NEXT:%.*]] = add nuw nsw i32 10, [[RED]]
; CHECK-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 2 ; CHECK-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 2
; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 [[IV_NEXT]] ; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 [[IV_NEXT]]
; CHECK-NEXT: store i32 [[RED_NEXT]], ptr [[PTR]], align 4 ; CHECK-NEXT: store i32 [[RED_NEXT]], ptr [[PTR]], align 4
; CHECK-NEXT: br label [[FOR_LATCH:%.*]] ; CHECK-NEXT: br label [[FOR_LATCH:%.*]]
; CHECK: for.latch: ; CHECK: for.latch:
; CHECK-NEXT: [[RED_NEXT_1:%.*]] = add nuw nsw i32 10, [[RED_NEXT]] ; CHECK-NEXT: [[RED_NEXT_1:%.*]] = add nuw nsw i32 10, [[RED_NEXT]]
; CHECK-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV_NEXT]], 2 ; CHECK-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV]], 4
; CHECK-NEXT: [[PTR_1:%.*]] = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 [[IV_NEXT_1]] ; CHECK-NEXT: [[PTR_1:%.*]] = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 [[IV_NEXT_1]]
; CHECK-NEXT: store i32 [[RED_NEXT_1]], ptr [[PTR_1]], align 4 ; CHECK-NEXT: store i32 [[RED_NEXT_1]], ptr [[PTR_1]], align 4
; CHECK-NEXT: br label [[FOR_LATCH_1:%.*]] ; CHECK-NEXT: br label [[FOR_LATCH_1:%.*]]
; CHECK: for.latch.1: ; CHECK: for.latch.1:
; CHECK-NEXT: [[RED_NEXT_2:%.*]] = add nuw nsw i32 10, [[RED_NEXT_1]] ; CHECK-NEXT: [[RED_NEXT_2:%.*]] = add nuw nsw i32 10, [[RED_NEXT_1]]
; CHECK-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV_NEXT_1]], 2 ; CHECK-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV]], 6
; CHECK-NEXT: [[PTR_2:%.*]] = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 [[IV_NEXT_2]] ; CHECK-NEXT: [[PTR_2:%.*]] = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 [[IV_NEXT_2]]
; CHECK-NEXT: store i32 [[RED_NEXT_2]], ptr [[PTR_2]], align 4 ; CHECK-NEXT: store i32 [[RED_NEXT_2]], ptr [[PTR_2]], align 4
; CHECK-NEXT: br label [[FOR_LATCH_2:%.*]] ; CHECK-NEXT: br label [[FOR_LATCH_2:%.*]]
; CHECK: for.latch.2: ; CHECK: for.latch.2:
; CHECK-NEXT: [[RED_NEXT_3]] = add nuw nsw i32 10, [[RED_NEXT_2]] ; CHECK-NEXT: [[RED_NEXT_3]] = add nuw nsw i32 10, [[RED_NEXT_2]]
; CHECK-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV_NEXT_2]], 2 ; CHECK-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 8
; CHECK-NEXT: [[PTR_3:%.*]] = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 [[IV_NEXT_3]] ; CHECK-NEXT: [[PTR_3:%.*]] = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 [[IV_NEXT_3]]
; CHECK-NEXT: store i32 [[RED_NEXT_3]], ptr [[PTR_3]], align 4 ; CHECK-NEXT: store i32 [[RED_NEXT_3]], ptr [[PTR_3]], align 4
; CHECK-NEXT: [[EXITCOND_1_I_3:%.*]] = icmp eq i64 [[IV_NEXT_3]], 344 ; CHECK-NEXT: [[EXITCOND_1_I_3:%.*]] = icmp eq i64 [[IV_NEXT_3]], 344
; CHECK-NEXT: br i1 [[EXITCOND_1_I_3]], label [[EXIT:%.*]], label [[FOR_LATCH_3]] ; CHECK-NEXT: br i1 [[EXITCOND_1_I_3]], label [[EXIT:%.*]], label [[FOR_LATCH_3]]
; CHECK: for.latch.3: ; CHECK: for.latch.3:
; CHECK-NEXT: br label [[FOR_HEADER]] ; CHECK-NEXT: br label [[FOR_HEADER]]
; CHECK: exit: ; CHECK: exit:
; CHECK-NEXT: ret i32 0 ; CHECK-NEXT: ret i32 0
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llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll

Show All 21 Lines
; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], 7 ; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], 7
; CHECK-NEXT: br i1 [[TMP3]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[OUTER_HEADER_NEW:%.*]] ; CHECK-NEXT: br i1 [[TMP3]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[OUTER_HEADER_NEW:%.*]]
; CHECK: outer.header.new: ; CHECK: outer.header.new:
; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[TMP1]], [[XTRAITER]] ; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[TMP1]], [[XTRAITER]]
; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]] ; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]]
; CHECK: inner.1.header: ; CHECK: inner.1.header:
; CHECK-NEXT: [[INNER_1_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER_NEW]] ], [ [[INNER_1_IV_NEXT_7:%.*]], [[INNER_1_LATCH_7:%.*]] ] ; CHECK-NEXT: [[INNER_1_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER_NEW]] ], [ [[INNER_1_IV_NEXT_7:%.*]], [[INNER_1_LATCH_7:%.*]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[OUTER_HEADER_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[INNER_1_LATCH_7]] ] ; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[OUTER_HEADER_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[INNER_1_LATCH_7]] ]
; CHECK-NEXT: [[INNER_1_IV_NEXT:%.*]] = add nuw nsw i64 [[INNER_1_IV]], 1
; CHECK-NEXT: [[V:%.*]] = call i32 @get() ; CHECK-NEXT: [[V:%.*]] = call i32 @get()
; CHECK-NEXT: [[C_1:%.*]] = icmp ugt i32 [[V]], 0 ; CHECK-NEXT: [[C_1:%.*]] = icmp ugt i32 [[V]], 0
; CHECK-NEXT: br i1 [[C_1]], label [[INNER_1_LATCH:%.*]], label [[EXIT_DEOPT_LOOPEXIT:%.*]] ; CHECK-NEXT: br i1 [[C_1]], label [[INNER_1_LATCH:%.*]], label [[EXIT_DEOPT_LOOPEXIT:%.*]]
; CHECK: inner.1.latch: ; CHECK: inner.1.latch:
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1
; CHECK-NEXT: [[INNER_1_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT]], 1
; CHECK-NEXT: [[V_1:%.*]] = call i32 @get() ; CHECK-NEXT: [[V_1:%.*]] = call i32 @get()
; CHECK-NEXT: [[C_1_1:%.*]] = icmp ugt i32 [[V_1]], 0 ; CHECK-NEXT: [[C_1_1:%.*]] = icmp ugt i32 [[V_1]], 0
; CHECK-NEXT: br i1 [[C_1_1]], label [[INNER_1_LATCH_1:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] ; CHECK-NEXT: br i1 [[C_1_1]], label [[INNER_1_LATCH_1:%.*]], label [[EXIT_DEOPT_LOOPEXIT]]
; CHECK: inner.1.latch.1: ; CHECK: inner.1.latch.1:
; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i64 [[NITER_NEXT]], 1
; CHECK-NEXT: [[INNER_1_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_1]], 1
; CHECK-NEXT: [[V_2:%.*]] = call i32 @get() ; CHECK-NEXT: [[V_2:%.*]] = call i32 @get()
; CHECK-NEXT: [[C_1_2:%.*]] = icmp ugt i32 [[V_2]], 0 ; CHECK-NEXT: [[C_1_2:%.*]] = icmp ugt i32 [[V_2]], 0
; CHECK-NEXT: br i1 [[C_1_2]], label [[INNER_1_LATCH_2:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] ; CHECK-NEXT: br i1 [[C_1_2]], label [[INNER_1_LATCH_2:%.*]], label [[EXIT_DEOPT_LOOPEXIT]]
; CHECK: inner.1.latch.2: ; CHECK: inner.1.latch.2:
; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i64 [[NITER_NEXT_1]], 1
; CHECK-NEXT: [[INNER_1_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_2]], 1
; CHECK-NEXT: [[V_3:%.*]] = call i32 @get() ; CHECK-NEXT: [[V_3:%.*]] = call i32 @get()
; CHECK-NEXT: [[C_1_3:%.*]] = icmp ugt i32 [[V_3]], 0 ; CHECK-NEXT: [[C_1_3:%.*]] = icmp ugt i32 [[V_3]], 0
; CHECK-NEXT: br i1 [[C_1_3]], label [[INNER_1_LATCH_3:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] ; CHECK-NEXT: br i1 [[C_1_3]], label [[INNER_1_LATCH_3:%.*]], label [[EXIT_DEOPT_LOOPEXIT]]
; CHECK: inner.1.latch.3: ; CHECK: inner.1.latch.3:
; CHECK-NEXT: [[NITER_NEXT_3:%.*]] = add nuw nsw i64 [[NITER_NEXT_2]], 1
; CHECK-NEXT: [[INNER_1_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_3]], 1
; CHECK-NEXT: [[V_4:%.*]] = call i32 @get() ; CHECK-NEXT: [[V_4:%.*]] = call i32 @get()
; CHECK-NEXT: [[C_1_4:%.*]] = icmp ugt i32 [[V_4]], 0 ; CHECK-NEXT: [[C_1_4:%.*]] = icmp ugt i32 [[V_4]], 0
; CHECK-NEXT: br i1 [[C_1_4]], label [[INNER_1_LATCH_4:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] ; CHECK-NEXT: br i1 [[C_1_4]], label [[INNER_1_LATCH_4:%.*]], label [[EXIT_DEOPT_LOOPEXIT]]
; CHECK: inner.1.latch.4: ; CHECK: inner.1.latch.4:
; CHECK-NEXT: [[NITER_NEXT_4:%.*]] = add nuw nsw i64 [[NITER_NEXT_3]], 1
; CHECK-NEXT: [[INNER_1_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_4]], 1
; CHECK-NEXT: [[V_5:%.*]] = call i32 @get() ; CHECK-NEXT: [[V_5:%.*]] = call i32 @get()
; CHECK-NEXT: [[C_1_5:%.*]] = icmp ugt i32 [[V_5]], 0 ; CHECK-NEXT: [[C_1_5:%.*]] = icmp ugt i32 [[V_5]], 0
; CHECK-NEXT: br i1 [[C_1_5]], label [[INNER_1_LATCH_5:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] ; CHECK-NEXT: br i1 [[C_1_5]], label [[INNER_1_LATCH_5:%.*]], label [[EXIT_DEOPT_LOOPEXIT]]
; CHECK: inner.1.latch.5: ; CHECK: inner.1.latch.5:
; CHECK-NEXT: [[NITER_NEXT_5:%.*]] = add nuw nsw i64 [[NITER_NEXT_4]], 1
; CHECK-NEXT: [[INNER_1_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_5]], 1
; CHECK-NEXT: [[V_6:%.*]] = call i32 @get() ; CHECK-NEXT: [[V_6:%.*]] = call i32 @get()
; CHECK-NEXT: [[C_1_6:%.*]] = icmp ugt i32 [[V_6]], 0 ; CHECK-NEXT: [[C_1_6:%.*]] = icmp ugt i32 [[V_6]], 0
; CHECK-NEXT: br i1 [[C_1_6]], label [[INNER_1_LATCH_6:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] ; CHECK-NEXT: br i1 [[C_1_6]], label [[INNER_1_LATCH_6:%.*]], label [[EXIT_DEOPT_LOOPEXIT]]
; CHECK: inner.1.latch.6: ; CHECK: inner.1.latch.6:
; CHECK-NEXT: [[NITER_NEXT_6:%.*]] = add nuw nsw i64 [[NITER_NEXT_5]], 1 ; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add nuw nsw i64 [[INNER_1_IV]], 8
; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add nuw nsw i64 [[INNER_1_IV_NEXT_6]], 1
; CHECK-NEXT: [[V_7:%.*]] = call i32 @get() ; CHECK-NEXT: [[V_7:%.*]] = call i32 @get()
; CHECK-NEXT: [[C_1_7:%.*]] = icmp ugt i32 [[V_7]], 0 ; CHECK-NEXT: [[C_1_7:%.*]] = icmp ugt i32 [[V_7]], 0
; CHECK-NEXT: br i1 [[C_1_7]], label [[INNER_1_LATCH_7]], label [[EXIT_DEOPT_LOOPEXIT]] ; CHECK-NEXT: br i1 [[C_1_7]], label [[INNER_1_LATCH_7]], label [[EXIT_DEOPT_LOOPEXIT]]
; CHECK: inner.1.latch.7: ; CHECK: inner.1.latch.7:
; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER_NEXT_6]], 1 ; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp ne i64 [[NITER_NEXT_7]], [[UNROLL_ITER]] ; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp ne i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[INNER_1_HEADER]], label [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT:%.*]] ; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[INNER_1_HEADER]], label [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT:%.*]]
; CHECK: outer.middle.unr-lcssa.loopexit: ; CHECK: outer.middle.unr-lcssa.loopexit:
; CHECK-NEXT: [[V_LCSSA1_PH_PH:%.*]] = phi i32 [ [[V_7]], [[INNER_1_LATCH_7]] ] ; CHECK-NEXT: [[V_LCSSA1_PH_PH:%.*]] = phi i32 [ [[V_7]], [[INNER_1_LATCH_7]] ]
; CHECK-NEXT: [[INNER_1_IV_UNR_PH:%.*]] = phi i64 [ [[INNER_1_IV_NEXT_7]], [[INNER_1_LATCH_7]] ] ; CHECK-NEXT: [[INNER_1_IV_UNR_PH:%.*]] = phi i64 [ [[INNER_1_IV_NEXT_7]], [[INNER_1_LATCH_7]] ]
; CHECK-NEXT: br label [[OUTER_MIDDLE_UNR_LCSSA]] ; CHECK-NEXT: br label [[OUTER_MIDDLE_UNR_LCSSA]]
; CHECK: outer.middle.unr-lcssa: ; CHECK: outer.middle.unr-lcssa:
; CHECK-NEXT: [[V_LCSSA1_PH:%.*]] = phi i32 [ undef, [[OUTER_HEADER]] ], [ [[V_LCSSA1_PH_PH]], [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT]] ] ; CHECK-NEXT: [[V_LCSSA1_PH:%.*]] = phi i32 [ undef, [[OUTER_HEADER]] ], [ [[V_LCSSA1_PH_PH]], [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT]] ]
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; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]] ; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]]
; CHECK: inner.1.header: ; CHECK: inner.1.header:
; CHECK-NEXT: [[INNER_1_IV:%.*]] = phi i64 [ [[INNER_1_IV_UNR]], [[OUTER_HEADER_NEW]] ], [ [[INNER_1_IV_NEXT_7:%.*]], [[INNER_1_LATCH_7:%.*]] ] ; CHECK-NEXT: [[INNER_1_IV:%.*]] = phi i64 [ [[INNER_1_IV_UNR]], [[OUTER_HEADER_NEW]] ], [ [[INNER_1_IV_NEXT_7:%.*]], [[INNER_1_LATCH_7:%.*]] ]
; CHECK-NEXT: [[CMP_1:%.*]] = icmp sgt i32 [[OUTER_P]], 0 ; CHECK-NEXT: [[CMP_1:%.*]] = icmp sgt i32 [[OUTER_P]], 0
; CHECK-NEXT: br i1 [[CMP_1]], label [[EXIT_DEOPT_LOOPEXIT:%.*]], label [[INNER_1_LATCH:%.*]] ; CHECK-NEXT: br i1 [[CMP_1]], label [[EXIT_DEOPT_LOOPEXIT:%.*]], label [[INNER_1_LATCH:%.*]]
; CHECK: inner.1.latch: ; CHECK: inner.1.latch:
; CHECK-NEXT: [[L_1:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: [[L_1:%.*]] = load i32, ptr [[SRC]], align 4
; CHECK-NEXT: store i32 [[L_1]], ptr [[DST]], align 8 ; CHECK-NEXT: store i32 [[L_1]], ptr [[DST]], align 8
; CHECK-NEXT: [[INNER_1_IV_NEXT:%.*]] = add i64 [[INNER_1_IV]], 1
; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_1:%.*]] ; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_1:%.*]]
; CHECK: inner.1.latch.1: ; CHECK: inner.1.latch.1:
; CHECK-NEXT: [[L_1_1:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: [[L_1_1:%.*]] = load i32, ptr [[SRC]], align 4
; CHECK-NEXT: store i32 [[L_1_1]], ptr [[DST]], align 8 ; CHECK-NEXT: store i32 [[L_1_1]], ptr [[DST]], align 8
; CHECK-NEXT: [[INNER_1_IV_NEXT_1:%.*]] = add i64 [[INNER_1_IV_NEXT]], 1
; CHECK-NEXT: [[CMP_1_2:%.*]] = icmp sgt i32 [[OUTER_P]], 0 ; CHECK-NEXT: [[CMP_1_2:%.*]] = icmp sgt i32 [[OUTER_P]], 0
; CHECK-NEXT: br i1 [[CMP_1_2]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_2:%.*]] ; CHECK-NEXT: br i1 [[CMP_1_2]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_2:%.*]]
; CHECK: inner.1.latch.2: ; CHECK: inner.1.latch.2:
; CHECK-NEXT: [[L_1_2:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: [[L_1_2:%.*]] = load i32, ptr [[SRC]], align 4
; CHECK-NEXT: store i32 [[L_1_2]], ptr [[DST]], align 8 ; CHECK-NEXT: store i32 [[L_1_2]], ptr [[DST]], align 8
; CHECK-NEXT: [[INNER_1_IV_NEXT_2:%.*]] = add i64 [[INNER_1_IV_NEXT_1]], 1
; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_3:%.*]] ; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_3:%.*]]
; CHECK: inner.1.latch.3: ; CHECK: inner.1.latch.3:
; CHECK-NEXT: [[L_1_3:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: [[L_1_3:%.*]] = load i32, ptr [[SRC]], align 4
; CHECK-NEXT: store i32 [[L_1_3]], ptr [[DST]], align 8 ; CHECK-NEXT: store i32 [[L_1_3]], ptr [[DST]], align 8
; CHECK-NEXT: [[INNER_1_IV_NEXT_3:%.*]] = add i64 [[INNER_1_IV_NEXT_2]], 1
; CHECK-NEXT: [[CMP_1_4:%.*]] = icmp sgt i32 [[OUTER_P]], 0 ; CHECK-NEXT: [[CMP_1_4:%.*]] = icmp sgt i32 [[OUTER_P]], 0
; CHECK-NEXT: br i1 [[CMP_1_4]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_4:%.*]] ; CHECK-NEXT: br i1 [[CMP_1_4]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_4:%.*]]
; CHECK: inner.1.latch.4: ; CHECK: inner.1.latch.4:
; CHECK-NEXT: [[L_1_4:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: [[L_1_4:%.*]] = load i32, ptr [[SRC]], align 4
; CHECK-NEXT: store i32 [[L_1_4]], ptr [[DST]], align 8 ; CHECK-NEXT: store i32 [[L_1_4]], ptr [[DST]], align 8
; CHECK-NEXT: [[INNER_1_IV_NEXT_4:%.*]] = add i64 [[INNER_1_IV_NEXT_3]], 1
; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_5:%.*]] ; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_5:%.*]]
; CHECK: inner.1.latch.5: ; CHECK: inner.1.latch.5:
; CHECK-NEXT: [[L_1_5:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: [[L_1_5:%.*]] = load i32, ptr [[SRC]], align 4
; CHECK-NEXT: store i32 [[L_1_5]], ptr [[DST]], align 8 ; CHECK-NEXT: store i32 [[L_1_5]], ptr [[DST]], align 8
; CHECK-NEXT: [[INNER_1_IV_NEXT_5:%.*]] = add i64 [[INNER_1_IV_NEXT_4]], 1
; CHECK-NEXT: [[CMP_1_6:%.*]] = icmp sgt i32 [[OUTER_P]], 0 ; CHECK-NEXT: [[CMP_1_6:%.*]] = icmp sgt i32 [[OUTER_P]], 0
; CHECK-NEXT: br i1 [[CMP_1_6]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_6:%.*]] ; CHECK-NEXT: br i1 [[CMP_1_6]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_6:%.*]]
; CHECK: inner.1.latch.6: ; CHECK: inner.1.latch.6:
; CHECK-NEXT: [[L_1_6:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: [[L_1_6:%.*]] = load i32, ptr [[SRC]], align 4
; CHECK-NEXT: store i32 [[L_1_6]], ptr [[DST]], align 8 ; CHECK-NEXT: store i32 [[L_1_6]], ptr [[DST]], align 8
; CHECK-NEXT: [[INNER_1_IV_NEXT_6:%.*]] = add i64 [[INNER_1_IV_NEXT_5]], 1 ; CHECK-NEXT: [[INNER_1_IV_NEXT_6:%.*]] = add i64 [[INNER_1_IV]], 7
; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_7]] ; CHECK-NEXT: br i1 false, label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_7]]
; CHECK: inner.1.latch.7: ; CHECK: inner.1.latch.7:
; CHECK-NEXT: [[L_1_7:%.*]] = load i32, ptr [[SRC]], align 4 ; CHECK-NEXT: [[L_1_7:%.*]] = load i32, ptr [[SRC]], align 4
; CHECK-NEXT: store i32 [[L_1_7]], ptr [[DST]], align 8 ; CHECK-NEXT: store i32 [[L_1_7]], ptr [[DST]], align 8
; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add i64 [[INNER_1_IV_NEXT_6]], 1 ; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add i64 [[INNER_1_IV]], 8
; CHECK-NEXT: [[CMP_2_7:%.*]] = icmp sgt i64 [[INNER_1_IV_NEXT_6]], 0 ; CHECK-NEXT: [[CMP_2_7:%.*]] = icmp sgt i64 [[INNER_1_IV_NEXT_6]], 0
; CHECK-NEXT: br i1 [[CMP_2_7]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[INNER_1_HEADER]], !prof [[PROF5:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP_2_7]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[INNER_1_HEADER]], !prof [[PROF5:![0-9]+]]
; CHECK: outer.middle.unr-lcssa: ; CHECK: outer.middle.unr-lcssa:
; CHECK-NEXT: [[L_1_LCSSA_PH:%.*]] = phi i32 [ [[L_1_7]], [[INNER_1_LATCH_7]] ] ; CHECK-NEXT: [[L_1_LCSSA_PH:%.*]] = phi i32 [ [[L_1_7]], [[INNER_1_LATCH_7]] ]
; CHECK-NEXT: br label [[OUTER_MIDDLE]] ; CHECK-NEXT: br label [[OUTER_MIDDLE]]
; CHECK: outer.middle: ; CHECK: outer.middle:
; CHECK-NEXT: [[L_1_LCSSA]] = phi i32 [ [[L_1_LCSSA_UNR]], [[INNER_1_HEADER_PROL_LOOPEXIT]] ], [ [[L_1_LCSSA_PH]], [[OUTER_MIDDLE_UNR_LCSSA]] ] ; CHECK-NEXT: [[L_1_LCSSA]] = phi i32 [ [[L_1_LCSSA_UNR]], [[INNER_1_HEADER_PROL_LOOPEXIT]] ], [ [[L_1_LCSSA_PH]], [[OUTER_MIDDLE_UNR_LCSSA]] ]
; CHECK-NEXT: br label [[INNER_2:%.*]] ; CHECK-NEXT: br label [[INNER_2:%.*]]
; CHECK: inner.2: ; CHECK: inner.2:
; CHECK-NEXT: [[INNER_2_IV:%.*]] = phi i32 [ [[L_1_LCSSA]], [[OUTER_MIDDLE]] ], [ [[INNER_2_IV_NEXT_2:%.*]], [[INNER_2]] ] ; CHECK-NEXT: [[INNER_2_IV:%.*]] = phi i32 [ [[L_1_LCSSA]], [[OUTER_MIDDLE]] ], [ [[INNER_2_IV_NEXT_2:%.*]], [[INNER_2]] ]
; CHECK-NEXT: [[TMP15:%.*]] = phi i32 [ 0, [[OUTER_MIDDLE]] ], [ [[TMP33_2:%.*]], [[INNER_2]] ] ; CHECK-NEXT: [[TMP15:%.*]] = phi i32 [ 0, [[OUTER_MIDDLE]] ], [ [[TMP33_2:%.*]], [[INNER_2]] ]
; CHECK-NEXT: [[L_2:%.*]] = load i32, ptr [[SRC]], align 8 ; CHECK-NEXT: [[L_2:%.*]] = load i32, ptr [[SRC]], align 8
; CHECK-NEXT: [[INNER_2_IV_NEXT:%.*]] = add i32 [[INNER_2_IV]], 1 ; CHECK-NEXT: [[INNER_2_IV_NEXT:%.*]] = add i32 [[INNER_2_IV]], 1
; CHECK-NEXT: [[TMP27:%.*]] = load ptr, ptr [[PTR_SRC:%.*]], align 8 ; CHECK-NEXT: [[TMP27:%.*]] = load ptr, ptr [[PTR_SRC:%.*]], align 8
; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[INNER_2_IV]], [[L_2]] ; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[INNER_2_IV]], [[L_2]]
; CHECK-NEXT: [[TMP281:%.*]] = call i32 @use.2(ptr [[TMP27]], i32 [[ADD_1]]) ; CHECK-NEXT: [[TMP281:%.*]] = call i32 @use.2(ptr [[TMP27]], i32 [[ADD_1]])
; CHECK-NEXT: [[TMP31:%.*]] = shl nuw nsw i32 [[TMP15]], 16 ; CHECK-NEXT: [[TMP31:%.*]] = shl nuw nsw i32 [[TMP15]], 16
; CHECK-NEXT: [[TMP32:%.*]] = add nuw i32 [[TMP31]], 262144
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: [[L_2_1:%.*]] = load i32, ptr [[SRC]], align 8 ; CHECK-NEXT: [[L_2_1:%.*]] = load i32, ptr [[SRC]], align 8
; CHECK-NEXT: [[INNER_2_IV_NEXT_1:%.*]] = add i32 [[INNER_2_IV_NEXT]], 1 ; CHECK-NEXT: [[INNER_2_IV_NEXT_1:%.*]] = add i32 [[INNER_2_IV]], 2
; CHECK-NEXT: [[TMP27_1:%.*]] = load ptr, ptr [[PTR_SRC]], align 8 ; CHECK-NEXT: [[TMP27_1:%.*]] = load ptr, ptr [[PTR_SRC]], align 8
; CHECK-NEXT: [[ADD_1_1:%.*]] = add i32 [[INNER_2_IV_NEXT]], [[L_2_1]] ; CHECK-NEXT: [[ADD_1_1:%.*]] = add i32 [[INNER_2_IV_NEXT]], [[L_2_1]]
; CHECK-NEXT: [[TMP281_1:%.*]] = call i32 @use.2(ptr [[TMP27_1]], i32 [[ADD_1_1]]) ; CHECK-NEXT: [[TMP281_1:%.*]] = call i32 @use.2(ptr [[TMP27_1]], i32 [[ADD_1_1]])
; CHECK-NEXT: [[TMP32_1:%.*]] = add nuw i32 [[TMP32]], 262144 ; CHECK-NEXT: [[TMP32_1:%.*]] = add nuw i32 [[TMP31]], 524288
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: [[L_2_2:%.*]] = load i32, ptr [[SRC]], align 8 ; CHECK-NEXT: [[L_2_2:%.*]] = load i32, ptr [[SRC]], align 8
; CHECK-NEXT: [[INNER_2_IV_NEXT_2]] = add i32 [[INNER_2_IV_NEXT_1]], 1 ; CHECK-NEXT: [[INNER_2_IV_NEXT_2]] = add i32 [[INNER_2_IV]], 3
; CHECK-NEXT: [[TMP27_2:%.*]] = load ptr, ptr [[PTR_SRC]], align 8 ; CHECK-NEXT: [[TMP27_2:%.*]] = load ptr, ptr [[PTR_SRC]], align 8
; CHECK-NEXT: [[ADD_1_2:%.*]] = add i32 [[INNER_2_IV_NEXT_1]], [[L_2_2]] ; CHECK-NEXT: [[ADD_1_2:%.*]] = add i32 [[INNER_2_IV_NEXT_1]], [[L_2_2]]
; CHECK-NEXT: [[TMP281_2:%.*]] = call i32 @use.2(ptr [[TMP27_2]], i32 [[ADD_1_2]]) ; CHECK-NEXT: [[TMP281_2:%.*]] = call i32 @use.2(ptr [[TMP27_2]], i32 [[ADD_1_2]])
; CHECK-NEXT: [[TMP32_2:%.*]] = add nuw i32 [[TMP32_1]], 262144 ; CHECK-NEXT: [[TMP32_2:%.*]] = add nuw i32 [[TMP31]], 786432
; CHECK-NEXT: [[TMP33_2]] = ashr exact i32 [[TMP32_2]], 16 ; CHECK-NEXT: [[TMP33_2]] = ashr exact i32 [[TMP32_2]], 16
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
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llvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll

Show All 18 Lines
; ENABLED-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[FOR_BODY_7]] ] ; ENABLED-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[FOR_BODY_7]] ]
; ENABLED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP]], label [[FOR_EXIT2_LOOPEXIT:%.*]], label [[FOR_BODY:%.*]] ; ENABLED-NEXT: br i1 [[CMP]], label [[FOR_EXIT2_LOOPEXIT:%.*]], label [[FOR_BODY:%.*]]
; ENABLED: for.body: ; ENABLED: for.body:
; ENABLED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV]] ; ENABLED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV]]
; ENABLED-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 ; ENABLED-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; ENABLED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[SUM_02]] ; ENABLED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[SUM_02]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
; ENABLED-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1
; ENABLED-NEXT: br i1 false, label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_1:%.*]] ; ENABLED-NEXT: br i1 false, label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_1:%.*]]
; ENABLED: for.body.1: ; ENABLED: for.body.1:
; ENABLED-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]] ; ENABLED-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]]
; ENABLED-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4 ; ENABLED-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
; ENABLED-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP4]], [[ADD]] ; ENABLED-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP4]], [[ADD]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
; ENABLED-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i64 [[NITER_NEXT]], 1
; ENABLED-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_2]], label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_2:%.*]] ; ENABLED-NEXT: br i1 [[CMP_2]], label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_2:%.*]]
; ENABLED: for.body.2: ; ENABLED: for.body.2:
; ENABLED-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_1]] ; ENABLED-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_1]]
; ENABLED-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4 ; ENABLED-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
; ENABLED-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]] ; ENABLED-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 3
; ENABLED-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i64 [[NITER_NEXT_1]], 1
; ENABLED-NEXT: br i1 false, label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_3:%.*]] ; ENABLED-NEXT: br i1 false, label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_3:%.*]]
; ENABLED: for.body.3: ; ENABLED: for.body.3:
; ENABLED-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]] ; ENABLED-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]]
; ENABLED-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4 ; ENABLED-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
; ENABLED-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], [[ADD_2]] ; ENABLED-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], [[ADD_2]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 4
; ENABLED-NEXT: [[NITER_NEXT_3:%.*]] = add nuw nsw i64 [[NITER_NEXT_2]], 1
; ENABLED-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_4]], label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_4:%.*]] ; ENABLED-NEXT: br i1 [[CMP_4]], label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_4:%.*]]
; ENABLED: for.body.4: ; ENABLED: for.body.4:
; ENABLED-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_3]] ; ENABLED-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_3]]
; ENABLED-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4 ; ENABLED-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4
; ENABLED-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]] ; ENABLED-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_3]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 5
; ENABLED-NEXT: [[NITER_NEXT_4:%.*]] = add nuw nsw i64 [[NITER_NEXT_3]], 1
; ENABLED-NEXT: br i1 false, label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_5:%.*]] ; ENABLED-NEXT: br i1 false, label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_5:%.*]]
; ENABLED: for.body.5: ; ENABLED: for.body.5:
; ENABLED-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_4]] ; ENABLED-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_4]]
; ENABLED-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4 ; ENABLED-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4
; ENABLED-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP8]], [[ADD_4]] ; ENABLED-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP8]], [[ADD_4]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_4]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 6
; ENABLED-NEXT: [[NITER_NEXT_5:%.*]] = add nuw nsw i64 [[NITER_NEXT_4]], 1
; ENABLED-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_6]], label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_6:%.*]] ; ENABLED-NEXT: br i1 [[CMP_6]], label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_6:%.*]]
; ENABLED: for.body.6: ; ENABLED: for.body.6:
; ENABLED-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_5]] ; ENABLED-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_5]]
; ENABLED-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4 ; ENABLED-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4
; ENABLED-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]] ; ENABLED-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_5]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 7
; ENABLED-NEXT: [[NITER_NEXT_6:%.*]] = add nuw nsw i64 [[NITER_NEXT_5]], 1
; ENABLED-NEXT: br i1 false, label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_7]] ; ENABLED-NEXT: br i1 false, label [[FOR_EXIT2_LOOPEXIT]], label [[FOR_BODY_7]]
; ENABLED: for.body.7: ; ENABLED: for.body.7:
; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]] ; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4 ; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]] ; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV_NEXT_6]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER_NEXT_6]], 1 ; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]] ; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[FOR_END_UNR_LCSSA_LOOPEXIT:%.*]], label [[HEADER]] ; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[FOR_END_UNR_LCSSA_LOOPEXIT:%.*]], label [[HEADER]]
; ENABLED: for.end.unr-lcssa.loopexit: ; ENABLED: for.end.unr-lcssa.loopexit:
; ENABLED-NEXT: [[SUM_0_LCSSA_PH_PH:%.*]] = phi i32 [ [[ADD_7]], [[FOR_BODY_7]] ] ; ENABLED-NEXT: [[SUM_0_LCSSA_PH_PH:%.*]] = phi i32 [ [[ADD_7]], [[FOR_BODY_7]] ]
; ENABLED-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_7]], [[FOR_BODY_7]] ] ; ENABLED-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_7]], [[FOR_BODY_7]] ]
; ENABLED-NEXT: [[SUM_02_UNR_PH:%.*]] = phi i32 [ [[ADD_7]], [[FOR_BODY_7]] ] ; ENABLED-NEXT: [[SUM_02_UNR_PH:%.*]] = phi i32 [ [[ADD_7]], [[FOR_BODY_7]] ]
; ENABLED-NEXT: br label [[FOR_END_UNR_LCSSA]] ; ENABLED-NEXT: br label [[FOR_END_UNR_LCSSA]]
; ENABLED: for.end.unr-lcssa: ; ENABLED: for.end.unr-lcssa:
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llvm/test/Transforms/LoopUnroll/runtime-loop-multiexit-dom-verify.ll

Show All 21 Lines
; CHECK-NEXT: [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2 ; CHECK-NEXT: [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]] ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]] ; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]]
; CHECK: latch: ; CHECK: latch:
; CHECK-NEXT: [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1 ; CHECK-NEXT: [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]] ; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]] ; CHECK-NEXT: br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]]
; CHECK: header.1: ; CHECK: header.1:
; CHECK-NEXT: [[ADD_IV_1:%.*]] = add nuw nsw i64 [[ADD_IV]], 2 ; CHECK-NEXT: [[ADD_IV_1:%.*]] = add nuw nsw i64 [[IV]], 4
; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]] ; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP1_1]], label [[LATCH_1:%.*]], label [[HEADEREXIT]] ; CHECK-NEXT: br i1 [[CMP1_1]], label [[LATCH_1:%.*]], label [[HEADEREXIT]]
; CHECK: latch.1: ; CHECK: latch.1:
; CHECK-NEXT: [[SHFT_1:%.*]] = ashr i64 [[ADD_IV_1]], 1 ; CHECK-NEXT: [[SHFT_1:%.*]] = ashr i64 [[ADD_IV_1]], 1
; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]] ; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]] ; CHECK-NEXT: br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]]
; CHECK: header.2: ; CHECK: header.2:
; CHECK-NEXT: [[ADD_IV_2:%.*]] = add nuw nsw i64 [[ADD_IV_1]], 2 ; CHECK-NEXT: [[ADD_IV_2:%.*]] = add nuw nsw i64 [[IV]], 6
; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]] ; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP1_2]], label [[LATCH_2:%.*]], label [[HEADEREXIT]] ; CHECK-NEXT: br i1 [[CMP1_2]], label [[LATCH_2:%.*]], label [[HEADEREXIT]]
; CHECK: latch.2: ; CHECK: latch.2:
; CHECK-NEXT: [[SHFT_2:%.*]] = ashr i64 [[ADD_IV_2]], 1 ; CHECK-NEXT: [[SHFT_2:%.*]] = ashr i64 [[ADD_IV_2]], 1
; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]] ; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]] ; CHECK-NEXT: br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]]
; CHECK: header.3: ; CHECK: header.3:
; CHECK-NEXT: [[ADD_IV_3]] = add nuw nsw i64 [[ADD_IV_2]], 2 ; CHECK-NEXT: [[ADD_IV_3]] = add nuw nsw i64 [[IV]], 8
; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]] ; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]] ; CHECK-NEXT: br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]]
; CHECK: latch.3: ; CHECK: latch.3:
; CHECK-NEXT: [[SHFT_3:%.*]] = ashr i64 [[ADD_IV_3]], 1 ; CHECK-NEXT: [[SHFT_3:%.*]] = ashr i64 [[ADD_IV_3]], 1
; CHECK-NEXT: [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]] ; CHECK-NEXT: [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: headerexit: ; CHECK: headerexit:
; CHECK-NEXT: [[ADDPHI:%.*]] = phi i64 [ [[ADD_IV]], [[HEADER]] ], [ [[ADD_IV_1]], [[HEADER_1]] ], [ [[ADD_IV_2]], [[HEADER_2]] ], [ [[ADD_IV_3]], [[HEADER_3]] ] ; CHECK-NEXT: [[ADDPHI:%.*]] = phi i64 [ [[ADD_IV]], [[HEADER]] ], [ [[ADD_IV_1]], [[HEADER_1]] ], [ [[ADD_IV_2]], [[HEADER_2]] ], [ [[ADD_IV_3]], [[HEADER_3]] ]
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; CHECK-NEXT: [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2 ; CHECK-NEXT: [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]] ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]] ; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]]
; CHECK: latch: ; CHECK: latch:
; CHECK-NEXT: [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1 ; CHECK-NEXT: [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]] ; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]] ; CHECK-NEXT: br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]]
; CHECK: header.1: ; CHECK: header.1:
; CHECK-NEXT: [[ADD_IV_1:%.*]] = add nuw nsw i64 [[ADD_IV]], 2 ; CHECK-NEXT: [[ADD_IV_1:%.*]] = add nuw nsw i64 [[IV]], 4
; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]] ; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP1_1]], label [[LATCH_1:%.*]], label [[HEADEREXIT]] ; CHECK-NEXT: br i1 [[CMP1_1]], label [[LATCH_1:%.*]], label [[HEADEREXIT]]
; CHECK: latch.1: ; CHECK: latch.1:
; CHECK-NEXT: [[SHFT_1:%.*]] = ashr i64 [[ADD_IV_1]], 1 ; CHECK-NEXT: [[SHFT_1:%.*]] = ashr i64 [[ADD_IV_1]], 1
; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]] ; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]] ; CHECK-NEXT: br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]]
; CHECK: header.2: ; CHECK: header.2:
; CHECK-NEXT: [[ADD_IV_2:%.*]] = add nuw nsw i64 [[ADD_IV_1]], 2 ; CHECK-NEXT: [[ADD_IV_2:%.*]] = add nuw nsw i64 [[IV]], 6
; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]] ; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP1_2]], label [[LATCH_2:%.*]], label [[HEADEREXIT]] ; CHECK-NEXT: br i1 [[CMP1_2]], label [[LATCH_2:%.*]], label [[HEADEREXIT]]
; CHECK: latch.2: ; CHECK: latch.2:
; CHECK-NEXT: [[SHFT_2:%.*]] = ashr i64 [[ADD_IV_2]], 1 ; CHECK-NEXT: [[SHFT_2:%.*]] = ashr i64 [[ADD_IV_2]], 1
; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]] ; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]] ; CHECK-NEXT: br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]]
; CHECK: header.3: ; CHECK: header.3:
; CHECK-NEXT: [[ADD_IV_3]] = add nuw nsw i64 [[ADD_IV_2]], 2 ; CHECK-NEXT: [[ADD_IV_3]] = add nuw nsw i64 [[IV]], 8
; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]] ; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]] ; CHECK-NEXT: br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]]
; CHECK: latch.3: ; CHECK: latch.3:
; CHECK-NEXT: [[SHFT_3:%.*]] = ashr i64 [[ADD_IV_3]], 1 ; CHECK-NEXT: [[SHFT_3:%.*]] = ashr i64 [[ADD_IV_3]], 1
; CHECK-NEXT: [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]] ; CHECK-NEXT: [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP2:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: headerexit: ; CHECK: headerexit:
; CHECK-NEXT: br label [[MERGEDEXIT]] ; CHECK-NEXT: br label [[MERGEDEXIT]]
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; CHECK-NEXT: [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2 ; CHECK-NEXT: [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]] ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]] ; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]]
; CHECK: latch: ; CHECK: latch:
; CHECK-NEXT: [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1 ; CHECK-NEXT: [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]] ; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]] ; CHECK-NEXT: br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]]
; CHECK: header.1: ; CHECK: header.1:
; CHECK-NEXT: [[ADD_IV_1:%.*]] = add nuw nsw i64 [[ADD_IV]], 2 ; CHECK-NEXT: [[ADD_IV_1:%.*]] = add nuw nsw i64 [[IV]], 4
; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]] ; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP1_1]], label [[LATCH_1:%.*]], label [[HEADEREXIT]] ; CHECK-NEXT: br i1 [[CMP1_1]], label [[LATCH_1:%.*]], label [[HEADEREXIT]]
; CHECK: latch.1: ; CHECK: latch.1:
; CHECK-NEXT: [[SHFT_1:%.*]] = ashr i64 [[ADD_IV_1]], 1 ; CHECK-NEXT: [[SHFT_1:%.*]] = ashr i64 [[ADD_IV_1]], 1
; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]] ; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]] ; CHECK-NEXT: br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]]
; CHECK: header.2: ; CHECK: header.2:
; CHECK-NEXT: [[ADD_IV_2:%.*]] = add nuw nsw i64 [[ADD_IV_1]], 2 ; CHECK-NEXT: [[ADD_IV_2:%.*]] = add nuw nsw i64 [[IV]], 6
; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]] ; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP1_2]], label [[LATCH_2:%.*]], label [[HEADEREXIT]] ; CHECK-NEXT: br i1 [[CMP1_2]], label [[LATCH_2:%.*]], label [[HEADEREXIT]]
; CHECK: latch.2: ; CHECK: latch.2:
; CHECK-NEXT: [[SHFT_2:%.*]] = ashr i64 [[ADD_IV_2]], 1 ; CHECK-NEXT: [[SHFT_2:%.*]] = ashr i64 [[ADD_IV_2]], 1
; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]] ; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]] ; CHECK-NEXT: br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]]
; CHECK: header.3: ; CHECK: header.3:
; CHECK-NEXT: [[ADD_IV_3]] = add nuw nsw i64 [[ADD_IV_2]], 2 ; CHECK-NEXT: [[ADD_IV_3]] = add nuw nsw i64 [[IV]], 8
; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]] ; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]] ; CHECK-NEXT: br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]]
; CHECK: latch.3: ; CHECK: latch.3:
; CHECK-NEXT: [[SHFT_3:%.*]] = ashr i64 [[ADD_IV_3]], 1 ; CHECK-NEXT: [[SHFT_3:%.*]] = ashr i64 [[ADD_IV_3]], 1
; CHECK-NEXT: [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]] ; CHECK-NEXT: [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]]
; CHECK-NEXT: br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP3:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: headerexit: ; CHECK: headerexit:
; CHECK-NEXT: br label [[EXITSUCC:%.*]] ; CHECK-NEXT: br label [[EXITSUCC:%.*]]
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_UNR]], [[PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_3:%.*]], [[LATCH_3:%.*]] ] ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_UNR]], [[PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_3:%.*]], [[LATCH_3:%.*]] ]
; CHECK-NEXT: br label [[EXITING:%.*]] ; CHECK-NEXT: br label [[EXITING:%.*]]
; CHECK: exiting: ; CHECK: exiting:
; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT:%.*]] [ ; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT:%.*]] [
; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT:%.*]] ; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT:%.*]]
; CHECK-NEXT: i16 95, label [[LATCH:%.*]] ; CHECK-NEXT: i16 95, label [[LATCH:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: latch: ; CHECK: latch:
; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: br label [[EXITING_1:%.*]] ; CHECK-NEXT: br label [[EXITING_1:%.*]]
; CHECK: exiting.1: ; CHECK: exiting.1:
; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [ ; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [
; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT]] ; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT]]
; CHECK-NEXT: i16 95, label [[LATCH_1:%.*]] ; CHECK-NEXT: i16 95, label [[LATCH_1:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: latch.1: ; CHECK: latch.1:
; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1
; CHECK-NEXT: br label [[EXITING_2:%.*]] ; CHECK-NEXT: br label [[EXITING_2:%.*]]
; CHECK: exiting.2: ; CHECK: exiting.2:
; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [ ; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [
; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT]] ; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT]]
; CHECK-NEXT: i16 95, label [[LATCH_2:%.*]] ; CHECK-NEXT: i16 95, label [[LATCH_2:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: latch.2: ; CHECK: latch.2:
; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1
; CHECK-NEXT: br label [[EXITING_3:%.*]] ; CHECK-NEXT: br label [[EXITING_3:%.*]]
; CHECK: exiting.3: ; CHECK: exiting.3:
; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [ ; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [
; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT]] ; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT]]
; CHECK-NEXT: i16 95, label [[LATCH_3]] ; CHECK-NEXT: i16 95, label [[LATCH_3]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: latch.3: ; CHECK: latch.3:
; CHECK-NEXT: [[INDVARS_IV_NEXT_3]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT_3]] = add nuw nsw i64 [[INDVARS_IV]], 4
; CHECK-NEXT: [[C2_3:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT_3]], [[C1]] ; CHECK-NEXT: [[C2_3:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT_3]], [[C1]]
; CHECK-NEXT: br i1 [[C2_3]], label [[HEADER]], label [[LATCHEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP5:![0-9]+]] ; CHECK-NEXT: br i1 [[C2_3]], label [[HEADER]], label [[LATCHEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: latchexit.unr-lcssa: ; CHECK: latchexit.unr-lcssa:
; CHECK-NEXT: br label [[LATCHEXIT]] ; CHECK-NEXT: br label [[LATCHEXIT]]
; CHECK: latchexit: ; CHECK: latchexit:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: default.loopexit.loopexit: ; CHECK: default.loopexit.loopexit:
; CHECK-NEXT: br label [[DEFAULT_LOOPEXIT:%.*]] ; CHECK-NEXT: br label [[DEFAULT_LOOPEXIT:%.*]]
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; CHECK-NEXT: [[C1_3:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C1_3:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C1_3]], label [[INNEREXITING_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT]] ; CHECK-NEXT: br i1 [[C1_3]], label [[INNEREXITING_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT]]
; CHECK: innerexiting.3: ; CHECK: innerexiting.3:
; CHECK-NEXT: [[C2_3:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C2_3:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C2_3]], label [[INNERLATCH_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT]] ; CHECK-NEXT: br i1 [[C2_3]], label [[INNERLATCH_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT]]
; CHECK: innerLatch.3: ; CHECK: innerLatch.3:
; CHECK-NEXT: br i1 false, label [[INNERH]], label [[OUTERLATCH]], !llvm.loop [[LOOP6]] ; CHECK-NEXT: br i1 false, label [[INNERH]], label [[OUTERLATCH]], !llvm.loop [[LOOP6]]
; CHECK: outerLatch: ; CHECK: outerLatch:
; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP4]], 1
; CHECK-NEXT: br label [[INNERH_14:%.*]] ; CHECK-NEXT: br label [[INNERH_14:%.*]]
; CHECK: innerH.14: ; CHECK: innerH.14:
; CHECK-NEXT: [[C1_13:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C1_13:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C1_13]], label [[INNEREXITING_16:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT18:%.*]] ; CHECK-NEXT: br i1 [[C1_13]], label [[INNEREXITING_16:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT18:%.*]]
; CHECK: innerexiting.16: ; CHECK: innerexiting.16:
; CHECK-NEXT: [[C2_15:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C2_15:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C2_15]], label [[INNERLATCH_17:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT19:%.*]] ; CHECK-NEXT: br i1 [[C2_15]], label [[INNERLATCH_17:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT19:%.*]]
; CHECK: innerLatch.17: ; CHECK: innerLatch.17:
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; CHECK-NEXT: [[C1_3_1:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C1_3_1:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C1_3_1]], label [[INNEREXITING_3_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT18]] ; CHECK-NEXT: br i1 [[C1_3_1]], label [[INNEREXITING_3_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT18]]
; CHECK: innerexiting.3.1: ; CHECK: innerexiting.3.1:
; CHECK-NEXT: [[C2_3_1:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C2_3_1:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C2_3_1]], label [[INNERLATCH_3_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT19]] ; CHECK-NEXT: br i1 [[C2_3_1]], label [[INNERLATCH_3_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT19]]
; CHECK: innerLatch.3.1: ; CHECK: innerLatch.3.1:
; CHECK-NEXT: br i1 false, label [[INNERH_14]], label [[OUTERLATCH_1]], !llvm.loop [[LOOP6]] ; CHECK-NEXT: br i1 false, label [[INNERH_14]], label [[OUTERLATCH_1]], !llvm.loop [[LOOP6]]
; CHECK: outerLatch.1: ; CHECK: outerLatch.1:
; CHECK-NEXT: [[TMP6_1:%.*]] = add i32 [[TMP6]], 1
; CHECK-NEXT: br label [[INNERH_29:%.*]] ; CHECK-NEXT: br label [[INNERH_29:%.*]]
; CHECK: innerH.29: ; CHECK: innerH.29:
; CHECK-NEXT: [[C1_28:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C1_28:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C1_28]], label [[INNEREXITING_211:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT20:%.*]] ; CHECK-NEXT: br i1 [[C1_28]], label [[INNEREXITING_211:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT20:%.*]]
; CHECK: innerexiting.211: ; CHECK: innerexiting.211:
; CHECK-NEXT: [[C2_210:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C2_210:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C2_210]], label [[INNERLATCH_212:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT21:%.*]] ; CHECK-NEXT: br i1 [[C2_210]], label [[INNERLATCH_212:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT21:%.*]]
; CHECK: innerLatch.212: ; CHECK: innerLatch.212:
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; CHECK-NEXT: [[C1_3_2:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C1_3_2:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C1_3_2]], label [[INNEREXITING_3_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT20]] ; CHECK-NEXT: br i1 [[C1_3_2]], label [[INNEREXITING_3_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT20]]
; CHECK: innerexiting.3.2: ; CHECK: innerexiting.3.2:
; CHECK-NEXT: [[C2_3_2:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C2_3_2:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C2_3_2]], label [[INNERLATCH_3_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT21]] ; CHECK-NEXT: br i1 [[C2_3_2]], label [[INNERLATCH_3_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT21]]
; CHECK: innerLatch.3.2: ; CHECK: innerLatch.3.2:
; CHECK-NEXT: br i1 false, label [[INNERH_29]], label [[OUTERLATCH_2]], !llvm.loop [[LOOP6]] ; CHECK-NEXT: br i1 false, label [[INNERH_29]], label [[OUTERLATCH_2]], !llvm.loop [[LOOP6]]
; CHECK: outerLatch.2: ; CHECK: outerLatch.2:
; CHECK-NEXT: [[TMP6_2:%.*]] = add i32 [[TMP6_1]], 1
; CHECK-NEXT: br label [[INNERH_314:%.*]] ; CHECK-NEXT: br label [[INNERH_314:%.*]]
; CHECK: innerH.314: ; CHECK: innerH.314:
; CHECK-NEXT: [[C1_313:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C1_313:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C1_313]], label [[INNEREXITING_316:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT22:%.*]] ; CHECK-NEXT: br i1 [[C1_313]], label [[INNEREXITING_316:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT22:%.*]]
; CHECK: innerexiting.316: ; CHECK: innerexiting.316:
; CHECK-NEXT: [[C2_315:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C2_315:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C2_315]], label [[INNERLATCH_317:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT23:%.*]] ; CHECK-NEXT: br i1 [[C2_315]], label [[INNERLATCH_317:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT23:%.*]]
; CHECK: innerLatch.317: ; CHECK: innerLatch.317:
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; CHECK-NEXT: [[C1_3_3:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C1_3_3:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C1_3_3]], label [[INNEREXITING_3_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT22]] ; CHECK-NEXT: br i1 [[C1_3_3]], label [[INNEREXITING_3_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT22]]
; CHECK: innerexiting.3.3: ; CHECK: innerexiting.3.3:
; CHECK-NEXT: [[C2_3_3:%.*]] = call i1 @unknown(i32 0) ; CHECK-NEXT: [[C2_3_3:%.*]] = call i1 @unknown(i32 0)
; CHECK-NEXT: br i1 [[C2_3_3]], label [[INNERLATCH_3_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT23]] ; CHECK-NEXT: br i1 [[C2_3_3]], label [[INNERLATCH_3_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT23]]
; CHECK: innerLatch.3.3: ; CHECK: innerLatch.3.3:
; CHECK-NEXT: br i1 false, label [[INNERH_314]], label [[OUTERLATCH_3]], !llvm.loop [[LOOP6]] ; CHECK-NEXT: br i1 false, label [[INNERH_314]], label [[OUTERLATCH_3]], !llvm.loop [[LOOP6]]
; CHECK: outerLatch.3: ; CHECK: outerLatch.3:
; CHECK-NEXT: [[TMP6_3]] = add i32 [[TMP6_2]], 1 ; CHECK-NEXT: [[TMP6_3]] = add i32 [[TMP4]], 4
; CHECK-NEXT: [[TMP7_3:%.*]] = icmp sgt i32 [[TMP6_3]], 79 ; CHECK-NEXT: [[TMP7_3:%.*]] = icmp sgt i32 [[TMP6_3]], 79
; CHECK-NEXT: br i1 [[TMP7_3]], label [[OUTERLATCHEXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[OUTERH]], !llvm.loop [[LOOP8:![0-9]+]] ; CHECK-NEXT: br i1 [[TMP7_3]], label [[OUTERLATCHEXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[OUTERH]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK: outerLatchExit.loopexit.unr-lcssa: ; CHECK: outerLatchExit.loopexit.unr-lcssa:
; CHECK-NEXT: br label [[OUTERLATCHEXIT_LOOPEXIT]] ; CHECK-NEXT: br label [[OUTERLATCHEXIT_LOOPEXIT]]
; CHECK: outerLatchExit.loopexit: ; CHECK: outerLatchExit.loopexit:
; CHECK-NEXT: br label [[OUTERLATCHEXIT]] ; CHECK-NEXT: br label [[OUTERLATCHEXIT]]
; CHECK: outerLatchExit: ; CHECK: outerLatchExit:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
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; CHECK-NEXT: [[C1:%.*]] = call i1 @unknown(i32 [[IV_I32]]) ; CHECK-NEXT: [[C1:%.*]] = call i1 @unknown(i32 [[IV_I32]])
; CHECK-NEXT: br i1 [[C1]], label [[LATCH:%.*]], label [[OTHEREXIT_LOOPEXIT:%.*]] ; CHECK-NEXT: br i1 [[C1]], label [[LATCH:%.*]], label [[OTHEREXIT_LOOPEXIT:%.*]]
; CHECK: latch: ; CHECK: latch:
; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nsw i64 [[INDVARS_IV]], 2 ; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nsw i64 [[INDVARS_IV]], 2
; CHECK-NEXT: [[IV_I32_1:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32 ; CHECK-NEXT: [[IV_I32_1:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
; CHECK-NEXT: [[C1_1:%.*]] = call i1 @unknown(i32 [[IV_I32_1]]) ; CHECK-NEXT: [[C1_1:%.*]] = call i1 @unknown(i32 [[IV_I32_1]])
; CHECK-NEXT: br i1 [[C1_1]], label [[LATCH_1:%.*]], label [[OTHEREXIT_LOOPEXIT]] ; CHECK-NEXT: br i1 [[C1_1]], label [[LATCH_1:%.*]], label [[OTHEREXIT_LOOPEXIT]]
; CHECK: latch.1: ; CHECK: latch.1:
; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nsw i64 [[INDVARS_IV_NEXT]], 2 ; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nsw i64 [[INDVARS_IV]], 4
; CHECK-NEXT: [[IV_I32_2:%.*]] = trunc i64 [[INDVARS_IV_NEXT_1]] to i32 ; CHECK-NEXT: [[IV_I32_2:%.*]] = trunc i64 [[INDVARS_IV_NEXT_1]] to i32
; CHECK-NEXT: [[C1_2:%.*]] = call i1 @unknown(i32 [[IV_I32_2]]) ; CHECK-NEXT: [[C1_2:%.*]] = call i1 @unknown(i32 [[IV_I32_2]])
; CHECK-NEXT: br i1 [[C1_2]], label [[LATCH_2:%.*]], label [[OTHEREXIT_LOOPEXIT]] ; CHECK-NEXT: br i1 [[C1_2]], label [[LATCH_2:%.*]], label [[OTHEREXIT_LOOPEXIT]]
; CHECK: latch.2: ; CHECK: latch.2:
; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nsw i64 [[INDVARS_IV_NEXT_1]], 2 ; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nsw i64 [[INDVARS_IV]], 6
; CHECK-NEXT: [[IV_I32_3:%.*]] = trunc i64 [[INDVARS_IV_NEXT_2]] to i32 ; CHECK-NEXT: [[IV_I32_3:%.*]] = trunc i64 [[INDVARS_IV_NEXT_2]] to i32
; CHECK-NEXT: [[C1_3:%.*]] = call i1 @unknown(i32 [[IV_I32_3]]) ; CHECK-NEXT: [[C1_3:%.*]] = call i1 @unknown(i32 [[IV_I32_3]])
; CHECK-NEXT: br i1 [[C1_3]], label [[LATCH_3]], label [[OTHEREXIT_LOOPEXIT]] ; CHECK-NEXT: br i1 [[C1_3]], label [[LATCH_3]], label [[OTHEREXIT_LOOPEXIT]]
; CHECK: latch.3: ; CHECK: latch.3:
; CHECK-NEXT: [[INDVARS_IV_NEXT_3]] = add nsw i64 [[INDVARS_IV_NEXT_2]], 2 ; CHECK-NEXT: [[INDVARS_IV_NEXT_3]] = add nsw i64 [[INDVARS_IV]], 8
; CHECK-NEXT: [[TMP9:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT_3]], 616 ; CHECK-NEXT: [[TMP9:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT_3]], 616
; CHECK-NEXT: br i1 [[TMP9]], label [[HEADER]], label [[LATCHEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP10:![0-9]+]] ; CHECK-NEXT: br i1 [[TMP9]], label [[HEADER]], label [[LATCHEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK: latchexit.unr-lcssa: ; CHECK: latchexit.unr-lcssa:
; CHECK-NEXT: br label [[LATCHEXIT]] ; CHECK-NEXT: br label [[LATCHEXIT]]
; CHECK: latchexit: ; CHECK: latchexit:
; CHECK-NEXT: br label [[LATCHEXITSUCC:%.*]] ; CHECK-NEXT: br label [[LATCHEXITSUCC:%.*]]
; CHECK: otherexit.loopexit: ; CHECK: otherexit.loopexit:
; CHECK-NEXT: br label [[OTHEREXIT:%.*]] ; CHECK-NEXT: br label [[OTHEREXIT:%.*]]
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llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll

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; EPILOG-NEXT: br i1 false, label %loop_latch, label %exit3.loopexit ; EPILOG-NEXT: br i1 false, label %loop_latch, label %exit3.loopexit
; EPILOG: exit3.loopexit: ; EPILOG: exit3.loopexit:
; EPILOG-NEXT: br label %exit3 ; EPILOG-NEXT: br label %exit3
; EPILOG: exit3.loopexit2: ; EPILOG: exit3.loopexit2:
; EPILOG-NEXT: br label %exit3 ; EPILOG-NEXT: br label %exit3
; EPILOG: exit3: ; EPILOG: exit3:
; EPILOG-NEXT: ret void ; EPILOG-NEXT: ret void
; EPILOG: loop_latch: ; EPILOG: loop_latch:
; EPILOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting_bb1.1 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting_bb1.1
; EPILOG: loop_exiting_bb1.1: ; EPILOG: loop_exiting_bb1.1:
; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.1, label %exit1.loopexit ; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.1, label %exit1.loopexit
; EPILOG: loop_exiting_bb2.1: ; EPILOG: loop_exiting_bb2.1:
; EPILOG-NEXT: br i1 false, label %loop_latch.1, label %exit3.loopexit ; EPILOG-NEXT: br i1 false, label %loop_latch.1, label %exit3.loopexit
; EPILOG: loop_latch.1: ; EPILOG: loop_latch.1:
; EPILOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.2, label %loop_exiting_bb1.2 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.2, label %loop_exiting_bb1.2
; EPILOG: loop_exiting_bb1.2: ; EPILOG: loop_exiting_bb1.2:
; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.2, label %exit1.loopexit ; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.2, label %exit1.loopexit
; EPILOG: loop_exiting_bb2.2: ; EPILOG: loop_exiting_bb2.2:
; EPILOG-NEXT: br i1 false, label %loop_latch.2, label %exit3.loopexit ; EPILOG-NEXT: br i1 false, label %loop_latch.2, label %exit3.loopexit
; EPILOG: loop_latch.2: ; EPILOG: loop_latch.2:
; EPILOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv_next.1, 1
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.3, label %loop_exiting_bb1.3 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.3, label %loop_exiting_bb1.3
; EPILOG: loop_exiting_bb1.3: ; EPILOG: loop_exiting_bb1.3:
; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.3, label %exit1.loopexit ; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.3, label %exit1.loopexit
; EPILOG: loop_exiting_bb2.3: ; EPILOG: loop_exiting_bb2.3:
; EPILOG-NEXT: br i1 false, label %loop_latch.3, label %exit3.loopexit ; EPILOG-NEXT: br i1 false, label %loop_latch.3, label %exit3.loopexit
; EPILOG: loop_latch.3: ; EPILOG: loop_latch.3:
; EPILOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv_next.2, 1
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.4, label %loop_exiting_bb1.4 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.4, label %loop_exiting_bb1.4
; EPILOG: loop_exiting_bb1.4: ; EPILOG: loop_exiting_bb1.4:
; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.4, label %exit1.loopexit ; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.4, label %exit1.loopexit
; EPILOG: loop_exiting_bb2.4: ; EPILOG: loop_exiting_bb2.4:
; EPILOG-NEXT: br i1 false, label %loop_latch.4, label %exit3.loopexit ; EPILOG-NEXT: br i1 false, label %loop_latch.4, label %exit3.loopexit
; EPILOG: loop_latch.4: ; EPILOG: loop_latch.4:
; EPILOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv_next.3, 1
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.5, label %loop_exiting_bb1.5 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.5, label %loop_exiting_bb1.5
; EPILOG: loop_exiting_bb1.5: ; EPILOG: loop_exiting_bb1.5:
; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.5, label %exit1.loopexit ; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.5, label %exit1.loopexit
; EPILOG: loop_exiting_bb2.5: ; EPILOG: loop_exiting_bb2.5:
; EPILOG-NEXT: br i1 false, label %loop_latch.5, label %exit3.loopexit ; EPILOG-NEXT: br i1 false, label %loop_latch.5, label %exit3.loopexit
; EPILOG: loop_latch.5: ; EPILOG: loop_latch.5:
; EPILOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv_next.4, 1
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.6, label %loop_exiting_bb1.6 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.6, label %loop_exiting_bb1.6
; EPILOG: loop_exiting_bb1.6: ; EPILOG: loop_exiting_bb1.6:
; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.6, label %exit1.loopexit ; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.6, label %exit1.loopexit
; EPILOG: loop_exiting_bb2.6: ; EPILOG: loop_exiting_bb2.6:
; EPILOG-NEXT: br i1 false, label %loop_latch.6, label %exit3.loopexit ; EPILOG-NEXT: br i1 false, label %loop_latch.6, label %exit3.loopexit
; EPILOG: loop_latch.6: ; EPILOG: loop_latch.6:
; EPILOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv_next.5, 1
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.7, label %loop_exiting_bb1.7 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.7, label %loop_exiting_bb1.7
; EPILOG: loop_exiting_bb1.7: ; EPILOG: loop_exiting_bb1.7:
; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.7, label %exit1.loopexit ; EPILOG-NEXT: br i1 false, label %loop_exiting_bb2.7, label %exit1.loopexit
; EPILOG: loop_exiting_bb2.7: ; EPILOG: loop_exiting_bb2.7:
; EPILOG-NEXT: br i1 false, label %loop_latch.7, label %exit3.loopexit ; EPILOG-NEXT: br i1 false, label %loop_latch.7, label %exit3.loopexit
; EPILOG: loop_latch.7: ; EPILOG: loop_latch.7:
; EPILOG-NEXT: %iv_next.7 = add i64 %iv_next.6, 1 ; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa.loopexit ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa.loopexit
; EPILOG: exit1.loopexit: ; EPILOG: exit1.loopexit:
; EPILOG-NEXT: br label %exit1 ; EPILOG-NEXT: br label %exit1
; EPILOG: exit1.loopexit1: ; EPILOG: exit1.loopexit1:
; EPILOG-NEXT: br label %exit1 ; EPILOG-NEXT: br label %exit1
; EPILOG: exit1: ; EPILOG: exit1:
; EPILOG-NEXT: ret void ; EPILOG-NEXT: ret void
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; EPILOG-BLOCK-NEXT: br i1 false, label %loop_exiting_bb2, label %exit1.loopexit ; EPILOG-BLOCK-NEXT: br i1 false, label %loop_exiting_bb2, label %exit1.loopexit
; EPILOG-BLOCK: loop_exiting_bb2: ; EPILOG-BLOCK: loop_exiting_bb2:
; EPILOG-BLOCK-NEXT: br i1 false, label %loop_latch, label %exit3.loopexit ; EPILOG-BLOCK-NEXT: br i1 false, label %loop_latch, label %exit3.loopexit
; EPILOG-BLOCK: exit3.loopexit: ; EPILOG-BLOCK: exit3.loopexit:
; EPILOG-BLOCK-NEXT: br label %exit3 ; EPILOG-BLOCK-NEXT: br label %exit3
; EPILOG-BLOCK: exit3: ; EPILOG-BLOCK: exit3:
; EPILOG-BLOCK-NEXT: ret void ; EPILOG-BLOCK-NEXT: ret void
; EPILOG-BLOCK: loop_latch: ; EPILOG-BLOCK: loop_latch:
; EPILOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting_bb1.1 ; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting_bb1.1
; EPILOG-BLOCK: loop_exiting_bb1.1: ; EPILOG-BLOCK: loop_exiting_bb1.1:
; EPILOG-BLOCK-NEXT: br i1 false, label %loop_exiting_bb2.1, label %exit1.loopexit ; EPILOG-BLOCK-NEXT: br i1 false, label %loop_exiting_bb2.1, label %exit1.loopexit
; EPILOG-BLOCK: loop_exiting_bb2.1: ; EPILOG-BLOCK: loop_exiting_bb2.1:
; EPILOG-BLOCK-NEXT: br i1 false, label %loop_latch.1, label %exit3.loopexit ; EPILOG-BLOCK-NEXT: br i1 false, label %loop_latch.1, label %exit3.loopexit
; EPILOG-BLOCK: loop_latch.1: ; EPILOG-BLOCK: loop_latch.1:
; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.loopexit.unr-lcssa.loopexit, !llvm.loop !0 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.loopexit.unr-lcssa.loopexit, !llvm.loop !0
; EPILOG-BLOCK: exit1.loopexit: ; EPILOG-BLOCK: exit1.loopexit:
; EPILOG-BLOCK-NEXT: br label %exit1 ; EPILOG-BLOCK-NEXT: br label %exit1
; EPILOG-BLOCK: exit1: ; EPILOG-BLOCK: exit1:
; EPILOG-BLOCK-NEXT: ret void ; EPILOG-BLOCK-NEXT: ret void
; EPILOG-BLOCK: exit2.loopexit.unr-lcssa.loopexit: ; EPILOG-BLOCK: exit2.loopexit.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: br label %exit2.loopexit.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %exit2.loopexit.unr-lcssa
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; PROLOG-NEXT: br i1 false, label %loop_latch, label %exit3.loopexit ; PROLOG-NEXT: br i1 false, label %loop_latch, label %exit3.loopexit
; PROLOG: exit3.loopexit: ; PROLOG: exit3.loopexit:
; PROLOG-NEXT: br label %exit3 ; PROLOG-NEXT: br label %exit3
; PROLOG: exit3.loopexit2: ; PROLOG: exit3.loopexit2:
; PROLOG-NEXT: br label %exit3 ; PROLOG-NEXT: br label %exit3
; PROLOG: exit3: ; PROLOG: exit3:
; PROLOG-NEXT: ret void ; PROLOG-NEXT: ret void
; PROLOG: loop_latch: ; PROLOG: loop_latch:
; PROLOG-NEXT: %iv_next = add i64 %iv, 1
; PROLOG-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting_bb1.1 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting_bb1.1
; PROLOG: loop_exiting_bb1.1: ; PROLOG: loop_exiting_bb1.1:
; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.1, label %exit1.loopexit ; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.1, label %exit1.loopexit
; PROLOG: loop_exiting_bb2.1: ; PROLOG: loop_exiting_bb2.1:
; PROLOG-NEXT: br i1 false, label %loop_latch.1, label %exit3.loopexit ; PROLOG-NEXT: br i1 false, label %loop_latch.1, label %exit3.loopexit
; PROLOG: loop_latch.1: ; PROLOG: loop_latch.1:
; PROLOG-NEXT: %iv_next.1 = add i64 %iv_next, 1
; PROLOG-NEXT: br i1 %cond, label %loop_latch.2, label %loop_exiting_bb1.2 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.2, label %loop_exiting_bb1.2
; PROLOG: loop_exiting_bb1.2: ; PROLOG: loop_exiting_bb1.2:
; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.2, label %exit1.loopexit ; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.2, label %exit1.loopexit
; PROLOG: loop_exiting_bb2.2: ; PROLOG: loop_exiting_bb2.2:
; PROLOG-NEXT: br i1 false, label %loop_latch.2, label %exit3.loopexit ; PROLOG-NEXT: br i1 false, label %loop_latch.2, label %exit3.loopexit
; PROLOG: loop_latch.2: ; PROLOG: loop_latch.2:
; PROLOG-NEXT: %iv_next.2 = add i64 %iv_next.1, 1
; PROLOG-NEXT: br i1 %cond, label %loop_latch.3, label %loop_exiting_bb1.3 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.3, label %loop_exiting_bb1.3
; PROLOG: loop_exiting_bb1.3: ; PROLOG: loop_exiting_bb1.3:
; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.3, label %exit1.loopexit ; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.3, label %exit1.loopexit
; PROLOG: loop_exiting_bb2.3: ; PROLOG: loop_exiting_bb2.3:
; PROLOG-NEXT: br i1 false, label %loop_latch.3, label %exit3.loopexit ; PROLOG-NEXT: br i1 false, label %loop_latch.3, label %exit3.loopexit
; PROLOG: loop_latch.3: ; PROLOG: loop_latch.3:
; PROLOG-NEXT: %iv_next.3 = add i64 %iv_next.2, 1
; PROLOG-NEXT: br i1 %cond, label %loop_latch.4, label %loop_exiting_bb1.4 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.4, label %loop_exiting_bb1.4
; PROLOG: loop_exiting_bb1.4: ; PROLOG: loop_exiting_bb1.4:
; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.4, label %exit1.loopexit ; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.4, label %exit1.loopexit
; PROLOG: loop_exiting_bb2.4: ; PROLOG: loop_exiting_bb2.4:
; PROLOG-NEXT: br i1 false, label %loop_latch.4, label %exit3.loopexit ; PROLOG-NEXT: br i1 false, label %loop_latch.4, label %exit3.loopexit
; PROLOG: loop_latch.4: ; PROLOG: loop_latch.4:
; PROLOG-NEXT: %iv_next.4 = add i64 %iv_next.3, 1
; PROLOG-NEXT: br i1 %cond, label %loop_latch.5, label %loop_exiting_bb1.5 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.5, label %loop_exiting_bb1.5
; PROLOG: loop_exiting_bb1.5: ; PROLOG: loop_exiting_bb1.5:
; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.5, label %exit1.loopexit ; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.5, label %exit1.loopexit
; PROLOG: loop_exiting_bb2.5: ; PROLOG: loop_exiting_bb2.5:
; PROLOG-NEXT: br i1 false, label %loop_latch.5, label %exit3.loopexit ; PROLOG-NEXT: br i1 false, label %loop_latch.5, label %exit3.loopexit
; PROLOG: loop_latch.5: ; PROLOG: loop_latch.5:
; PROLOG-NEXT: %iv_next.5 = add i64 %iv_next.4, 1
; PROLOG-NEXT: br i1 %cond, label %loop_latch.6, label %loop_exiting_bb1.6 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.6, label %loop_exiting_bb1.6
; PROLOG: loop_exiting_bb1.6: ; PROLOG: loop_exiting_bb1.6:
; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.6, label %exit1.loopexit ; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.6, label %exit1.loopexit
; PROLOG: loop_exiting_bb2.6: ; PROLOG: loop_exiting_bb2.6:
; PROLOG-NEXT: br i1 false, label %loop_latch.6, label %exit3.loopexit ; PROLOG-NEXT: br i1 false, label %loop_latch.6, label %exit3.loopexit
; PROLOG: loop_latch.6: ; PROLOG: loop_latch.6:
; PROLOG-NEXT: %iv_next.6 = add i64 %iv_next.5, 1
; PROLOG-NEXT: br i1 %cond, label %loop_latch.7, label %loop_exiting_bb1.7 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.7, label %loop_exiting_bb1.7
; PROLOG: loop_exiting_bb1.7: ; PROLOG: loop_exiting_bb1.7:
; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.7, label %exit1.loopexit ; PROLOG-NEXT: br i1 false, label %loop_exiting_bb2.7, label %exit1.loopexit
; PROLOG: loop_exiting_bb2.7: ; PROLOG: loop_exiting_bb2.7:
; PROLOG-NEXT: br i1 false, label %loop_latch.7, label %exit3.loopexit ; PROLOG-NEXT: br i1 false, label %loop_latch.7, label %exit3.loopexit
; PROLOG: loop_latch.7: ; PROLOG: loop_latch.7:
; PROLOG-NEXT: %iv_next.7 = add i64 %iv_next.6, 1 ; PROLOG-NEXT: %iv_next.7 = add i64 %iv, 8
; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip ; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip
; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa ; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa
; PROLOG: exit1.loopexit: ; PROLOG: exit1.loopexit:
; PROLOG-NEXT: br label %exit1 ; PROLOG-NEXT: br label %exit1
; PROLOG: exit1.loopexit1: ; PROLOG: exit1.loopexit1:
; PROLOG-NEXT: br label %exit1 ; PROLOG-NEXT: br label %exit1
; PROLOG: exit1: ; PROLOG: exit1:
; PROLOG-NEXT: ret void ; PROLOG-NEXT: ret void
Show All 32 Lines
; PROLOG-BLOCK-NEXT: br i1 false, label %loop_exiting_bb2, label %exit1.loopexit ; PROLOG-BLOCK-NEXT: br i1 false, label %loop_exiting_bb2, label %exit1.loopexit
; PROLOG-BLOCK: loop_exiting_bb2: ; PROLOG-BLOCK: loop_exiting_bb2:
; PROLOG-BLOCK-NEXT: br i1 false, label %loop_latch, label %exit3.loopexit ; PROLOG-BLOCK-NEXT: br i1 false, label %loop_latch, label %exit3.loopexit
; PROLOG-BLOCK: exit3.loopexit: ; PROLOG-BLOCK: exit3.loopexit:
; PROLOG-BLOCK-NEXT: br label %exit3 ; PROLOG-BLOCK-NEXT: br label %exit3
; PROLOG-BLOCK: exit3: ; PROLOG-BLOCK: exit3:
; PROLOG-BLOCK-NEXT: ret void ; PROLOG-BLOCK-NEXT: ret void
; PROLOG-BLOCK: loop_latch: ; PROLOG-BLOCK: loop_latch:
; PROLOG-BLOCK-NEXT: %iv_next = add i64 %iv, 1
; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting_bb1.1 ; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting_bb1.1
; PROLOG-BLOCK: loop_exiting_bb1.1: ; PROLOG-BLOCK: loop_exiting_bb1.1:
; PROLOG-BLOCK-NEXT: br i1 false, label %loop_exiting_bb2.1, label %exit1.loopexit ; PROLOG-BLOCK-NEXT: br i1 false, label %loop_exiting_bb2.1, label %exit1.loopexit
; PROLOG-BLOCK: loop_exiting_bb2.1: ; PROLOG-BLOCK: loop_exiting_bb2.1:
; PROLOG-BLOCK-NEXT: br i1 false, label %loop_latch.1, label %exit3.loopexit ; PROLOG-BLOCK-NEXT: br i1 false, label %loop_latch.1, label %exit3.loopexit
; PROLOG-BLOCK: loop_latch.1: ; PROLOG-BLOCK: loop_latch.1:
; PROLOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; PROLOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit2.loopexit.unr-lcssa, !llvm.loop !0 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit2.loopexit.unr-lcssa, !llvm.loop !0
; PROLOG-BLOCK: exit1.loopexit: ; PROLOG-BLOCK: exit1.loopexit:
; PROLOG-BLOCK-NEXT: br label %exit1 ; PROLOG-BLOCK-NEXT: br label %exit1
; PROLOG-BLOCK: exit1: ; PROLOG-BLOCK: exit1:
; PROLOG-BLOCK-NEXT: ret void ; PROLOG-BLOCK-NEXT: ret void
; PROLOG-BLOCK: exit2.loopexit.unr-lcssa: ; PROLOG-BLOCK: exit2.loopexit.unr-lcssa:
; PROLOG-BLOCK-NEXT: br label %exit2.loopexit ; PROLOG-BLOCK-NEXT: br label %exit2.loopexit
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; EPILOG: for.exiting_block: ; EPILOG: for.exiting_block:
; EPILOG-NEXT: %cmp = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp, label %for.exit2.loopexit, label %for.body ; EPILOG-NEXT: br i1 %cmp, label %for.exit2.loopexit, label %for.body
; EPILOG: for.body: ; EPILOG: for.body:
; EPILOG-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv ; EPILOG-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
; EPILOG-NEXT: %3 = load i32, ptr %arrayidx, align 4 ; EPILOG-NEXT: %3 = load i32, ptr %arrayidx, align 4
; EPILOG-NEXT: %add = add nsw i32 %3, %sum.02 ; EPILOG-NEXT: %add = add nsw i32 %3, %sum.02
; EPILOG-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 ; EPILOG-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1
; EPILOG: for.exiting_block.1: ; EPILOG: for.exiting_block.1:
; EPILOG-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %for.body.1 ; EPILOG-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %for.body.1
; EPILOG: for.body.1: ; EPILOG: for.body.1:
; EPILOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; EPILOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-NEXT: %4 = load i32, ptr %arrayidx.1, align 4 ; EPILOG-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-NEXT: %add.1 = add nsw i32 %4, %add ; EPILOG-NEXT: %add.1 = add nsw i32 %4, %add
; EPILOG-NEXT: %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv.next, 1 ; EPILOG-NEXT: %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.2 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.2
; EPILOG: for.exiting_block.2: ; EPILOG: for.exiting_block.2:
; EPILOG-NEXT: %cmp.2 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.2 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.2, label %for.exit2.loopexit, label %for.body.2 ; EPILOG-NEXT: br i1 %cmp.2, label %for.exit2.loopexit, label %for.body.2
; EPILOG: for.body.2: ; EPILOG: for.body.2:
; EPILOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1 ; EPILOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1
; EPILOG-NEXT: %5 = load i32, ptr %arrayidx.2, align 4 ; EPILOG-NEXT: %5 = load i32, ptr %arrayidx.2, align 4
; EPILOG-NEXT: %add.2 = add nsw i32 %5, %add.1 ; EPILOG-NEXT: %add.2 = add nsw i32 %5, %add.1
; EPILOG-NEXT: %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv.next.1, 1 ; EPILOG-NEXT: %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv, 3
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.3 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.3
; EPILOG: for.exiting_block.3: ; EPILOG: for.exiting_block.3:
; EPILOG-NEXT: %cmp.3 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.3 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.3, label %for.exit2.loopexit, label %for.body.3 ; EPILOG-NEXT: br i1 %cmp.3, label %for.exit2.loopexit, label %for.body.3
; EPILOG: for.body.3: ; EPILOG: for.body.3:
; EPILOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2 ; EPILOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2
; EPILOG-NEXT: %6 = load i32, ptr %arrayidx.3, align 4 ; EPILOG-NEXT: %6 = load i32, ptr %arrayidx.3, align 4
; EPILOG-NEXT: %add.3 = add nsw i32 %6, %add.2 ; EPILOG-NEXT: %add.3 = add nsw i32 %6, %add.2
; EPILOG-NEXT: %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv.next.2, 1 ; EPILOG-NEXT: %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv, 4
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.4 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.4
; EPILOG: for.exiting_block.4: ; EPILOG: for.exiting_block.4:
; EPILOG-NEXT: %cmp.4 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.4 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.4, label %for.exit2.loopexit, label %for.body.4 ; EPILOG-NEXT: br i1 %cmp.4, label %for.exit2.loopexit, label %for.body.4
; EPILOG: for.body.4: ; EPILOG: for.body.4:
; EPILOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3 ; EPILOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3
; EPILOG-NEXT: %7 = load i32, ptr %arrayidx.4, align 4 ; EPILOG-NEXT: %7 = load i32, ptr %arrayidx.4, align 4
; EPILOG-NEXT: %add.4 = add nsw i32 %7, %add.3 ; EPILOG-NEXT: %add.4 = add nsw i32 %7, %add.3
; EPILOG-NEXT: %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv.next.3, 1 ; EPILOG-NEXT: %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv, 5
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.5 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.5
; EPILOG: for.exiting_block.5: ; EPILOG: for.exiting_block.5:
; EPILOG-NEXT: %cmp.5 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.5 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.5, label %for.exit2.loopexit, label %for.body.5 ; EPILOG-NEXT: br i1 %cmp.5, label %for.exit2.loopexit, label %for.body.5
; EPILOG: for.body.5: ; EPILOG: for.body.5:
; EPILOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4 ; EPILOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4
; EPILOG-NEXT: %8 = load i32, ptr %arrayidx.5, align 4 ; EPILOG-NEXT: %8 = load i32, ptr %arrayidx.5, align 4
; EPILOG-NEXT: %add.5 = add nsw i32 %8, %add.4 ; EPILOG-NEXT: %add.5 = add nsw i32 %8, %add.4
; EPILOG-NEXT: %indvars.iv.next.5 = add nuw nsw i64 %indvars.iv.next.4, 1 ; EPILOG-NEXT: %indvars.iv.next.5 = add nuw nsw i64 %indvars.iv, 6
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.6 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.6
; EPILOG: for.exiting_block.6: ; EPILOG: for.exiting_block.6:
; EPILOG-NEXT: %cmp.6 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.6 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.6, label %for.exit2.loopexit, label %for.body.6 ; EPILOG-NEXT: br i1 %cmp.6, label %for.exit2.loopexit, label %for.body.6
; EPILOG: for.body.6: ; EPILOG: for.body.6:
; EPILOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5 ; EPILOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5
; EPILOG-NEXT: %9 = load i32, ptr %arrayidx.6, align 4 ; EPILOG-NEXT: %9 = load i32, ptr %arrayidx.6, align 4
; EPILOG-NEXT: %add.6 = add nsw i32 %9, %add.5 ; EPILOG-NEXT: %add.6 = add nsw i32 %9, %add.5
; EPILOG-NEXT: %indvars.iv.next.6 = add nuw nsw i64 %indvars.iv.next.5, 1 ; EPILOG-NEXT: %indvars.iv.next.6 = add nuw nsw i64 %indvars.iv, 7
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.7 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.7
; EPILOG: for.exiting_block.7: ; EPILOG: for.exiting_block.7:
; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.7, label %for.exit2.loopexit, label %for.body.7 ; EPILOG-NEXT: br i1 %cmp.7, label %for.exit2.loopexit, label %for.body.7
; EPILOG: for.body.7: ; EPILOG: for.body.7:
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6 ; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4 ; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6 ; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv.next.6, 1 ; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %for.end.unr-lcssa.loopexit, label %header ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %for.end.unr-lcssa.loopexit, label %header
; EPILOG: for.end.unr-lcssa.loopexit: ; EPILOG: for.end.unr-lcssa.loopexit:
; EPILOG-NEXT: %sum.0.lcssa.ph.ph = phi i32 [ %add.7, %for.body.7 ] ; EPILOG-NEXT: %sum.0.lcssa.ph.ph = phi i32 [ %add.7, %for.body.7 ]
; EPILOG-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.7, %for.body.7 ] ; EPILOG-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.7, %for.body.7 ]
; EPILOG-NEXT: %sum.02.unr.ph = phi i32 [ %add.7, %for.body.7 ] ; EPILOG-NEXT: %sum.02.unr.ph = phi i32 [ %add.7, %for.body.7 ]
; EPILOG-NEXT: br label %for.end.unr-lcssa ; EPILOG-NEXT: br label %for.end.unr-lcssa
; EPILOG: for.end.unr-lcssa: ; EPILOG: for.end.unr-lcssa:
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; EPILOG-BLOCK: for.exiting_block: ; EPILOG-BLOCK: for.exiting_block:
; EPILOG-BLOCK-NEXT: %cmp = icmp eq i64 %n, 42 ; EPILOG-BLOCK-NEXT: %cmp = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp, label %for.exit2.loopexit, label %for.body ; EPILOG-BLOCK-NEXT: br i1 %cmp, label %for.exit2.loopexit, label %for.body
; EPILOG-BLOCK: for.body: ; EPILOG-BLOCK: for.body:
; EPILOG-BLOCK-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv ; EPILOG-BLOCK-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
; EPILOG-BLOCK-NEXT: %3 = load i32, ptr %arrayidx, align 4 ; EPILOG-BLOCK-NEXT: %3 = load i32, ptr %arrayidx, align 4
; EPILOG-BLOCK-NEXT: %add = add nsw i32 %3, %sum.02 ; EPILOG-BLOCK-NEXT: %add = add nsw i32 %3, %sum.02
; EPILOG-BLOCK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 ; EPILOG-BLOCK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1 ; EPILOG-BLOCK-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1
; EPILOG-BLOCK: for.exiting_block.1: ; EPILOG-BLOCK: for.exiting_block.1:
; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %for.body.1 ; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %for.body.1
; EPILOG-BLOCK: for.body.1: ; EPILOG-BLOCK: for.body.1:
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4 ; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add ; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %for.end.unr-lcssa.loopexit, label %header, !llvm.loop !2 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %for.end.unr-lcssa.loopexit, label %header, !llvm.loop !2
; EPILOG-BLOCK: for.end.unr-lcssa.loopexit: ; EPILOG-BLOCK: for.end.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: %sum.0.lcssa.ph.ph = phi i32 [ %add.1, %for.body.1 ] ; EPILOG-BLOCK-NEXT: %sum.0.lcssa.ph.ph = phi i32 [ %add.1, %for.body.1 ]
; EPILOG-BLOCK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.1, %for.body.1 ] ; EPILOG-BLOCK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.1, %for.body.1 ]
; EPILOG-BLOCK-NEXT: %sum.02.unr.ph = phi i32 [ %add.1, %for.body.1 ] ; EPILOG-BLOCK-NEXT: %sum.02.unr.ph = phi i32 [ %add.1, %for.body.1 ]
; EPILOG-BLOCK-NEXT: br label %for.end.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %for.end.unr-lcssa
; EPILOG-BLOCK: for.end.unr-lcssa: ; EPILOG-BLOCK: for.end.unr-lcssa:
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1
; PROLOG: for.exiting_block.1: ; PROLOG: for.exiting_block.1:
; PROLOG-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.1 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %for.body.1 ; PROLOG-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %for.body.1
; PROLOG: for.body.1: ; PROLOG: for.body.1:
; PROLOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; PROLOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; PROLOG-NEXT: %5 = load i32, ptr %arrayidx.1, align 4 ; PROLOG-NEXT: %5 = load i32, ptr %arrayidx.1, align 4
; PROLOG-NEXT: %add.1 = add nsw i32 %5, %add ; PROLOG-NEXT: %add.1 = add nsw i32 %5, %add
; PROLOG-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; PROLOG-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.2 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.2
; PROLOG: for.exiting_block.2: ; PROLOG: for.exiting_block.2:
; PROLOG-NEXT: %cmp.2 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.2 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.2, label %for.exit2.loopexit, label %for.body.2 ; PROLOG-NEXT: br i1 %cmp.2, label %for.exit2.loopexit, label %for.body.2
; PROLOG: for.body.2: ; PROLOG: for.body.2:
; PROLOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1 ; PROLOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1
; PROLOG-NEXT: %6 = load i32, ptr %arrayidx.2, align 4 ; PROLOG-NEXT: %6 = load i32, ptr %arrayidx.2, align 4
; PROLOG-NEXT: %add.2 = add nsw i32 %6, %add.1 ; PROLOG-NEXT: %add.2 = add nsw i32 %6, %add.1
; PROLOG-NEXT: %indvars.iv.next.2 = add i64 %indvars.iv.next.1, 1 ; PROLOG-NEXT: %indvars.iv.next.2 = add i64 %indvars.iv, 3
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.3 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.3
; PROLOG: for.exiting_block.3: ; PROLOG: for.exiting_block.3:
; PROLOG-NEXT: %cmp.3 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.3 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.3, label %for.exit2.loopexit, label %for.body.3 ; PROLOG-NEXT: br i1 %cmp.3, label %for.exit2.loopexit, label %for.body.3
; PROLOG: for.body.3: ; PROLOG: for.body.3:
; PROLOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2 ; PROLOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2
; PROLOG-NEXT: %7 = load i32, ptr %arrayidx.3, align 4 ; PROLOG-NEXT: %7 = load i32, ptr %arrayidx.3, align 4
; PROLOG-NEXT: %add.3 = add nsw i32 %7, %add.2 ; PROLOG-NEXT: %add.3 = add nsw i32 %7, %add.2
; PROLOG-NEXT: %indvars.iv.next.3 = add i64 %indvars.iv.next.2, 1 ; PROLOG-NEXT: %indvars.iv.next.3 = add i64 %indvars.iv, 4
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.4 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.4
; PROLOG: for.exiting_block.4: ; PROLOG: for.exiting_block.4:
; PROLOG-NEXT: %cmp.4 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.4 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.4, label %for.exit2.loopexit, label %for.body.4 ; PROLOG-NEXT: br i1 %cmp.4, label %for.exit2.loopexit, label %for.body.4
; PROLOG: for.body.4: ; PROLOG: for.body.4:
; PROLOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3 ; PROLOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3
; PROLOG-NEXT: %8 = load i32, ptr %arrayidx.4, align 4 ; PROLOG-NEXT: %8 = load i32, ptr %arrayidx.4, align 4
; PROLOG-NEXT: %add.4 = add nsw i32 %8, %add.3 ; PROLOG-NEXT: %add.4 = add nsw i32 %8, %add.3
; PROLOG-NEXT: %indvars.iv.next.4 = add i64 %indvars.iv.next.3, 1 ; PROLOG-NEXT: %indvars.iv.next.4 = add i64 %indvars.iv, 5
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.5 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.5
; PROLOG: for.exiting_block.5: ; PROLOG: for.exiting_block.5:
; PROLOG-NEXT: %cmp.5 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.5 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.5, label %for.exit2.loopexit, label %for.body.5 ; PROLOG-NEXT: br i1 %cmp.5, label %for.exit2.loopexit, label %for.body.5
; PROLOG: for.body.5: ; PROLOG: for.body.5:
; PROLOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4 ; PROLOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4
; PROLOG-NEXT: %9 = load i32, ptr %arrayidx.5, align 4 ; PROLOG-NEXT: %9 = load i32, ptr %arrayidx.5, align 4
; PROLOG-NEXT: %add.5 = add nsw i32 %9, %add.4 ; PROLOG-NEXT: %add.5 = add nsw i32 %9, %add.4
; PROLOG-NEXT: %indvars.iv.next.5 = add i64 %indvars.iv.next.4, 1 ; PROLOG-NEXT: %indvars.iv.next.5 = add i64 %indvars.iv, 6
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.6 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.6
; PROLOG: for.exiting_block.6: ; PROLOG: for.exiting_block.6:
; PROLOG-NEXT: %cmp.6 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.6 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.6, label %for.exit2.loopexit, label %for.body.6 ; PROLOG-NEXT: br i1 %cmp.6, label %for.exit2.loopexit, label %for.body.6
; PROLOG: for.body.6: ; PROLOG: for.body.6:
; PROLOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5 ; PROLOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5
; PROLOG-NEXT: %10 = load i32, ptr %arrayidx.6, align 4 ; PROLOG-NEXT: %10 = load i32, ptr %arrayidx.6, align 4
; PROLOG-NEXT: %add.6 = add nsw i32 %10, %add.5 ; PROLOG-NEXT: %add.6 = add nsw i32 %10, %add.5
; PROLOG-NEXT: %indvars.iv.next.6 = add i64 %indvars.iv.next.5, 1 ; PROLOG-NEXT: %indvars.iv.next.6 = add i64 %indvars.iv, 7
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.7 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.7
; PROLOG: for.exiting_block.7: ; PROLOG: for.exiting_block.7:
; PROLOG-NEXT: %cmp.7 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.7, label %for.exit2.loopexit, label %for.body.7 ; PROLOG-NEXT: br i1 %cmp.7, label %for.exit2.loopexit, label %for.body.7
; PROLOG: for.body.7: ; PROLOG: for.body.7:
; PROLOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6 ; PROLOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; PROLOG-NEXT: %11 = load i32, ptr %arrayidx.7, align 4 ; PROLOG-NEXT: %11 = load i32, ptr %arrayidx.7, align 4
; PROLOG-NEXT: %add.7 = add nsw i32 %11, %add.6 ; PROLOG-NEXT: %add.7 = add nsw i32 %11, %add.6
; PROLOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv.next.6, 1 ; PROLOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
; PROLOG-NEXT: %exitcond.7 = icmp eq i64 %indvars.iv.next.7, %n ; PROLOG-NEXT: %exitcond.7 = icmp eq i64 %indvars.iv.next.7, %n
; PROLOG-NEXT: br i1 %exitcond.7, label %for.end.unr-lcssa, label %header ; PROLOG-NEXT: br i1 %exitcond.7, label %for.end.unr-lcssa, label %header
; PROLOG: for.end.unr-lcssa: ; PROLOG: for.end.unr-lcssa:
; PROLOG-NEXT: %sum.0.lcssa.ph = phi i32 [ %add.7, %for.body.7 ] ; PROLOG-NEXT: %sum.0.lcssa.ph = phi i32 [ %add.7, %for.body.7 ]
; PROLOG-NEXT: br label %for.end ; PROLOG-NEXT: br label %for.end
; PROLOG: for.end: ; PROLOG: for.end:
; PROLOG-NEXT: %sum.0.lcssa = phi i32 [ %sum.0.lcssa.unr, %header.prol.loopexit ], [ %sum.0.lcssa.ph, %for.end.unr-lcssa ] ; PROLOG-NEXT: %sum.0.lcssa = phi i32 [ %sum.0.lcssa.unr, %header.prol.loopexit ], [ %sum.0.lcssa.ph, %for.end.unr-lcssa ]
; PROLOG-NEXT: ret i32 %sum.0.lcssa ; PROLOG-NEXT: ret i32 %sum.0.lcssa
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; PROLOG-BLOCK-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1 ; PROLOG-BLOCK-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1
; PROLOG-BLOCK: for.exiting_block.1: ; PROLOG-BLOCK: for.exiting_block.1:
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %for.body.1 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %for.body.1
; PROLOG-BLOCK: for.body.1: ; PROLOG-BLOCK: for.body.1:
; PROLOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; PROLOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; PROLOG-BLOCK-NEXT: %5 = load i32, ptr %arrayidx.1, align 4 ; PROLOG-BLOCK-NEXT: %5 = load i32, ptr %arrayidx.1, align 4
; PROLOG-BLOCK-NEXT: %add.1 = add nsw i32 %5, %add ; PROLOG-BLOCK-NEXT: %add.1 = add nsw i32 %5, %add
; PROLOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; PROLOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; PROLOG-BLOCK-NEXT: %exitcond.1 = icmp eq i64 %indvars.iv.next.1, %n ; PROLOG-BLOCK-NEXT: %exitcond.1 = icmp eq i64 %indvars.iv.next.1, %n
; PROLOG-BLOCK-NEXT: br i1 %exitcond.1, label %for.end.unr-lcssa, label %header, !llvm.loop !2 ; PROLOG-BLOCK-NEXT: br i1 %exitcond.1, label %for.end.unr-lcssa, label %header, !llvm.loop !2
; PROLOG-BLOCK: for.end.unr-lcssa: ; PROLOG-BLOCK: for.end.unr-lcssa:
; PROLOG-BLOCK-NEXT: %sum.0.lcssa.ph = phi i32 [ %add.1, %for.body.1 ] ; PROLOG-BLOCK-NEXT: %sum.0.lcssa.ph = phi i32 [ %add.1, %for.body.1 ]
; PROLOG-BLOCK-NEXT: br label %for.end ; PROLOG-BLOCK-NEXT: br label %for.end
; PROLOG-BLOCK: for.end: ; PROLOG-BLOCK: for.end:
; PROLOG-BLOCK-NEXT: %sum.0.lcssa = phi i32 [ %sum.0.lcssa.unr, %header.prol.loopexit ], [ %sum.0.lcssa.ph, %for.end.unr-lcssa ] ; PROLOG-BLOCK-NEXT: %sum.0.lcssa = phi i32 [ %sum.0.lcssa.unr, %header.prol.loopexit ], [ %sum.0.lcssa.ph, %for.end.unr-lcssa ]
; PROLOG-BLOCK-NEXT: ret i32 %sum.0.lcssa ; PROLOG-BLOCK-NEXT: ret i32 %sum.0.lcssa
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: exit3.loopexit: ; EPILOG: exit3.loopexit:
; EPILOG-NEXT: br label %exit3 ; EPILOG-NEXT: br label %exit3
; EPILOG: exit3.loopexit2: ; EPILOG: exit3.loopexit2:
; EPILOG-NEXT: br label %exit3 ; EPILOG-NEXT: br label %exit3
; EPILOG: exit3: ; EPILOG: exit3:
; EPILOG-NEXT: ret void ; EPILOG-NEXT: ret void
; EPILOG: loop_latch: ; EPILOG: loop_latch:
; EPILOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-NEXT: %sum.next = add i64 %sum, %add ; EPILOG-NEXT: %sum.next = add i64 %sum, %add
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: br i1 undef, label %loop_latch.1, label %loop_exiting_bb1.1 ; EPILOG-NEXT: br i1 undef, label %loop_latch.1, label %loop_exiting_bb1.1
; EPILOG: loop_exiting_bb1.1: ; EPILOG: loop_exiting_bb1.1:
; EPILOG-NEXT: switch i64 %sum.next, label %loop_latch.1 [ ; EPILOG-NEXT: switch i64 %sum.next, label %loop_latch.1 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit3.loopexit ; EPILOG-NEXT: i64 42, label %exit3.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.1: ; EPILOG: loop_latch.1:
; EPILOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1
; EPILOG-NEXT: %sum.next.1 = add i64 %sum.next, %add ; EPILOG-NEXT: %sum.next.1 = add i64 %sum.next, %add
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: br i1 undef, label %loop_latch.2, label %loop_exiting_bb1.2 ; EPILOG-NEXT: br i1 undef, label %loop_latch.2, label %loop_exiting_bb1.2
; EPILOG: loop_exiting_bb1.2: ; EPILOG: loop_exiting_bb1.2:
; EPILOG-NEXT: switch i64 %sum.next.1, label %loop_latch.2 [ ; EPILOG-NEXT: switch i64 %sum.next.1, label %loop_latch.2 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit3.loopexit ; EPILOG-NEXT: i64 42, label %exit3.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.2: ; EPILOG: loop_latch.2:
; EPILOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv_next.1, 1
; EPILOG-NEXT: %sum.next.2 = add i64 %sum.next.1, %add ; EPILOG-NEXT: %sum.next.2 = add i64 %sum.next.1, %add
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: br i1 undef, label %loop_latch.3, label %loop_exiting_bb1.3 ; EPILOG-NEXT: br i1 undef, label %loop_latch.3, label %loop_exiting_bb1.3
; EPILOG: loop_exiting_bb1.3: ; EPILOG: loop_exiting_bb1.3:
; EPILOG-NEXT: switch i64 %sum.next.2, label %loop_latch.3 [ ; EPILOG-NEXT: switch i64 %sum.next.2, label %loop_latch.3 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit3.loopexit ; EPILOG-NEXT: i64 42, label %exit3.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.3: ; EPILOG: loop_latch.3:
; EPILOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv_next.2, 1
; EPILOG-NEXT: %sum.next.3 = add i64 %sum.next.2, %add ; EPILOG-NEXT: %sum.next.3 = add i64 %sum.next.2, %add
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: br i1 undef, label %loop_latch.4, label %loop_exiting_bb1.4 ; EPILOG-NEXT: br i1 undef, label %loop_latch.4, label %loop_exiting_bb1.4
; EPILOG: loop_exiting_bb1.4: ; EPILOG: loop_exiting_bb1.4:
; EPILOG-NEXT: switch i64 %sum.next.3, label %loop_latch.4 [ ; EPILOG-NEXT: switch i64 %sum.next.3, label %loop_latch.4 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit3.loopexit ; EPILOG-NEXT: i64 42, label %exit3.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.4: ; EPILOG: loop_latch.4:
; EPILOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv_next.3, 1
; EPILOG-NEXT: %sum.next.4 = add i64 %sum.next.3, %add ; EPILOG-NEXT: %sum.next.4 = add i64 %sum.next.3, %add
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: br i1 undef, label %loop_latch.5, label %loop_exiting_bb1.5 ; EPILOG-NEXT: br i1 undef, label %loop_latch.5, label %loop_exiting_bb1.5
; EPILOG: loop_exiting_bb1.5: ; EPILOG: loop_exiting_bb1.5:
; EPILOG-NEXT: switch i64 %sum.next.4, label %loop_latch.5 [ ; EPILOG-NEXT: switch i64 %sum.next.4, label %loop_latch.5 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit3.loopexit ; EPILOG-NEXT: i64 42, label %exit3.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.5: ; EPILOG: loop_latch.5:
; EPILOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv_next.4, 1
; EPILOG-NEXT: %sum.next.5 = add i64 %sum.next.4, %add ; EPILOG-NEXT: %sum.next.5 = add i64 %sum.next.4, %add
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: br i1 undef, label %loop_latch.6, label %loop_exiting_bb1.6 ; EPILOG-NEXT: br i1 undef, label %loop_latch.6, label %loop_exiting_bb1.6
; EPILOG: loop_exiting_bb1.6: ; EPILOG: loop_exiting_bb1.6:
; EPILOG-NEXT: switch i64 %sum.next.5, label %loop_latch.6 [ ; EPILOG-NEXT: switch i64 %sum.next.5, label %loop_latch.6 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit3.loopexit ; EPILOG-NEXT: i64 42, label %exit3.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.6: ; EPILOG: loop_latch.6:
; EPILOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv_next.5, 1
; EPILOG-NEXT: %sum.next.6 = add i64 %sum.next.5, %add ; EPILOG-NEXT: %sum.next.6 = add i64 %sum.next.5, %add
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: br i1 undef, label %loop_latch.7, label %loop_exiting_bb1.7 ; EPILOG-NEXT: br i1 undef, label %loop_latch.7, label %loop_exiting_bb1.7
; EPILOG: loop_exiting_bb1.7: ; EPILOG: loop_exiting_bb1.7:
; EPILOG-NEXT: switch i64 %sum.next.6, label %loop_latch.7 [ ; EPILOG-NEXT: switch i64 %sum.next.6, label %loop_latch.7 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit3.loopexit ; EPILOG-NEXT: i64 42, label %exit3.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.7: ; EPILOG: loop_latch.7:
; EPILOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv_next.6, 1 ; EPILOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv, 8
; EPILOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add ; EPILOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa.loopexit ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa.loopexit
; EPILOG: exit1.loopexit: ; EPILOG: exit1.loopexit:
; EPILOG-NEXT: br label %exit1 ; EPILOG-NEXT: br label %exit1
; EPILOG: exit1.loopexit1: ; EPILOG: exit1.loopexit1:
; EPILOG-NEXT: br label %exit1 ; EPILOG-NEXT: br label %exit1
; EPILOG: exit1: ; EPILOG: exit1:
; EPILOG-NEXT: ret void ; EPILOG-NEXT: ret void
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; EPILOG-BLOCK-NEXT: i64 24, label %exit1.loopexit ; EPILOG-BLOCK-NEXT: i64 24, label %exit1.loopexit
; EPILOG-BLOCK-NEXT: i64 42, label %exit3.loopexit ; EPILOG-BLOCK-NEXT: i64 42, label %exit3.loopexit
; EPILOG-BLOCK-NEXT: ] ; EPILOG-BLOCK-NEXT: ]
; EPILOG-BLOCK: exit3.loopexit: ; EPILOG-BLOCK: exit3.loopexit:
; EPILOG-BLOCK-NEXT: br label %exit3 ; EPILOG-BLOCK-NEXT: br label %exit3
; EPILOG-BLOCK: exit3: ; EPILOG-BLOCK: exit3:
; EPILOG-BLOCK-NEXT: ret void ; EPILOG-BLOCK-NEXT: ret void
; EPILOG-BLOCK: loop_latch: ; EPILOG-BLOCK: loop_latch:
; EPILOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-BLOCK-NEXT: %sum.next = add i64 %sum, %add ; EPILOG-BLOCK-NEXT: %sum.next = add i64 %sum, %add
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: br i1 undef, label %loop_latch.1, label %loop_exiting_bb1.1 ; EPILOG-BLOCK-NEXT: br i1 undef, label %loop_latch.1, label %loop_exiting_bb1.1
; EPILOG-BLOCK: loop_exiting_bb1.1: ; EPILOG-BLOCK: loop_exiting_bb1.1:
; EPILOG-BLOCK-NEXT: switch i64 %sum.next, label %loop_latch.1 [ ; EPILOG-BLOCK-NEXT: switch i64 %sum.next, label %loop_latch.1 [
; EPILOG-BLOCK-NEXT: i64 24, label %exit1.loopexit ; EPILOG-BLOCK-NEXT: i64 24, label %exit1.loopexit
; EPILOG-BLOCK-NEXT: i64 42, label %exit3.loopexit ; EPILOG-BLOCK-NEXT: i64 42, label %exit3.loopexit
; EPILOG-BLOCK-NEXT: ] ; EPILOG-BLOCK-NEXT: ]
; EPILOG-BLOCK: loop_latch.1: ; EPILOG-BLOCK: loop_latch.1:
; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1 ; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; EPILOG-BLOCK-NEXT: %sum.next.1 = add i64 %sum.next, %add ; EPILOG-BLOCK-NEXT: %sum.next.1 = add i64 %sum.next, %add
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.loopexit.unr-lcssa.loopexit, !llvm.loop !3 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.loopexit.unr-lcssa.loopexit, !llvm.loop !3
; EPILOG-BLOCK: exit1.loopexit: ; EPILOG-BLOCK: exit1.loopexit:
; EPILOG-BLOCK-NEXT: br label %exit1 ; EPILOG-BLOCK-NEXT: br label %exit1
; EPILOG-BLOCK: exit1: ; EPILOG-BLOCK: exit1:
; EPILOG-BLOCK-NEXT: ret void ; EPILOG-BLOCK-NEXT: ret void
; EPILOG-BLOCK: exit2.loopexit.unr-lcssa.loopexit: ; EPILOG-BLOCK: exit2.loopexit.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: %sum.unr.ph = phi i64 [ %sum.next.1, %loop_latch.1 ] ; EPILOG-BLOCK-NEXT: %sum.unr.ph = phi i64 [ %sum.next.1, %loop_latch.1 ]
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: exit3.loopexit: ; PROLOG: exit3.loopexit:
; PROLOG-NEXT: br label %exit3 ; PROLOG-NEXT: br label %exit3
; PROLOG: exit3.loopexit2: ; PROLOG: exit3.loopexit2:
; PROLOG-NEXT: br label %exit3 ; PROLOG-NEXT: br label %exit3
; PROLOG: exit3: ; PROLOG: exit3:
; PROLOG-NEXT: ret void ; PROLOG-NEXT: ret void
; PROLOG: loop_latch: ; PROLOG: loop_latch:
; PROLOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; PROLOG-NEXT: %sum.next = add i64 %sum, %add ; PROLOG-NEXT: %sum.next = add i64 %sum, %add
; PROLOG-NEXT: br i1 undef, label %loop_latch.1, label %loop_exiting_bb1.1 ; PROLOG-NEXT: br i1 undef, label %loop_latch.1, label %loop_exiting_bb1.1
; PROLOG: loop_exiting_bb1.1: ; PROLOG: loop_exiting_bb1.1:
; PROLOG-NEXT: switch i64 %sum.next, label %loop_latch.1 [ ; PROLOG-NEXT: switch i64 %sum.next, label %loop_latch.1 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit3.loopexit ; PROLOG-NEXT: i64 42, label %exit3.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.1: ; PROLOG: loop_latch.1:
; PROLOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1
; PROLOG-NEXT: %sum.next.1 = add i64 %sum.next, %add ; PROLOG-NEXT: %sum.next.1 = add i64 %sum.next, %add
; PROLOG-NEXT: br i1 undef, label %loop_latch.2, label %loop_exiting_bb1.2 ; PROLOG-NEXT: br i1 undef, label %loop_latch.2, label %loop_exiting_bb1.2
; PROLOG: loop_exiting_bb1.2: ; PROLOG: loop_exiting_bb1.2:
; PROLOG-NEXT: switch i64 %sum.next.1, label %loop_latch.2 [ ; PROLOG-NEXT: switch i64 %sum.next.1, label %loop_latch.2 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit3.loopexit ; PROLOG-NEXT: i64 42, label %exit3.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.2: ; PROLOG: loop_latch.2:
; PROLOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv_next.1, 1
; PROLOG-NEXT: %sum.next.2 = add i64 %sum.next.1, %add ; PROLOG-NEXT: %sum.next.2 = add i64 %sum.next.1, %add
; PROLOG-NEXT: br i1 undef, label %loop_latch.3, label %loop_exiting_bb1.3 ; PROLOG-NEXT: br i1 undef, label %loop_latch.3, label %loop_exiting_bb1.3
; PROLOG: loop_exiting_bb1.3: ; PROLOG: loop_exiting_bb1.3:
; PROLOG-NEXT: switch i64 %sum.next.2, label %loop_latch.3 [ ; PROLOG-NEXT: switch i64 %sum.next.2, label %loop_latch.3 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit3.loopexit ; PROLOG-NEXT: i64 42, label %exit3.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.3: ; PROLOG: loop_latch.3:
; PROLOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv_next.2, 1
; PROLOG-NEXT: %sum.next.3 = add i64 %sum.next.2, %add ; PROLOG-NEXT: %sum.next.3 = add i64 %sum.next.2, %add
; PROLOG-NEXT: br i1 undef, label %loop_latch.4, label %loop_exiting_bb1.4 ; PROLOG-NEXT: br i1 undef, label %loop_latch.4, label %loop_exiting_bb1.4
; PROLOG: loop_exiting_bb1.4: ; PROLOG: loop_exiting_bb1.4:
; PROLOG-NEXT: switch i64 %sum.next.3, label %loop_latch.4 [ ; PROLOG-NEXT: switch i64 %sum.next.3, label %loop_latch.4 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit3.loopexit ; PROLOG-NEXT: i64 42, label %exit3.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.4: ; PROLOG: loop_latch.4:
; PROLOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv_next.3, 1
; PROLOG-NEXT: %sum.next.4 = add i64 %sum.next.3, %add ; PROLOG-NEXT: %sum.next.4 = add i64 %sum.next.3, %add
; PROLOG-NEXT: br i1 undef, label %loop_latch.5, label %loop_exiting_bb1.5 ; PROLOG-NEXT: br i1 undef, label %loop_latch.5, label %loop_exiting_bb1.5
; PROLOG: loop_exiting_bb1.5: ; PROLOG: loop_exiting_bb1.5:
; PROLOG-NEXT: switch i64 %sum.next.4, label %loop_latch.5 [ ; PROLOG-NEXT: switch i64 %sum.next.4, label %loop_latch.5 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit3.loopexit ; PROLOG-NEXT: i64 42, label %exit3.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.5: ; PROLOG: loop_latch.5:
; PROLOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv_next.4, 1
; PROLOG-NEXT: %sum.next.5 = add i64 %sum.next.4, %add ; PROLOG-NEXT: %sum.next.5 = add i64 %sum.next.4, %add
; PROLOG-NEXT: br i1 undef, label %loop_latch.6, label %loop_exiting_bb1.6 ; PROLOG-NEXT: br i1 undef, label %loop_latch.6, label %loop_exiting_bb1.6
; PROLOG: loop_exiting_bb1.6: ; PROLOG: loop_exiting_bb1.6:
; PROLOG-NEXT: switch i64 %sum.next.5, label %loop_latch.6 [ ; PROLOG-NEXT: switch i64 %sum.next.5, label %loop_latch.6 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit3.loopexit ; PROLOG-NEXT: i64 42, label %exit3.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.6: ; PROLOG: loop_latch.6:
; PROLOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv_next.5, 1
; PROLOG-NEXT: %sum.next.6 = add i64 %sum.next.5, %add ; PROLOG-NEXT: %sum.next.6 = add i64 %sum.next.5, %add
; PROLOG-NEXT: br i1 undef, label %loop_latch.7, label %loop_exiting_bb1.7 ; PROLOG-NEXT: br i1 undef, label %loop_latch.7, label %loop_exiting_bb1.7
; PROLOG: loop_exiting_bb1.7: ; PROLOG: loop_exiting_bb1.7:
; PROLOG-NEXT: switch i64 %sum.next.6, label %loop_latch.7 [ ; PROLOG-NEXT: switch i64 %sum.next.6, label %loop_latch.7 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit3.loopexit ; PROLOG-NEXT: i64 42, label %exit3.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.7: ; PROLOG: loop_latch.7:
; PROLOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv_next.6, 1 ; PROLOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv, 8
; PROLOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add ; PROLOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add
; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip ; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip
; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa ; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa
; PROLOG: exit1.loopexit: ; PROLOG: exit1.loopexit:
; PROLOG-NEXT: br label %exit1 ; PROLOG-NEXT: br label %exit1
; PROLOG: exit1.loopexit1: ; PROLOG: exit1.loopexit1:
; PROLOG-NEXT: br label %exit1 ; PROLOG-NEXT: br label %exit1
; PROLOG: exit1: ; PROLOG: exit1:
Show All 37 Lines
; PROLOG-BLOCK-NEXT: i64 24, label %exit1.loopexit ; PROLOG-BLOCK-NEXT: i64 24, label %exit1.loopexit
; PROLOG-BLOCK-NEXT: i64 42, label %exit3.loopexit ; PROLOG-BLOCK-NEXT: i64 42, label %exit3.loopexit
; PROLOG-BLOCK-NEXT: ] ; PROLOG-BLOCK-NEXT: ]
; PROLOG-BLOCK: exit3.loopexit: ; PROLOG-BLOCK: exit3.loopexit:
; PROLOG-BLOCK-NEXT: br label %exit3 ; PROLOG-BLOCK-NEXT: br label %exit3
; PROLOG-BLOCK: exit3: ; PROLOG-BLOCK: exit3:
; PROLOG-BLOCK-NEXT: ret void ; PROLOG-BLOCK-NEXT: ret void
; PROLOG-BLOCK: loop_latch: ; PROLOG-BLOCK: loop_latch:
; PROLOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; PROLOG-BLOCK-NEXT: %sum.next = add i64 %sum, %add ; PROLOG-BLOCK-NEXT: %sum.next = add i64 %sum, %add
; PROLOG-BLOCK-NEXT: br i1 undef, label %loop_latch.1, label %loop_exiting_bb1.1 ; PROLOG-BLOCK-NEXT: br i1 undef, label %loop_latch.1, label %loop_exiting_bb1.1
; PROLOG-BLOCK: loop_exiting_bb1.1: ; PROLOG-BLOCK: loop_exiting_bb1.1:
; PROLOG-BLOCK-NEXT: switch i64 %sum.next, label %loop_latch.1 [ ; PROLOG-BLOCK-NEXT: switch i64 %sum.next, label %loop_latch.1 [
; PROLOG-BLOCK-NEXT: i64 24, label %exit1.loopexit ; PROLOG-BLOCK-NEXT: i64 24, label %exit1.loopexit
; PROLOG-BLOCK-NEXT: i64 42, label %exit3.loopexit ; PROLOG-BLOCK-NEXT: i64 42, label %exit3.loopexit
; PROLOG-BLOCK-NEXT: ] ; PROLOG-BLOCK-NEXT: ]
; PROLOG-BLOCK: loop_latch.1: ; PROLOG-BLOCK: loop_latch.1:
; PROLOG-BLOCK-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1 ; PROLOG-BLOCK-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; PROLOG-BLOCK-NEXT: %sum.next.1 = add i64 %sum.next, %add ; PROLOG-BLOCK-NEXT: %sum.next.1 = add i64 %sum.next, %add
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit2.loopexit.unr-lcssa, !llvm.loop !3 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit2.loopexit.unr-lcssa, !llvm.loop !3
; PROLOG-BLOCK: exit1.loopexit: ; PROLOG-BLOCK: exit1.loopexit:
; PROLOG-BLOCK-NEXT: br label %exit1 ; PROLOG-BLOCK-NEXT: br label %exit1
; PROLOG-BLOCK: exit1: ; PROLOG-BLOCK: exit1:
; PROLOG-BLOCK-NEXT: ret void ; PROLOG-BLOCK-NEXT: ret void
; PROLOG-BLOCK: exit2.loopexit.unr-lcssa: ; PROLOG-BLOCK: exit2.loopexit.unr-lcssa:
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; EPILOG: for.exiting_block: ; EPILOG: for.exiting_block:
; EPILOG-NEXT: %cmp = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp, label %for.exit2.loopexit, label %latch ; EPILOG-NEXT: br i1 %cmp, label %for.exit2.loopexit, label %latch
; EPILOG: latch: ; EPILOG: latch:
; EPILOG-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv ; EPILOG-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
; EPILOG-NEXT: %3 = load i32, ptr %arrayidx, align 4 ; EPILOG-NEXT: %3 = load i32, ptr %arrayidx, align 4
; EPILOG-NEXT: %add = add nsw i32 %3, %sum.02 ; EPILOG-NEXT: %add = add nsw i32 %3, %sum.02
; EPILOG-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 ; EPILOG-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.1 ; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.1
; EPILOG: for.exiting_block.1: ; EPILOG: for.exiting_block.1:
; EPILOG-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1 ; EPILOG-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1
; EPILOG: latch.1: ; EPILOG: latch.1:
; EPILOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; EPILOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-NEXT: %4 = load i32, ptr %arrayidx.1, align 4 ; EPILOG-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-NEXT: %add.1 = add nsw i32 %4, %add ; EPILOG-NEXT: %add.1 = add nsw i32 %4, %add
; EPILOG-NEXT: %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv.next, 1 ; EPILOG-NEXT: %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.2 ; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.2
; EPILOG: for.exiting_block.2: ; EPILOG: for.exiting_block.2:
; EPILOG-NEXT: %cmp.2 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.2 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.2, label %for.exit2.loopexit, label %latch.2 ; EPILOG-NEXT: br i1 %cmp.2, label %for.exit2.loopexit, label %latch.2
; EPILOG: latch.2: ; EPILOG: latch.2:
; EPILOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1 ; EPILOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1
; EPILOG-NEXT: %5 = load i32, ptr %arrayidx.2, align 4 ; EPILOG-NEXT: %5 = load i32, ptr %arrayidx.2, align 4
; EPILOG-NEXT: %add.2 = add nsw i32 %5, %add.1 ; EPILOG-NEXT: %add.2 = add nsw i32 %5, %add.1
; EPILOG-NEXT: %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv.next.1, 1 ; EPILOG-NEXT: %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv, 3
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.3 ; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.3
; EPILOG: for.exiting_block.3: ; EPILOG: for.exiting_block.3:
; EPILOG-NEXT: %cmp.3 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.3 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.3, label %for.exit2.loopexit, label %latch.3 ; EPILOG-NEXT: br i1 %cmp.3, label %for.exit2.loopexit, label %latch.3
; EPILOG: latch.3: ; EPILOG: latch.3:
; EPILOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2 ; EPILOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2
; EPILOG-NEXT: %6 = load i32, ptr %arrayidx.3, align 4 ; EPILOG-NEXT: %6 = load i32, ptr %arrayidx.3, align 4
; EPILOG-NEXT: %add.3 = add nsw i32 %6, %add.2 ; EPILOG-NEXT: %add.3 = add nsw i32 %6, %add.2
; EPILOG-NEXT: %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv.next.2, 1 ; EPILOG-NEXT: %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv, 4
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.4 ; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.4
; EPILOG: for.exiting_block.4: ; EPILOG: for.exiting_block.4:
; EPILOG-NEXT: %cmp.4 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.4 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.4, label %for.exit2.loopexit, label %latch.4 ; EPILOG-NEXT: br i1 %cmp.4, label %for.exit2.loopexit, label %latch.4
; EPILOG: latch.4: ; EPILOG: latch.4:
; EPILOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3 ; EPILOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3
; EPILOG-NEXT: %7 = load i32, ptr %arrayidx.4, align 4 ; EPILOG-NEXT: %7 = load i32, ptr %arrayidx.4, align 4
; EPILOG-NEXT: %add.4 = add nsw i32 %7, %add.3 ; EPILOG-NEXT: %add.4 = add nsw i32 %7, %add.3
; EPILOG-NEXT: %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv.next.3, 1 ; EPILOG-NEXT: %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv, 5
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.5 ; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.5
; EPILOG: for.exiting_block.5: ; EPILOG: for.exiting_block.5:
; EPILOG-NEXT: %cmp.5 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.5 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.5, label %for.exit2.loopexit, label %latch.5 ; EPILOG-NEXT: br i1 %cmp.5, label %for.exit2.loopexit, label %latch.5
; EPILOG: latch.5: ; EPILOG: latch.5:
; EPILOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4 ; EPILOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4
; EPILOG-NEXT: %8 = load i32, ptr %arrayidx.5, align 4 ; EPILOG-NEXT: %8 = load i32, ptr %arrayidx.5, align 4
; EPILOG-NEXT: %add.5 = add nsw i32 %8, %add.4 ; EPILOG-NEXT: %add.5 = add nsw i32 %8, %add.4
; EPILOG-NEXT: %indvars.iv.next.5 = add nuw nsw i64 %indvars.iv.next.4, 1 ; EPILOG-NEXT: %indvars.iv.next.5 = add nuw nsw i64 %indvars.iv, 6
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.6 ; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.6
; EPILOG: for.exiting_block.6: ; EPILOG: for.exiting_block.6:
; EPILOG-NEXT: %cmp.6 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.6 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.6, label %for.exit2.loopexit, label %latch.6 ; EPILOG-NEXT: br i1 %cmp.6, label %for.exit2.loopexit, label %latch.6
; EPILOG: latch.6: ; EPILOG: latch.6:
; EPILOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5 ; EPILOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5
; EPILOG-NEXT: %9 = load i32, ptr %arrayidx.6, align 4 ; EPILOG-NEXT: %9 = load i32, ptr %arrayidx.6, align 4
; EPILOG-NEXT: %add.6 = add nsw i32 %9, %add.5 ; EPILOG-NEXT: %add.6 = add nsw i32 %9, %add.5
; EPILOG-NEXT: %indvars.iv.next.6 = add nuw nsw i64 %indvars.iv.next.5, 1 ; EPILOG-NEXT: %indvars.iv.next.6 = add nuw nsw i64 %indvars.iv, 7
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.7 ; EPILOG-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.7
; EPILOG: for.exiting_block.7: ; EPILOG: for.exiting_block.7:
; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.7, label %for.exit2.loopexit, label %latch.7 ; EPILOG-NEXT: br i1 %cmp.7, label %for.exit2.loopexit, label %latch.7
; EPILOG: latch.7: ; EPILOG: latch.7:
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6 ; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4 ; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6 ; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv.next.6, 1 ; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa.loopexit, label %header ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa.loopexit, label %header
; EPILOG: latchExit.unr-lcssa.loopexit: ; EPILOG: latchExit.unr-lcssa.loopexit:
; EPILOG-NEXT: %result.ph.ph = phi i32 [ %add.7, %latch.7 ] ; EPILOG-NEXT: %result.ph.ph = phi i32 [ %add.7, %latch.7 ]
; EPILOG-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.7, %latch.7 ] ; EPILOG-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.7, %latch.7 ]
; EPILOG-NEXT: %sum.02.unr.ph = phi i32 [ %add.7, %latch.7 ] ; EPILOG-NEXT: %sum.02.unr.ph = phi i32 [ %add.7, %latch.7 ]
; EPILOG-NEXT: br label %latchExit.unr-lcssa ; EPILOG-NEXT: br label %latchExit.unr-lcssa
; EPILOG: latchExit.unr-lcssa: ; EPILOG: latchExit.unr-lcssa:
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; EPILOG-BLOCK: for.exiting_block: ; EPILOG-BLOCK: for.exiting_block:
; EPILOG-BLOCK-NEXT: %cmp = icmp eq i64 %n, 42 ; EPILOG-BLOCK-NEXT: %cmp = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp, label %for.exit2.loopexit, label %latch ; EPILOG-BLOCK-NEXT: br i1 %cmp, label %for.exit2.loopexit, label %latch
; EPILOG-BLOCK: latch: ; EPILOG-BLOCK: latch:
; EPILOG-BLOCK-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv ; EPILOG-BLOCK-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
; EPILOG-BLOCK-NEXT: %3 = load i32, ptr %arrayidx, align 4 ; EPILOG-BLOCK-NEXT: %3 = load i32, ptr %arrayidx, align 4
; EPILOG-BLOCK-NEXT: %add = add nsw i32 %3, %sum.02 ; EPILOG-BLOCK-NEXT: %add = add nsw i32 %3, %sum.02
; EPILOG-BLOCK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 ; EPILOG-BLOCK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.1 ; EPILOG-BLOCK-NEXT: br i1 %cond, label %latchExit.epilog-lcssa.loopexit, label %for.exiting_block.1
; EPILOG-BLOCK: for.exiting_block.1: ; EPILOG-BLOCK: for.exiting_block.1:
; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1 ; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1
; EPILOG-BLOCK: latch.1: ; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4 ; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add ; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !4 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !4
; EPILOG-BLOCK: latchExit.unr-lcssa.loopexit: ; EPILOG-BLOCK: latchExit.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ %add.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ %add.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %sum.02.unr.ph = phi i32 [ %add.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %sum.02.unr.ph = phi i32 [ %add.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: br label %latchExit.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %latchExit.unr-lcssa
; EPILOG-BLOCK: latchExit.unr-lcssa: ; EPILOG-BLOCK: latchExit.unr-lcssa:
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; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.1 ; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.1
; PROLOG: for.exiting_block.1: ; PROLOG: for.exiting_block.1:
; PROLOG-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.1 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1 ; PROLOG-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1
; PROLOG: latch.1: ; PROLOG: latch.1:
; PROLOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; PROLOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; PROLOG-NEXT: %5 = load i32, ptr %arrayidx.1, align 4 ; PROLOG-NEXT: %5 = load i32, ptr %arrayidx.1, align 4
; PROLOG-NEXT: %add.1 = add nsw i32 %5, %add ; PROLOG-NEXT: %add.1 = add nsw i32 %5, %add
; PROLOG-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; PROLOG-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.2 ; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.2
; PROLOG: for.exiting_block.2: ; PROLOG: for.exiting_block.2:
; PROLOG-NEXT: %cmp.2 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.2 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.2, label %for.exit2.loopexit, label %latch.2 ; PROLOG-NEXT: br i1 %cmp.2, label %for.exit2.loopexit, label %latch.2
; PROLOG: latch.2: ; PROLOG: latch.2:
; PROLOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1 ; PROLOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1
; PROLOG-NEXT: %6 = load i32, ptr %arrayidx.2, align 4 ; PROLOG-NEXT: %6 = load i32, ptr %arrayidx.2, align 4
; PROLOG-NEXT: %add.2 = add nsw i32 %6, %add.1 ; PROLOG-NEXT: %add.2 = add nsw i32 %6, %add.1
; PROLOG-NEXT: %indvars.iv.next.2 = add i64 %indvars.iv.next.1, 1 ; PROLOG-NEXT: %indvars.iv.next.2 = add i64 %indvars.iv, 3
; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.3 ; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.3
; PROLOG: for.exiting_block.3: ; PROLOG: for.exiting_block.3:
; PROLOG-NEXT: %cmp.3 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.3 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.3, label %for.exit2.loopexit, label %latch.3 ; PROLOG-NEXT: br i1 %cmp.3, label %for.exit2.loopexit, label %latch.3
; PROLOG: latch.3: ; PROLOG: latch.3:
; PROLOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2 ; PROLOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2
; PROLOG-NEXT: %7 = load i32, ptr %arrayidx.3, align 4 ; PROLOG-NEXT: %7 = load i32, ptr %arrayidx.3, align 4
; PROLOG-NEXT: %add.3 = add nsw i32 %7, %add.2 ; PROLOG-NEXT: %add.3 = add nsw i32 %7, %add.2
; PROLOG-NEXT: %indvars.iv.next.3 = add i64 %indvars.iv.next.2, 1 ; PROLOG-NEXT: %indvars.iv.next.3 = add i64 %indvars.iv, 4
; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.4 ; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.4
; PROLOG: for.exiting_block.4: ; PROLOG: for.exiting_block.4:
; PROLOG-NEXT: %cmp.4 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.4 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.4, label %for.exit2.loopexit, label %latch.4 ; PROLOG-NEXT: br i1 %cmp.4, label %for.exit2.loopexit, label %latch.4
; PROLOG: latch.4: ; PROLOG: latch.4:
; PROLOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3 ; PROLOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3
; PROLOG-NEXT: %8 = load i32, ptr %arrayidx.4, align 4 ; PROLOG-NEXT: %8 = load i32, ptr %arrayidx.4, align 4
; PROLOG-NEXT: %add.4 = add nsw i32 %8, %add.3 ; PROLOG-NEXT: %add.4 = add nsw i32 %8, %add.3
; PROLOG-NEXT: %indvars.iv.next.4 = add i64 %indvars.iv.next.3, 1 ; PROLOG-NEXT: %indvars.iv.next.4 = add i64 %indvars.iv, 5
; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.5 ; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.5
; PROLOG: for.exiting_block.5: ; PROLOG: for.exiting_block.5:
; PROLOG-NEXT: %cmp.5 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.5 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.5, label %for.exit2.loopexit, label %latch.5 ; PROLOG-NEXT: br i1 %cmp.5, label %for.exit2.loopexit, label %latch.5
; PROLOG: latch.5: ; PROLOG: latch.5:
; PROLOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4 ; PROLOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4
; PROLOG-NEXT: %9 = load i32, ptr %arrayidx.5, align 4 ; PROLOG-NEXT: %9 = load i32, ptr %arrayidx.5, align 4
; PROLOG-NEXT: %add.5 = add nsw i32 %9, %add.4 ; PROLOG-NEXT: %add.5 = add nsw i32 %9, %add.4
; PROLOG-NEXT: %indvars.iv.next.5 = add i64 %indvars.iv.next.4, 1 ; PROLOG-NEXT: %indvars.iv.next.5 = add i64 %indvars.iv, 6
; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.6 ; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.6
; PROLOG: for.exiting_block.6: ; PROLOG: for.exiting_block.6:
; PROLOG-NEXT: %cmp.6 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.6 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.6, label %for.exit2.loopexit, label %latch.6 ; PROLOG-NEXT: br i1 %cmp.6, label %for.exit2.loopexit, label %latch.6
; PROLOG: latch.6: ; PROLOG: latch.6:
; PROLOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5 ; PROLOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5
; PROLOG-NEXT: %10 = load i32, ptr %arrayidx.6, align 4 ; PROLOG-NEXT: %10 = load i32, ptr %arrayidx.6, align 4
; PROLOG-NEXT: %add.6 = add nsw i32 %10, %add.5 ; PROLOG-NEXT: %add.6 = add nsw i32 %10, %add.5
; PROLOG-NEXT: %indvars.iv.next.6 = add i64 %indvars.iv.next.5, 1 ; PROLOG-NEXT: %indvars.iv.next.6 = add i64 %indvars.iv, 7
; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.7 ; PROLOG-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.7
; PROLOG: for.exiting_block.7: ; PROLOG: for.exiting_block.7:
; PROLOG-NEXT: %cmp.7 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.7, label %for.exit2.loopexit, label %latch.7 ; PROLOG-NEXT: br i1 %cmp.7, label %for.exit2.loopexit, label %latch.7
; PROLOG: latch.7: ; PROLOG: latch.7:
; PROLOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6 ; PROLOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; PROLOG-NEXT: %11 = load i32, ptr %arrayidx.7, align 4 ; PROLOG-NEXT: %11 = load i32, ptr %arrayidx.7, align 4
; PROLOG-NEXT: %add.7 = add nsw i32 %11, %add.6 ; PROLOG-NEXT: %add.7 = add nsw i32 %11, %add.6
; PROLOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv.next.6, 1 ; PROLOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
; PROLOG-NEXT: %exitcond.7 = icmp eq i64 %indvars.iv.next.7, %n ; PROLOG-NEXT: %exitcond.7 = icmp eq i64 %indvars.iv.next.7, %n
; PROLOG-NEXT: br i1 %exitcond.7, label %latchExit.unr-lcssa.loopexit, label %header ; PROLOG-NEXT: br i1 %exitcond.7, label %latchExit.unr-lcssa.loopexit, label %header
; PROLOG: latchExit.unr-lcssa.loopexit: ; PROLOG: latchExit.unr-lcssa.loopexit:
; PROLOG-NEXT: %result.ph.ph = phi i32 [ 0, %header ], [ 0, %latch ], [ 0, %latch.1 ], [ 0, %latch.2 ], [ 0, %latch.3 ], [ 0, %latch.4 ], [ 0, %latch.5 ], [ 0, %latch.6 ], [ %add.7, %latch.7 ] ; PROLOG-NEXT: %result.ph.ph = phi i32 [ 0, %header ], [ 0, %latch ], [ 0, %latch.1 ], [ 0, %latch.2 ], [ 0, %latch.3 ], [ 0, %latch.4 ], [ 0, %latch.5 ], [ 0, %latch.6 ], [ %add.7, %latch.7 ]
; PROLOG-NEXT: br label %latchExit.unr-lcssa ; PROLOG-NEXT: br label %latchExit.unr-lcssa
; PROLOG: latchExit.unr-lcssa.loopexit1: ; PROLOG: latchExit.unr-lcssa.loopexit1:
; PROLOG-NEXT: %result.ph.ph2 = phi i32 [ 0, %header.prol ] ; PROLOG-NEXT: %result.ph.ph2 = phi i32 [ 0, %header.prol ]
; PROLOG-NEXT: br label %latchExit.unr-lcssa ; PROLOG-NEXT: br label %latchExit.unr-lcssa
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; PROLOG-BLOCK-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.1 ; PROLOG-BLOCK-NEXT: br i1 %cond, label %latchExit.unr-lcssa.loopexit, label %for.exiting_block.1
; PROLOG-BLOCK: for.exiting_block.1: ; PROLOG-BLOCK: for.exiting_block.1:
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1
; PROLOG-BLOCK: latch.1: ; PROLOG-BLOCK: latch.1:
; PROLOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; PROLOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; PROLOG-BLOCK-NEXT: %5 = load i32, ptr %arrayidx.1, align 4 ; PROLOG-BLOCK-NEXT: %5 = load i32, ptr %arrayidx.1, align 4
; PROLOG-BLOCK-NEXT: %add.1 = add nsw i32 %5, %add ; PROLOG-BLOCK-NEXT: %add.1 = add nsw i32 %5, %add
; PROLOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; PROLOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; PROLOG-BLOCK-NEXT: %exitcond.1 = icmp eq i64 %indvars.iv.next.1, %n ; PROLOG-BLOCK-NEXT: %exitcond.1 = icmp eq i64 %indvars.iv.next.1, %n
; PROLOG-BLOCK-NEXT: br i1 %exitcond.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !4 ; PROLOG-BLOCK-NEXT: br i1 %exitcond.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !4
; PROLOG-BLOCK: latchExit.unr-lcssa.loopexit: ; PROLOG-BLOCK: latchExit.unr-lcssa.loopexit:
; PROLOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ 0, %header ], [ 0, %latch ], [ %add.1, %latch.1 ] ; PROLOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ 0, %header ], [ 0, %latch ], [ %add.1, %latch.1 ]
; PROLOG-BLOCK-NEXT: br label %latchExit.unr-lcssa ; PROLOG-BLOCK-NEXT: br label %latchExit.unr-lcssa
; PROLOG-BLOCK: latchExit.unr-lcssa: ; PROLOG-BLOCK: latchExit.unr-lcssa:
; PROLOG-BLOCK-NEXT: %result.ph = phi i32 [ 0, %header.prol ], [ %result.ph.ph, %latchExit.unr-lcssa.loopexit ] ; PROLOG-BLOCK-NEXT: %result.ph = phi i32 [ 0, %header.prol ], [ %result.ph.ph, %latchExit.unr-lcssa.loopexit ]
; PROLOG-BLOCK-NEXT: br label %latchExit ; PROLOG-BLOCK-NEXT: br label %latchExit
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; EPILOG: for.exiting_block: ; EPILOG: for.exiting_block:
; EPILOG-NEXT: %cmp = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp, label %latchExit.epilog-lcssa.loopexit, label %latch ; EPILOG-NEXT: br i1 %cmp, label %latchExit.epilog-lcssa.loopexit, label %latch
; EPILOG: latch: ; EPILOG: latch:
; EPILOG-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv ; EPILOG-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
; EPILOG-NEXT: %3 = load i32, ptr %arrayidx, align 4 ; EPILOG-NEXT: %3 = load i32, ptr %arrayidx, align 4
; EPILOG-NEXT: %add = add nsw i32 %3, %sum.02 ; EPILOG-NEXT: %add = add nsw i32 %3, %sum.02
; EPILOG-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 ; EPILOG-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1
; EPILOG: for.exiting_block.1: ; EPILOG: for.exiting_block.1:
; EPILOG-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1 ; EPILOG-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1
; EPILOG: latch.1: ; EPILOG: latch.1:
; EPILOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; EPILOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-NEXT: %4 = load i32, ptr %arrayidx.1, align 4 ; EPILOG-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-NEXT: %add.1 = add nsw i32 %4, %add ; EPILOG-NEXT: %add.1 = add nsw i32 %4, %add
; EPILOG-NEXT: %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv.next, 1 ; EPILOG-NEXT: %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.2 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.2
; EPILOG: for.exiting_block.2: ; EPILOG: for.exiting_block.2:
; EPILOG-NEXT: %cmp.2 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.2 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.2, label %latchExit.epilog-lcssa.loopexit, label %latch.2 ; EPILOG-NEXT: br i1 %cmp.2, label %latchExit.epilog-lcssa.loopexit, label %latch.2
; EPILOG: latch.2: ; EPILOG: latch.2:
; EPILOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1 ; EPILOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1
; EPILOG-NEXT: %5 = load i32, ptr %arrayidx.2, align 4 ; EPILOG-NEXT: %5 = load i32, ptr %arrayidx.2, align 4
; EPILOG-NEXT: %add.2 = add nsw i32 %5, %add.1 ; EPILOG-NEXT: %add.2 = add nsw i32 %5, %add.1
; EPILOG-NEXT: %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv.next.1, 1 ; EPILOG-NEXT: %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv, 3
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.3 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.3
; EPILOG: for.exiting_block.3: ; EPILOG: for.exiting_block.3:
; EPILOG-NEXT: %cmp.3 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.3 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.3, label %latchExit.epilog-lcssa.loopexit, label %latch.3 ; EPILOG-NEXT: br i1 %cmp.3, label %latchExit.epilog-lcssa.loopexit, label %latch.3
; EPILOG: latch.3: ; EPILOG: latch.3:
; EPILOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2 ; EPILOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2
; EPILOG-NEXT: %6 = load i32, ptr %arrayidx.3, align 4 ; EPILOG-NEXT: %6 = load i32, ptr %arrayidx.3, align 4
; EPILOG-NEXT: %add.3 = add nsw i32 %6, %add.2 ; EPILOG-NEXT: %add.3 = add nsw i32 %6, %add.2
; EPILOG-NEXT: %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv.next.2, 1 ; EPILOG-NEXT: %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv, 4
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.4 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.4
; EPILOG: for.exiting_block.4: ; EPILOG: for.exiting_block.4:
; EPILOG-NEXT: %cmp.4 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.4 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.4, label %latchExit.epilog-lcssa.loopexit, label %latch.4 ; EPILOG-NEXT: br i1 %cmp.4, label %latchExit.epilog-lcssa.loopexit, label %latch.4
; EPILOG: latch.4: ; EPILOG: latch.4:
; EPILOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3 ; EPILOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3
; EPILOG-NEXT: %7 = load i32, ptr %arrayidx.4, align 4 ; EPILOG-NEXT: %7 = load i32, ptr %arrayidx.4, align 4
; EPILOG-NEXT: %add.4 = add nsw i32 %7, %add.3 ; EPILOG-NEXT: %add.4 = add nsw i32 %7, %add.3
; EPILOG-NEXT: %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv.next.3, 1 ; EPILOG-NEXT: %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv, 5
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.5 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.5
; EPILOG: for.exiting_block.5: ; EPILOG: for.exiting_block.5:
; EPILOG-NEXT: %cmp.5 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.5 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.5, label %latchExit.epilog-lcssa.loopexit, label %latch.5 ; EPILOG-NEXT: br i1 %cmp.5, label %latchExit.epilog-lcssa.loopexit, label %latch.5
; EPILOG: latch.5: ; EPILOG: latch.5:
; EPILOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4 ; EPILOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4
; EPILOG-NEXT: %8 = load i32, ptr %arrayidx.5, align 4 ; EPILOG-NEXT: %8 = load i32, ptr %arrayidx.5, align 4
; EPILOG-NEXT: %add.5 = add nsw i32 %8, %add.4 ; EPILOG-NEXT: %add.5 = add nsw i32 %8, %add.4
; EPILOG-NEXT: %indvars.iv.next.5 = add nuw nsw i64 %indvars.iv.next.4, 1 ; EPILOG-NEXT: %indvars.iv.next.5 = add nuw nsw i64 %indvars.iv, 6
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.6 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.6
; EPILOG: for.exiting_block.6: ; EPILOG: for.exiting_block.6:
; EPILOG-NEXT: %cmp.6 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.6 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.6, label %latchExit.epilog-lcssa.loopexit, label %latch.6 ; EPILOG-NEXT: br i1 %cmp.6, label %latchExit.epilog-lcssa.loopexit, label %latch.6
; EPILOG: latch.6: ; EPILOG: latch.6:
; EPILOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5 ; EPILOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5
; EPILOG-NEXT: %9 = load i32, ptr %arrayidx.6, align 4 ; EPILOG-NEXT: %9 = load i32, ptr %arrayidx.6, align 4
; EPILOG-NEXT: %add.6 = add nsw i32 %9, %add.5 ; EPILOG-NEXT: %add.6 = add nsw i32 %9, %add.5
; EPILOG-NEXT: %indvars.iv.next.6 = add nuw nsw i64 %indvars.iv.next.5, 1 ; EPILOG-NEXT: %indvars.iv.next.6 = add nuw nsw i64 %indvars.iv, 7
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.7 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.7
; EPILOG: for.exiting_block.7: ; EPILOG: for.exiting_block.7:
; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.7, label %latchExit.epilog-lcssa.loopexit, label %latch.7 ; EPILOG-NEXT: br i1 %cmp.7, label %latchExit.epilog-lcssa.loopexit, label %latch.7
; EPILOG: latch.7: ; EPILOG: latch.7:
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6 ; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4 ; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6 ; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv.next.6, 1 ; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa.loopexit, label %header ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa.loopexit, label %header
; EPILOG: latchExit.unr-lcssa.loopexit: ; EPILOG: latchExit.unr-lcssa.loopexit:
; EPILOG-NEXT: %result.ph.ph = phi i32 [ %add.7, %latch.7 ] ; EPILOG-NEXT: %result.ph.ph = phi i32 [ %add.7, %latch.7 ]
; EPILOG-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.7, %latch.7 ] ; EPILOG-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.7, %latch.7 ]
; EPILOG-NEXT: %sum.02.unr.ph = phi i32 [ %add.7, %latch.7 ] ; EPILOG-NEXT: %sum.02.unr.ph = phi i32 [ %add.7, %latch.7 ]
; EPILOG-NEXT: br label %latchExit.unr-lcssa ; EPILOG-NEXT: br label %latchExit.unr-lcssa
; EPILOG: latchExit.unr-lcssa: ; EPILOG: latchExit.unr-lcssa:
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; EPILOG-BLOCK: for.exiting_block: ; EPILOG-BLOCK: for.exiting_block:
; EPILOG-BLOCK-NEXT: %cmp = icmp eq i64 %n, 42 ; EPILOG-BLOCK-NEXT: %cmp = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp, label %latchExit.epilog-lcssa.loopexit, label %latch ; EPILOG-BLOCK-NEXT: br i1 %cmp, label %latchExit.epilog-lcssa.loopexit, label %latch
; EPILOG-BLOCK: latch: ; EPILOG-BLOCK: latch:
; EPILOG-BLOCK-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv ; EPILOG-BLOCK-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
; EPILOG-BLOCK-NEXT: %3 = load i32, ptr %arrayidx, align 4 ; EPILOG-BLOCK-NEXT: %3 = load i32, ptr %arrayidx, align 4
; EPILOG-BLOCK-NEXT: %add = add nsw i32 %3, %sum.02 ; EPILOG-BLOCK-NEXT: %add = add nsw i32 %3, %sum.02
; EPILOG-BLOCK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 ; EPILOG-BLOCK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1 ; EPILOG-BLOCK-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1
; EPILOG-BLOCK: for.exiting_block.1: ; EPILOG-BLOCK: for.exiting_block.1:
; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1 ; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1
; EPILOG-BLOCK: latch.1: ; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4 ; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add ; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !5 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !5
; EPILOG-BLOCK: latchExit.unr-lcssa.loopexit: ; EPILOG-BLOCK: latchExit.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ %add.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ %add.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %sum.02.unr.ph = phi i32 [ %add.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %sum.02.unr.ph = phi i32 [ %add.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: br label %latchExit.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %latchExit.unr-lcssa
; EPILOG-BLOCK: latchExit.unr-lcssa: ; EPILOG-BLOCK: latchExit.unr-lcssa:
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; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1
; PROLOG: for.exiting_block.1: ; PROLOG: for.exiting_block.1:
; PROLOG-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.1 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.1, label %latchExit.unr-lcssa.loopexit, label %latch.1 ; PROLOG-NEXT: br i1 %cmp.1, label %latchExit.unr-lcssa.loopexit, label %latch.1
; PROLOG: latch.1: ; PROLOG: latch.1:
; PROLOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; PROLOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; PROLOG-NEXT: %5 = load i32, ptr %arrayidx.1, align 4 ; PROLOG-NEXT: %5 = load i32, ptr %arrayidx.1, align 4
; PROLOG-NEXT: %add.1 = add nsw i32 %5, %add ; PROLOG-NEXT: %add.1 = add nsw i32 %5, %add
; PROLOG-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; PROLOG-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.2 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.2
; PROLOG: for.exiting_block.2: ; PROLOG: for.exiting_block.2:
; PROLOG-NEXT: %cmp.2 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.2 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.2, label %latchExit.unr-lcssa.loopexit, label %latch.2 ; PROLOG-NEXT: br i1 %cmp.2, label %latchExit.unr-lcssa.loopexit, label %latch.2
; PROLOG: latch.2: ; PROLOG: latch.2:
; PROLOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1 ; PROLOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1
; PROLOG-NEXT: %6 = load i32, ptr %arrayidx.2, align 4 ; PROLOG-NEXT: %6 = load i32, ptr %arrayidx.2, align 4
; PROLOG-NEXT: %add.2 = add nsw i32 %6, %add.1 ; PROLOG-NEXT: %add.2 = add nsw i32 %6, %add.1
; PROLOG-NEXT: %indvars.iv.next.2 = add i64 %indvars.iv.next.1, 1 ; PROLOG-NEXT: %indvars.iv.next.2 = add i64 %indvars.iv, 3
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.3 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.3
; PROLOG: for.exiting_block.3: ; PROLOG: for.exiting_block.3:
; PROLOG-NEXT: %cmp.3 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.3 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.3, label %latchExit.unr-lcssa.loopexit, label %latch.3 ; PROLOG-NEXT: br i1 %cmp.3, label %latchExit.unr-lcssa.loopexit, label %latch.3
; PROLOG: latch.3: ; PROLOG: latch.3:
; PROLOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2 ; PROLOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2
; PROLOG-NEXT: %7 = load i32, ptr %arrayidx.3, align 4 ; PROLOG-NEXT: %7 = load i32, ptr %arrayidx.3, align 4
; PROLOG-NEXT: %add.3 = add nsw i32 %7, %add.2 ; PROLOG-NEXT: %add.3 = add nsw i32 %7, %add.2
; PROLOG-NEXT: %indvars.iv.next.3 = add i64 %indvars.iv.next.2, 1 ; PROLOG-NEXT: %indvars.iv.next.3 = add i64 %indvars.iv, 4
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.4 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.4
; PROLOG: for.exiting_block.4: ; PROLOG: for.exiting_block.4:
; PROLOG-NEXT: %cmp.4 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.4 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.4, label %latchExit.unr-lcssa.loopexit, label %latch.4 ; PROLOG-NEXT: br i1 %cmp.4, label %latchExit.unr-lcssa.loopexit, label %latch.4
; PROLOG: latch.4: ; PROLOG: latch.4:
; PROLOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3 ; PROLOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3
; PROLOG-NEXT: %8 = load i32, ptr %arrayidx.4, align 4 ; PROLOG-NEXT: %8 = load i32, ptr %arrayidx.4, align 4
; PROLOG-NEXT: %add.4 = add nsw i32 %8, %add.3 ; PROLOG-NEXT: %add.4 = add nsw i32 %8, %add.3
; PROLOG-NEXT: %indvars.iv.next.4 = add i64 %indvars.iv.next.3, 1 ; PROLOG-NEXT: %indvars.iv.next.4 = add i64 %indvars.iv, 5
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.5 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.5
; PROLOG: for.exiting_block.5: ; PROLOG: for.exiting_block.5:
; PROLOG-NEXT: %cmp.5 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.5 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.5, label %latchExit.unr-lcssa.loopexit, label %latch.5 ; PROLOG-NEXT: br i1 %cmp.5, label %latchExit.unr-lcssa.loopexit, label %latch.5
; PROLOG: latch.5: ; PROLOG: latch.5:
; PROLOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4 ; PROLOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4
; PROLOG-NEXT: %9 = load i32, ptr %arrayidx.5, align 4 ; PROLOG-NEXT: %9 = load i32, ptr %arrayidx.5, align 4
; PROLOG-NEXT: %add.5 = add nsw i32 %9, %add.4 ; PROLOG-NEXT: %add.5 = add nsw i32 %9, %add.4
; PROLOG-NEXT: %indvars.iv.next.5 = add i64 %indvars.iv.next.4, 1 ; PROLOG-NEXT: %indvars.iv.next.5 = add i64 %indvars.iv, 6
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.6 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.6
; PROLOG: for.exiting_block.6: ; PROLOG: for.exiting_block.6:
; PROLOG-NEXT: %cmp.6 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.6 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.6, label %latchExit.unr-lcssa.loopexit, label %latch.6 ; PROLOG-NEXT: br i1 %cmp.6, label %latchExit.unr-lcssa.loopexit, label %latch.6
; PROLOG: latch.6: ; PROLOG: latch.6:
; PROLOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5 ; PROLOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5
; PROLOG-NEXT: %10 = load i32, ptr %arrayidx.6, align 4 ; PROLOG-NEXT: %10 = load i32, ptr %arrayidx.6, align 4
; PROLOG-NEXT: %add.6 = add nsw i32 %10, %add.5 ; PROLOG-NEXT: %add.6 = add nsw i32 %10, %add.5
; PROLOG-NEXT: %indvars.iv.next.6 = add i64 %indvars.iv.next.5, 1 ; PROLOG-NEXT: %indvars.iv.next.6 = add i64 %indvars.iv, 7
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.7 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.7
; PROLOG: for.exiting_block.7: ; PROLOG: for.exiting_block.7:
; PROLOG-NEXT: %cmp.7 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.7, label %latchExit.unr-lcssa.loopexit, label %latch.7 ; PROLOG-NEXT: br i1 %cmp.7, label %latchExit.unr-lcssa.loopexit, label %latch.7
; PROLOG: latch.7: ; PROLOG: latch.7:
; PROLOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6 ; PROLOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; PROLOG-NEXT: %11 = load i32, ptr %arrayidx.7, align 4 ; PROLOG-NEXT: %11 = load i32, ptr %arrayidx.7, align 4
; PROLOG-NEXT: %add.7 = add nsw i32 %11, %add.6 ; PROLOG-NEXT: %add.7 = add nsw i32 %11, %add.6
; PROLOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv.next.6, 1 ; PROLOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
; PROLOG-NEXT: %exitcond.7 = icmp eq i64 %indvars.iv.next.7, %n ; PROLOG-NEXT: %exitcond.7 = icmp eq i64 %indvars.iv.next.7, %n
; PROLOG-NEXT: br i1 %exitcond.7, label %latchExit.unr-lcssa.loopexit, label %header ; PROLOG-NEXT: br i1 %exitcond.7, label %latchExit.unr-lcssa.loopexit, label %header
; PROLOG: latchExit.unr-lcssa.loopexit: ; PROLOG: latchExit.unr-lcssa.loopexit:
; PROLOG-NEXT: %result.ph.ph = phi i32 [ 2, %for.exiting_block ], [ 2, %for.exiting_block.1 ], [ 2, %for.exiting_block.2 ], [ 2, %for.exiting_block.3 ], [ 2, %for.exiting_block.4 ], [ 2, %for.exiting_block.5 ], [ 2, %for.exiting_block.6 ], [ 2, %for.exiting_block.7 ], [ %add.7, %latch.7 ] ; PROLOG-NEXT: %result.ph.ph = phi i32 [ 2, %for.exiting_block ], [ 2, %for.exiting_block.1 ], [ 2, %for.exiting_block.2 ], [ 2, %for.exiting_block.3 ], [ 2, %for.exiting_block.4 ], [ 2, %for.exiting_block.5 ], [ 2, %for.exiting_block.6 ], [ 2, %for.exiting_block.7 ], [ %add.7, %latch.7 ]
; PROLOG-NEXT: br label %latchExit.unr-lcssa ; PROLOG-NEXT: br label %latchExit.unr-lcssa
; PROLOG: latchExit.unr-lcssa.loopexit2: ; PROLOG: latchExit.unr-lcssa.loopexit2:
; PROLOG-NEXT: %result.ph.ph3 = phi i32 [ 2, %for.exiting_block.prol ] ; PROLOG-NEXT: %result.ph.ph3 = phi i32 [ 2, %for.exiting_block.prol ]
; PROLOG-NEXT: br label %latchExit.unr-lcssa ; PROLOG-NEXT: br label %latchExit.unr-lcssa
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; PROLOG-BLOCK-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1 ; PROLOG-BLOCK-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1
; PROLOG-BLOCK: for.exiting_block.1: ; PROLOG-BLOCK: for.exiting_block.1:
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.unr-lcssa.loopexit, label %latch.1 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.unr-lcssa.loopexit, label %latch.1
; PROLOG-BLOCK: latch.1: ; PROLOG-BLOCK: latch.1:
; PROLOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; PROLOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; PROLOG-BLOCK-NEXT: %5 = load i32, ptr %arrayidx.1, align 4 ; PROLOG-BLOCK-NEXT: %5 = load i32, ptr %arrayidx.1, align 4
; PROLOG-BLOCK-NEXT: %add.1 = add nsw i32 %5, %add ; PROLOG-BLOCK-NEXT: %add.1 = add nsw i32 %5, %add
; PROLOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; PROLOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; PROLOG-BLOCK-NEXT: %exitcond.1 = icmp eq i64 %indvars.iv.next.1, %n ; PROLOG-BLOCK-NEXT: %exitcond.1 = icmp eq i64 %indvars.iv.next.1, %n
; PROLOG-BLOCK-NEXT: br i1 %exitcond.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !5 ; PROLOG-BLOCK-NEXT: br i1 %exitcond.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !5
; PROLOG-BLOCK: latchExit.unr-lcssa.loopexit: ; PROLOG-BLOCK: latchExit.unr-lcssa.loopexit:
; PROLOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ 2, %for.exiting_block ], [ 2, %for.exiting_block.1 ], [ %add.1, %latch.1 ] ; PROLOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ 2, %for.exiting_block ], [ 2, %for.exiting_block.1 ], [ %add.1, %latch.1 ]
; PROLOG-BLOCK-NEXT: br label %latchExit.unr-lcssa ; PROLOG-BLOCK-NEXT: br label %latchExit.unr-lcssa
; PROLOG-BLOCK: latchExit.unr-lcssa: ; PROLOG-BLOCK: latchExit.unr-lcssa:
; PROLOG-BLOCK-NEXT: %result.ph = phi i32 [ 2, %for.exiting_block.prol ], [ %result.ph.ph, %latchExit.unr-lcssa.loopexit ] ; PROLOG-BLOCK-NEXT: %result.ph = phi i32 [ 2, %for.exiting_block.prol ], [ %result.ph.ph, %latchExit.unr-lcssa.loopexit ]
; PROLOG-BLOCK-NEXT: br label %latchExit ; PROLOG-BLOCK-NEXT: br label %latchExit
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; EPILOG: for.exiting_block: ; EPILOG: for.exiting_block:
; EPILOG-NEXT: %cmp = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp, label %latchExit.epilog-lcssa.loopexit, label %latch ; EPILOG-NEXT: br i1 %cmp, label %latchExit.epilog-lcssa.loopexit, label %latch
; EPILOG: latch: ; EPILOG: latch:
; EPILOG-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv ; EPILOG-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
; EPILOG-NEXT: %3 = load i32, ptr %arrayidx, align 4 ; EPILOG-NEXT: %3 = load i32, ptr %arrayidx, align 4
; EPILOG-NEXT: %add = add nsw i32 %3, %sum.02 ; EPILOG-NEXT: %add = add nsw i32 %3, %sum.02
; EPILOG-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 ; EPILOG-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1
; EPILOG: for.exiting_block.1: ; EPILOG: for.exiting_block.1:
; EPILOG-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1 ; EPILOG-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1
; EPILOG: latch.1: ; EPILOG: latch.1:
; EPILOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; EPILOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-NEXT: %4 = load i32, ptr %arrayidx.1, align 4 ; EPILOG-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-NEXT: %add.1 = add nsw i32 %4, %add ; EPILOG-NEXT: %add.1 = add nsw i32 %4, %add
; EPILOG-NEXT: %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv.next, 1 ; EPILOG-NEXT: %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.2 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.2
; EPILOG: for.exiting_block.2: ; EPILOG: for.exiting_block.2:
; EPILOG-NEXT: %cmp.2 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.2 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.2, label %latchExit.epilog-lcssa.loopexit, label %latch.2 ; EPILOG-NEXT: br i1 %cmp.2, label %latchExit.epilog-lcssa.loopexit, label %latch.2
; EPILOG: latch.2: ; EPILOG: latch.2:
; EPILOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1 ; EPILOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1
; EPILOG-NEXT: %5 = load i32, ptr %arrayidx.2, align 4 ; EPILOG-NEXT: %5 = load i32, ptr %arrayidx.2, align 4
; EPILOG-NEXT: %add.2 = add nsw i32 %5, %add.1 ; EPILOG-NEXT: %add.2 = add nsw i32 %5, %add.1
; EPILOG-NEXT: %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv.next.1, 1 ; EPILOG-NEXT: %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv, 3
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.3 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.3
; EPILOG: for.exiting_block.3: ; EPILOG: for.exiting_block.3:
; EPILOG-NEXT: %cmp.3 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.3 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.3, label %latchExit.epilog-lcssa.loopexit, label %latch.3 ; EPILOG-NEXT: br i1 %cmp.3, label %latchExit.epilog-lcssa.loopexit, label %latch.3
; EPILOG: latch.3: ; EPILOG: latch.3:
; EPILOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2 ; EPILOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2
; EPILOG-NEXT: %6 = load i32, ptr %arrayidx.3, align 4 ; EPILOG-NEXT: %6 = load i32, ptr %arrayidx.3, align 4
; EPILOG-NEXT: %add.3 = add nsw i32 %6, %add.2 ; EPILOG-NEXT: %add.3 = add nsw i32 %6, %add.2
; EPILOG-NEXT: %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv.next.2, 1 ; EPILOG-NEXT: %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv, 4
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.4 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.4
; EPILOG: for.exiting_block.4: ; EPILOG: for.exiting_block.4:
; EPILOG-NEXT: %cmp.4 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.4 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.4, label %latchExit.epilog-lcssa.loopexit, label %latch.4 ; EPILOG-NEXT: br i1 %cmp.4, label %latchExit.epilog-lcssa.loopexit, label %latch.4
; EPILOG: latch.4: ; EPILOG: latch.4:
; EPILOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3 ; EPILOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3
; EPILOG-NEXT: %7 = load i32, ptr %arrayidx.4, align 4 ; EPILOG-NEXT: %7 = load i32, ptr %arrayidx.4, align 4
; EPILOG-NEXT: %add.4 = add nsw i32 %7, %add.3 ; EPILOG-NEXT: %add.4 = add nsw i32 %7, %add.3
; EPILOG-NEXT: %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv.next.3, 1 ; EPILOG-NEXT: %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv, 5
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.5 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.5
; EPILOG: for.exiting_block.5: ; EPILOG: for.exiting_block.5:
; EPILOG-NEXT: %cmp.5 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.5 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.5, label %latchExit.epilog-lcssa.loopexit, label %latch.5 ; EPILOG-NEXT: br i1 %cmp.5, label %latchExit.epilog-lcssa.loopexit, label %latch.5
; EPILOG: latch.5: ; EPILOG: latch.5:
; EPILOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4 ; EPILOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4
; EPILOG-NEXT: %8 = load i32, ptr %arrayidx.5, align 4 ; EPILOG-NEXT: %8 = load i32, ptr %arrayidx.5, align 4
; EPILOG-NEXT: %add.5 = add nsw i32 %8, %add.4 ; EPILOG-NEXT: %add.5 = add nsw i32 %8, %add.4
; EPILOG-NEXT: %indvars.iv.next.5 = add nuw nsw i64 %indvars.iv.next.4, 1 ; EPILOG-NEXT: %indvars.iv.next.5 = add nuw nsw i64 %indvars.iv, 6
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.6 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.6
; EPILOG: for.exiting_block.6: ; EPILOG: for.exiting_block.6:
; EPILOG-NEXT: %cmp.6 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.6 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.6, label %latchExit.epilog-lcssa.loopexit, label %latch.6 ; EPILOG-NEXT: br i1 %cmp.6, label %latchExit.epilog-lcssa.loopexit, label %latch.6
; EPILOG: latch.6: ; EPILOG: latch.6:
; EPILOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5 ; EPILOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5
; EPILOG-NEXT: %9 = load i32, ptr %arrayidx.6, align 4 ; EPILOG-NEXT: %9 = load i32, ptr %arrayidx.6, align 4
; EPILOG-NEXT: %add.6 = add nsw i32 %9, %add.5 ; EPILOG-NEXT: %add.6 = add nsw i32 %9, %add.5
; EPILOG-NEXT: %indvars.iv.next.6 = add nuw nsw i64 %indvars.iv.next.5, 1 ; EPILOG-NEXT: %indvars.iv.next.6 = add nuw nsw i64 %indvars.iv, 7
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.7 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.7
; EPILOG: for.exiting_block.7: ; EPILOG: for.exiting_block.7:
; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.7, label %latchExit.epilog-lcssa.loopexit, label %latch.7 ; EPILOG-NEXT: br i1 %cmp.7, label %latchExit.epilog-lcssa.loopexit, label %latch.7
; EPILOG: latch.7: ; EPILOG: latch.7:
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6 ; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4 ; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6 ; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv.next.6, 1 ; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa.loopexit, label %header ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa.loopexit, label %header
; EPILOG: latchExit.unr-lcssa.loopexit: ; EPILOG: latchExit.unr-lcssa.loopexit:
; EPILOG-NEXT: %result.ph.ph = phi i32 [ %add.7, %latch.7 ] ; EPILOG-NEXT: %result.ph.ph = phi i32 [ %add.7, %latch.7 ]
; EPILOG-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.7, %latch.7 ] ; EPILOG-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.7, %latch.7 ]
; EPILOG-NEXT: %sum.02.unr.ph = phi i32 [ %add.7, %latch.7 ] ; EPILOG-NEXT: %sum.02.unr.ph = phi i32 [ %add.7, %latch.7 ]
; EPILOG-NEXT: br label %latchExit.unr-lcssa ; EPILOG-NEXT: br label %latchExit.unr-lcssa
; EPILOG: latchExit.unr-lcssa: ; EPILOG: latchExit.unr-lcssa:
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; EPILOG-BLOCK: for.exiting_block: ; EPILOG-BLOCK: for.exiting_block:
; EPILOG-BLOCK-NEXT: %cmp = icmp eq i64 %n, 42 ; EPILOG-BLOCK-NEXT: %cmp = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp, label %latchExit.epilog-lcssa.loopexit, label %latch ; EPILOG-BLOCK-NEXT: br i1 %cmp, label %latchExit.epilog-lcssa.loopexit, label %latch
; EPILOG-BLOCK: latch: ; EPILOG-BLOCK: latch:
; EPILOG-BLOCK-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv ; EPILOG-BLOCK-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
; EPILOG-BLOCK-NEXT: %3 = load i32, ptr %arrayidx, align 4 ; EPILOG-BLOCK-NEXT: %3 = load i32, ptr %arrayidx, align 4
; EPILOG-BLOCK-NEXT: %add = add nsw i32 %3, %sum.02 ; EPILOG-BLOCK-NEXT: %add = add nsw i32 %3, %sum.02
; EPILOG-BLOCK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 ; EPILOG-BLOCK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1 ; EPILOG-BLOCK-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1
; EPILOG-BLOCK: for.exiting_block.1: ; EPILOG-BLOCK: for.exiting_block.1:
; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1 ; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1
; EPILOG-BLOCK: latch.1: ; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4 ; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add ; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !6 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !6
; EPILOG-BLOCK: latchExit.unr-lcssa.loopexit: ; EPILOG-BLOCK: latchExit.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ %add.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ %add.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %sum.02.unr.ph = phi i32 [ %add.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %sum.02.unr.ph = phi i32 [ %add.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: br label %latchExit.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %latchExit.unr-lcssa
; EPILOG-BLOCK: latchExit.unr-lcssa: ; EPILOG-BLOCK: latchExit.unr-lcssa:
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; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1
; PROLOG: for.exiting_block.1: ; PROLOG: for.exiting_block.1:
; PROLOG-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.1 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.1, label %latchExit.unr-lcssa.loopexit, label %latch.1 ; PROLOG-NEXT: br i1 %cmp.1, label %latchExit.unr-lcssa.loopexit, label %latch.1
; PROLOG: latch.1: ; PROLOG: latch.1:
; PROLOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; PROLOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; PROLOG-NEXT: %5 = load i32, ptr %arrayidx.1, align 4 ; PROLOG-NEXT: %5 = load i32, ptr %arrayidx.1, align 4
; PROLOG-NEXT: %add.1 = add nsw i32 %5, %add ; PROLOG-NEXT: %add.1 = add nsw i32 %5, %add
; PROLOG-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; PROLOG-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.2 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.2
; PROLOG: for.exiting_block.2: ; PROLOG: for.exiting_block.2:
; PROLOG-NEXT: %cmp.2 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.2 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.2, label %latchExit.unr-lcssa.loopexit, label %latch.2 ; PROLOG-NEXT: br i1 %cmp.2, label %latchExit.unr-lcssa.loopexit, label %latch.2
; PROLOG: latch.2: ; PROLOG: latch.2:
; PROLOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1 ; PROLOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1
; PROLOG-NEXT: %6 = load i32, ptr %arrayidx.2, align 4 ; PROLOG-NEXT: %6 = load i32, ptr %arrayidx.2, align 4
; PROLOG-NEXT: %add.2 = add nsw i32 %6, %add.1 ; PROLOG-NEXT: %add.2 = add nsw i32 %6, %add.1
; PROLOG-NEXT: %indvars.iv.next.2 = add i64 %indvars.iv.next.1, 1 ; PROLOG-NEXT: %indvars.iv.next.2 = add i64 %indvars.iv, 3
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.3 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.3
; PROLOG: for.exiting_block.3: ; PROLOG: for.exiting_block.3:
; PROLOG-NEXT: %cmp.3 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.3 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.3, label %latchExit.unr-lcssa.loopexit, label %latch.3 ; PROLOG-NEXT: br i1 %cmp.3, label %latchExit.unr-lcssa.loopexit, label %latch.3
; PROLOG: latch.3: ; PROLOG: latch.3:
; PROLOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2 ; PROLOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2
; PROLOG-NEXT: %7 = load i32, ptr %arrayidx.3, align 4 ; PROLOG-NEXT: %7 = load i32, ptr %arrayidx.3, align 4
; PROLOG-NEXT: %add.3 = add nsw i32 %7, %add.2 ; PROLOG-NEXT: %add.3 = add nsw i32 %7, %add.2
; PROLOG-NEXT: %indvars.iv.next.3 = add i64 %indvars.iv.next.2, 1 ; PROLOG-NEXT: %indvars.iv.next.3 = add i64 %indvars.iv, 4
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.4 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.4
; PROLOG: for.exiting_block.4: ; PROLOG: for.exiting_block.4:
; PROLOG-NEXT: %cmp.4 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.4 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.4, label %latchExit.unr-lcssa.loopexit, label %latch.4 ; PROLOG-NEXT: br i1 %cmp.4, label %latchExit.unr-lcssa.loopexit, label %latch.4
; PROLOG: latch.4: ; PROLOG: latch.4:
; PROLOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3 ; PROLOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3
; PROLOG-NEXT: %8 = load i32, ptr %arrayidx.4, align 4 ; PROLOG-NEXT: %8 = load i32, ptr %arrayidx.4, align 4
; PROLOG-NEXT: %add.4 = add nsw i32 %8, %add.3 ; PROLOG-NEXT: %add.4 = add nsw i32 %8, %add.3
; PROLOG-NEXT: %indvars.iv.next.4 = add i64 %indvars.iv.next.3, 1 ; PROLOG-NEXT: %indvars.iv.next.4 = add i64 %indvars.iv, 5
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.5 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.5
; PROLOG: for.exiting_block.5: ; PROLOG: for.exiting_block.5:
; PROLOG-NEXT: %cmp.5 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.5 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.5, label %latchExit.unr-lcssa.loopexit, label %latch.5 ; PROLOG-NEXT: br i1 %cmp.5, label %latchExit.unr-lcssa.loopexit, label %latch.5
; PROLOG: latch.5: ; PROLOG: latch.5:
; PROLOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4 ; PROLOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4
; PROLOG-NEXT: %9 = load i32, ptr %arrayidx.5, align 4 ; PROLOG-NEXT: %9 = load i32, ptr %arrayidx.5, align 4
; PROLOG-NEXT: %add.5 = add nsw i32 %9, %add.4 ; PROLOG-NEXT: %add.5 = add nsw i32 %9, %add.4
; PROLOG-NEXT: %indvars.iv.next.5 = add i64 %indvars.iv.next.4, 1 ; PROLOG-NEXT: %indvars.iv.next.5 = add i64 %indvars.iv, 6
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.6 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.6
; PROLOG: for.exiting_block.6: ; PROLOG: for.exiting_block.6:
; PROLOG-NEXT: %cmp.6 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.6 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.6, label %latchExit.unr-lcssa.loopexit, label %latch.6 ; PROLOG-NEXT: br i1 %cmp.6, label %latchExit.unr-lcssa.loopexit, label %latch.6
; PROLOG: latch.6: ; PROLOG: latch.6:
; PROLOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5 ; PROLOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5
; PROLOG-NEXT: %10 = load i32, ptr %arrayidx.6, align 4 ; PROLOG-NEXT: %10 = load i32, ptr %arrayidx.6, align 4
; PROLOG-NEXT: %add.6 = add nsw i32 %10, %add.5 ; PROLOG-NEXT: %add.6 = add nsw i32 %10, %add.5
; PROLOG-NEXT: %indvars.iv.next.6 = add i64 %indvars.iv.next.5, 1 ; PROLOG-NEXT: %indvars.iv.next.6 = add i64 %indvars.iv, 7
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.7 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.7
; PROLOG: for.exiting_block.7: ; PROLOG: for.exiting_block.7:
; PROLOG-NEXT: %cmp.7 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.7, label %latchExit.unr-lcssa.loopexit, label %latch.7 ; PROLOG-NEXT: br i1 %cmp.7, label %latchExit.unr-lcssa.loopexit, label %latch.7
; PROLOG: latch.7: ; PROLOG: latch.7:
; PROLOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6 ; PROLOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; PROLOG-NEXT: %11 = load i32, ptr %arrayidx.7, align 4 ; PROLOG-NEXT: %11 = load i32, ptr %arrayidx.7, align 4
; PROLOG-NEXT: %add.7 = add nsw i32 %11, %add.6 ; PROLOG-NEXT: %add.7 = add nsw i32 %11, %add.6
; PROLOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv.next.6, 1 ; PROLOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
; PROLOG-NEXT: %exitcond.7 = icmp eq i64 %indvars.iv.next.7, %n ; PROLOG-NEXT: %exitcond.7 = icmp eq i64 %indvars.iv.next.7, %n
; PROLOG-NEXT: br i1 %exitcond.7, label %latchExit.unr-lcssa.loopexit, label %header ; PROLOG-NEXT: br i1 %exitcond.7, label %latchExit.unr-lcssa.loopexit, label %header
; PROLOG: latchExit.unr-lcssa.loopexit: ; PROLOG: latchExit.unr-lcssa.loopexit:
; PROLOG-NEXT: %result.ph.ph = phi i32 [ %sum.02, %for.exiting_block ], [ %add, %for.exiting_block.1 ], [ %add.1, %for.exiting_block.2 ], [ %add.2, %for.exiting_block.3 ], [ %add.3, %for.exiting_block.4 ], [ %add.4, %for.exiting_block.5 ], [ %add.5, %for.exiting_block.6 ], [ %add.6, %for.exiting_block.7 ], [ %add.7, %latch.7 ] ; PROLOG-NEXT: %result.ph.ph = phi i32 [ %sum.02, %for.exiting_block ], [ %add, %for.exiting_block.1 ], [ %add.1, %for.exiting_block.2 ], [ %add.2, %for.exiting_block.3 ], [ %add.3, %for.exiting_block.4 ], [ %add.4, %for.exiting_block.5 ], [ %add.5, %for.exiting_block.6 ], [ %add.6, %for.exiting_block.7 ], [ %add.7, %latch.7 ]
; PROLOG-NEXT: br label %latchExit.unr-lcssa ; PROLOG-NEXT: br label %latchExit.unr-lcssa
; PROLOG: latchExit.unr-lcssa.loopexit2: ; PROLOG: latchExit.unr-lcssa.loopexit2:
; PROLOG-NEXT: %result.ph.ph3 = phi i32 [ %sum.02.prol, %for.exiting_block.prol ] ; PROLOG-NEXT: %result.ph.ph3 = phi i32 [ %sum.02.prol, %for.exiting_block.prol ]
; PROLOG-NEXT: br label %latchExit.unr-lcssa ; PROLOG-NEXT: br label %latchExit.unr-lcssa
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; PROLOG-BLOCK-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1 ; PROLOG-BLOCK-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1
; PROLOG-BLOCK: for.exiting_block.1: ; PROLOG-BLOCK: for.exiting_block.1:
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.unr-lcssa.loopexit, label %latch.1 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.unr-lcssa.loopexit, label %latch.1
; PROLOG-BLOCK: latch.1: ; PROLOG-BLOCK: latch.1:
; PROLOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; PROLOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; PROLOG-BLOCK-NEXT: %5 = load i32, ptr %arrayidx.1, align 4 ; PROLOG-BLOCK-NEXT: %5 = load i32, ptr %arrayidx.1, align 4
; PROLOG-BLOCK-NEXT: %add.1 = add nsw i32 %5, %add ; PROLOG-BLOCK-NEXT: %add.1 = add nsw i32 %5, %add
; PROLOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; PROLOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; PROLOG-BLOCK-NEXT: %exitcond.1 = icmp eq i64 %indvars.iv.next.1, %n ; PROLOG-BLOCK-NEXT: %exitcond.1 = icmp eq i64 %indvars.iv.next.1, %n
; PROLOG-BLOCK-NEXT: br i1 %exitcond.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !6 ; PROLOG-BLOCK-NEXT: br i1 %exitcond.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !6
; PROLOG-BLOCK: latchExit.unr-lcssa.loopexit: ; PROLOG-BLOCK: latchExit.unr-lcssa.loopexit:
; PROLOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ %sum.02, %for.exiting_block ], [ %add, %for.exiting_block.1 ], [ %add.1, %latch.1 ] ; PROLOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ %sum.02, %for.exiting_block ], [ %add, %for.exiting_block.1 ], [ %add.1, %latch.1 ]
; PROLOG-BLOCK-NEXT: br label %latchExit.unr-lcssa ; PROLOG-BLOCK-NEXT: br label %latchExit.unr-lcssa
; PROLOG-BLOCK: latchExit.unr-lcssa: ; PROLOG-BLOCK: latchExit.unr-lcssa:
; PROLOG-BLOCK-NEXT: %result.ph = phi i32 [ 0, %for.exiting_block.prol ], [ %result.ph.ph, %latchExit.unr-lcssa.loopexit ] ; PROLOG-BLOCK-NEXT: %result.ph = phi i32 [ 0, %for.exiting_block.prol ], [ %result.ph.ph, %latchExit.unr-lcssa.loopexit ]
; PROLOG-BLOCK-NEXT: br label %latchExit ; PROLOG-BLOCK-NEXT: br label %latchExit
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; EPILOG: for.exiting_block: ; EPILOG: for.exiting_block:
; EPILOG-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv ; EPILOG-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
; EPILOG-NEXT: %3 = load i32, ptr %arrayidx, align 4 ; EPILOG-NEXT: %3 = load i32, ptr %arrayidx, align 4
; EPILOG-NEXT: %add = add nsw i32 %3, %sum.02 ; EPILOG-NEXT: %add = add nsw i32 %3, %sum.02
; EPILOG-NEXT: %cmp = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp, label %latchExit.epilog-lcssa.loopexit, label %latch ; EPILOG-NEXT: br i1 %cmp, label %latchExit.epilog-lcssa.loopexit, label %latch
; EPILOG: latch: ; EPILOG: latch:
; EPILOG-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 ; EPILOG-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1
; EPILOG: for.exiting_block.1: ; EPILOG: for.exiting_block.1:
; EPILOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; EPILOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-NEXT: %4 = load i32, ptr %arrayidx.1, align 4 ; EPILOG-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-NEXT: %add.1 = add nsw i32 %4, %add ; EPILOG-NEXT: %add.1 = add nsw i32 %4, %add
; EPILOG-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1 ; EPILOG-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1
; EPILOG: latch.1: ; EPILOG: latch.1:
; EPILOG-NEXT: %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv.next, 1 ; EPILOG-NEXT: %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.2 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.2
; EPILOG: for.exiting_block.2: ; EPILOG: for.exiting_block.2:
; EPILOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1 ; EPILOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1
; EPILOG-NEXT: %5 = load i32, ptr %arrayidx.2, align 4 ; EPILOG-NEXT: %5 = load i32, ptr %arrayidx.2, align 4
; EPILOG-NEXT: %add.2 = add nsw i32 %5, %add.1 ; EPILOG-NEXT: %add.2 = add nsw i32 %5, %add.1
; EPILOG-NEXT: %cmp.2 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.2 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.2, label %latchExit.epilog-lcssa.loopexit, label %latch.2 ; EPILOG-NEXT: br i1 %cmp.2, label %latchExit.epilog-lcssa.loopexit, label %latch.2
; EPILOG: latch.2: ; EPILOG: latch.2:
; EPILOG-NEXT: %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv.next.1, 1 ; EPILOG-NEXT: %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv, 3
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.3 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.3
; EPILOG: for.exiting_block.3: ; EPILOG: for.exiting_block.3:
; EPILOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2 ; EPILOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2
; EPILOG-NEXT: %6 = load i32, ptr %arrayidx.3, align 4 ; EPILOG-NEXT: %6 = load i32, ptr %arrayidx.3, align 4
; EPILOG-NEXT: %add.3 = add nsw i32 %6, %add.2 ; EPILOG-NEXT: %add.3 = add nsw i32 %6, %add.2
; EPILOG-NEXT: %cmp.3 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.3 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.3, label %latchExit.epilog-lcssa.loopexit, label %latch.3 ; EPILOG-NEXT: br i1 %cmp.3, label %latchExit.epilog-lcssa.loopexit, label %latch.3
; EPILOG: latch.3: ; EPILOG: latch.3:
; EPILOG-NEXT: %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv.next.2, 1 ; EPILOG-NEXT: %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv, 4
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.4 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.4
; EPILOG: for.exiting_block.4: ; EPILOG: for.exiting_block.4:
; EPILOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3 ; EPILOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3
; EPILOG-NEXT: %7 = load i32, ptr %arrayidx.4, align 4 ; EPILOG-NEXT: %7 = load i32, ptr %arrayidx.4, align 4
; EPILOG-NEXT: %add.4 = add nsw i32 %7, %add.3 ; EPILOG-NEXT: %add.4 = add nsw i32 %7, %add.3
; EPILOG-NEXT: %cmp.4 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.4 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.4, label %latchExit.epilog-lcssa.loopexit, label %latch.4 ; EPILOG-NEXT: br i1 %cmp.4, label %latchExit.epilog-lcssa.loopexit, label %latch.4
; EPILOG: latch.4: ; EPILOG: latch.4:
; EPILOG-NEXT: %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv.next.3, 1 ; EPILOG-NEXT: %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv, 5
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.5 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.5
; EPILOG: for.exiting_block.5: ; EPILOG: for.exiting_block.5:
; EPILOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4 ; EPILOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4
; EPILOG-NEXT: %8 = load i32, ptr %arrayidx.5, align 4 ; EPILOG-NEXT: %8 = load i32, ptr %arrayidx.5, align 4
; EPILOG-NEXT: %add.5 = add nsw i32 %8, %add.4 ; EPILOG-NEXT: %add.5 = add nsw i32 %8, %add.4
; EPILOG-NEXT: %cmp.5 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.5 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.5, label %latchExit.epilog-lcssa.loopexit, label %latch.5 ; EPILOG-NEXT: br i1 %cmp.5, label %latchExit.epilog-lcssa.loopexit, label %latch.5
; EPILOG: latch.5: ; EPILOG: latch.5:
; EPILOG-NEXT: %indvars.iv.next.5 = add nuw nsw i64 %indvars.iv.next.4, 1 ; EPILOG-NEXT: %indvars.iv.next.5 = add nuw nsw i64 %indvars.iv, 6
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.6 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.6
; EPILOG: for.exiting_block.6: ; EPILOG: for.exiting_block.6:
; EPILOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5 ; EPILOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5
; EPILOG-NEXT: %9 = load i32, ptr %arrayidx.6, align 4 ; EPILOG-NEXT: %9 = load i32, ptr %arrayidx.6, align 4
; EPILOG-NEXT: %add.6 = add nsw i32 %9, %add.5 ; EPILOG-NEXT: %add.6 = add nsw i32 %9, %add.5
; EPILOG-NEXT: %cmp.6 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.6 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.6, label %latchExit.epilog-lcssa.loopexit, label %latch.6 ; EPILOG-NEXT: br i1 %cmp.6, label %latchExit.epilog-lcssa.loopexit, label %latch.6
; EPILOG: latch.6: ; EPILOG: latch.6:
; EPILOG-NEXT: %indvars.iv.next.6 = add nuw nsw i64 %indvars.iv.next.5, 1 ; EPILOG-NEXT: %indvars.iv.next.6 = add nuw nsw i64 %indvars.iv, 7
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.7 ; EPILOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.7
; EPILOG: for.exiting_block.7: ; EPILOG: for.exiting_block.7:
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6 ; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4 ; EPILOG-NEXT: %10 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6 ; EPILOG-NEXT: %add.7 = add nsw i32 %10, %add.6
; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.7, label %latchExit.epilog-lcssa.loopexit, label %latch.7 ; EPILOG-NEXT: br i1 %cmp.7, label %latchExit.epilog-lcssa.loopexit, label %latch.7
; EPILOG: latch.7: ; EPILOG: latch.7:
; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv.next.6, 1 ; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa.loopexit, label %header ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latchExit.unr-lcssa.loopexit, label %header
; EPILOG: latchExit.unr-lcssa.loopexit: ; EPILOG: latchExit.unr-lcssa.loopexit:
; EPILOG-NEXT: %result.ph.ph = phi i32 [ %add.7, %latch.7 ] ; EPILOG-NEXT: %result.ph.ph = phi i32 [ %add.7, %latch.7 ]
; EPILOG-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.7, %latch.7 ] ; EPILOG-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.7, %latch.7 ]
; EPILOG-NEXT: %sum.02.unr.ph = phi i32 [ %add.7, %latch.7 ] ; EPILOG-NEXT: %sum.02.unr.ph = phi i32 [ %add.7, %latch.7 ]
; EPILOG-NEXT: br label %latchExit.unr-lcssa ; EPILOG-NEXT: br label %latchExit.unr-lcssa
; EPILOG: latchExit.unr-lcssa: ; EPILOG: latchExit.unr-lcssa:
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; EPILOG-BLOCK: for.exiting_block: ; EPILOG-BLOCK: for.exiting_block:
; EPILOG-BLOCK-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv ; EPILOG-BLOCK-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
; EPILOG-BLOCK-NEXT: %3 = load i32, ptr %arrayidx, align 4 ; EPILOG-BLOCK-NEXT: %3 = load i32, ptr %arrayidx, align 4
; EPILOG-BLOCK-NEXT: %add = add nsw i32 %3, %sum.02 ; EPILOG-BLOCK-NEXT: %add = add nsw i32 %3, %sum.02
; EPILOG-BLOCK-NEXT: %cmp = icmp eq i64 %n, 42 ; EPILOG-BLOCK-NEXT: %cmp = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp, label %latchExit.epilog-lcssa.loopexit, label %latch ; EPILOG-BLOCK-NEXT: br i1 %cmp, label %latchExit.epilog-lcssa.loopexit, label %latch
; EPILOG-BLOCK: latch: ; EPILOG-BLOCK: latch:
; EPILOG-BLOCK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 ; EPILOG-BLOCK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1 ; EPILOG-BLOCK-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1
; EPILOG-BLOCK: for.exiting_block.1: ; EPILOG-BLOCK: for.exiting_block.1:
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4 ; EPILOG-BLOCK-NEXT: %4 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add ; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %4, %add
; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1 ; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.epilog-lcssa.loopexit, label %latch.1
; EPILOG-BLOCK: latch.1: ; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !7 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !7
; EPILOG-BLOCK: latchExit.unr-lcssa.loopexit: ; EPILOG-BLOCK: latchExit.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ %add.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ %add.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %sum.02.unr.ph = phi i32 [ %add.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %sum.02.unr.ph = phi i32 [ %add.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: br label %latchExit.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %latchExit.unr-lcssa
; EPILOG-BLOCK: latchExit.unr-lcssa: ; EPILOG-BLOCK: latchExit.unr-lcssa:
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; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1
; PROLOG: for.exiting_block.1: ; PROLOG: for.exiting_block.1:
; PROLOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; PROLOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; PROLOG-NEXT: %5 = load i32, ptr %arrayidx.1, align 4 ; PROLOG-NEXT: %5 = load i32, ptr %arrayidx.1, align 4
; PROLOG-NEXT: %add.1 = add nsw i32 %5, %add ; PROLOG-NEXT: %add.1 = add nsw i32 %5, %add
; PROLOG-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.1 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.1, label %latchExit.unr-lcssa.loopexit, label %latch.1 ; PROLOG-NEXT: br i1 %cmp.1, label %latchExit.unr-lcssa.loopexit, label %latch.1
; PROLOG: latch.1: ; PROLOG: latch.1:
; PROLOG-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; PROLOG-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.2 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.2
; PROLOG: for.exiting_block.2: ; PROLOG: for.exiting_block.2:
; PROLOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1 ; PROLOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1
; PROLOG-NEXT: %6 = load i32, ptr %arrayidx.2, align 4 ; PROLOG-NEXT: %6 = load i32, ptr %arrayidx.2, align 4
; PROLOG-NEXT: %add.2 = add nsw i32 %6, %add.1 ; PROLOG-NEXT: %add.2 = add nsw i32 %6, %add.1
; PROLOG-NEXT: %cmp.2 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.2 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.2, label %latchExit.unr-lcssa.loopexit, label %latch.2 ; PROLOG-NEXT: br i1 %cmp.2, label %latchExit.unr-lcssa.loopexit, label %latch.2
; PROLOG: latch.2: ; PROLOG: latch.2:
; PROLOG-NEXT: %indvars.iv.next.2 = add i64 %indvars.iv.next.1, 1 ; PROLOG-NEXT: %indvars.iv.next.2 = add i64 %indvars.iv, 3
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.3 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.3
; PROLOG: for.exiting_block.3: ; PROLOG: for.exiting_block.3:
; PROLOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2 ; PROLOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2
; PROLOG-NEXT: %7 = load i32, ptr %arrayidx.3, align 4 ; PROLOG-NEXT: %7 = load i32, ptr %arrayidx.3, align 4
; PROLOG-NEXT: %add.3 = add nsw i32 %7, %add.2 ; PROLOG-NEXT: %add.3 = add nsw i32 %7, %add.2
; PROLOG-NEXT: %cmp.3 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.3 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.3, label %latchExit.unr-lcssa.loopexit, label %latch.3 ; PROLOG-NEXT: br i1 %cmp.3, label %latchExit.unr-lcssa.loopexit, label %latch.3
; PROLOG: latch.3: ; PROLOG: latch.3:
; PROLOG-NEXT: %indvars.iv.next.3 = add i64 %indvars.iv.next.2, 1 ; PROLOG-NEXT: %indvars.iv.next.3 = add i64 %indvars.iv, 4
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.4 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.4
; PROLOG: for.exiting_block.4: ; PROLOG: for.exiting_block.4:
; PROLOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3 ; PROLOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3
; PROLOG-NEXT: %8 = load i32, ptr %arrayidx.4, align 4 ; PROLOG-NEXT: %8 = load i32, ptr %arrayidx.4, align 4
; PROLOG-NEXT: %add.4 = add nsw i32 %8, %add.3 ; PROLOG-NEXT: %add.4 = add nsw i32 %8, %add.3
; PROLOG-NEXT: %cmp.4 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.4 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.4, label %latchExit.unr-lcssa.loopexit, label %latch.4 ; PROLOG-NEXT: br i1 %cmp.4, label %latchExit.unr-lcssa.loopexit, label %latch.4
; PROLOG: latch.4: ; PROLOG: latch.4:
; PROLOG-NEXT: %indvars.iv.next.4 = add i64 %indvars.iv.next.3, 1 ; PROLOG-NEXT: %indvars.iv.next.4 = add i64 %indvars.iv, 5
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.5 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.5
; PROLOG: for.exiting_block.5: ; PROLOG: for.exiting_block.5:
; PROLOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4 ; PROLOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4
; PROLOG-NEXT: %9 = load i32, ptr %arrayidx.5, align 4 ; PROLOG-NEXT: %9 = load i32, ptr %arrayidx.5, align 4
; PROLOG-NEXT: %add.5 = add nsw i32 %9, %add.4 ; PROLOG-NEXT: %add.5 = add nsw i32 %9, %add.4
; PROLOG-NEXT: %cmp.5 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.5 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.5, label %latchExit.unr-lcssa.loopexit, label %latch.5 ; PROLOG-NEXT: br i1 %cmp.5, label %latchExit.unr-lcssa.loopexit, label %latch.5
; PROLOG: latch.5: ; PROLOG: latch.5:
; PROLOG-NEXT: %indvars.iv.next.5 = add i64 %indvars.iv.next.4, 1 ; PROLOG-NEXT: %indvars.iv.next.5 = add i64 %indvars.iv, 6
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.6 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.6
; PROLOG: for.exiting_block.6: ; PROLOG: for.exiting_block.6:
; PROLOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5 ; PROLOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5
; PROLOG-NEXT: %10 = load i32, ptr %arrayidx.6, align 4 ; PROLOG-NEXT: %10 = load i32, ptr %arrayidx.6, align 4
; PROLOG-NEXT: %add.6 = add nsw i32 %10, %add.5 ; PROLOG-NEXT: %add.6 = add nsw i32 %10, %add.5
; PROLOG-NEXT: %cmp.6 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.6 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.6, label %latchExit.unr-lcssa.loopexit, label %latch.6 ; PROLOG-NEXT: br i1 %cmp.6, label %latchExit.unr-lcssa.loopexit, label %latch.6
; PROLOG: latch.6: ; PROLOG: latch.6:
; PROLOG-NEXT: %indvars.iv.next.6 = add i64 %indvars.iv.next.5, 1 ; PROLOG-NEXT: %indvars.iv.next.6 = add i64 %indvars.iv, 7
; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.7 ; PROLOG-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.7
; PROLOG: for.exiting_block.7: ; PROLOG: for.exiting_block.7:
; PROLOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6 ; PROLOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; PROLOG-NEXT: %11 = load i32, ptr %arrayidx.7, align 4 ; PROLOG-NEXT: %11 = load i32, ptr %arrayidx.7, align 4
; PROLOG-NEXT: %add.7 = add nsw i32 %11, %add.6 ; PROLOG-NEXT: %add.7 = add nsw i32 %11, %add.6
; PROLOG-NEXT: %cmp.7 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.7, label %latchExit.unr-lcssa.loopexit, label %latch.7 ; PROLOG-NEXT: br i1 %cmp.7, label %latchExit.unr-lcssa.loopexit, label %latch.7
; PROLOG: latch.7: ; PROLOG: latch.7:
; PROLOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv.next.6, 1 ; PROLOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
; PROLOG-NEXT: %exitcond.7 = icmp eq i64 %indvars.iv.next.7, %n ; PROLOG-NEXT: %exitcond.7 = icmp eq i64 %indvars.iv.next.7, %n
; PROLOG-NEXT: br i1 %exitcond.7, label %latchExit.unr-lcssa.loopexit, label %header ; PROLOG-NEXT: br i1 %exitcond.7, label %latchExit.unr-lcssa.loopexit, label %header
; PROLOG: latchExit.unr-lcssa.loopexit: ; PROLOG: latchExit.unr-lcssa.loopexit:
; PROLOG-NEXT: %result.ph.ph = phi i32 [ %sum.02, %for.exiting_block ], [ %add, %for.exiting_block.1 ], [ %add.1, %for.exiting_block.2 ], [ %add.2, %for.exiting_block.3 ], [ %add.3, %for.exiting_block.4 ], [ %add.4, %for.exiting_block.5 ], [ %add.5, %for.exiting_block.6 ], [ %add.6, %for.exiting_block.7 ], [ %add.7, %latch.7 ] ; PROLOG-NEXT: %result.ph.ph = phi i32 [ %sum.02, %for.exiting_block ], [ %add, %for.exiting_block.1 ], [ %add.1, %for.exiting_block.2 ], [ %add.2, %for.exiting_block.3 ], [ %add.3, %for.exiting_block.4 ], [ %add.4, %for.exiting_block.5 ], [ %add.5, %for.exiting_block.6 ], [ %add.6, %for.exiting_block.7 ], [ %add.7, %latch.7 ]
; PROLOG-NEXT: br label %latchExit.unr-lcssa ; PROLOG-NEXT: br label %latchExit.unr-lcssa
; PROLOG: latchExit.unr-lcssa.loopexit2: ; PROLOG: latchExit.unr-lcssa.loopexit2:
; PROLOG-NEXT: %result.ph.ph3 = phi i32 [ %sum.02.prol, %for.exiting_block.prol ] ; PROLOG-NEXT: %result.ph.ph3 = phi i32 [ %sum.02.prol, %for.exiting_block.prol ]
; PROLOG-NEXT: br label %latchExit.unr-lcssa ; PROLOG-NEXT: br label %latchExit.unr-lcssa
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; PROLOG-BLOCK-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1 ; PROLOG-BLOCK-NEXT: br i1 %cond, label %for.exit2.loopexit, label %for.exiting_block.1
; PROLOG-BLOCK: for.exiting_block.1: ; PROLOG-BLOCK: for.exiting_block.1:
; PROLOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; PROLOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; PROLOG-BLOCK-NEXT: %5 = load i32, ptr %arrayidx.1, align 4 ; PROLOG-BLOCK-NEXT: %5 = load i32, ptr %arrayidx.1, align 4
; PROLOG-BLOCK-NEXT: %add.1 = add nsw i32 %5, %add ; PROLOG-BLOCK-NEXT: %add.1 = add nsw i32 %5, %add
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.unr-lcssa.loopexit, label %latch.1 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %latchExit.unr-lcssa.loopexit, label %latch.1
; PROLOG-BLOCK: latch.1: ; PROLOG-BLOCK: latch.1:
; PROLOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; PROLOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; PROLOG-BLOCK-NEXT: %exitcond.1 = icmp eq i64 %indvars.iv.next.1, %n ; PROLOG-BLOCK-NEXT: %exitcond.1 = icmp eq i64 %indvars.iv.next.1, %n
; PROLOG-BLOCK-NEXT: br i1 %exitcond.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !7 ; PROLOG-BLOCK-NEXT: br i1 %exitcond.1, label %latchExit.unr-lcssa.loopexit, label %header, !llvm.loop !7
; PROLOG-BLOCK: latchExit.unr-lcssa.loopexit: ; PROLOG-BLOCK: latchExit.unr-lcssa.loopexit:
; PROLOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ %sum.02, %for.exiting_block ], [ %add, %for.exiting_block.1 ], [ %add.1, %latch.1 ] ; PROLOG-BLOCK-NEXT: %result.ph.ph = phi i32 [ %sum.02, %for.exiting_block ], [ %add, %for.exiting_block.1 ], [ %add.1, %latch.1 ]
; PROLOG-BLOCK-NEXT: br label %latchExit.unr-lcssa ; PROLOG-BLOCK-NEXT: br label %latchExit.unr-lcssa
; PROLOG-BLOCK: latchExit.unr-lcssa: ; PROLOG-BLOCK: latchExit.unr-lcssa:
; PROLOG-BLOCK-NEXT: %result.ph = phi i32 [ 0, %for.exiting_block.prol ], [ %result.ph.ph, %latchExit.unr-lcssa.loopexit ] ; PROLOG-BLOCK-NEXT: %result.ph = phi i32 [ 0, %for.exiting_block.prol ], [ %result.ph.ph, %latchExit.unr-lcssa.loopexit ]
; PROLOG-BLOCK-NEXT: br label %latchExit ; PROLOG-BLOCK-NEXT: br label %latchExit
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; EPILOG-NEXT: br label %header ; EPILOG-NEXT: br label %header
; EPILOG: header: ; EPILOG: header:
; EPILOG-NEXT: %i4 = phi i32 [ 0, %preheader.new ], [ %inc.7, %latch.7 ] ; EPILOG-NEXT: %i4 = phi i32 [ 0, %preheader.new ], [ %inc.7, %latch.7 ]
; EPILOG-NEXT: %niter = phi i32 [ 0, %preheader.new ], [ %niter.next.7, %latch.7 ] ; EPILOG-NEXT: %niter = phi i32 [ 0, %preheader.new ], [ %niter.next.7, %latch.7 ]
; EPILOG-NEXT: %inc = add nuw nsw i32 %i4, 1 ; EPILOG-NEXT: %inc = add nuw nsw i32 %i4, 1
; EPILOG-NEXT: %cmp1 = icmp ult i32 %inc, %N ; EPILOG-NEXT: %cmp1 = icmp ult i32 %inc, %N
; EPILOG-NEXT: br i1 %cmp1, label %latch, label %latchExit.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp1, label %latch, label %latchExit.epilog-lcssa.loopexit
; EPILOG: latch: ; EPILOG: latch:
; EPILOG-NEXT: %niter.next = add nuw nsw i32 %niter, 1 ; EPILOG-NEXT: %inc.1 = add nuw nsw i32 %i4, 2
; EPILOG-NEXT: %inc.1 = add nuw nsw i32 %inc, 1
; EPILOG-NEXT: %cmp1.1 = icmp ult i32 %inc.1, %N ; EPILOG-NEXT: %cmp1.1 = icmp ult i32 %inc.1, %N
; EPILOG-NEXT: br i1 %cmp1.1, label %latch.1, label %latchExit.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp1.1, label %latch.1, label %latchExit.epilog-lcssa.loopexit
; EPILOG: latch.1: ; EPILOG: latch.1:
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i32 %niter.next, 1 ; EPILOG-NEXT: %inc.2 = add nuw nsw i32 %i4, 3
; EPILOG-NEXT: %inc.2 = add nuw nsw i32 %inc.1, 1
; EPILOG-NEXT: %cmp1.2 = icmp ult i32 %inc.2, %N ; EPILOG-NEXT: %cmp1.2 = icmp ult i32 %inc.2, %N
; EPILOG-NEXT: br i1 %cmp1.2, label %latch.2, label %latchExit.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp1.2, label %latch.2, label %latchExit.epilog-lcssa.loopexit
; EPILOG: latch.2: ; EPILOG: latch.2:
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i32 %niter.next.1, 1 ; EPILOG-NEXT: %inc.3 = add nuw nsw i32 %i4, 4
; EPILOG-NEXT: %inc.3 = add nuw nsw i32 %inc.2, 1
; EPILOG-NEXT: %cmp1.3 = icmp ult i32 %inc.3, %N ; EPILOG-NEXT: %cmp1.3 = icmp ult i32 %inc.3, %N
; EPILOG-NEXT: br i1 %cmp1.3, label %latch.3, label %latchExit.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp1.3, label %latch.3, label %latchExit.epilog-lcssa.loopexit
; EPILOG: latch.3: ; EPILOG: latch.3:
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i32 %niter.next.2, 1 ; EPILOG-NEXT: %inc.4 = add nuw nsw i32 %i4, 5
; EPILOG-NEXT: %inc.4 = add nuw nsw i32 %inc.3, 1
; EPILOG-NEXT: %cmp1.4 = icmp ult i32 %inc.4, %N ; EPILOG-NEXT: %cmp1.4 = icmp ult i32 %inc.4, %N
; EPILOG-NEXT: br i1 %cmp1.4, label %latch.4, label %latchExit.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp1.4, label %latch.4, label %latchExit.epilog-lcssa.loopexit
; EPILOG: latch.4: ; EPILOG: latch.4:
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i32 %niter.next.3, 1 ; EPILOG-NEXT: %inc.5 = add nuw nsw i32 %i4, 6
; EPILOG-NEXT: %inc.5 = add nuw nsw i32 %inc.4, 1
; EPILOG-NEXT: %cmp1.5 = icmp ult i32 %inc.5, %N ; EPILOG-NEXT: %cmp1.5 = icmp ult i32 %inc.5, %N
; EPILOG-NEXT: br i1 %cmp1.5, label %latch.5, label %latchExit.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp1.5, label %latch.5, label %latchExit.epilog-lcssa.loopexit
; EPILOG: latch.5: ; EPILOG: latch.5:
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i32 %niter.next.4, 1 ; EPILOG-NEXT: %inc.6 = add nuw nsw i32 %i4, 7
; EPILOG-NEXT: %inc.6 = add nuw nsw i32 %inc.5, 1
; EPILOG-NEXT: %cmp1.6 = icmp ult i32 %inc.6, %N ; EPILOG-NEXT: %cmp1.6 = icmp ult i32 %inc.6, %N
; EPILOG-NEXT: br i1 %cmp1.6, label %latch.6, label %latchExit.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp1.6, label %latch.6, label %latchExit.epilog-lcssa.loopexit
; EPILOG: latch.6: ; EPILOG: latch.6:
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i32 %niter.next.5, 1 ; EPILOG-NEXT: %inc.7 = add nuw i32 %i4, 8
; EPILOG-NEXT: %inc.7 = add nuw i32 %inc.6, 1
; EPILOG-NEXT: %cmp1.7 = icmp ult i32 %inc.7, %N ; EPILOG-NEXT: %cmp1.7 = icmp ult i32 %inc.7, %N
; EPILOG-NEXT: br i1 %cmp1.7, label %latch.7, label %latchExit.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp1.7, label %latch.7, label %latchExit.epilog-lcssa.loopexit
; EPILOG: latch.7: ; EPILOG: latch.7:
; EPILOG-NEXT: %niter.next.7 = add nuw i32 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add nuw i32 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i32 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i32 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %header, label %latchExit.unr-lcssa.loopexit ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %header, label %latchExit.unr-lcssa.loopexit
; EPILOG: latchExit.unr-lcssa.loopexit: ; EPILOG: latchExit.unr-lcssa.loopexit:
; EPILOG-NEXT: %i2.ph.ph.ph = phi i32 [ -1, %latch.7 ] ; EPILOG-NEXT: %i2.ph.ph.ph = phi i32 [ -1, %latch.7 ]
; EPILOG-NEXT: %i4.unr.ph = phi i32 [ %inc.7, %latch.7 ] ; EPILOG-NEXT: %i4.unr.ph = phi i32 [ %inc.7, %latch.7 ]
; EPILOG-NEXT: br label %latchExit.unr-lcssa ; EPILOG-NEXT: br label %latchExit.unr-lcssa
; EPILOG: latchExit.unr-lcssa: ; EPILOG: latchExit.unr-lcssa:
; EPILOG-NEXT: %i2.ph.ph = phi i32 [ undef, %preheader ], [ %i2.ph.ph.ph, %latchExit.unr-lcssa.loopexit ] ; EPILOG-NEXT: %i2.ph.ph = phi i32 [ undef, %preheader ], [ %i2.ph.ph.ph, %latchExit.unr-lcssa.loopexit ]
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; EPILOG-BLOCK-NEXT: br label %header ; EPILOG-BLOCK-NEXT: br label %header
; EPILOG-BLOCK: header: ; EPILOG-BLOCK: header:
; EPILOG-BLOCK-NEXT: %i4 = phi i32 [ 0, %preheader.new ], [ %inc.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %i4 = phi i32 [ 0, %preheader.new ], [ %inc.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %niter = phi i32 [ 0, %preheader.new ], [ %niter.next.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %niter = phi i32 [ 0, %preheader.new ], [ %niter.next.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %inc = add nuw nsw i32 %i4, 1 ; EPILOG-BLOCK-NEXT: %inc = add nuw nsw i32 %i4, 1
; EPILOG-BLOCK-NEXT: %cmp1 = icmp ult i32 %inc, %N ; EPILOG-BLOCK-NEXT: %cmp1 = icmp ult i32 %inc, %N
; EPILOG-BLOCK-NEXT: br i1 %cmp1, label %latch, label %latchExit.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cmp1, label %latch, label %latchExit.epilog-lcssa.loopexit
; EPILOG-BLOCK: latch: ; EPILOG-BLOCK: latch:
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i32 %niter, 1 ; EPILOG-BLOCK-NEXT: %inc.1 = add nuw i32 %i4, 2
; EPILOG-BLOCK-NEXT: %inc.1 = add nuw i32 %inc, 1
; EPILOG-BLOCK-NEXT: %cmp1.1 = icmp ult i32 %inc.1, %N ; EPILOG-BLOCK-NEXT: %cmp1.1 = icmp ult i32 %inc.1, %N
; EPILOG-BLOCK-NEXT: br i1 %cmp1.1, label %latch.1, label %latchExit.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cmp1.1, label %latch.1, label %latchExit.epilog-lcssa.loopexit
; EPILOG-BLOCK: latch.1: ; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i32 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add nuw i32 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i32 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i32 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %header, label %latchExit.unr-lcssa.loopexit, !llvm.loop !8 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %header, label %latchExit.unr-lcssa.loopexit, !llvm.loop !8
; EPILOG-BLOCK: latchExit.unr-lcssa.loopexit: ; EPILOG-BLOCK: latchExit.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: %i2.ph.ph.ph = phi i32 [ -1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %i2.ph.ph.ph = phi i32 [ -1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %i4.unr.ph = phi i32 [ %inc.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %i4.unr.ph = phi i32 [ %inc.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: br label %latchExit.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %latchExit.unr-lcssa
; EPILOG-BLOCK: latchExit.unr-lcssa: ; EPILOG-BLOCK: latchExit.unr-lcssa:
; EPILOG-BLOCK-NEXT: %i2.ph.ph = phi i32 [ undef, %preheader ], [ %i2.ph.ph.ph, %latchExit.unr-lcssa.loopexit ] ; EPILOG-BLOCK-NEXT: %i2.ph.ph = phi i32 [ undef, %preheader ], [ %i2.ph.ph.ph, %latchExit.unr-lcssa.loopexit ]
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; PROLOG: preheader.new: ; PROLOG: preheader.new:
; PROLOG-NEXT: br label %header ; PROLOG-NEXT: br label %header
; PROLOG: header: ; PROLOG: header:
; PROLOG-NEXT: %i4 = phi i32 [ %i4.unr, %preheader.new ], [ %inc.7, %latch.7 ] ; PROLOG-NEXT: %i4 = phi i32 [ %i4.unr, %preheader.new ], [ %inc.7, %latch.7 ]
; PROLOG-NEXT: %inc = add nuw i32 %i4, 1 ; PROLOG-NEXT: %inc = add nuw i32 %i4, 1
; PROLOG-NEXT: %cmp1 = icmp ult i32 %inc, %N ; PROLOG-NEXT: %cmp1 = icmp ult i32 %inc, %N
; PROLOG-NEXT: br i1 %cmp1, label %latch, label %latchExit.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp1, label %latch, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch: ; PROLOG: latch:
; PROLOG-NEXT: %inc.1 = add nuw i32 %inc, 1 ; PROLOG-NEXT: %inc.1 = add nuw i32 %i4, 2
; PROLOG-NEXT: %cmp1.1 = icmp ult i32 %inc.1, %N ; PROLOG-NEXT: %cmp1.1 = icmp ult i32 %inc.1, %N
; PROLOG-NEXT: br i1 %cmp1.1, label %latch.1, label %latchExit.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp1.1, label %latch.1, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.1: ; PROLOG: latch.1:
; PROLOG-NEXT: %inc.2 = add nuw i32 %inc.1, 1 ; PROLOG-NEXT: %inc.2 = add nuw i32 %i4, 3
; PROLOG-NEXT: %cmp1.2 = icmp ult i32 %inc.2, %N ; PROLOG-NEXT: %cmp1.2 = icmp ult i32 %inc.2, %N
; PROLOG-NEXT: br i1 %cmp1.2, label %latch.2, label %latchExit.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp1.2, label %latch.2, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.2: ; PROLOG: latch.2:
; PROLOG-NEXT: %inc.3 = add nuw i32 %inc.2, 1 ; PROLOG-NEXT: %inc.3 = add nuw i32 %i4, 4
; PROLOG-NEXT: %cmp1.3 = icmp ult i32 %inc.3, %N ; PROLOG-NEXT: %cmp1.3 = icmp ult i32 %inc.3, %N
; PROLOG-NEXT: br i1 %cmp1.3, label %latch.3, label %latchExit.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp1.3, label %latch.3, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.3: ; PROLOG: latch.3:
; PROLOG-NEXT: %inc.4 = add nuw i32 %inc.3, 1 ; PROLOG-NEXT: %inc.4 = add nuw i32 %i4, 5
; PROLOG-NEXT: %cmp1.4 = icmp ult i32 %inc.4, %N ; PROLOG-NEXT: %cmp1.4 = icmp ult i32 %inc.4, %N
; PROLOG-NEXT: br i1 %cmp1.4, label %latch.4, label %latchExit.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp1.4, label %latch.4, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.4: ; PROLOG: latch.4:
; PROLOG-NEXT: %inc.5 = add nuw i32 %inc.4, 1 ; PROLOG-NEXT: %inc.5 = add nuw i32 %i4, 6
; PROLOG-NEXT: %cmp1.5 = icmp ult i32 %inc.5, %N ; PROLOG-NEXT: %cmp1.5 = icmp ult i32 %inc.5, %N
; PROLOG-NEXT: br i1 %cmp1.5, label %latch.5, label %latchExit.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp1.5, label %latch.5, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.5: ; PROLOG: latch.5:
; PROLOG-NEXT: %inc.6 = add nuw i32 %inc.5, 1 ; PROLOG-NEXT: %inc.6 = add nuw i32 %i4, 7
; PROLOG-NEXT: %cmp1.6 = icmp ult i32 %inc.6, %N ; PROLOG-NEXT: %cmp1.6 = icmp ult i32 %inc.6, %N
; PROLOG-NEXT: br i1 %cmp1.6, label %latch.6, label %latchExit.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp1.6, label %latch.6, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.6: ; PROLOG: latch.6:
; PROLOG-NEXT: %inc.7 = add nuw i32 %inc.6, 1 ; PROLOG-NEXT: %inc.7 = add nuw i32 %i4, 8
; PROLOG-NEXT: %cmp1.7 = icmp ult i32 %inc.7, %N ; PROLOG-NEXT: %cmp1.7 = icmp ult i32 %inc.7, %N
; PROLOG-NEXT: br i1 %cmp1.7, label %latch.7, label %latchExit.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp1.7, label %latch.7, label %latchExit.unr-lcssa.loopexit
; PROLOG: latch.7: ; PROLOG: latch.7:
; PROLOG-NEXT: %cmp.7 = icmp ult i32 %inc.7, %M.shifted ; PROLOG-NEXT: %cmp.7 = icmp ult i32 %inc.7, %M.shifted
; PROLOG-NEXT: br i1 %cmp.7, label %header, label %latchExit.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp.7, label %header, label %latchExit.unr-lcssa.loopexit
; PROLOG: latchExit.unr-lcssa.loopexit: ; PROLOG: latchExit.unr-lcssa.loopexit:
; PROLOG-NEXT: %i2.ph.ph.ph = phi i32 [ %i4, %header ], [ %inc, %latch ], [ %inc.1, %latch.1 ], [ %inc.2, %latch.2 ], [ %inc.3, %latch.3 ], [ %inc.4, %latch.4 ], [ %inc.5, %latch.5 ], [ %inc.6, %latch.6 ], [ -1, %latch.7 ] ; PROLOG-NEXT: %i2.ph.ph.ph = phi i32 [ %i4, %header ], [ %inc, %latch ], [ %inc.1, %latch.1 ], [ %inc.2, %latch.2 ], [ %inc.3, %latch.3 ], [ %inc.4, %latch.4 ], [ %inc.5, %latch.5 ], [ %inc.6, %latch.6 ], [ -1, %latch.7 ]
; PROLOG-NEXT: br label %latchExit.unr-lcssa ; PROLOG-NEXT: br label %latchExit.unr-lcssa
Show All 31 Lines
; PROLOG-BLOCK: preheader.new: ; PROLOG-BLOCK: preheader.new:
; PROLOG-BLOCK-NEXT: br label %header ; PROLOG-BLOCK-NEXT: br label %header
; PROLOG-BLOCK: header: ; PROLOG-BLOCK: header:
; PROLOG-BLOCK-NEXT: %i4 = phi i32 [ %i4.unr, %preheader.new ], [ %inc.1, %latch.1 ] ; PROLOG-BLOCK-NEXT: %i4 = phi i32 [ %i4.unr, %preheader.new ], [ %inc.1, %latch.1 ]
; PROLOG-BLOCK-NEXT: %inc = add nuw i32 %i4, 1 ; PROLOG-BLOCK-NEXT: %inc = add nuw i32 %i4, 1
; PROLOG-BLOCK-NEXT: %cmp1 = icmp ult i32 %inc, %N ; PROLOG-BLOCK-NEXT: %cmp1 = icmp ult i32 %inc, %N
; PROLOG-BLOCK-NEXT: br i1 %cmp1, label %latch, label %latchExit.unr-lcssa.loopexit ; PROLOG-BLOCK-NEXT: br i1 %cmp1, label %latch, label %latchExit.unr-lcssa.loopexit
; PROLOG-BLOCK: latch: ; PROLOG-BLOCK: latch:
; PROLOG-BLOCK-NEXT: %inc.1 = add nuw i32 %inc, 1 ; PROLOG-BLOCK-NEXT: %inc.1 = add nuw i32 %i4, 2
; PROLOG-BLOCK-NEXT: %cmp1.1 = icmp ult i32 %inc.1, %N ; PROLOG-BLOCK-NEXT: %cmp1.1 = icmp ult i32 %inc.1, %N
; PROLOG-BLOCK-NEXT: br i1 %cmp1.1, label %latch.1, label %latchExit.unr-lcssa.loopexit ; PROLOG-BLOCK-NEXT: br i1 %cmp1.1, label %latch.1, label %latchExit.unr-lcssa.loopexit
; PROLOG-BLOCK: latch.1: ; PROLOG-BLOCK: latch.1:
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ult i32 %inc.1, %M.shifted ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ult i32 %inc.1, %M.shifted
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %header, label %latchExit.unr-lcssa.loopexit, !llvm.loop !8 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %header, label %latchExit.unr-lcssa.loopexit, !llvm.loop !8
; PROLOG-BLOCK: latchExit.unr-lcssa.loopexit: ; PROLOG-BLOCK: latchExit.unr-lcssa.loopexit:
; PROLOG-BLOCK-NEXT: %i2.ph.ph.ph = phi i32 [ %i4, %header ], [ %inc, %latch ], [ -1, %latch.1 ] ; PROLOG-BLOCK-NEXT: %i2.ph.ph.ph = phi i32 [ %i4, %header ], [ %inc, %latch ], [ -1, %latch.1 ]
; PROLOG-BLOCK-NEXT: br label %latchExit.unr-lcssa ; PROLOG-BLOCK-NEXT: br label %latchExit.unr-lcssa
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; EPILOG-NEXT: %ivy = add i64 %iv, %add ; EPILOG-NEXT: %ivy = add i64 %iv, %add
; EPILOG-NEXT: switch i64 %sum, label %loop_latch [ ; EPILOG-NEXT: switch i64 %sum, label %loop_latch [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit1.loopexit ; EPILOG-NEXT: i64 42, label %exit1.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch: ; EPILOG: loop_latch:
; EPILOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1 ; EPILOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-NEXT: %sum.next = add i64 %sum, %add ; EPILOG-NEXT: %sum.next = add i64 %sum, %add
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting.1 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting.1
; EPILOG: loop_exiting.1: ; EPILOG: loop_exiting.1:
; EPILOG-NEXT: %ivy.1 = add i64 %iv_next, %add ; EPILOG-NEXT: %ivy.1 = add i64 %iv_next, %add
; EPILOG-NEXT: switch i64 %sum.next, label %loop_latch.1 [ ; EPILOG-NEXT: switch i64 %sum.next, label %loop_latch.1 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit1.loopexit ; EPILOG-NEXT: i64 42, label %exit1.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.1: ; EPILOG: loop_latch.1:
; EPILOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1 ; EPILOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; EPILOG-NEXT: %sum.next.1 = add i64 %sum.next, %add ; EPILOG-NEXT: %sum.next.1 = add i64 %sum.next, %add
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.2, label %loop_exiting.2 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.2, label %loop_exiting.2
; EPILOG: loop_exiting.2: ; EPILOG: loop_exiting.2:
; EPILOG-NEXT: %ivy.2 = add i64 %iv_next.1, %add ; EPILOG-NEXT: %ivy.2 = add i64 %iv_next.1, %add
; EPILOG-NEXT: switch i64 %sum.next.1, label %loop_latch.2 [ ; EPILOG-NEXT: switch i64 %sum.next.1, label %loop_latch.2 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit1.loopexit ; EPILOG-NEXT: i64 42, label %exit1.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.2: ; EPILOG: loop_latch.2:
; EPILOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv_next.1, 1 ; EPILOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv, 3
; EPILOG-NEXT: %sum.next.2 = add i64 %sum.next.1, %add ; EPILOG-NEXT: %sum.next.2 = add i64 %sum.next.1, %add
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.3, label %loop_exiting.3 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.3, label %loop_exiting.3
; EPILOG: loop_exiting.3: ; EPILOG: loop_exiting.3:
; EPILOG-NEXT: %ivy.3 = add i64 %iv_next.2, %add ; EPILOG-NEXT: %ivy.3 = add i64 %iv_next.2, %add
; EPILOG-NEXT: switch i64 %sum.next.2, label %loop_latch.3 [ ; EPILOG-NEXT: switch i64 %sum.next.2, label %loop_latch.3 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit1.loopexit ; EPILOG-NEXT: i64 42, label %exit1.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.3: ; EPILOG: loop_latch.3:
; EPILOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv_next.2, 1 ; EPILOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv, 4
; EPILOG-NEXT: %sum.next.3 = add i64 %sum.next.2, %add ; EPILOG-NEXT: %sum.next.3 = add i64 %sum.next.2, %add
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.4, label %loop_exiting.4 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.4, label %loop_exiting.4
; EPILOG: loop_exiting.4: ; EPILOG: loop_exiting.4:
; EPILOG-NEXT: %ivy.4 = add i64 %iv_next.3, %add ; EPILOG-NEXT: %ivy.4 = add i64 %iv_next.3, %add
; EPILOG-NEXT: switch i64 %sum.next.3, label %loop_latch.4 [ ; EPILOG-NEXT: switch i64 %sum.next.3, label %loop_latch.4 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit1.loopexit ; EPILOG-NEXT: i64 42, label %exit1.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.4: ; EPILOG: loop_latch.4:
; EPILOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv_next.3, 1 ; EPILOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv, 5
; EPILOG-NEXT: %sum.next.4 = add i64 %sum.next.3, %add ; EPILOG-NEXT: %sum.next.4 = add i64 %sum.next.3, %add
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.5, label %loop_exiting.5 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.5, label %loop_exiting.5
; EPILOG: loop_exiting.5: ; EPILOG: loop_exiting.5:
; EPILOG-NEXT: %ivy.5 = add i64 %iv_next.4, %add ; EPILOG-NEXT: %ivy.5 = add i64 %iv_next.4, %add
; EPILOG-NEXT: switch i64 %sum.next.4, label %loop_latch.5 [ ; EPILOG-NEXT: switch i64 %sum.next.4, label %loop_latch.5 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit1.loopexit ; EPILOG-NEXT: i64 42, label %exit1.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.5: ; EPILOG: loop_latch.5:
; EPILOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv_next.4, 1 ; EPILOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv, 6
; EPILOG-NEXT: %sum.next.5 = add i64 %sum.next.4, %add ; EPILOG-NEXT: %sum.next.5 = add i64 %sum.next.4, %add
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.6, label %loop_exiting.6 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.6, label %loop_exiting.6
; EPILOG: loop_exiting.6: ; EPILOG: loop_exiting.6:
; EPILOG-NEXT: %ivy.6 = add i64 %iv_next.5, %add ; EPILOG-NEXT: %ivy.6 = add i64 %iv_next.5, %add
; EPILOG-NEXT: switch i64 %sum.next.5, label %loop_latch.6 [ ; EPILOG-NEXT: switch i64 %sum.next.5, label %loop_latch.6 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit1.loopexit ; EPILOG-NEXT: i64 42, label %exit1.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.6: ; EPILOG: loop_latch.6:
; EPILOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv_next.5, 1 ; EPILOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv, 7
; EPILOG-NEXT: %sum.next.6 = add i64 %sum.next.5, %add ; EPILOG-NEXT: %sum.next.6 = add i64 %sum.next.5, %add
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: br i1 %cond, label %loop_latch.7, label %loop_exiting.7 ; EPILOG-NEXT: br i1 %cond, label %loop_latch.7, label %loop_exiting.7
; EPILOG: loop_exiting.7: ; EPILOG: loop_exiting.7:
; EPILOG-NEXT: %ivy.7 = add i64 %iv_next.6, %add ; EPILOG-NEXT: %ivy.7 = add i64 %iv_next.6, %add
; EPILOG-NEXT: switch i64 %sum.next.6, label %loop_latch.7 [ ; EPILOG-NEXT: switch i64 %sum.next.6, label %loop_latch.7 [
; EPILOG-NEXT: i64 24, label %exit1.loopexit ; EPILOG-NEXT: i64 24, label %exit1.loopexit
; EPILOG-NEXT: i64 42, label %exit1.loopexit ; EPILOG-NEXT: i64 42, label %exit1.loopexit
; EPILOG-NEXT: ] ; EPILOG-NEXT: ]
; EPILOG: loop_latch.7: ; EPILOG: loop_latch.7:
; EPILOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv_next.6, 1 ; EPILOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv, 8
; EPILOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add ; EPILOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %latchexit.unr-lcssa.loopexit ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %latchexit.unr-lcssa.loopexit
; EPILOG: exit1.loopexit: ; EPILOG: exit1.loopexit:
; EPILOG-NEXT: %result.ph = phi i64 [ %ivy, %loop_exiting ], [ %ivy, %loop_exiting ], [ %ivy.1, %loop_exiting.1 ], [ %ivy.1, %loop_exiting.1 ], [ %ivy.2, %loop_exiting.2 ], [ %ivy.2, %loop_exiting.2 ], [ %ivy.3, %loop_exiting.3 ], [ %ivy.3, %loop_exiting.3 ], [ %ivy.4, %loop_exiting.4 ], [ %ivy.4, %loop_exiting.4 ], [ %ivy.5, %loop_exiting.5 ], [ %ivy.5, %loop_exiting.5 ], [ %ivy.6, %loop_exiting.6 ], [ %ivy.6, %loop_exiting.6 ], [ %ivy.7, %loop_exiting.7 ], [ %ivy.7, %loop_exiting.7 ] ; EPILOG-NEXT: %result.ph = phi i64 [ %ivy, %loop_exiting ], [ %ivy, %loop_exiting ], [ %ivy.1, %loop_exiting.1 ], [ %ivy.1, %loop_exiting.1 ], [ %ivy.2, %loop_exiting.2 ], [ %ivy.2, %loop_exiting.2 ], [ %ivy.3, %loop_exiting.3 ], [ %ivy.3, %loop_exiting.3 ], [ %ivy.4, %loop_exiting.4 ], [ %ivy.4, %loop_exiting.4 ], [ %ivy.5, %loop_exiting.5 ], [ %ivy.5, %loop_exiting.5 ], [ %ivy.6, %loop_exiting.6 ], [ %ivy.6, %loop_exiting.6 ], [ %ivy.7, %loop_exiting.7 ], [ %ivy.7, %loop_exiting.7 ]
; EPILOG-NEXT: br label %exit1 ; EPILOG-NEXT: br label %exit1
; EPILOG: exit1.loopexit2: ; EPILOG: exit1.loopexit2:
; EPILOG-NEXT: %result.ph3 = phi i64 [ %ivy.epil, %loop_exiting.epil ], [ %ivy.epil, %loop_exiting.epil ] ; EPILOG-NEXT: %result.ph3 = phi i64 [ %ivy.epil, %loop_exiting.epil ], [ %ivy.epil, %loop_exiting.epil ]
; EPILOG-NEXT: br label %exit1 ; EPILOG-NEXT: br label %exit1
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; EPILOG-BLOCK-NEXT: %ivy = add i64 %iv, %add ; EPILOG-BLOCK-NEXT: %ivy = add i64 %iv, %add
; EPILOG-BLOCK-NEXT: switch i64 %sum, label %loop_latch [ ; EPILOG-BLOCK-NEXT: switch i64 %sum, label %loop_latch [
; EPILOG-BLOCK-NEXT: i64 24, label %exit1.loopexit ; EPILOG-BLOCK-NEXT: i64 24, label %exit1.loopexit
; EPILOG-BLOCK-NEXT: i64 42, label %exit1.loopexit ; EPILOG-BLOCK-NEXT: i64 42, label %exit1.loopexit
; EPILOG-BLOCK-NEXT: ] ; EPILOG-BLOCK-NEXT: ]
; EPILOG-BLOCK: loop_latch: ; EPILOG-BLOCK: loop_latch:
; EPILOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1 ; EPILOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-BLOCK-NEXT: %sum.next = add i64 %sum, %add ; EPILOG-BLOCK-NEXT: %sum.next = add i64 %sum, %add
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting.1 ; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting.1
; EPILOG-BLOCK: loop_exiting.1: ; EPILOG-BLOCK: loop_exiting.1:
; EPILOG-BLOCK-NEXT: %ivy.1 = add i64 %iv_next, %add ; EPILOG-BLOCK-NEXT: %ivy.1 = add i64 %iv_next, %add
; EPILOG-BLOCK-NEXT: switch i64 %sum.next, label %loop_latch.1 [ ; EPILOG-BLOCK-NEXT: switch i64 %sum.next, label %loop_latch.1 [
; EPILOG-BLOCK-NEXT: i64 24, label %exit1.loopexit ; EPILOG-BLOCK-NEXT: i64 24, label %exit1.loopexit
; EPILOG-BLOCK-NEXT: i64 42, label %exit1.loopexit ; EPILOG-BLOCK-NEXT: i64 42, label %exit1.loopexit
; EPILOG-BLOCK-NEXT: ] ; EPILOG-BLOCK-NEXT: ]
; EPILOG-BLOCK: loop_latch.1: ; EPILOG-BLOCK: loop_latch.1:
; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1 ; EPILOG-BLOCK-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; EPILOG-BLOCK-NEXT: %sum.next.1 = add i64 %sum.next, %add ; EPILOG-BLOCK-NEXT: %sum.next.1 = add i64 %sum.next, %add
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %latchexit.unr-lcssa.loopexit, !llvm.loop !9 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %latchexit.unr-lcssa.loopexit, !llvm.loop !9
; EPILOG-BLOCK: exit1.loopexit: ; EPILOG-BLOCK: exit1.loopexit:
; EPILOG-BLOCK-NEXT: %result.ph = phi i64 [ %ivy, %loop_exiting ], [ %ivy, %loop_exiting ], [ %ivy.1, %loop_exiting.1 ], [ %ivy.1, %loop_exiting.1 ] ; EPILOG-BLOCK-NEXT: %result.ph = phi i64 [ %ivy, %loop_exiting ], [ %ivy, %loop_exiting ], [ %ivy.1, %loop_exiting.1 ], [ %ivy.1, %loop_exiting.1 ]
; EPILOG-BLOCK-NEXT: br label %exit1 ; EPILOG-BLOCK-NEXT: br label %exit1
; EPILOG-BLOCK: exit1: ; EPILOG-BLOCK: exit1:
; EPILOG-BLOCK-NEXT: %result = phi i64 [ %ivy.epil, %loop_exiting.epil ], [ %ivy.epil, %loop_exiting.epil ], [ %result.ph, %exit1.loopexit ] ; EPILOG-BLOCK-NEXT: %result = phi i64 [ %ivy.epil, %loop_exiting.epil ], [ %ivy.epil, %loop_exiting.epil ], [ %result.ph, %exit1.loopexit ]
; EPILOG-BLOCK-NEXT: ret i64 %result ; EPILOG-BLOCK-NEXT: ret i64 %result
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; PROLOG-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting.1 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting.1
; PROLOG: loop_exiting.1: ; PROLOG: loop_exiting.1:
; PROLOG-NEXT: %ivy.1 = add i64 %iv_next, %add ; PROLOG-NEXT: %ivy.1 = add i64 %iv_next, %add
; PROLOG-NEXT: switch i64 %sum.next, label %loop_latch.1 [ ; PROLOG-NEXT: switch i64 %sum.next, label %loop_latch.1 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit1.loopexit ; PROLOG-NEXT: i64 42, label %exit1.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.1: ; PROLOG: loop_latch.1:
; PROLOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1 ; PROLOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; PROLOG-NEXT: %sum.next.1 = add i64 %sum.next, %add ; PROLOG-NEXT: %sum.next.1 = add i64 %sum.next, %add
; PROLOG-NEXT: br i1 %cond, label %loop_latch.2, label %loop_exiting.2 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.2, label %loop_exiting.2
; PROLOG: loop_exiting.2: ; PROLOG: loop_exiting.2:
; PROLOG-NEXT: %ivy.2 = add i64 %iv_next.1, %add ; PROLOG-NEXT: %ivy.2 = add i64 %iv_next.1, %add
; PROLOG-NEXT: switch i64 %sum.next.1, label %loop_latch.2 [ ; PROLOG-NEXT: switch i64 %sum.next.1, label %loop_latch.2 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit1.loopexit ; PROLOG-NEXT: i64 42, label %exit1.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.2: ; PROLOG: loop_latch.2:
; PROLOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv_next.1, 1 ; PROLOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv, 3
; PROLOG-NEXT: %sum.next.2 = add i64 %sum.next.1, %add ; PROLOG-NEXT: %sum.next.2 = add i64 %sum.next.1, %add
; PROLOG-NEXT: br i1 %cond, label %loop_latch.3, label %loop_exiting.3 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.3, label %loop_exiting.3
; PROLOG: loop_exiting.3: ; PROLOG: loop_exiting.3:
; PROLOG-NEXT: %ivy.3 = add i64 %iv_next.2, %add ; PROLOG-NEXT: %ivy.3 = add i64 %iv_next.2, %add
; PROLOG-NEXT: switch i64 %sum.next.2, label %loop_latch.3 [ ; PROLOG-NEXT: switch i64 %sum.next.2, label %loop_latch.3 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit1.loopexit ; PROLOG-NEXT: i64 42, label %exit1.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.3: ; PROLOG: loop_latch.3:
; PROLOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv_next.2, 1 ; PROLOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv, 4
; PROLOG-NEXT: %sum.next.3 = add i64 %sum.next.2, %add ; PROLOG-NEXT: %sum.next.3 = add i64 %sum.next.2, %add
; PROLOG-NEXT: br i1 %cond, label %loop_latch.4, label %loop_exiting.4 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.4, label %loop_exiting.4
; PROLOG: loop_exiting.4: ; PROLOG: loop_exiting.4:
; PROLOG-NEXT: %ivy.4 = add i64 %iv_next.3, %add ; PROLOG-NEXT: %ivy.4 = add i64 %iv_next.3, %add
; PROLOG-NEXT: switch i64 %sum.next.3, label %loop_latch.4 [ ; PROLOG-NEXT: switch i64 %sum.next.3, label %loop_latch.4 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit1.loopexit ; PROLOG-NEXT: i64 42, label %exit1.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.4: ; PROLOG: loop_latch.4:
; PROLOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv_next.3, 1 ; PROLOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv, 5
; PROLOG-NEXT: %sum.next.4 = add i64 %sum.next.3, %add ; PROLOG-NEXT: %sum.next.4 = add i64 %sum.next.3, %add
; PROLOG-NEXT: br i1 %cond, label %loop_latch.5, label %loop_exiting.5 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.5, label %loop_exiting.5
; PROLOG: loop_exiting.5: ; PROLOG: loop_exiting.5:
; PROLOG-NEXT: %ivy.5 = add i64 %iv_next.4, %add ; PROLOG-NEXT: %ivy.5 = add i64 %iv_next.4, %add
; PROLOG-NEXT: switch i64 %sum.next.4, label %loop_latch.5 [ ; PROLOG-NEXT: switch i64 %sum.next.4, label %loop_latch.5 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit1.loopexit ; PROLOG-NEXT: i64 42, label %exit1.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.5: ; PROLOG: loop_latch.5:
; PROLOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv_next.4, 1 ; PROLOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv, 6
; PROLOG-NEXT: %sum.next.5 = add i64 %sum.next.4, %add ; PROLOG-NEXT: %sum.next.5 = add i64 %sum.next.4, %add
; PROLOG-NEXT: br i1 %cond, label %loop_latch.6, label %loop_exiting.6 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.6, label %loop_exiting.6
; PROLOG: loop_exiting.6: ; PROLOG: loop_exiting.6:
; PROLOG-NEXT: %ivy.6 = add i64 %iv_next.5, %add ; PROLOG-NEXT: %ivy.6 = add i64 %iv_next.5, %add
; PROLOG-NEXT: switch i64 %sum.next.5, label %loop_latch.6 [ ; PROLOG-NEXT: switch i64 %sum.next.5, label %loop_latch.6 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit1.loopexit ; PROLOG-NEXT: i64 42, label %exit1.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.6: ; PROLOG: loop_latch.6:
; PROLOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv_next.5, 1 ; PROLOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv, 7
; PROLOG-NEXT: %sum.next.6 = add i64 %sum.next.5, %add ; PROLOG-NEXT: %sum.next.6 = add i64 %sum.next.5, %add
; PROLOG-NEXT: br i1 %cond, label %loop_latch.7, label %loop_exiting.7 ; PROLOG-NEXT: br i1 %cond, label %loop_latch.7, label %loop_exiting.7
; PROLOG: loop_exiting.7: ; PROLOG: loop_exiting.7:
; PROLOG-NEXT: %ivy.7 = add i64 %iv_next.6, %add ; PROLOG-NEXT: %ivy.7 = add i64 %iv_next.6, %add
; PROLOG-NEXT: switch i64 %sum.next.6, label %loop_latch.7 [ ; PROLOG-NEXT: switch i64 %sum.next.6, label %loop_latch.7 [
; PROLOG-NEXT: i64 24, label %exit1.loopexit ; PROLOG-NEXT: i64 24, label %exit1.loopexit
; PROLOG-NEXT: i64 42, label %exit1.loopexit ; PROLOG-NEXT: i64 42, label %exit1.loopexit
; PROLOG-NEXT: ] ; PROLOG-NEXT: ]
; PROLOG: loop_latch.7: ; PROLOG: loop_latch.7:
; PROLOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv_next.6, 1 ; PROLOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv, 8
; PROLOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add ; PROLOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add
; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip ; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip
; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %latchexit.unr-lcssa ; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %latchexit.unr-lcssa
; PROLOG: exit1.loopexit: ; PROLOG: exit1.loopexit:
; PROLOG-NEXT: %result.ph = phi i64 [ %ivy, %loop_exiting ], [ %ivy, %loop_exiting ], [ %ivy.1, %loop_exiting.1 ], [ %ivy.1, %loop_exiting.1 ], [ %ivy.2, %loop_exiting.2 ], [ %ivy.2, %loop_exiting.2 ], [ %ivy.3, %loop_exiting.3 ], [ %ivy.3, %loop_exiting.3 ], [ %ivy.4, %loop_exiting.4 ], [ %ivy.4, %loop_exiting.4 ], [ %ivy.5, %loop_exiting.5 ], [ %ivy.5, %loop_exiting.5 ], [ %ivy.6, %loop_exiting.6 ], [ %ivy.6, %loop_exiting.6 ], [ %ivy.7, %loop_exiting.7 ], [ %ivy.7, %loop_exiting.7 ] ; PROLOG-NEXT: %result.ph = phi i64 [ %ivy, %loop_exiting ], [ %ivy, %loop_exiting ], [ %ivy.1, %loop_exiting.1 ], [ %ivy.1, %loop_exiting.1 ], [ %ivy.2, %loop_exiting.2 ], [ %ivy.2, %loop_exiting.2 ], [ %ivy.3, %loop_exiting.3 ], [ %ivy.3, %loop_exiting.3 ], [ %ivy.4, %loop_exiting.4 ], [ %ivy.4, %loop_exiting.4 ], [ %ivy.5, %loop_exiting.5 ], [ %ivy.5, %loop_exiting.5 ], [ %ivy.6, %loop_exiting.6 ], [ %ivy.6, %loop_exiting.6 ], [ %ivy.7, %loop_exiting.7 ], [ %ivy.7, %loop_exiting.7 ]
; PROLOG-NEXT: br label %exit1 ; PROLOG-NEXT: br label %exit1
; PROLOG: exit1.loopexit1: ; PROLOG: exit1.loopexit1:
; PROLOG-NEXT: %result.ph2 = phi i64 [ %ivy.prol, %loop_exiting.prol ], [ %ivy.prol, %loop_exiting.prol ] ; PROLOG-NEXT: %result.ph2 = phi i64 [ %ivy.prol, %loop_exiting.prol ], [ %ivy.prol, %loop_exiting.prol ]
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; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting.1 ; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %loop_exiting.1
; PROLOG-BLOCK: loop_exiting.1: ; PROLOG-BLOCK: loop_exiting.1:
; PROLOG-BLOCK-NEXT: %ivy.1 = add i64 %iv_next, %add ; PROLOG-BLOCK-NEXT: %ivy.1 = add i64 %iv_next, %add
; PROLOG-BLOCK-NEXT: switch i64 %sum.next, label %loop_latch.1 [ ; PROLOG-BLOCK-NEXT: switch i64 %sum.next, label %loop_latch.1 [
; PROLOG-BLOCK-NEXT: i64 24, label %exit1.loopexit ; PROLOG-BLOCK-NEXT: i64 24, label %exit1.loopexit
; PROLOG-BLOCK-NEXT: i64 42, label %exit1.loopexit ; PROLOG-BLOCK-NEXT: i64 42, label %exit1.loopexit
; PROLOG-BLOCK-NEXT: ] ; PROLOG-BLOCK-NEXT: ]
; PROLOG-BLOCK: loop_latch.1: ; PROLOG-BLOCK: loop_latch.1:
; PROLOG-BLOCK-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1 ; PROLOG-BLOCK-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; PROLOG-BLOCK-NEXT: %sum.next.1 = add i64 %sum.next, %add ; PROLOG-BLOCK-NEXT: %sum.next.1 = add i64 %sum.next, %add
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %latchexit.unr-lcssa, !llvm.loop !9 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %latchexit.unr-lcssa, !llvm.loop !9
; PROLOG-BLOCK: exit1.loopexit: ; PROLOG-BLOCK: exit1.loopexit:
; PROLOG-BLOCK-NEXT: %result.ph = phi i64 [ %ivy, %loop_exiting ], [ %ivy, %loop_exiting ], [ %ivy.1, %loop_exiting.1 ], [ %ivy.1, %loop_exiting.1 ] ; PROLOG-BLOCK-NEXT: %result.ph = phi i64 [ %ivy, %loop_exiting ], [ %ivy, %loop_exiting ], [ %ivy.1, %loop_exiting.1 ], [ %ivy.1, %loop_exiting.1 ]
; PROLOG-BLOCK-NEXT: br label %exit1 ; PROLOG-BLOCK-NEXT: br label %exit1
; PROLOG-BLOCK: exit1: ; PROLOG-BLOCK: exit1:
; PROLOG-BLOCK-NEXT: %result = phi i64 [ %add, %loop_exiting.prol ], [ %add, %loop_exiting.prol ], [ %result.ph, %exit1.loopexit ] ; PROLOG-BLOCK-NEXT: %result = phi i64 [ %add, %loop_exiting.prol ], [ %add, %loop_exiting.prol ], [ %result.ph, %exit1.loopexit ]
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; EPILOG: for.exiting_block: ; EPILOG: for.exiting_block:
; EPILOG-NEXT: %cmp = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp, label %for.exit2.loopexit, label %latch ; EPILOG-NEXT: br i1 %cmp, label %for.exit2.loopexit, label %latch
; EPILOG: latch: ; EPILOG: latch:
; EPILOG-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv ; EPILOG-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
; EPILOG-NEXT: %load = load i32, ptr %arrayidx, align 4 ; EPILOG-NEXT: %load = load i32, ptr %arrayidx, align 4
; EPILOG-NEXT: %add = add nsw i32 %load, %sum.02 ; EPILOG-NEXT: %add = add nsw i32 %load, %sum.02
; EPILOG-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 ; EPILOG-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1
; EPILOG: for.exiting_block.1: ; EPILOG: for.exiting_block.1:
; EPILOG-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1 ; EPILOG-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1
; EPILOG: latch.1: ; EPILOG: latch.1:
; EPILOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; EPILOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-NEXT: %load.1 = load i32, ptr %arrayidx.1, align 4 ; EPILOG-NEXT: %load.1 = load i32, ptr %arrayidx.1, align 4
; EPILOG-NEXT: %add.1 = add nsw i32 %load.1, %add ; EPILOG-NEXT: %add.1 = add nsw i32 %load.1, %add
; EPILOG-NEXT: %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv.next, 1 ; EPILOG-NEXT: %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.2 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.2
; EPILOG: for.exiting_block.2: ; EPILOG: for.exiting_block.2:
; EPILOG-NEXT: %cmp.2 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.2 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.2, label %for.exit2.loopexit, label %latch.2 ; EPILOG-NEXT: br i1 %cmp.2, label %for.exit2.loopexit, label %latch.2
; EPILOG: latch.2: ; EPILOG: latch.2:
; EPILOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1 ; EPILOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1
; EPILOG-NEXT: %load.2 = load i32, ptr %arrayidx.2, align 4 ; EPILOG-NEXT: %load.2 = load i32, ptr %arrayidx.2, align 4
; EPILOG-NEXT: %add.2 = add nsw i32 %load.2, %add.1 ; EPILOG-NEXT: %add.2 = add nsw i32 %load.2, %add.1
; EPILOG-NEXT: %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv.next.1, 1 ; EPILOG-NEXT: %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv, 3
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.3 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.3
; EPILOG: for.exiting_block.3: ; EPILOG: for.exiting_block.3:
; EPILOG-NEXT: %cmp.3 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.3 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.3, label %for.exit2.loopexit, label %latch.3 ; EPILOG-NEXT: br i1 %cmp.3, label %for.exit2.loopexit, label %latch.3
; EPILOG: latch.3: ; EPILOG: latch.3:
; EPILOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2 ; EPILOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2
; EPILOG-NEXT: %load.3 = load i32, ptr %arrayidx.3, align 4 ; EPILOG-NEXT: %load.3 = load i32, ptr %arrayidx.3, align 4
; EPILOG-NEXT: %add.3 = add nsw i32 %load.3, %add.2 ; EPILOG-NEXT: %add.3 = add nsw i32 %load.3, %add.2
; EPILOG-NEXT: %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv.next.2, 1 ; EPILOG-NEXT: %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv, 4
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.4 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.4
; EPILOG: for.exiting_block.4: ; EPILOG: for.exiting_block.4:
; EPILOG-NEXT: %cmp.4 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.4 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.4, label %for.exit2.loopexit, label %latch.4 ; EPILOG-NEXT: br i1 %cmp.4, label %for.exit2.loopexit, label %latch.4
; EPILOG: latch.4: ; EPILOG: latch.4:
; EPILOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3 ; EPILOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3
; EPILOG-NEXT: %load.4 = load i32, ptr %arrayidx.4, align 4 ; EPILOG-NEXT: %load.4 = load i32, ptr %arrayidx.4, align 4
; EPILOG-NEXT: %add.4 = add nsw i32 %load.4, %add.3 ; EPILOG-NEXT: %add.4 = add nsw i32 %load.4, %add.3
; EPILOG-NEXT: %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv.next.3, 1 ; EPILOG-NEXT: %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv, 5
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.5 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.5
; EPILOG: for.exiting_block.5: ; EPILOG: for.exiting_block.5:
; EPILOG-NEXT: %cmp.5 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.5 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.5, label %for.exit2.loopexit, label %latch.5 ; EPILOG-NEXT: br i1 %cmp.5, label %for.exit2.loopexit, label %latch.5
; EPILOG: latch.5: ; EPILOG: latch.5:
; EPILOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4 ; EPILOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4
; EPILOG-NEXT: %load.5 = load i32, ptr %arrayidx.5, align 4 ; EPILOG-NEXT: %load.5 = load i32, ptr %arrayidx.5, align 4
; EPILOG-NEXT: %add.5 = add nsw i32 %load.5, %add.4 ; EPILOG-NEXT: %add.5 = add nsw i32 %load.5, %add.4
; EPILOG-NEXT: %indvars.iv.next.5 = add nuw nsw i64 %indvars.iv.next.4, 1 ; EPILOG-NEXT: %indvars.iv.next.5 = add nuw nsw i64 %indvars.iv, 6
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.6 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.6
; EPILOG: for.exiting_block.6: ; EPILOG: for.exiting_block.6:
; EPILOG-NEXT: %cmp.6 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.6 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.6, label %for.exit2.loopexit, label %latch.6 ; EPILOG-NEXT: br i1 %cmp.6, label %for.exit2.loopexit, label %latch.6
; EPILOG: latch.6: ; EPILOG: latch.6:
; EPILOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5 ; EPILOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5
; EPILOG-NEXT: %load.6 = load i32, ptr %arrayidx.6, align 4 ; EPILOG-NEXT: %load.6 = load i32, ptr %arrayidx.6, align 4
; EPILOG-NEXT: %add.6 = add nsw i32 %load.6, %add.5 ; EPILOG-NEXT: %add.6 = add nsw i32 %load.6, %add.5
; EPILOG-NEXT: %indvars.iv.next.6 = add nuw nsw i64 %indvars.iv.next.5, 1 ; EPILOG-NEXT: %indvars.iv.next.6 = add nuw nsw i64 %indvars.iv, 7
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.7 ; EPILOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.7
; EPILOG: for.exiting_block.7: ; EPILOG: for.exiting_block.7:
; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42 ; EPILOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; EPILOG-NEXT: br i1 %cmp.7, label %for.exit2.loopexit, label %latch.7 ; EPILOG-NEXT: br i1 %cmp.7, label %for.exit2.loopexit, label %latch.7
; EPILOG: latch.7: ; EPILOG: latch.7:
; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6 ; EPILOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; EPILOG-NEXT: %load.7 = load i32, ptr %arrayidx.7, align 4 ; EPILOG-NEXT: %load.7 = load i32, ptr %arrayidx.7, align 4
; EPILOG-NEXT: %add.7 = add nsw i32 %load.7, %add.6 ; EPILOG-NEXT: %add.7 = add nsw i32 %load.7, %add.6
; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv.next.6, 1 ; EPILOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latch_exit.unr-lcssa.loopexit, label %header ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %latch_exit.unr-lcssa.loopexit, label %header
; EPILOG: latch_exit.unr-lcssa.loopexit: ; EPILOG: latch_exit.unr-lcssa.loopexit:
; EPILOG-NEXT: %sum.0.lcssa.ph.ph = phi i32 [ %add.7, %latch.7 ] ; EPILOG-NEXT: %sum.0.lcssa.ph.ph = phi i32 [ %add.7, %latch.7 ]
; EPILOG-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.7, %latch.7 ] ; EPILOG-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.7, %latch.7 ]
; EPILOG-NEXT: %sum.02.unr.ph = phi i32 [ %add.7, %latch.7 ] ; EPILOG-NEXT: %sum.02.unr.ph = phi i32 [ %add.7, %latch.7 ]
; EPILOG-NEXT: br label %latch_exit.unr-lcssa ; EPILOG-NEXT: br label %latch_exit.unr-lcssa
; EPILOG: latch_exit.unr-lcssa: ; EPILOG: latch_exit.unr-lcssa:
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; EPILOG-BLOCK: for.exiting_block: ; EPILOG-BLOCK: for.exiting_block:
; EPILOG-BLOCK-NEXT: %cmp = icmp eq i64 %n, 42 ; EPILOG-BLOCK-NEXT: %cmp = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp, label %for.exit2.loopexit, label %latch ; EPILOG-BLOCK-NEXT: br i1 %cmp, label %for.exit2.loopexit, label %latch
; EPILOG-BLOCK: latch: ; EPILOG-BLOCK: latch:
; EPILOG-BLOCK-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv ; EPILOG-BLOCK-NEXT: %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
; EPILOG-BLOCK-NEXT: %load = load i32, ptr %arrayidx, align 4 ; EPILOG-BLOCK-NEXT: %load = load i32, ptr %arrayidx, align 4
; EPILOG-BLOCK-NEXT: %add = add nsw i32 %load, %sum.02 ; EPILOG-BLOCK-NEXT: %add = add nsw i32 %load, %sum.02
; EPILOG-BLOCK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 ; EPILOG-BLOCK-NEXT: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1 ; EPILOG-BLOCK-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1
; EPILOG-BLOCK: for.exiting_block.1: ; EPILOG-BLOCK: for.exiting_block.1:
; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; EPILOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1 ; EPILOG-BLOCK-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1
; EPILOG-BLOCK: latch.1: ; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; EPILOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; EPILOG-BLOCK-NEXT: %load.1 = load i32, ptr %arrayidx.1, align 4 ; EPILOG-BLOCK-NEXT: %load.1 = load i32, ptr %arrayidx.1, align 4
; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %load.1, %add ; EPILOG-BLOCK-NEXT: %add.1 = add nsw i32 %load.1, %add
; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; EPILOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latch_exit.unr-lcssa.loopexit, label %header, !llvm.loop !10 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %latch_exit.unr-lcssa.loopexit, label %header, !llvm.loop !10
; EPILOG-BLOCK: latch_exit.unr-lcssa.loopexit: ; EPILOG-BLOCK: latch_exit.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: %sum.0.lcssa.ph.ph = phi i32 [ %add.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %sum.0.lcssa.ph.ph = phi i32 [ %add.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %indvars.iv.unr.ph = phi i64 [ %indvars.iv.next.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %sum.02.unr.ph = phi i32 [ %add.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %sum.02.unr.ph = phi i32 [ %add.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: br label %latch_exit.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %latch_exit.unr-lcssa
; EPILOG-BLOCK: latch_exit.unr-lcssa: ; EPILOG-BLOCK: latch_exit.unr-lcssa:
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; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1
; PROLOG: for.exiting_block.1: ; PROLOG: for.exiting_block.1:
; PROLOG-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.1 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1 ; PROLOG-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1
; PROLOG: latch.1: ; PROLOG: latch.1:
; PROLOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; PROLOG-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; PROLOG-NEXT: %load.1 = load i32, ptr %arrayidx.1, align 4 ; PROLOG-NEXT: %load.1 = load i32, ptr %arrayidx.1, align 4
; PROLOG-NEXT: %add.1 = add nsw i32 %load.1, %add ; PROLOG-NEXT: %add.1 = add nsw i32 %load.1, %add
; PROLOG-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; PROLOG-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.2 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.2
; PROLOG: for.exiting_block.2: ; PROLOG: for.exiting_block.2:
; PROLOG-NEXT: %cmp.2 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.2 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.2, label %for.exit2.loopexit, label %latch.2 ; PROLOG-NEXT: br i1 %cmp.2, label %for.exit2.loopexit, label %latch.2
; PROLOG: latch.2: ; PROLOG: latch.2:
; PROLOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1 ; PROLOG-NEXT: %arrayidx.2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.1
; PROLOG-NEXT: %load.2 = load i32, ptr %arrayidx.2, align 4 ; PROLOG-NEXT: %load.2 = load i32, ptr %arrayidx.2, align 4
; PROLOG-NEXT: %add.2 = add nsw i32 %load.2, %add.1 ; PROLOG-NEXT: %add.2 = add nsw i32 %load.2, %add.1
; PROLOG-NEXT: %indvars.iv.next.2 = add i64 %indvars.iv.next.1, 1 ; PROLOG-NEXT: %indvars.iv.next.2 = add i64 %indvars.iv, 3
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.3 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.3
; PROLOG: for.exiting_block.3: ; PROLOG: for.exiting_block.3:
; PROLOG-NEXT: %cmp.3 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.3 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.3, label %for.exit2.loopexit, label %latch.3 ; PROLOG-NEXT: br i1 %cmp.3, label %for.exit2.loopexit, label %latch.3
; PROLOG: latch.3: ; PROLOG: latch.3:
; PROLOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2 ; PROLOG-NEXT: %arrayidx.3 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.2
; PROLOG-NEXT: %load.3 = load i32, ptr %arrayidx.3, align 4 ; PROLOG-NEXT: %load.3 = load i32, ptr %arrayidx.3, align 4
; PROLOG-NEXT: %add.3 = add nsw i32 %load.3, %add.2 ; PROLOG-NEXT: %add.3 = add nsw i32 %load.3, %add.2
; PROLOG-NEXT: %indvars.iv.next.3 = add i64 %indvars.iv.next.2, 1 ; PROLOG-NEXT: %indvars.iv.next.3 = add i64 %indvars.iv, 4
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.4 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.4
; PROLOG: for.exiting_block.4: ; PROLOG: for.exiting_block.4:
; PROLOG-NEXT: %cmp.4 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.4 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.4, label %for.exit2.loopexit, label %latch.4 ; PROLOG-NEXT: br i1 %cmp.4, label %for.exit2.loopexit, label %latch.4
; PROLOG: latch.4: ; PROLOG: latch.4:
; PROLOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3 ; PROLOG-NEXT: %arrayidx.4 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.3
; PROLOG-NEXT: %load.4 = load i32, ptr %arrayidx.4, align 4 ; PROLOG-NEXT: %load.4 = load i32, ptr %arrayidx.4, align 4
; PROLOG-NEXT: %add.4 = add nsw i32 %load.4, %add.3 ; PROLOG-NEXT: %add.4 = add nsw i32 %load.4, %add.3
; PROLOG-NEXT: %indvars.iv.next.4 = add i64 %indvars.iv.next.3, 1 ; PROLOG-NEXT: %indvars.iv.next.4 = add i64 %indvars.iv, 5
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.5 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.5
; PROLOG: for.exiting_block.5: ; PROLOG: for.exiting_block.5:
; PROLOG-NEXT: %cmp.5 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.5 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.5, label %for.exit2.loopexit, label %latch.5 ; PROLOG-NEXT: br i1 %cmp.5, label %for.exit2.loopexit, label %latch.5
; PROLOG: latch.5: ; PROLOG: latch.5:
; PROLOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4 ; PROLOG-NEXT: %arrayidx.5 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.4
; PROLOG-NEXT: %load.5 = load i32, ptr %arrayidx.5, align 4 ; PROLOG-NEXT: %load.5 = load i32, ptr %arrayidx.5, align 4
; PROLOG-NEXT: %add.5 = add nsw i32 %load.5, %add.4 ; PROLOG-NEXT: %add.5 = add nsw i32 %load.5, %add.4
; PROLOG-NEXT: %indvars.iv.next.5 = add i64 %indvars.iv.next.4, 1 ; PROLOG-NEXT: %indvars.iv.next.5 = add i64 %indvars.iv, 6
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.6 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.6
; PROLOG: for.exiting_block.6: ; PROLOG: for.exiting_block.6:
; PROLOG-NEXT: %cmp.6 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.6 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.6, label %for.exit2.loopexit, label %latch.6 ; PROLOG-NEXT: br i1 %cmp.6, label %for.exit2.loopexit, label %latch.6
; PROLOG: latch.6: ; PROLOG: latch.6:
; PROLOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5 ; PROLOG-NEXT: %arrayidx.6 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.5
; PROLOG-NEXT: %load.6 = load i32, ptr %arrayidx.6, align 4 ; PROLOG-NEXT: %load.6 = load i32, ptr %arrayidx.6, align 4
; PROLOG-NEXT: %add.6 = add nsw i32 %load.6, %add.5 ; PROLOG-NEXT: %add.6 = add nsw i32 %load.6, %add.5
; PROLOG-NEXT: %indvars.iv.next.6 = add i64 %indvars.iv.next.5, 1 ; PROLOG-NEXT: %indvars.iv.next.6 = add i64 %indvars.iv, 7
; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.7 ; PROLOG-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.7
; PROLOG: for.exiting_block.7: ; PROLOG: for.exiting_block.7:
; PROLOG-NEXT: %cmp.7 = icmp eq i64 %n, 42 ; PROLOG-NEXT: %cmp.7 = icmp eq i64 %n, 42
; PROLOG-NEXT: br i1 %cmp.7, label %for.exit2.loopexit, label %latch.7 ; PROLOG-NEXT: br i1 %cmp.7, label %for.exit2.loopexit, label %latch.7
; PROLOG: latch.7: ; PROLOG: latch.7:
; PROLOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6 ; PROLOG-NEXT: %arrayidx.7 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next.6
; PROLOG-NEXT: %load.7 = load i32, ptr %arrayidx.7, align 4 ; PROLOG-NEXT: %load.7 = load i32, ptr %arrayidx.7, align 4
; PROLOG-NEXT: %add.7 = add nsw i32 %load.7, %add.6 ; PROLOG-NEXT: %add.7 = add nsw i32 %load.7, %add.6
; PROLOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv.next.6, 1 ; PROLOG-NEXT: %indvars.iv.next.7 = add i64 %indvars.iv, 8
; PROLOG-NEXT: %exitcond.7 = icmp eq i64 %indvars.iv.next.7, %n ; PROLOG-NEXT: %exitcond.7 = icmp eq i64 %indvars.iv.next.7, %n
; PROLOG-NEXT: br i1 %exitcond.7, label %latch_exit.unr-lcssa, label %header ; PROLOG-NEXT: br i1 %exitcond.7, label %latch_exit.unr-lcssa, label %header
; PROLOG: latch_exit.unr-lcssa: ; PROLOG: latch_exit.unr-lcssa:
; PROLOG-NEXT: %sum.0.lcssa.ph = phi i32 [ %add.7, %latch.7 ] ; PROLOG-NEXT: %sum.0.lcssa.ph = phi i32 [ %add.7, %latch.7 ]
; PROLOG-NEXT: br label %latch_exit ; PROLOG-NEXT: br label %latch_exit
; PROLOG: latch_exit: ; PROLOG: latch_exit:
; PROLOG-NEXT: %sum.0.lcssa = phi i32 [ %sum.0.lcssa.unr, %header.prol.loopexit ], [ %sum.0.lcssa.ph, %latch_exit.unr-lcssa ] ; PROLOG-NEXT: %sum.0.lcssa = phi i32 [ %sum.0.lcssa.unr, %header.prol.loopexit ], [ %sum.0.lcssa.ph, %latch_exit.unr-lcssa ]
; PROLOG-NEXT: ret i32 %sum.0.lcssa ; PROLOG-NEXT: ret i32 %sum.0.lcssa
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; PROLOG-BLOCK-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1 ; PROLOG-BLOCK-NEXT: br i1 false, label %for.exit2.loopexit, label %for.exiting_block.1
; PROLOG-BLOCK: for.exiting_block.1: ; PROLOG-BLOCK: for.exiting_block.1:
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42 ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp eq i64 %n, 42
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %for.exit2.loopexit, label %latch.1
; PROLOG-BLOCK: latch.1: ; PROLOG-BLOCK: latch.1:
; PROLOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next ; PROLOG-BLOCK-NEXT: %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
; PROLOG-BLOCK-NEXT: %load.1 = load i32, ptr %arrayidx.1, align 4 ; PROLOG-BLOCK-NEXT: %load.1 = load i32, ptr %arrayidx.1, align 4
; PROLOG-BLOCK-NEXT: %add.1 = add nsw i32 %load.1, %add ; PROLOG-BLOCK-NEXT: %add.1 = add nsw i32 %load.1, %add
; PROLOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv.next, 1 ; PROLOG-BLOCK-NEXT: %indvars.iv.next.1 = add i64 %indvars.iv, 2
; PROLOG-BLOCK-NEXT: %exitcond.1 = icmp eq i64 %indvars.iv.next.1, %n ; PROLOG-BLOCK-NEXT: %exitcond.1 = icmp eq i64 %indvars.iv.next.1, %n
; PROLOG-BLOCK-NEXT: br i1 %exitcond.1, label %latch_exit.unr-lcssa, label %header, !llvm.loop !10 ; PROLOG-BLOCK-NEXT: br i1 %exitcond.1, label %latch_exit.unr-lcssa, label %header, !llvm.loop !10
; PROLOG-BLOCK: latch_exit.unr-lcssa: ; PROLOG-BLOCK: latch_exit.unr-lcssa:
; PROLOG-BLOCK-NEXT: %sum.0.lcssa.ph = phi i32 [ %add.1, %latch.1 ] ; PROLOG-BLOCK-NEXT: %sum.0.lcssa.ph = phi i32 [ %add.1, %latch.1 ]
; PROLOG-BLOCK-NEXT: br label %latch_exit ; PROLOG-BLOCK-NEXT: br label %latch_exit
; PROLOG-BLOCK: latch_exit: ; PROLOG-BLOCK: latch_exit:
; PROLOG-BLOCK-NEXT: %sum.0.lcssa = phi i32 [ %sum.0.lcssa.unr, %header.prol.loopexit ], [ %sum.0.lcssa.ph, %latch_exit.unr-lcssa ] ; PROLOG-BLOCK-NEXT: %sum.0.lcssa = phi i32 [ %sum.0.lcssa.unr, %header.prol.loopexit ], [ %sum.0.lcssa.ph, %latch_exit.unr-lcssa ]
; PROLOG-BLOCK-NEXT: ret i32 %sum.0.lcssa ; PROLOG-BLOCK-NEXT: ret i32 %sum.0.lcssa
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; EPILOG: preheader.new: ; EPILOG: preheader.new:
; EPILOG-NEXT: %unroll_iter = sub i64 %1, %xtraiter ; EPILOG-NEXT: %unroll_iter = sub i64 %1, %xtraiter
; EPILOG-NEXT: br label %header ; EPILOG-NEXT: br label %header
; EPILOG: header: ; EPILOG: header:
; EPILOG-NEXT: %i6 = phi i64 [ 1, %preheader.new ], [ %add.7, %latch.7 ] ; EPILOG-NEXT: %i6 = phi i64 [ 1, %preheader.new ], [ %add.7, %latch.7 ]
; EPILOG-NEXT: %niter = phi i64 [ 0, %preheader.new ], [ %niter.next.7, %latch.7 ] ; EPILOG-NEXT: %niter = phi i64 [ 0, %preheader.new ], [ %niter.next.7, %latch.7 ]
; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch ; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch
; EPILOG: latch: ; EPILOG: latch:
; EPILOG-NEXT: %add = add nuw nsw i64 %i6, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.1 ; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.1
; EPILOG: latch.1: ; EPILOG: latch.1:
; EPILOG-NEXT: %add.1 = add nuw nsw i64 %add, 1
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.2 ; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.2
; EPILOG: latch.2: ; EPILOG: latch.2:
; EPILOG-NEXT: %add.2 = add nuw nsw i64 %add.1, 1
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.3 ; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.3
; EPILOG: latch.3: ; EPILOG: latch.3:
; EPILOG-NEXT: %add.3 = add nuw nsw i64 %add.2, 1
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.4 ; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.4
; EPILOG: latch.4: ; EPILOG: latch.4:
; EPILOG-NEXT: %add.4 = add nuw nsw i64 %add.3, 1
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.5 ; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.5
; EPILOG: latch.5: ; EPILOG: latch.5:
; EPILOG-NEXT: %add.5 = add nuw nsw i64 %add.4, 1
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.6 ; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.6
; EPILOG: latch.6: ; EPILOG: latch.6:
; EPILOG-NEXT: %add.6 = add nuw nsw i64 %add.5, 1
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.7 ; EPILOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.7
; EPILOG: latch.7: ; EPILOG: latch.7:
; EPILOG-NEXT: %add.7 = add nuw nsw i64 %add.6, 1 ; EPILOG-NEXT: %add.7 = add nuw nsw i64 %i6, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %header, label %latchexit.unr-lcssa.loopexit ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %header, label %latchexit.unr-lcssa.loopexit
; EPILOG: latchexit.unr-lcssa.loopexit: ; EPILOG: latchexit.unr-lcssa.loopexit:
; EPILOG-NEXT: %i6.unr.ph = phi i64 [ %add.7, %latch.7 ] ; EPILOG-NEXT: %i6.unr.ph = phi i64 [ %add.7, %latch.7 ]
; EPILOG-NEXT: br label %latchexit.unr-lcssa ; EPILOG-NEXT: br label %latchexit.unr-lcssa
; EPILOG: latchexit.unr-lcssa: ; EPILOG: latchexit.unr-lcssa:
; EPILOG-NEXT: %i6.unr = phi i64 [ 1, %preheader ], [ %i6.unr.ph, %latchexit.unr-lcssa.loopexit ] ; EPILOG-NEXT: %i6.unr = phi i64 [ 1, %preheader ], [ %i6.unr.ph, %latchexit.unr-lcssa.loopexit ]
; EPILOG-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0 ; EPILOG-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; EPILOG-BLOCK: preheader.new: ; EPILOG-BLOCK: preheader.new:
; EPILOG-BLOCK-NEXT: %unroll_iter = sub i64 %1, %xtraiter ; EPILOG-BLOCK-NEXT: %unroll_iter = sub i64 %1, %xtraiter
; EPILOG-BLOCK-NEXT: br label %header ; EPILOG-BLOCK-NEXT: br label %header
; EPILOG-BLOCK: header: ; EPILOG-BLOCK: header:
; EPILOG-BLOCK-NEXT: %i6 = phi i64 [ 1, %preheader.new ], [ %add.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %i6 = phi i64 [ 1, %preheader.new ], [ %add.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %preheader.new ], [ %niter.next.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %preheader.new ], [ %niter.next.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: br i1 false, label %loopexit1.loopexit, label %latch ; EPILOG-BLOCK-NEXT: br i1 false, label %loopexit1.loopexit, label %latch
; EPILOG-BLOCK: latch: ; EPILOG-BLOCK: latch:
; EPILOG-BLOCK-NEXT: %add = add nuw nsw i64 %i6, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.1 ; EPILOG-BLOCK-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.1
; EPILOG-BLOCK: latch.1: ; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %add.1 = add nuw nsw i64 %add, 1 ; EPILOG-BLOCK-NEXT: %add.1 = add nuw nsw i64 %i6, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %header, label %latchexit.unr-lcssa.loopexit, !llvm.loop !11 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %header, label %latchexit.unr-lcssa.loopexit, !llvm.loop !11
; EPILOG-BLOCK: latchexit.unr-lcssa.loopexit: ; EPILOG-BLOCK: latchexit.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: br label %latchexit.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %latchexit.unr-lcssa
; EPILOG-BLOCK: latchexit.unr-lcssa: ; EPILOG-BLOCK: latchexit.unr-lcssa:
; EPILOG-BLOCK-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0 ; EPILOG-BLOCK-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0
; EPILOG-BLOCK-NEXT: br i1 %lcmp.mod, label %header.epil.preheader, label %latchexit ; EPILOG-BLOCK-NEXT: br i1 %lcmp.mod, label %header.epil.preheader, label %latchexit
; EPILOG-BLOCK: header.epil.preheader: ; EPILOG-BLOCK: header.epil.preheader:
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; PROLOG-NEXT: %3 = icmp ult i64 %2, 7 ; PROLOG-NEXT: %3 = icmp ult i64 %2, 7
; PROLOG-NEXT: br i1 %3, label %latchexit, label %preheader.new ; PROLOG-NEXT: br i1 %3, label %latchexit, label %preheader.new
; PROLOG: preheader.new: ; PROLOG: preheader.new:
; PROLOG-NEXT: br label %header ; PROLOG-NEXT: br label %header
; PROLOG: header: ; PROLOG: header:
; PROLOG-NEXT: %i6 = phi i64 [ %i6.unr, %preheader.new ], [ %add.7, %latch.7 ] ; PROLOG-NEXT: %i6 = phi i64 [ %i6.unr, %preheader.new ], [ %add.7, %latch.7 ]
; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch ; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch
; PROLOG: latch: ; PROLOG: latch:
; PROLOG-NEXT: %add = add nuw nsw i64 %i6, 1
; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.1 ; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.1
; PROLOG: latch.1: ; PROLOG: latch.1:
; PROLOG-NEXT: %add.1 = add nuw nsw i64 %add, 1
; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.2 ; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.2
; PROLOG: latch.2: ; PROLOG: latch.2:
; PROLOG-NEXT: %add.2 = add nuw nsw i64 %add.1, 1
; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.3 ; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.3
; PROLOG: latch.3: ; PROLOG: latch.3:
; PROLOG-NEXT: %add.3 = add nuw nsw i64 %add.2, 1
; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.4 ; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.4
; PROLOG: latch.4: ; PROLOG: latch.4:
; PROLOG-NEXT: %add.4 = add nuw nsw i64 %add.3, 1
; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.5 ; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.5
; PROLOG: latch.5: ; PROLOG: latch.5:
; PROLOG-NEXT: %add.5 = add nuw nsw i64 %add.4, 1
; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.6 ; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.6
; PROLOG: latch.6: ; PROLOG: latch.6:
; PROLOG-NEXT: %add.6 = add nuw nsw i64 %add.5, 1
; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.7 ; PROLOG-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.7
; PROLOG: latch.7: ; PROLOG: latch.7:
; PROLOG-NEXT: %add.7 = add nuw nsw i64 %add.6, 1 ; PROLOG-NEXT: %add.7 = add nuw nsw i64 %i6, 8
; PROLOG-NEXT: %i9.7 = icmp slt i64 %add.7, %sext ; PROLOG-NEXT: %i9.7 = icmp slt i64 %add.7, %sext
; PROLOG-NEXT: br i1 %i9.7, label %header, label %latchexit.unr-lcssa ; PROLOG-NEXT: br i1 %i9.7, label %header, label %latchexit.unr-lcssa
; PROLOG: latchexit.unr-lcssa: ; PROLOG: latchexit.unr-lcssa:
; PROLOG-NEXT: br label %latchexit ; PROLOG-NEXT: br label %latchexit
; PROLOG: latchexit: ; PROLOG: latchexit:
; PROLOG-NEXT: unreachable ; PROLOG-NEXT: unreachable
; PROLOG: loopexit2: ; PROLOG: loopexit2:
; PROLOG-NEXT: ret i32 %shft ; PROLOG-NEXT: ret i32 %shft
Show All 31 Lines
; PROLOG-BLOCK-NEXT: %3 = icmp ult i64 %2, 1 ; PROLOG-BLOCK-NEXT: %3 = icmp ult i64 %2, 1
; PROLOG-BLOCK-NEXT: br i1 %3, label %latchexit, label %preheader.new ; PROLOG-BLOCK-NEXT: br i1 %3, label %latchexit, label %preheader.new
; PROLOG-BLOCK: preheader.new: ; PROLOG-BLOCK: preheader.new:
; PROLOG-BLOCK-NEXT: br label %header ; PROLOG-BLOCK-NEXT: br label %header
; PROLOG-BLOCK: header: ; PROLOG-BLOCK: header:
; PROLOG-BLOCK-NEXT: %i6 = phi i64 [ %i6.unr, %preheader.new ], [ %add.1, %latch.1 ] ; PROLOG-BLOCK-NEXT: %i6 = phi i64 [ %i6.unr, %preheader.new ], [ %add.1, %latch.1 ]
; PROLOG-BLOCK-NEXT: br i1 false, label %loopexit1.loopexit, label %latch ; PROLOG-BLOCK-NEXT: br i1 false, label %loopexit1.loopexit, label %latch
; PROLOG-BLOCK: latch: ; PROLOG-BLOCK: latch:
; PROLOG-BLOCK-NEXT: %add = add nuw nsw i64 %i6, 1
; PROLOG-BLOCK-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.1 ; PROLOG-BLOCK-NEXT: br i1 false, label %loopexit1.loopexit, label %latch.1
; PROLOG-BLOCK: latch.1: ; PROLOG-BLOCK: latch.1:
; PROLOG-BLOCK-NEXT: %add.1 = add nuw nsw i64 %add, 1 ; PROLOG-BLOCK-NEXT: %add.1 = add nuw nsw i64 %i6, 2
; PROLOG-BLOCK-NEXT: %i9.1 = icmp slt i64 %add.1, %sext ; PROLOG-BLOCK-NEXT: %i9.1 = icmp slt i64 %add.1, %sext
; PROLOG-BLOCK-NEXT: br i1 %i9.1, label %header, label %latchexit.unr-lcssa, !llvm.loop !11 ; PROLOG-BLOCK-NEXT: br i1 %i9.1, label %header, label %latchexit.unr-lcssa, !llvm.loop !11
; PROLOG-BLOCK: latchexit.unr-lcssa: ; PROLOG-BLOCK: latchexit.unr-lcssa:
; PROLOG-BLOCK-NEXT: br label %latchexit ; PROLOG-BLOCK-NEXT: br label %latchexit
; PROLOG-BLOCK: latchexit: ; PROLOG-BLOCK: latchexit:
; PROLOG-BLOCK-NEXT: unreachable ; PROLOG-BLOCK-NEXT: unreachable
; PROLOG-BLOCK: loopexit2: ; PROLOG-BLOCK: loopexit2:
; PROLOG-BLOCK-NEXT: ret i32 %shft ; PROLOG-BLOCK-NEXT: ret i32 %shft
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; EPILOG-NEXT: %2 = icmp ult i64 %1, 7 ; EPILOG-NEXT: %2 = icmp ult i64 %1, 7
; EPILOG-NEXT: br i1 %2, label %exit.unr-lcssa, label %outerloop.new ; EPILOG-NEXT: br i1 %2, label %exit.unr-lcssa, label %outerloop.new
; EPILOG: outerloop.new: ; EPILOG: outerloop.new:
; EPILOG-NEXT: %unroll_iter = sub i64 %0, %xtraiter ; EPILOG-NEXT: %unroll_iter = sub i64 %0, %xtraiter
; EPILOG-NEXT: br label %innerH ; EPILOG-NEXT: br label %innerH
; EPILOG: innerH: ; EPILOG: innerH:
; EPILOG-NEXT: %i3 = phi i64 [ %i, %outerloop.new ], [ %i4.7, %latch.7 ] ; EPILOG-NEXT: %i3 = phi i64 [ %i, %outerloop.new ], [ %i4.7, %latch.7 ]
; EPILOG-NEXT: %niter = phi i64 [ 0, %outerloop.new ], [ %niter.next.7, %latch.7 ] ; EPILOG-NEXT: %niter = phi i64 [ 0, %outerloop.new ], [ %niter.next.7, %latch.7 ]
; EPILOG-NEXT: %i4 = add nuw nsw i64 %i3, 1
; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch ; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch
; EPILOG: latch: ; EPILOG: latch:
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: %i4.1 = add nuw nsw i64 %i4, 1
; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.1 ; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.1
; EPILOG: latch.1: ; EPILOG: latch.1:
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: %i4.2 = add nuw nsw i64 %i4.1, 1
; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.2 ; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.2
; EPILOG: latch.2: ; EPILOG: latch.2:
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: %i4.3 = add nuw nsw i64 %i4.2, 1
; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.3 ; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.3
; EPILOG: latch.3: ; EPILOG: latch.3:
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: %i4.4 = add nuw nsw i64 %i4.3, 1
; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.4 ; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.4
; EPILOG: latch.4: ; EPILOG: latch.4:
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: %i4.5 = add nuw nsw i64 %i4.4, 1
; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.5 ; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.5
; EPILOG: latch.5: ; EPILOG: latch.5:
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: %i4.6 = add nuw nsw i64 %i4.5, 1
; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.6 ; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.6
; EPILOG: latch.6: ; EPILOG: latch.6:
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1 ; EPILOG-NEXT: %i4.7 = add nuw nsw i64 %i3, 8
; EPILOG-NEXT: %i4.7 = add nuw nsw i64 %i4.6, 1
; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.7 ; EPILOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.7
; EPILOG: latch.7: ; EPILOG: latch.7:
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %innerH, label %exit.unr-lcssa.loopexit ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %innerH, label %exit.unr-lcssa.loopexit
; EPILOG: exit.unr-lcssa.loopexit: ; EPILOG: exit.unr-lcssa.loopexit:
; EPILOG-NEXT: %i3.unr.ph = phi i64 [ %i4.7, %latch.7 ] ; EPILOG-NEXT: %i3.unr.ph = phi i64 [ %i4.7, %latch.7 ]
; EPILOG-NEXT: br label %exit.unr-lcssa ; EPILOG-NEXT: br label %exit.unr-lcssa
; EPILOG: exit.unr-lcssa: ; EPILOG: exit.unr-lcssa:
; EPILOG-NEXT: %i3.unr = phi i64 [ %i, %outerloop ], [ %i3.unr.ph, %exit.unr-lcssa.loopexit ] ; EPILOG-NEXT: %i3.unr = phi i64 [ %i, %outerloop ], [ %i3.unr.ph, %exit.unr-lcssa.loopexit ]
; EPILOG-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0 ; EPILOG-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0
Show All 24 Lines
; EPILOG-BLOCK-NEXT: br label %outerloop.loopexit ; EPILOG-BLOCK-NEXT: br label %outerloop.loopexit
; EPILOG-BLOCK: outerloop.loopexit: ; EPILOG-BLOCK: outerloop.loopexit:
; EPILOG-BLOCK-NEXT: br i1 false, label %exit.unr-lcssa.1, label %outerloop.new.1 ; EPILOG-BLOCK-NEXT: br i1 false, label %exit.unr-lcssa.1, label %outerloop.new.1
; EPILOG-BLOCK: outerloop.new.1: ; EPILOG-BLOCK: outerloop.new.1:
; EPILOG-BLOCK-NEXT: br label %innerH.1 ; EPILOG-BLOCK-NEXT: br label %innerH.1
; EPILOG-BLOCK: innerH.1: ; EPILOG-BLOCK: innerH.1:
; EPILOG-BLOCK-NEXT: %i3.1 = phi i64 [ 0, %outerloop.new.1 ], [ %i4.1.1, %latch.1.1 ] ; EPILOG-BLOCK-NEXT: %i3.1 = phi i64 [ 0, %outerloop.new.1 ], [ %i4.1.1, %latch.1.1 ]
; EPILOG-BLOCK-NEXT: %niter.1 = phi i64 [ 0, %outerloop.new.1 ], [ %niter.next.1.1, %latch.1.1 ] ; EPILOG-BLOCK-NEXT: %niter.1 = phi i64 [ 0, %outerloop.new.1 ], [ %niter.next.1.1, %latch.1.1 ]
; EPILOG-BLOCK-NEXT: %i4.12 = add nuw nsw i64 %i3.1, 1 ; EPILOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit.1, label %latch.12
; EPILOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit.1, label %latch.14 ; EPILOG-BLOCK: latch.12:
; EPILOG-BLOCK: latch.14: ; EPILOG-BLOCK-NEXT: %i4.1.1 = add nuw nsw i64 %i3.1, 2
; EPILOG-BLOCK-NEXT: %niter.next.13 = add nuw nsw i64 %niter.1, 1
; EPILOG-BLOCK-NEXT: %i4.1.1 = add nuw nsw i64 %i4.12, 1
; EPILOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit.1, label %latch.1.1 ; EPILOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit.1, label %latch.1.1
; EPILOG-BLOCK: latch.1.1: ; EPILOG-BLOCK: latch.1.1:
; EPILOG-BLOCK-NEXT: %niter.next.1.1 = add i64 %niter.next.13, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1.1 = add i64 %niter.1, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1.1 = icmp ne i64 %niter.next.1.1, 100 ; EPILOG-BLOCK-NEXT: %niter.ncmp.1.1 = icmp ne i64 %niter.next.1.1, 100
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1.1, label %innerH.1, label %exit.unr-lcssa.loopexit.1, !llvm.loop !12 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1.1, label %innerH.1, label %exit.unr-lcssa.loopexit.1, !llvm.loop !12
; EPILOG-BLOCK: exit.unr-lcssa.loopexit.1: ; EPILOG-BLOCK: exit.unr-lcssa.loopexit.1:
; EPILOG-BLOCK-NEXT: br label %exit.unr-lcssa.1 ; EPILOG-BLOCK-NEXT: br label %exit.unr-lcssa.1
; EPILOG-BLOCK: outerloop.loopexit.loopexit.1: ; EPILOG-BLOCK: outerloop.loopexit.loopexit.1:
; EPILOG-BLOCK-NEXT: br label %outerloop.loopexit.1 ; EPILOG-BLOCK-NEXT: br label %outerloop.loopexit.1
; EPILOG-BLOCK: exit.unr-lcssa.1: ; EPILOG-BLOCK: exit.unr-lcssa.1:
; EPILOG-BLOCK-NEXT: br i1 false, label %innerH.epil.preheader.1, label %exit.loopexit ; EPILOG-BLOCK-NEXT: br i1 false, label %innerH.epil.preheader.1, label %exit.loopexit
Show All 11 Lines
; EPILOG-BLOCK-NEXT: %2 = icmp ult i64 %1, 1 ; EPILOG-BLOCK-NEXT: %2 = icmp ult i64 %1, 1
; EPILOG-BLOCK-NEXT: br i1 %2, label %exit.unr-lcssa, label %outerloop.new ; EPILOG-BLOCK-NEXT: br i1 %2, label %exit.unr-lcssa, label %outerloop.new
; EPILOG-BLOCK: outerloop.new: ; EPILOG-BLOCK: outerloop.new:
; EPILOG-BLOCK-NEXT: %unroll_iter = sub i64 %0, %xtraiter ; EPILOG-BLOCK-NEXT: %unroll_iter = sub i64 %0, %xtraiter
; EPILOG-BLOCK-NEXT: br label %innerH ; EPILOG-BLOCK-NEXT: br label %innerH
; EPILOG-BLOCK: innerH: ; EPILOG-BLOCK: innerH:
; EPILOG-BLOCK-NEXT: %i3 = phi i64 [ %i, %outerloop.new ], [ %i4.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %i3 = phi i64 [ %i, %outerloop.new ], [ %i4.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %outerloop.new ], [ %niter.next.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %outerloop.new ], [ %niter.next.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %i4 = add nuw nsw i64 %i3, 1
; EPILOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch ; EPILOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch
; EPILOG-BLOCK: latch: ; EPILOG-BLOCK: latch:
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1 ; EPILOG-BLOCK-NEXT: %i4.1 = add nuw nsw i64 %i3, 2
; EPILOG-BLOCK-NEXT: %i4.1 = add nuw nsw i64 %i4, 1
; EPILOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.1 ; EPILOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.1
; EPILOG-BLOCK: latch.1: ; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %innerH, label %exit.unr-lcssa.loopexit, !llvm.loop !12 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %innerH, label %exit.unr-lcssa.loopexit, !llvm.loop !12
; EPILOG-BLOCK: exit.unr-lcssa.loopexit: ; EPILOG-BLOCK: exit.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: br label %exit.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %exit.unr-lcssa
; EPILOG-BLOCK: exit.unr-lcssa: ; EPILOG-BLOCK: exit.unr-lcssa:
; EPILOG-BLOCK-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0 ; EPILOG-BLOCK-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0
; EPILOG-BLOCK-NEXT: br i1 %lcmp.mod, label %innerH.epil.preheader, label %exit.loopexit ; EPILOG-BLOCK-NEXT: br i1 %lcmp.mod, label %innerH.epil.preheader, label %exit.loopexit
; EPILOG-BLOCK: innerH.epil.preheader: ; EPILOG-BLOCK: innerH.epil.preheader:
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; PROLOG: innerH.prol.loopexit: ; PROLOG: innerH.prol.loopexit:
; PROLOG-NEXT: %i3.unr = phi i64 [ %i, %outerloop ], [ %i3.unr.ph, %innerH.prol.loopexit.unr-lcssa ] ; PROLOG-NEXT: %i3.unr = phi i64 [ %i, %outerloop ], [ %i3.unr.ph, %innerH.prol.loopexit.unr-lcssa ]
; PROLOG-NEXT: %2 = icmp ult i64 %1, 7 ; PROLOG-NEXT: %2 = icmp ult i64 %1, 7
; PROLOG-NEXT: br i1 %2, label %exit.loopexit, label %outerloop.new ; PROLOG-NEXT: br i1 %2, label %exit.loopexit, label %outerloop.new
; PROLOG: outerloop.new: ; PROLOG: outerloop.new:
; PROLOG-NEXT: br label %innerH ; PROLOG-NEXT: br label %innerH
; PROLOG: innerH: ; PROLOG: innerH:
; PROLOG-NEXT: %i3 = phi i64 [ %i3.unr, %outerloop.new ], [ %i4.7, %latch.7 ] ; PROLOG-NEXT: %i3 = phi i64 [ %i3.unr, %outerloop.new ], [ %i4.7, %latch.7 ]
; PROLOG-NEXT: %i4 = add nuw nsw i64 %i3, 1
; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch ; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch
; PROLOG: latch: ; PROLOG: latch:
; PROLOG-NEXT: %i4.1 = add nuw nsw i64 %i4, 1
; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.1 ; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.1
; PROLOG: latch.1: ; PROLOG: latch.1:
; PROLOG-NEXT: %i4.2 = add nuw nsw i64 %i4.1, 1
; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.2 ; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.2
; PROLOG: latch.2: ; PROLOG: latch.2:
; PROLOG-NEXT: %i4.3 = add nuw nsw i64 %i4.2, 1
; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.3 ; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.3
; PROLOG: latch.3: ; PROLOG: latch.3:
; PROLOG-NEXT: %i4.4 = add nuw nsw i64 %i4.3, 1
; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.4 ; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.4
; PROLOG: latch.4: ; PROLOG: latch.4:
; PROLOG-NEXT: %i4.5 = add nuw nsw i64 %i4.4, 1
; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.5 ; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.5
; PROLOG: latch.5: ; PROLOG: latch.5:
; PROLOG-NEXT: %i4.6 = add nuw nsw i64 %i4.5, 1
; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.6 ; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.6
; PROLOG: latch.6: ; PROLOG: latch.6:
; PROLOG-NEXT: %i4.7 = add nuw nsw i64 %i4.6, 1 ; PROLOG-NEXT: %i4.7 = add nuw nsw i64 %i3, 8
; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.7 ; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.7
; PROLOG: latch.7: ; PROLOG: latch.7:
; PROLOG-NEXT: %i6.7 = icmp ult i64 %i4.7, 100 ; PROLOG-NEXT: %i6.7 = icmp ult i64 %i4.7, 100
; PROLOG-NEXT: br i1 %i6.7, label %innerH, label %exit.unr-lcssa ; PROLOG-NEXT: br i1 %i6.7, label %innerH, label %exit.unr-lcssa
; PROLOG: exit.unr-lcssa: ; PROLOG: exit.unr-lcssa:
; PROLOG-NEXT: br label %exit ; PROLOG-NEXT: br label %exit
; PROLOG: exit.loopexit: ; PROLOG: exit.loopexit:
; PROLOG-NEXT: br label %exit ; PROLOG-NEXT: br label %exit
Show All 15 Lines
; PROLOG-BLOCK-NEXT: br label %innerH.prol.loopexit.1 ; PROLOG-BLOCK-NEXT: br label %innerH.prol.loopexit.1
; PROLOG-BLOCK: innerH.prol.loopexit.1: ; PROLOG-BLOCK: innerH.prol.loopexit.1:
; PROLOG-BLOCK-NEXT: %i3.unr.1 = phi i64 [ 0, %outerloop.loopexit ], [ 1, %latch.prol.1 ] ; PROLOG-BLOCK-NEXT: %i3.unr.1 = phi i64 [ 0, %outerloop.loopexit ], [ 1, %latch.prol.1 ]
; PROLOG-BLOCK-NEXT: br i1 false, label %exit.loopexit, label %outerloop.new.1 ; PROLOG-BLOCK-NEXT: br i1 false, label %exit.loopexit, label %outerloop.new.1
; PROLOG-BLOCK: outerloop.new.1: ; PROLOG-BLOCK: outerloop.new.1:
; PROLOG-BLOCK-NEXT: br label %innerH.1 ; PROLOG-BLOCK-NEXT: br label %innerH.1
; PROLOG-BLOCK: innerH.1: ; PROLOG-BLOCK: innerH.1:
; PROLOG-BLOCK-NEXT: %i3.1 = phi i64 [ %i3.unr.1, %outerloop.new.1 ], [ %i4.1.1, %latch.1.1 ] ; PROLOG-BLOCK-NEXT: %i3.1 = phi i64 [ %i3.unr.1, %outerloop.new.1 ], [ %i4.1.1, %latch.1.1 ]
; PROLOG-BLOCK-NEXT: %i4.11 = add nuw nsw i64 %i3.1, 1 ; PROLOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit.1, label %latch.11
; PROLOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit.1, label %latch.12 ; PROLOG-BLOCK: latch.11:
; PROLOG-BLOCK: latch.12: ; PROLOG-BLOCK-NEXT: %i4.1.1 = add nuw nsw i64 %i3.1, 2
; PROLOG-BLOCK-NEXT: %i4.1.1 = add nuw nsw i64 %i4.11, 1
; PROLOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit.1, label %latch.1.1 ; PROLOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit.1, label %latch.1.1
; PROLOG-BLOCK: latch.1.1: ; PROLOG-BLOCK: latch.1.1:
; PROLOG-BLOCK-NEXT: %i6.1.1 = icmp ult i64 %i4.1.1, 100 ; PROLOG-BLOCK-NEXT: %i6.1.1 = icmp ult i64 %i4.1.1, 100
; PROLOG-BLOCK-NEXT: br i1 %i6.1.1, label %innerH.1, label %exit.unr-lcssa.loopexit3, !llvm.loop !12 ; PROLOG-BLOCK-NEXT: br i1 %i6.1.1, label %innerH.1, label %exit.unr-lcssa.loopexit2, !llvm.loop !12
; PROLOG-BLOCK: outerloop.loopexit.loopexit.1: ; PROLOG-BLOCK: outerloop.loopexit.loopexit.1:
; PROLOG-BLOCK-NEXT: br label %outerloop.loopexit.1 ; PROLOG-BLOCK-NEXT: br label %outerloop.loopexit.1
; PROLOG-BLOCK: outerloop.loopexit.1: ; PROLOG-BLOCK: outerloop.loopexit.1:
; PROLOG-BLOCK-NEXT: br label %outerloop, !llvm.loop !13 ; PROLOG-BLOCK-NEXT: br label %outerloop, !llvm.loop !13
; PROLOG-BLOCK: outerloop: ; PROLOG-BLOCK: outerloop:
; PROLOG-BLOCK-NEXT: %i = phi i64 [ 3, %bb ], [ 0, %outerloop.loopexit.1 ] ; PROLOG-BLOCK-NEXT: %i = phi i64 [ 3, %bb ], [ 0, %outerloop.loopexit.1 ]
; PROLOG-BLOCK-NEXT: %0 = sub i64 100, %i ; PROLOG-BLOCK-NEXT: %0 = sub i64 100, %i
; PROLOG-BLOCK-NEXT: %1 = sub i64 99, %i ; PROLOG-BLOCK-NEXT: %1 = sub i64 99, %i
Show All 10 Lines
; PROLOG-BLOCK: innerH.prol.loopexit: ; PROLOG-BLOCK: innerH.prol.loopexit:
; PROLOG-BLOCK-NEXT: %i3.unr = phi i64 [ %i, %outerloop ], [ %i4.prol, %latch.prol ] ; PROLOG-BLOCK-NEXT: %i3.unr = phi i64 [ %i, %outerloop ], [ %i4.prol, %latch.prol ]
; PROLOG-BLOCK-NEXT: %2 = icmp ult i64 %1, 1 ; PROLOG-BLOCK-NEXT: %2 = icmp ult i64 %1, 1
; PROLOG-BLOCK-NEXT: br i1 %2, label %exit.loopexit, label %outerloop.new ; PROLOG-BLOCK-NEXT: br i1 %2, label %exit.loopexit, label %outerloop.new
; PROLOG-BLOCK: outerloop.new: ; PROLOG-BLOCK: outerloop.new:
; PROLOG-BLOCK-NEXT: br label %innerH ; PROLOG-BLOCK-NEXT: br label %innerH
; PROLOG-BLOCK: innerH: ; PROLOG-BLOCK: innerH:
; PROLOG-BLOCK-NEXT: %i3 = phi i64 [ %i3.unr, %outerloop.new ], [ %i4.1, %latch.1 ] ; PROLOG-BLOCK-NEXT: %i3 = phi i64 [ %i3.unr, %outerloop.new ], [ %i4.1, %latch.1 ]
; PROLOG-BLOCK-NEXT: %i4 = add nuw nsw i64 %i3, 1
; PROLOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch ; PROLOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch
; PROLOG-BLOCK: latch: ; PROLOG-BLOCK: latch:
; PROLOG-BLOCK-NEXT: %i4.1 = add nuw nsw i64 %i4, 1 ; PROLOG-BLOCK-NEXT: %i4.1 = add nuw nsw i64 %i3, 2
; PROLOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.1 ; PROLOG-BLOCK-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.1
; PROLOG-BLOCK: latch.1: ; PROLOG-BLOCK: latch.1:
; PROLOG-BLOCK-NEXT: %i6.1 = icmp ult i64 %i4.1, 100 ; PROLOG-BLOCK-NEXT: %i6.1 = icmp ult i64 %i4.1, 100
; PROLOG-BLOCK-NEXT: br i1 %i6.1, label %innerH, label %exit.unr-lcssa.loopexit, !llvm.loop !12 ; PROLOG-BLOCK-NEXT: br i1 %i6.1, label %innerH, label %exit.unr-lcssa.loopexit, !llvm.loop !12
; PROLOG-BLOCK: exit.unr-lcssa.loopexit: ; PROLOG-BLOCK: exit.unr-lcssa.loopexit:
; PROLOG-BLOCK-NEXT: br label %exit.unr-lcssa ; PROLOG-BLOCK-NEXT: br label %exit.unr-lcssa
; PROLOG-BLOCK: exit.unr-lcssa.loopexit3: ; PROLOG-BLOCK: exit.unr-lcssa.loopexit2:
; PROLOG-BLOCK-NEXT: br label %exit.unr-lcssa ; PROLOG-BLOCK-NEXT: br label %exit.unr-lcssa
; PROLOG-BLOCK: exit.unr-lcssa: ; PROLOG-BLOCK: exit.unr-lcssa:
; PROLOG-BLOCK-NEXT: br label %exit ; PROLOG-BLOCK-NEXT: br label %exit
; PROLOG-BLOCK: exit.loopexit: ; PROLOG-BLOCK: exit.loopexit:
; PROLOG-BLOCK-NEXT: br label %exit ; PROLOG-BLOCK-NEXT: br label %exit
; PROLOG-BLOCK: exit: ; PROLOG-BLOCK: exit:
; PROLOG-BLOCK-NEXT: ret void ; PROLOG-BLOCK-NEXT: ret void
; ;
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; EPILOG: innerexit.loopexit1: ; EPILOG: innerexit.loopexit1:
; EPILOG-NEXT: %trip.lcssa.ph2 = phi i32 [ %trip, %header.epil ] ; EPILOG-NEXT: %trip.lcssa.ph2 = phi i32 [ %trip, %header.epil ]
; EPILOG-NEXT: br label %innerexit ; EPILOG-NEXT: br label %innerexit
; EPILOG: innerexit: ; EPILOG: innerexit:
; EPILOG-NEXT: %trip.lcssa = phi i32 [ %trip.lcssa.ph, %innerexit.loopexit ], [ %trip.lcssa.ph2, %innerexit.loopexit1 ] ; EPILOG-NEXT: %trip.lcssa = phi i32 [ %trip.lcssa.ph, %innerexit.loopexit ], [ %trip.lcssa.ph2, %innerexit.loopexit1 ]
; EPILOG-NEXT: %i9 = call ptr addrspace(1) @foo(i32 %trip.lcssa) ; EPILOG-NEXT: %i9 = call ptr addrspace(1) @foo(i32 %trip.lcssa)
; EPILOG-NEXT: ret ptr addrspace(1) %i9 ; EPILOG-NEXT: ret ptr addrspace(1) %i9
; EPILOG: latch: ; EPILOG: latch:
; EPILOG-NEXT: %iv.next = add nuw nsw i64 %phi, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i32 %niter, 1
; EPILOG-NEXT: br i1 true, label %latch.1, label %innerexit.loopexit ; EPILOG-NEXT: br i1 true, label %latch.1, label %innerexit.loopexit
; EPILOG: latch.1: ; EPILOG: latch.1:
; EPILOG-NEXT: %iv.next.1 = add nuw nsw i64 %iv.next, 1
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i32 %niter.next, 1
; EPILOG-NEXT: br i1 true, label %latch.2, label %innerexit.loopexit ; EPILOG-NEXT: br i1 true, label %latch.2, label %innerexit.loopexit
; EPILOG: latch.2: ; EPILOG: latch.2:
; EPILOG-NEXT: %iv.next.2 = add nuw nsw i64 %iv.next.1, 1
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i32 %niter.next.1, 1
; EPILOG-NEXT: br i1 true, label %latch.3, label %innerexit.loopexit ; EPILOG-NEXT: br i1 true, label %latch.3, label %innerexit.loopexit
; EPILOG: latch.3: ; EPILOG: latch.3:
; EPILOG-NEXT: %iv.next.3 = add nuw nsw i64 %iv.next.2, 1
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i32 %niter.next.2, 1
; EPILOG-NEXT: br i1 true, label %latch.4, label %innerexit.loopexit ; EPILOG-NEXT: br i1 true, label %latch.4, label %innerexit.loopexit
; EPILOG: latch.4: ; EPILOG: latch.4:
; EPILOG-NEXT: %iv.next.4 = add nuw nsw i64 %iv.next.3, 1
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i32 %niter.next.3, 1
; EPILOG-NEXT: br i1 true, label %latch.5, label %innerexit.loopexit ; EPILOG-NEXT: br i1 true, label %latch.5, label %innerexit.loopexit
; EPILOG: latch.5: ; EPILOG: latch.5:
; EPILOG-NEXT: %iv.next.5 = add nuw nsw i64 %iv.next.4, 1
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i32 %niter.next.4, 1
; EPILOG-NEXT: br i1 true, label %latch.6, label %innerexit.loopexit ; EPILOG-NEXT: br i1 true, label %latch.6, label %innerexit.loopexit
; EPILOG: latch.6: ; EPILOG: latch.6:
; EPILOG-NEXT: %iv.next.6 = add nuw nsw i64 %iv.next.5, 1
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i32 %niter.next.5, 1
; EPILOG-NEXT: br i1 true, label %latch.7, label %innerexit.loopexit ; EPILOG-NEXT: br i1 true, label %latch.7, label %innerexit.loopexit
; EPILOG: latch.7: ; EPILOG: latch.7:
; EPILOG-NEXT: %iv.next.7 = add nuw nsw i64 %iv.next.6, 1 ; EPILOG-NEXT: %iv.next.7 = add nuw nsw i64 %phi, 8
; EPILOG-NEXT: %niter.next.7 = add i32 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i32 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i32 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i32 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %header, label %outerLatch.loopexit.unr-lcssa.loopexit ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %header, label %outerLatch.loopexit.unr-lcssa.loopexit
; EPILOG: outerLatch.loopexit.unr-lcssa.loopexit: ; EPILOG: outerLatch.loopexit.unr-lcssa.loopexit:
; EPILOG-NEXT: %phi.unr.ph = phi i64 [ %iv.next.7, %latch.7 ] ; EPILOG-NEXT: %phi.unr.ph = phi i64 [ %iv.next.7, %latch.7 ]
; EPILOG-NEXT: br label %outerLatch.loopexit.unr-lcssa ; EPILOG-NEXT: br label %outerLatch.loopexit.unr-lcssa
; EPILOG: outerLatch.loopexit.unr-lcssa: ; EPILOG: outerLatch.loopexit.unr-lcssa:
; EPILOG-NEXT: %phi.unr = phi i64 [ %i4, %preheader ], [ %phi.unr.ph, %outerLatch.loopexit.unr-lcssa.loopexit ] ; EPILOG-NEXT: %phi.unr = phi i64 [ %i4, %preheader ], [ %phi.unr.ph, %outerLatch.loopexit.unr-lcssa.loopexit ]
; EPILOG-NEXT: %lcmp.mod = icmp ne i32 %xtraiter, 0 ; EPILOG-NEXT: %lcmp.mod = icmp ne i32 %xtraiter, 0
Show All 38 Lines
; EPILOG-BLOCK-NEXT: br label %header ; EPILOG-BLOCK-NEXT: br label %header
; EPILOG-BLOCK: header: ; EPILOG-BLOCK: header:
; EPILOG-BLOCK-NEXT: %phi = phi i64 [ 0, %preheader.new ], [ %iv.next.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %phi = phi i64 [ 0, %preheader.new ], [ %iv.next.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: %niter = phi i32 [ 0, %preheader.new ], [ %niter.next.1, %latch.1 ] ; EPILOG-BLOCK-NEXT: %niter = phi i32 [ 0, %preheader.new ], [ %niter.next.1, %latch.1 ]
; EPILOG-BLOCK-NEXT: br i1 true, label %latch, label %innerexit.loopexit.loopexit ; EPILOG-BLOCK-NEXT: br i1 true, label %latch, label %innerexit.loopexit.loopexit
; EPILOG-BLOCK: innerexit.loopexit.loopexit: ; EPILOG-BLOCK: innerexit.loopexit.loopexit:
; EPILOG-BLOCK-NEXT: %trip.lcssa.ph.ph = phi i32 [ %trip, %latch ], [ %trip, %header ] ; EPILOG-BLOCK-NEXT: %trip.lcssa.ph.ph = phi i32 [ %trip, %latch ], [ %trip, %header ]
; EPILOG-BLOCK-NEXT: br label %innerexit.loopexit ; EPILOG-BLOCK-NEXT: br label %innerexit.loopexit
; EPILOG-BLOCK: innerexit.loopexit.loopexit6: ; EPILOG-BLOCK: innerexit.loopexit.loopexit4:
; EPILOG-BLOCK-NEXT: %trip.lcssa.ph.ph7 = phi i32 [ %trip.1, %latch.15 ], [ %trip.1, %header.1 ] ; EPILOG-BLOCK-NEXT: %trip.lcssa.ph.ph5 = phi i32 [ %trip.1, %latch.13 ], [ %trip.1, %header.1 ]
; EPILOG-BLOCK-NEXT: br label %innerexit.loopexit ; EPILOG-BLOCK-NEXT: br label %innerexit.loopexit
; EPILOG-BLOCK: innerexit.loopexit: ; EPILOG-BLOCK: innerexit.loopexit:
; EPILOG-BLOCK-NEXT: %trip.lcssa.ph = phi i32 [ %trip.lcssa.ph.ph, %innerexit.loopexit.loopexit ], [ %trip.lcssa.ph.ph7, %innerexit.loopexit.loopexit6 ] ; EPILOG-BLOCK-NEXT: %trip.lcssa.ph = phi i32 [ %trip.lcssa.ph.ph, %innerexit.loopexit.loopexit ], [ %trip.lcssa.ph.ph5, %innerexit.loopexit.loopexit4 ]
; EPILOG-BLOCK-NEXT: br label %innerexit ; EPILOG-BLOCK-NEXT: br label %innerexit
; EPILOG-BLOCK: innerexit.loopexit1: ; EPILOG-BLOCK: innerexit.loopexit1:
; EPILOG-BLOCK-NEXT: %trip.lcssa.ph2 = phi i32 [ %trip, %header.epil ], [ %trip.1, %header.epil.1 ] ; EPILOG-BLOCK-NEXT: %trip.lcssa.ph2 = phi i32 [ %trip, %header.epil ], [ %trip.1, %header.epil.1 ]
; EPILOG-BLOCK-NEXT: br label %innerexit ; EPILOG-BLOCK-NEXT: br label %innerexit
; EPILOG-BLOCK: innerexit: ; EPILOG-BLOCK: innerexit:
; EPILOG-BLOCK-NEXT: %trip.lcssa = phi i32 [ %trip.lcssa.ph, %innerexit.loopexit ], [ %trip.lcssa.ph2, %innerexit.loopexit1 ] ; EPILOG-BLOCK-NEXT: %trip.lcssa = phi i32 [ %trip.lcssa.ph, %innerexit.loopexit ], [ %trip.lcssa.ph2, %innerexit.loopexit1 ]
; EPILOG-BLOCK-NEXT: %i9 = call ptr addrspace(1) @foo(i32 %trip.lcssa) ; EPILOG-BLOCK-NEXT: %i9 = call ptr addrspace(1) @foo(i32 %trip.lcssa)
; EPILOG-BLOCK-NEXT: ret ptr addrspace(1) %i9 ; EPILOG-BLOCK-NEXT: ret ptr addrspace(1) %i9
; EPILOG-BLOCK: latch: ; EPILOG-BLOCK: latch:
; EPILOG-BLOCK-NEXT: %iv.next = add nuw nsw i64 %phi, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i32 %niter, 1
; EPILOG-BLOCK-NEXT: br i1 true, label %latch.1, label %innerexit.loopexit.loopexit ; EPILOG-BLOCK-NEXT: br i1 true, label %latch.1, label %innerexit.loopexit.loopexit
; EPILOG-BLOCK: latch.1: ; EPILOG-BLOCK: latch.1:
; EPILOG-BLOCK-NEXT: %iv.next.1 = add nuw nsw i64 %iv.next, 1 ; EPILOG-BLOCK-NEXT: %iv.next.1 = add nuw nsw i64 %phi, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i32 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i32 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i32 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i32 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %header, label %outerLatch.loopexit.unr-lcssa.loopexit, !llvm.loop !14 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %header, label %outerLatch.loopexit.unr-lcssa.loopexit, !llvm.loop !14
; EPILOG-BLOCK: outerLatch.loopexit.unr-lcssa.loopexit: ; EPILOG-BLOCK: outerLatch.loopexit.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: br label %outerLatch.loopexit.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %outerLatch.loopexit.unr-lcssa
; EPILOG-BLOCK: outerLatch.loopexit.unr-lcssa: ; EPILOG-BLOCK: outerLatch.loopexit.unr-lcssa:
; EPILOG-BLOCK-NEXT: %lcmp.mod = icmp ne i32 %xtraiter, 0 ; EPILOG-BLOCK-NEXT: %lcmp.mod = icmp ne i32 %xtraiter, 0
; EPILOG-BLOCK-NEXT: br i1 %lcmp.mod, label %header.epil.preheader, label %outerLatch.loopexit ; EPILOG-BLOCK-NEXT: br i1 %lcmp.mod, label %header.epil.preheader, label %outerLatch.loopexit
; EPILOG-BLOCK: header.epil.preheader: ; EPILOG-BLOCK: header.epil.preheader:
Show All 15 Lines
; EPILOG-BLOCK-NEXT: %6 = icmp ult i32 %5, 1 ; EPILOG-BLOCK-NEXT: %6 = icmp ult i32 %5, 1
; EPILOG-BLOCK-NEXT: br i1 %6, label %outerLatch.loopexit.unr-lcssa.1, label %preheader.new.1 ; EPILOG-BLOCK-NEXT: br i1 %6, label %outerLatch.loopexit.unr-lcssa.1, label %preheader.new.1
; EPILOG-BLOCK: preheader.new.1: ; EPILOG-BLOCK: preheader.new.1:
; EPILOG-BLOCK-NEXT: %unroll_iter.1 = sub i32 %4, %xtraiter.1 ; EPILOG-BLOCK-NEXT: %unroll_iter.1 = sub i32 %4, %xtraiter.1
; EPILOG-BLOCK-NEXT: br label %header.1 ; EPILOG-BLOCK-NEXT: br label %header.1
; EPILOG-BLOCK: header.1: ; EPILOG-BLOCK: header.1:
; EPILOG-BLOCK-NEXT: %phi.1 = phi i64 [ 0, %preheader.new.1 ], [ %iv.next.1.1, %latch.1.1 ] ; EPILOG-BLOCK-NEXT: %phi.1 = phi i64 [ 0, %preheader.new.1 ], [ %iv.next.1.1, %latch.1.1 ]
; EPILOG-BLOCK-NEXT: %niter.1 = phi i32 [ 0, %preheader.new.1 ], [ %niter.next.1.1, %latch.1.1 ] ; EPILOG-BLOCK-NEXT: %niter.1 = phi i32 [ 0, %preheader.new.1 ], [ %niter.next.1.1, %latch.1.1 ]
; EPILOG-BLOCK-NEXT: br i1 true, label %latch.15, label %innerexit.loopexit.loopexit6 ; EPILOG-BLOCK-NEXT: br i1 true, label %latch.13, label %innerexit.loopexit.loopexit4
; EPILOG-BLOCK: latch.15: ; EPILOG-BLOCK: latch.13:
; EPILOG-BLOCK-NEXT: %iv.next.13 = add nuw nsw i64 %phi.1, 1 ; EPILOG-BLOCK-NEXT: br i1 true, label %latch.1.1, label %innerexit.loopexit.loopexit4
; EPILOG-BLOCK-NEXT: %niter.next.14 = add nuw nsw i32 %niter.1, 1
; EPILOG-BLOCK-NEXT: br i1 true, label %latch.1.1, label %innerexit.loopexit.loopexit6
; EPILOG-BLOCK: latch.1.1: ; EPILOG-BLOCK: latch.1.1:
; EPILOG-BLOCK-NEXT: %iv.next.1.1 = add nuw nsw i64 %iv.next.13, 1 ; EPILOG-BLOCK-NEXT: %iv.next.1.1 = add nuw nsw i64 %phi.1, 2
; EPILOG-BLOCK-NEXT: %niter.next.1.1 = add i32 %niter.next.14, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1.1 = add i32 %niter.1, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1.1 = icmp ne i32 %niter.next.1.1, %unroll_iter.1 ; EPILOG-BLOCK-NEXT: %niter.ncmp.1.1 = icmp ne i32 %niter.next.1.1, %unroll_iter.1
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1.1, label %header.1, label %outerLatch.loopexit.unr-lcssa.loopexit.1, !llvm.loop !14 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1.1, label %header.1, label %outerLatch.loopexit.unr-lcssa.loopexit.1, !llvm.loop !14
; EPILOG-BLOCK: outerLatch.loopexit.unr-lcssa.loopexit.1: ; EPILOG-BLOCK: outerLatch.loopexit.unr-lcssa.loopexit.1:
; EPILOG-BLOCK-NEXT: br label %outerLatch.loopexit.unr-lcssa.1 ; EPILOG-BLOCK-NEXT: br label %outerLatch.loopexit.unr-lcssa.1
; EPILOG-BLOCK: outerLatch.loopexit.unr-lcssa.1: ; EPILOG-BLOCK: outerLatch.loopexit.unr-lcssa.1:
; EPILOG-BLOCK-NEXT: %lcmp.mod.1 = icmp ne i32 %xtraiter.1, 0 ; EPILOG-BLOCK-NEXT: %lcmp.mod.1 = icmp ne i32 %xtraiter.1, 0
; EPILOG-BLOCK-NEXT: br i1 %lcmp.mod.1, label %header.epil.preheader.1, label %outerLatch.loopexit.1 ; EPILOG-BLOCK-NEXT: br i1 %lcmp.mod.1, label %header.epil.preheader.1, label %outerLatch.loopexit.1
; EPILOG-BLOCK: header.epil.preheader.1: ; EPILOG-BLOCK: header.epil.preheader.1:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PROLOG: innerexit.loopexit1: ; PROLOG: innerexit.loopexit1:
; PROLOG-NEXT: %trip.lcssa.ph2 = phi i32 [ %trip, %header.prol ] ; PROLOG-NEXT: %trip.lcssa.ph2 = phi i32 [ %trip, %header.prol ]
; PROLOG-NEXT: br label %innerexit ; PROLOG-NEXT: br label %innerexit
; PROLOG: innerexit: ; PROLOG: innerexit:
; PROLOG-NEXT: %trip.lcssa = phi i32 [ %trip.lcssa.ph, %innerexit.loopexit ], [ %trip.lcssa.ph2, %innerexit.loopexit1 ] ; PROLOG-NEXT: %trip.lcssa = phi i32 [ %trip.lcssa.ph, %innerexit.loopexit ], [ %trip.lcssa.ph2, %innerexit.loopexit1 ]
; PROLOG-NEXT: %i9 = call ptr addrspace(1) @foo(i32 %trip.lcssa) ; PROLOG-NEXT: %i9 = call ptr addrspace(1) @foo(i32 %trip.lcssa)
; PROLOG-NEXT: ret ptr addrspace(1) %i9 ; PROLOG-NEXT: ret ptr addrspace(1) %i9
; PROLOG: latch: ; PROLOG: latch:
; PROLOG-NEXT: %iv.next = add nuw nsw i64 %phi, 1
; PROLOG-NEXT: br i1 true, label %latch.1, label %innerexit.loopexit ; PROLOG-NEXT: br i1 true, label %latch.1, label %innerexit.loopexit
; PROLOG: latch.1: ; PROLOG: latch.1:
; PROLOG-NEXT: %iv.next.1 = add nuw nsw i64 %iv.next, 1
; PROLOG-NEXT: br i1 true, label %latch.2, label %innerexit.loopexit ; PROLOG-NEXT: br i1 true, label %latch.2, label %innerexit.loopexit
; PROLOG: latch.2: ; PROLOG: latch.2:
; PROLOG-NEXT: %iv.next.2 = add nuw nsw i64 %iv.next.1, 1
; PROLOG-NEXT: br i1 true, label %latch.3, label %innerexit.loopexit ; PROLOG-NEXT: br i1 true, label %latch.3, label %innerexit.loopexit
; PROLOG: latch.3: ; PROLOG: latch.3:
; PROLOG-NEXT: %iv.next.3 = add nuw nsw i64 %iv.next.2, 1
; PROLOG-NEXT: br i1 true, label %latch.4, label %innerexit.loopexit ; PROLOG-NEXT: br i1 true, label %latch.4, label %innerexit.loopexit
; PROLOG: latch.4: ; PROLOG: latch.4:
; PROLOG-NEXT: %iv.next.4 = add nuw nsw i64 %iv.next.3, 1
; PROLOG-NEXT: br i1 true, label %latch.5, label %innerexit.loopexit ; PROLOG-NEXT: br i1 true, label %latch.5, label %innerexit.loopexit
; PROLOG: latch.5: ; PROLOG: latch.5:
; PROLOG-NEXT: %iv.next.5 = add nuw nsw i64 %iv.next.4, 1
; PROLOG-NEXT: br i1 true, label %latch.6, label %innerexit.loopexit ; PROLOG-NEXT: br i1 true, label %latch.6, label %innerexit.loopexit
; PROLOG: latch.6: ; PROLOG: latch.6:
; PROLOG-NEXT: %iv.next.6 = add nuw nsw i64 %iv.next.5, 1 ; PROLOG-NEXT: %iv.next.6 = add nuw nsw i64 %phi, 7
; PROLOG-NEXT: %i7.7 = trunc i64 %iv.next.6 to i32 ; PROLOG-NEXT: %i7.7 = trunc i64 %iv.next.6 to i32
; PROLOG-NEXT: br i1 true, label %latch.7, label %innerexit.loopexit ; PROLOG-NEXT: br i1 true, label %latch.7, label %innerexit.loopexit
; PROLOG: latch.7: ; PROLOG: latch.7:
; PROLOG-NEXT: %i11.7 = add nsw i32 %i7.7, 1 ; PROLOG-NEXT: %i11.7 = add nsw i32 %i7.7, 1
; PROLOG-NEXT: %innercnd.7 = icmp slt i32 %i11.7, %trip ; PROLOG-NEXT: %innercnd.7 = icmp slt i32 %i11.7, %trip
; PROLOG-NEXT: %iv.next.7 = add nuw nsw i64 %iv.next.6, 1 ; PROLOG-NEXT: %iv.next.7 = add nuw nsw i64 %phi, 8
; PROLOG-NEXT: br i1 %innercnd.7, label %header, label %outerLatch.loopexit.unr-lcssa ; PROLOG-NEXT: br i1 %innercnd.7, label %header, label %outerLatch.loopexit.unr-lcssa
; PROLOG: outerLatch.loopexit.unr-lcssa: ; PROLOG: outerLatch.loopexit.unr-lcssa:
; PROLOG-NEXT: br label %outerLatch.loopexit ; PROLOG-NEXT: br label %outerLatch.loopexit
; PROLOG: outerLatch.loopexit: ; PROLOG: outerLatch.loopexit:
; PROLOG-NEXT: br label %outerLatch ; PROLOG-NEXT: br label %outerLatch
; PROLOG: outerLatch: ; PROLOG: outerLatch:
; PROLOG-NEXT: br label %outerloopHdr ; PROLOG-NEXT: br label %outerloopHdr
; ;
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; PROLOG-BLOCK-NEXT: ret ptr addrspace(1) %i9 ; PROLOG-BLOCK-NEXT: ret ptr addrspace(1) %i9
; PROLOG-BLOCK: latch: ; PROLOG-BLOCK: latch:
; PROLOG-BLOCK-NEXT: %iv.next = add nuw nsw i64 %phi, 1 ; PROLOG-BLOCK-NEXT: %iv.next = add nuw nsw i64 %phi, 1
; PROLOG-BLOCK-NEXT: %i7.1 = trunc i64 %iv.next to i32 ; PROLOG-BLOCK-NEXT: %i7.1 = trunc i64 %iv.next to i32
; PROLOG-BLOCK-NEXT: br i1 true, label %latch.1, label %innerexit.loopexit.loopexit ; PROLOG-BLOCK-NEXT: br i1 true, label %latch.1, label %innerexit.loopexit.loopexit
; PROLOG-BLOCK: latch.1: ; PROLOG-BLOCK: latch.1:
; PROLOG-BLOCK-NEXT: %i11.1 = add nsw i32 %i7.1, 1 ; PROLOG-BLOCK-NEXT: %i11.1 = add nsw i32 %i7.1, 1
; PROLOG-BLOCK-NEXT: %innercnd.1 = icmp slt i32 %i11.1, %trip ; PROLOG-BLOCK-NEXT: %innercnd.1 = icmp slt i32 %i11.1, %trip
; PROLOG-BLOCK-NEXT: %iv.next.1 = add nuw nsw i64 %iv.next, 1 ; PROLOG-BLOCK-NEXT: %iv.next.1 = add nuw nsw i64 %phi, 2
; PROLOG-BLOCK-NEXT: br i1 %innercnd.1, label %header, label %outerLatch.loopexit.unr-lcssa, !llvm.loop !14 ; PROLOG-BLOCK-NEXT: br i1 %innercnd.1, label %header, label %outerLatch.loopexit.unr-lcssa, !llvm.loop !14
; PROLOG-BLOCK: outerLatch.loopexit.unr-lcssa: ; PROLOG-BLOCK: outerLatch.loopexit.unr-lcssa:
; PROLOG-BLOCK-NEXT: br label %outerLatch.loopexit ; PROLOG-BLOCK-NEXT: br label %outerLatch.loopexit
; PROLOG-BLOCK: outerLatch.loopexit: ; PROLOG-BLOCK: outerLatch.loopexit:
; PROLOG-BLOCK-NEXT: br label %outerLatch ; PROLOG-BLOCK-NEXT: br label %outerLatch
; PROLOG-BLOCK: outerLatch: ; PROLOG-BLOCK: outerLatch:
; PROLOG-BLOCK-NEXT: %trip.1 = add i32 %n, -1 ; PROLOG-BLOCK-NEXT: %trip.1 = add i32 %n, -1
; PROLOG-BLOCK-NEXT: %outercnd.1 = icmp slt i32 0, %trip.1 ; PROLOG-BLOCK-NEXT: %outercnd.1 = icmp slt i32 0, %trip.1
Show All 21 Lines
; PROLOG-BLOCK-NEXT: br i1 true, label %latch.14, label %innerexit.loopexit.loopexit5 ; PROLOG-BLOCK-NEXT: br i1 true, label %latch.14, label %innerexit.loopexit.loopexit5
; PROLOG-BLOCK: latch.14: ; PROLOG-BLOCK: latch.14:
; PROLOG-BLOCK-NEXT: %iv.next.13 = add nuw nsw i64 %phi.1, 1 ; PROLOG-BLOCK-NEXT: %iv.next.13 = add nuw nsw i64 %phi.1, 1
; PROLOG-BLOCK-NEXT: %i7.1.1 = trunc i64 %iv.next.13 to i32 ; PROLOG-BLOCK-NEXT: %i7.1.1 = trunc i64 %iv.next.13 to i32
; PROLOG-BLOCK-NEXT: br i1 true, label %latch.1.1, label %innerexit.loopexit.loopexit5 ; PROLOG-BLOCK-NEXT: br i1 true, label %latch.1.1, label %innerexit.loopexit.loopexit5
; PROLOG-BLOCK: latch.1.1: ; PROLOG-BLOCK: latch.1.1:
; PROLOG-BLOCK-NEXT: %i11.1.1 = add nsw i32 %i7.1.1, 1 ; PROLOG-BLOCK-NEXT: %i11.1.1 = add nsw i32 %i7.1.1, 1
; PROLOG-BLOCK-NEXT: %innercnd.1.1 = icmp slt i32 %i11.1.1, %trip.1 ; PROLOG-BLOCK-NEXT: %innercnd.1.1 = icmp slt i32 %i11.1.1, %trip.1
; PROLOG-BLOCK-NEXT: %iv.next.1.1 = add nuw nsw i64 %iv.next.13, 1 ; PROLOG-BLOCK-NEXT: %iv.next.1.1 = add nuw nsw i64 %phi.1, 2
; PROLOG-BLOCK-NEXT: br i1 %innercnd.1.1, label %header.1, label %outerLatch.loopexit.unr-lcssa.1, !llvm.loop !14 ; PROLOG-BLOCK-NEXT: br i1 %innercnd.1.1, label %header.1, label %outerLatch.loopexit.unr-lcssa.1, !llvm.loop !14
; PROLOG-BLOCK: outerLatch.loopexit.unr-lcssa.1: ; PROLOG-BLOCK: outerLatch.loopexit.unr-lcssa.1:
; PROLOG-BLOCK-NEXT: br label %outerLatch.loopexit.1 ; PROLOG-BLOCK-NEXT: br label %outerLatch.loopexit.1
; PROLOG-BLOCK: outerLatch.loopexit.1: ; PROLOG-BLOCK: outerLatch.loopexit.1:
; PROLOG-BLOCK-NEXT: br label %outerLatch.1 ; PROLOG-BLOCK-NEXT: br label %outerLatch.1
; PROLOG-BLOCK: outerLatch.1: ; PROLOG-BLOCK: outerLatch.1:
; PROLOG-BLOCK-NEXT: br label %outerloopHdr, !llvm.loop !15 ; PROLOG-BLOCK-NEXT: br label %outerloopHdr, !llvm.loop !15
; ;
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; EPILOG: loop_header: ; EPILOG: loop_header:
; EPILOG-NEXT: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.7, %loop_latch.7 ] ; EPILOG-NEXT: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.7, %loop_latch.7 ]
; EPILOG-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.7, %loop_latch.7 ] ; EPILOG-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.7, %loop_latch.7 ]
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early = icmp ne i64 %iv, %trip2 ; EPILOG-NEXT: %cmp_early = icmp ne i64 %iv, %trip2
; EPILOG-NEXT: br i1 %cmp_early, label %loop_latch, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cmp_early, label %loop_latch, label %exit1.loopexit
; EPILOG: loop_latch: ; EPILOG: loop_latch:
; EPILOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1 ; EPILOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2 ; EPILOG-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; EPILOG-NEXT: br i1 %cmp_early.1, label %loop_latch.1, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cmp_early.1, label %loop_latch.1, label %exit1.loopexit
; EPILOG: loop_latch.1: ; EPILOG: loop_latch.1:
; EPILOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1 ; EPILOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.2 = icmp ne i64 %iv_next.1, %trip2 ; EPILOG-NEXT: %cmp_early.2 = icmp ne i64 %iv_next.1, %trip2
; EPILOG-NEXT: br i1 %cmp_early.2, label %loop_latch.2, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cmp_early.2, label %loop_latch.2, label %exit1.loopexit
; EPILOG: loop_latch.2: ; EPILOG: loop_latch.2:
; EPILOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv_next.1, 1 ; EPILOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv, 3
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.3 = icmp ne i64 %iv_next.2, %trip2 ; EPILOG-NEXT: %cmp_early.3 = icmp ne i64 %iv_next.2, %trip2
; EPILOG-NEXT: br i1 %cmp_early.3, label %loop_latch.3, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cmp_early.3, label %loop_latch.3, label %exit1.loopexit
; EPILOG: loop_latch.3: ; EPILOG: loop_latch.3:
; EPILOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv_next.2, 1 ; EPILOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv, 4
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.4 = icmp ne i64 %iv_next.3, %trip2 ; EPILOG-NEXT: %cmp_early.4 = icmp ne i64 %iv_next.3, %trip2
; EPILOG-NEXT: br i1 %cmp_early.4, label %loop_latch.4, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cmp_early.4, label %loop_latch.4, label %exit1.loopexit
; EPILOG: loop_latch.4: ; EPILOG: loop_latch.4:
; EPILOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv_next.3, 1 ; EPILOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv, 5
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.5 = icmp ne i64 %iv_next.4, %trip2 ; EPILOG-NEXT: %cmp_early.5 = icmp ne i64 %iv_next.4, %trip2
; EPILOG-NEXT: br i1 %cmp_early.5, label %loop_latch.5, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cmp_early.5, label %loop_latch.5, label %exit1.loopexit
; EPILOG: loop_latch.5: ; EPILOG: loop_latch.5:
; EPILOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv_next.4, 1 ; EPILOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv, 6
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.6 = icmp ne i64 %iv_next.5, %trip2 ; EPILOG-NEXT: %cmp_early.6 = icmp ne i64 %iv_next.5, %trip2
; EPILOG-NEXT: br i1 %cmp_early.6, label %loop_latch.6, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cmp_early.6, label %loop_latch.6, label %exit1.loopexit
; EPILOG: loop_latch.6: ; EPILOG: loop_latch.6:
; EPILOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv_next.5, 1 ; EPILOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv, 7
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2 ; EPILOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2
; EPILOG-NEXT: br i1 %cmp_early.7, label %loop_latch.7, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cmp_early.7, label %loop_latch.7, label %exit1.loopexit
; EPILOG: loop_latch.7: ; EPILOG: loop_latch.7:
; EPILOG-NEXT: %iv_next.7 = add i64 %iv_next.6, 1 ; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.unr-lcssa.loopexit ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.unr-lcssa.loopexit
; EPILOG: exit1.loopexit: ; EPILOG: exit1.loopexit:
; EPILOG-NEXT: br label %exit1 ; EPILOG-NEXT: br label %exit1
; EPILOG: exit1.loopexit1: ; EPILOG: exit1.loopexit1:
; EPILOG-NEXT: br label %exit1 ; EPILOG-NEXT: br label %exit1
; EPILOG: exit1: ; EPILOG: exit1:
; EPILOG-NEXT: ret void ; EPILOG-NEXT: ret void
Show All 36 Lines
; EPILOG-BLOCK: loop_header: ; EPILOG-BLOCK: loop_header:
; EPILOG-BLOCK-NEXT: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.1, %loop_latch.1 ] ; EPILOG-BLOCK-NEXT: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.1, %loop_latch.1 ]
; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.1, %loop_latch.1 ] ; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.1, %loop_latch.1 ]
; EPILOG-BLOCK-NEXT: call void @bar() ; EPILOG-BLOCK-NEXT: call void @bar()
; EPILOG-BLOCK-NEXT: %cmp_early = icmp ne i64 %iv, %trip2 ; EPILOG-BLOCK-NEXT: %cmp_early = icmp ne i64 %iv, %trip2
; EPILOG-BLOCK-NEXT: br i1 %cmp_early, label %loop_latch, label %exit1.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cmp_early, label %loop_latch, label %exit1.loopexit
; EPILOG-BLOCK: loop_latch: ; EPILOG-BLOCK: loop_latch:
; EPILOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1 ; EPILOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: call void @bar() ; EPILOG-BLOCK-NEXT: call void @bar()
; EPILOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2 ; EPILOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; EPILOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_latch.1, label %exit1.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_latch.1, label %exit1.loopexit
; EPILOG-BLOCK: loop_latch.1: ; EPILOG-BLOCK: loop_latch.1:
; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.unr-lcssa.loopexit, !llvm.loop !16 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.unr-lcssa.loopexit, !llvm.loop !16
; EPILOG-BLOCK: exit1.loopexit: ; EPILOG-BLOCK: exit1.loopexit:
; EPILOG-BLOCK-NEXT: br label %exit1 ; EPILOG-BLOCK-NEXT: br label %exit1
; EPILOG-BLOCK: exit1: ; EPILOG-BLOCK: exit1:
; EPILOG-BLOCK-NEXT: ret void ; EPILOG-BLOCK-NEXT: ret void
; EPILOG-BLOCK: exit2.unr-lcssa.loopexit: ; EPILOG-BLOCK: exit2.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: %iv.unr.ph = phi i64 [ %iv_next.1, %loop_latch.1 ] ; EPILOG-BLOCK-NEXT: %iv.unr.ph = phi i64 [ %iv_next.1, %loop_latch.1 ]
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; PROLOG-NEXT: %cmp_early = icmp ne i64 %iv, %trip2 ; PROLOG-NEXT: %cmp_early = icmp ne i64 %iv, %trip2
; PROLOG-NEXT: br i1 %cmp_early, label %loop_latch, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cmp_early, label %loop_latch, label %exit1.loopexit
; PROLOG: loop_latch: ; PROLOG: loop_latch:
; PROLOG-NEXT: %iv_next = add i64 %iv, 1 ; PROLOG-NEXT: %iv_next = add i64 %iv, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2 ; PROLOG-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; PROLOG-NEXT: br i1 %cmp_early.1, label %loop_latch.1, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cmp_early.1, label %loop_latch.1, label %exit1.loopexit
; PROLOG: loop_latch.1: ; PROLOG: loop_latch.1:
; PROLOG-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; PROLOG-NEXT: %iv_next.1 = add i64 %iv, 2
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.2 = icmp ne i64 %iv_next.1, %trip2 ; PROLOG-NEXT: %cmp_early.2 = icmp ne i64 %iv_next.1, %trip2
; PROLOG-NEXT: br i1 %cmp_early.2, label %loop_latch.2, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cmp_early.2, label %loop_latch.2, label %exit1.loopexit
; PROLOG: loop_latch.2: ; PROLOG: loop_latch.2:
; PROLOG-NEXT: %iv_next.2 = add i64 %iv_next.1, 1 ; PROLOG-NEXT: %iv_next.2 = add i64 %iv, 3
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.3 = icmp ne i64 %iv_next.2, %trip2 ; PROLOG-NEXT: %cmp_early.3 = icmp ne i64 %iv_next.2, %trip2
; PROLOG-NEXT: br i1 %cmp_early.3, label %loop_latch.3, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cmp_early.3, label %loop_latch.3, label %exit1.loopexit
; PROLOG: loop_latch.3: ; PROLOG: loop_latch.3:
; PROLOG-NEXT: %iv_next.3 = add i64 %iv_next.2, 1 ; PROLOG-NEXT: %iv_next.3 = add i64 %iv, 4
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.4 = icmp ne i64 %iv_next.3, %trip2 ; PROLOG-NEXT: %cmp_early.4 = icmp ne i64 %iv_next.3, %trip2
; PROLOG-NEXT: br i1 %cmp_early.4, label %loop_latch.4, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cmp_early.4, label %loop_latch.4, label %exit1.loopexit
; PROLOG: loop_latch.4: ; PROLOG: loop_latch.4:
; PROLOG-NEXT: %iv_next.4 = add i64 %iv_next.3, 1 ; PROLOG-NEXT: %iv_next.4 = add i64 %iv, 5
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.5 = icmp ne i64 %iv_next.4, %trip2 ; PROLOG-NEXT: %cmp_early.5 = icmp ne i64 %iv_next.4, %trip2
; PROLOG-NEXT: br i1 %cmp_early.5, label %loop_latch.5, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cmp_early.5, label %loop_latch.5, label %exit1.loopexit
; PROLOG: loop_latch.5: ; PROLOG: loop_latch.5:
; PROLOG-NEXT: %iv_next.5 = add i64 %iv_next.4, 1 ; PROLOG-NEXT: %iv_next.5 = add i64 %iv, 6
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.6 = icmp ne i64 %iv_next.5, %trip2 ; PROLOG-NEXT: %cmp_early.6 = icmp ne i64 %iv_next.5, %trip2
; PROLOG-NEXT: br i1 %cmp_early.6, label %loop_latch.6, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cmp_early.6, label %loop_latch.6, label %exit1.loopexit
; PROLOG: loop_latch.6: ; PROLOG: loop_latch.6:
; PROLOG-NEXT: %iv_next.6 = add i64 %iv_next.5, 1 ; PROLOG-NEXT: %iv_next.6 = add i64 %iv, 7
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2 ; PROLOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2
; PROLOG-NEXT: br i1 %cmp_early.7, label %loop_latch.7, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cmp_early.7, label %loop_latch.7, label %exit1.loopexit
; PROLOG: loop_latch.7: ; PROLOG: loop_latch.7:
; PROLOG-NEXT: %iv_next.7 = add i64 %iv_next.6, 1 ; PROLOG-NEXT: %iv_next.7 = add i64 %iv, 8
; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip ; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip
; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit2.unr-lcssa ; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit2.unr-lcssa
; PROLOG: exit1.loopexit: ; PROLOG: exit1.loopexit:
; PROLOG-NEXT: br label %exit1 ; PROLOG-NEXT: br label %exit1
; PROLOG: exit1.loopexit1: ; PROLOG: exit1.loopexit1:
; PROLOG-NEXT: br label %exit1 ; PROLOG-NEXT: br label %exit1
; PROLOG: exit1: ; PROLOG: exit1:
; PROLOG-NEXT: ret void ; PROLOG-NEXT: ret void
Show All 29 Lines
; PROLOG-BLOCK-NEXT: %cmp_early = icmp ne i64 %iv, %trip2 ; PROLOG-BLOCK-NEXT: %cmp_early = icmp ne i64 %iv, %trip2
; PROLOG-BLOCK-NEXT: br i1 %cmp_early, label %loop_latch, label %exit1.loopexit ; PROLOG-BLOCK-NEXT: br i1 %cmp_early, label %loop_latch, label %exit1.loopexit
; PROLOG-BLOCK: loop_latch: ; PROLOG-BLOCK: loop_latch:
; PROLOG-BLOCK-NEXT: %iv_next = add i64 %iv, 1 ; PROLOG-BLOCK-NEXT: %iv_next = add i64 %iv, 1
; PROLOG-BLOCK-NEXT: call void @bar() ; PROLOG-BLOCK-NEXT: call void @bar()
; PROLOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2 ; PROLOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; PROLOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_latch.1, label %exit1.loopexit ; PROLOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_latch.1, label %exit1.loopexit
; PROLOG-BLOCK: loop_latch.1: ; PROLOG-BLOCK: loop_latch.1:
; PROLOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; PROLOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit2.unr-lcssa, !llvm.loop !16 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit2.unr-lcssa, !llvm.loop !16
; PROLOG-BLOCK: exit1.loopexit: ; PROLOG-BLOCK: exit1.loopexit:
; PROLOG-BLOCK-NEXT: br label %exit1 ; PROLOG-BLOCK-NEXT: br label %exit1
; PROLOG-BLOCK: exit1: ; PROLOG-BLOCK: exit1:
; PROLOG-BLOCK-NEXT: ret void ; PROLOG-BLOCK-NEXT: ret void
; PROLOG-BLOCK: exit2.unr-lcssa: ; PROLOG-BLOCK: exit2.unr-lcssa:
; PROLOG-BLOCK-NEXT: br label %exit2 ; PROLOG-BLOCK-NEXT: br label %exit2
Show All 35 Lines
; EPILOG-NEXT: %unroll_iter = sub i64 %0, %xtraiter ; EPILOG-NEXT: %unroll_iter = sub i64 %0, %xtraiter
; EPILOG-NEXT: br label %loop_header ; EPILOG-NEXT: br label %loop_header
; EPILOG: loop_header: ; EPILOG: loop_header:
; EPILOG-NEXT: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.7, %loop_latch.7 ] ; EPILOG-NEXT: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.7, %loop_latch.7 ]
; EPILOG-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.7, %loop_latch.7 ] ; EPILOG-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.7, %loop_latch.7 ]
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_latch, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch, label %exit1.loopexit
; EPILOG: loop_latch: ; EPILOG: loop_latch:
; EPILOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.loopexit
; EPILOG: loop_latch.1: ; EPILOG: loop_latch.1:
; EPILOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_latch.2, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.2, label %exit1.loopexit
; EPILOG: loop_latch.2: ; EPILOG: loop_latch.2:
; EPILOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv_next.1, 1
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_latch.3, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.3, label %exit1.loopexit
; EPILOG: loop_latch.3: ; EPILOG: loop_latch.3:
; EPILOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv_next.2, 1
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_latch.4, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.4, label %exit1.loopexit
; EPILOG: loop_latch.4: ; EPILOG: loop_latch.4:
; EPILOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv_next.3, 1
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_latch.5, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.5, label %exit1.loopexit
; EPILOG: loop_latch.5: ; EPILOG: loop_latch.5:
; EPILOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv_next.4, 1
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_latch.6, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.6, label %exit1.loopexit
; EPILOG: loop_latch.6: ; EPILOG: loop_latch.6:
; EPILOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv_next.5, 1
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_latch.7, label %exit1.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.7, label %exit1.loopexit
; EPILOG: loop_latch.7: ; EPILOG: loop_latch.7:
; EPILOG-NEXT: %iv_next.7 = add i64 %iv_next.6, 1 ; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.unr-lcssa.loopexit ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit2.unr-lcssa.loopexit
; EPILOG: exit1.loopexit: ; EPILOG: exit1.loopexit:
; EPILOG-NEXT: br label %exit1 ; EPILOG-NEXT: br label %exit1
; EPILOG: exit1.loopexit1: ; EPILOG: exit1.loopexit1:
; EPILOG-NEXT: br label %exit1 ; EPILOG-NEXT: br label %exit1
; EPILOG: exit1: ; EPILOG: exit1:
; EPILOG-NEXT: ret void ; EPILOG-NEXT: ret void
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; EPILOG-BLOCK-NEXT: %unroll_iter = sub i64 %0, %xtraiter ; EPILOG-BLOCK-NEXT: %unroll_iter = sub i64 %0, %xtraiter
; EPILOG-BLOCK-NEXT: br label %loop_header ; EPILOG-BLOCK-NEXT: br label %loop_header
; EPILOG-BLOCK: loop_header: ; EPILOG-BLOCK: loop_header:
; EPILOG-BLOCK-NEXT: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.1, %loop_latch.1 ] ; EPILOG-BLOCK-NEXT: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.1, %loop_latch.1 ]
; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.1, %loop_latch.1 ] ; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.1, %loop_latch.1 ]
; EPILOG-BLOCK-NEXT: call void @bar() ; EPILOG-BLOCK-NEXT: call void @bar()
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch, label %exit1.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch, label %exit1.loopexit
; EPILOG-BLOCK: loop_latch: ; EPILOG-BLOCK: loop_latch:
; EPILOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: call void @bar() ; EPILOG-BLOCK-NEXT: call void @bar()
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.loopexit
; EPILOG-BLOCK: loop_latch.1: ; EPILOG-BLOCK: loop_latch.1:
; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.unr-lcssa.loopexit, !llvm.loop !17 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit2.unr-lcssa.loopexit, !llvm.loop !17
; EPILOG-BLOCK: exit1.loopexit: ; EPILOG-BLOCK: exit1.loopexit:
; EPILOG-BLOCK-NEXT: br label %exit1 ; EPILOG-BLOCK-NEXT: br label %exit1
; EPILOG-BLOCK: exit1: ; EPILOG-BLOCK: exit1:
; EPILOG-BLOCK-NEXT: ret void ; EPILOG-BLOCK-NEXT: ret void
; EPILOG-BLOCK: exit2.unr-lcssa.loopexit: ; EPILOG-BLOCK: exit2.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: br label %exit2.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %exit2.unr-lcssa
Show All 39 Lines
; PROLOG-NEXT: br i1 %2, label %exit2, label %entry.new ; PROLOG-NEXT: br i1 %2, label %exit2, label %entry.new
; PROLOG: entry.new: ; PROLOG: entry.new:
; PROLOG-NEXT: br label %loop_header ; PROLOG-NEXT: br label %loop_header
; PROLOG: loop_header: ; PROLOG: loop_header:
; PROLOG-NEXT: %iv = phi i64 [ %iv.unr, %entry.new ], [ %iv_next.7, %loop_latch.7 ] ; PROLOG-NEXT: %iv = phi i64 [ %iv.unr, %entry.new ], [ %iv_next.7, %loop_latch.7 ]
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_latch, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch, label %exit1.loopexit
; PROLOG: loop_latch: ; PROLOG: loop_latch:
; PROLOG-NEXT: %iv_next = add i64 %iv, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.loopexit
; PROLOG: loop_latch.1: ; PROLOG: loop_latch.1:
; PROLOG-NEXT: %iv_next.1 = add i64 %iv_next, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_latch.2, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.2, label %exit1.loopexit
; PROLOG: loop_latch.2: ; PROLOG: loop_latch.2:
; PROLOG-NEXT: %iv_next.2 = add i64 %iv_next.1, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_latch.3, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.3, label %exit1.loopexit
; PROLOG: loop_latch.3: ; PROLOG: loop_latch.3:
; PROLOG-NEXT: %iv_next.3 = add i64 %iv_next.2, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_latch.4, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.4, label %exit1.loopexit
; PROLOG: loop_latch.4: ; PROLOG: loop_latch.4:
; PROLOG-NEXT: %iv_next.4 = add i64 %iv_next.3, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_latch.5, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.5, label %exit1.loopexit
; PROLOG: loop_latch.5: ; PROLOG: loop_latch.5:
; PROLOG-NEXT: %iv_next.5 = add i64 %iv_next.4, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_latch.6, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.6, label %exit1.loopexit
; PROLOG: loop_latch.6: ; PROLOG: loop_latch.6:
; PROLOG-NEXT: %iv_next.6 = add i64 %iv_next.5, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_latch.7, label %exit1.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.7, label %exit1.loopexit
; PROLOG: loop_latch.7: ; PROLOG: loop_latch.7:
; PROLOG-NEXT: %iv_next.7 = add i64 %iv_next.6, 1 ; PROLOG-NEXT: %iv_next.7 = add i64 %iv, 8
; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip ; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip
; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit2.unr-lcssa ; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit2.unr-lcssa
; PROLOG: exit1.loopexit: ; PROLOG: exit1.loopexit:
; PROLOG-NEXT: br label %exit1 ; PROLOG-NEXT: br label %exit1
; PROLOG: exit1.loopexit1: ; PROLOG: exit1.loopexit1:
; PROLOG-NEXT: br label %exit1 ; PROLOG-NEXT: br label %exit1
; PROLOG: exit1: ; PROLOG: exit1:
; PROLOG-NEXT: ret void ; PROLOG-NEXT: ret void
Show All 22 Lines
; PROLOG-BLOCK-NEXT: br i1 %2, label %exit2, label %entry.new ; PROLOG-BLOCK-NEXT: br i1 %2, label %exit2, label %entry.new
; PROLOG-BLOCK: entry.new: ; PROLOG-BLOCK: entry.new:
; PROLOG-BLOCK-NEXT: br label %loop_header ; PROLOG-BLOCK-NEXT: br label %loop_header
; PROLOG-BLOCK: loop_header: ; PROLOG-BLOCK: loop_header:
; PROLOG-BLOCK-NEXT: %iv = phi i64 [ %iv.unr, %entry.new ], [ %iv_next.1, %loop_latch.1 ] ; PROLOG-BLOCK-NEXT: %iv = phi i64 [ %iv.unr, %entry.new ], [ %iv_next.1, %loop_latch.1 ]
; PROLOG-BLOCK-NEXT: call void @bar() ; PROLOG-BLOCK-NEXT: call void @bar()
; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_latch, label %exit1.loopexit ; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_latch, label %exit1.loopexit
; PROLOG-BLOCK: loop_latch: ; PROLOG-BLOCK: loop_latch:
; PROLOG-BLOCK-NEXT: %iv_next = add i64 %iv, 1
; PROLOG-BLOCK-NEXT: call void @bar() ; PROLOG-BLOCK-NEXT: call void @bar()
; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.loopexit ; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.loopexit
; PROLOG-BLOCK: loop_latch.1: ; PROLOG-BLOCK: loop_latch.1:
; PROLOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; PROLOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit2.unr-lcssa, !llvm.loop !17 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit2.unr-lcssa, !llvm.loop !17
; PROLOG-BLOCK: exit1.loopexit: ; PROLOG-BLOCK: exit1.loopexit:
; PROLOG-BLOCK-NEXT: br label %exit1 ; PROLOG-BLOCK-NEXT: br label %exit1
; PROLOG-BLOCK: exit1: ; PROLOG-BLOCK: exit1:
; PROLOG-BLOCK-NEXT: ret void ; PROLOG-BLOCK-NEXT: ret void
; PROLOG-BLOCK: exit2.unr-lcssa: ; PROLOG-BLOCK: exit2.unr-lcssa:
; PROLOG-BLOCK-NEXT: br label %exit2 ; PROLOG-BLOCK-NEXT: br label %exit2
Show All 38 Lines
; EPILOG-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.7, %loop_latch.7 ] ; EPILOG-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.7, %loop_latch.7 ]
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early = icmp ne i64 %iv, %trip2 ; EPILOG-NEXT: %cmp_early = icmp ne i64 %iv, %trip2
; EPILOG-NEXT: br i1 %cmp_early, label %loop_exiting_bb2, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early, label %loop_exiting_bb2, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2: ; EPILOG: loop_exiting_bb2:
; EPILOG-NEXT: br i1 %cond, label %loop_latch, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch: ; EPILOG: loop_latch:
; EPILOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1 ; EPILOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2 ; EPILOG-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; EPILOG-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.1: ; EPILOG: loop_exiting_bb2.1:
; EPILOG-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.1: ; EPILOG: loop_latch.1:
; EPILOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1 ; EPILOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.2 = icmp ne i64 %iv_next.1, %trip2 ; EPILOG-NEXT: %cmp_early.2 = icmp ne i64 %iv_next.1, %trip2
; EPILOG-NEXT: br i1 %cmp_early.2, label %loop_exiting_bb2.2, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.2, label %loop_exiting_bb2.2, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.2: ; EPILOG: loop_exiting_bb2.2:
; EPILOG-NEXT: br i1 %cond, label %loop_latch.2, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.2, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.2: ; EPILOG: loop_latch.2:
; EPILOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv_next.1, 1 ; EPILOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv, 3
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.3 = icmp ne i64 %iv_next.2, %trip2 ; EPILOG-NEXT: %cmp_early.3 = icmp ne i64 %iv_next.2, %trip2
; EPILOG-NEXT: br i1 %cmp_early.3, label %loop_exiting_bb2.3, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.3, label %loop_exiting_bb2.3, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.3: ; EPILOG: loop_exiting_bb2.3:
; EPILOG-NEXT: br i1 %cond, label %loop_latch.3, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.3, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.3: ; EPILOG: loop_latch.3:
; EPILOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv_next.2, 1 ; EPILOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv, 4
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.4 = icmp ne i64 %iv_next.3, %trip2 ; EPILOG-NEXT: %cmp_early.4 = icmp ne i64 %iv_next.3, %trip2
; EPILOG-NEXT: br i1 %cmp_early.4, label %loop_exiting_bb2.4, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.4, label %loop_exiting_bb2.4, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.4: ; EPILOG: loop_exiting_bb2.4:
; EPILOG-NEXT: br i1 %cond, label %loop_latch.4, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.4, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.4: ; EPILOG: loop_latch.4:
; EPILOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv_next.3, 1 ; EPILOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv, 5
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.5 = icmp ne i64 %iv_next.4, %trip2 ; EPILOG-NEXT: %cmp_early.5 = icmp ne i64 %iv_next.4, %trip2
; EPILOG-NEXT: br i1 %cmp_early.5, label %loop_exiting_bb2.5, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.5, label %loop_exiting_bb2.5, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.5: ; EPILOG: loop_exiting_bb2.5:
; EPILOG-NEXT: br i1 %cond, label %loop_latch.5, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.5, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.5: ; EPILOG: loop_latch.5:
; EPILOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv_next.4, 1 ; EPILOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv, 6
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.6 = icmp ne i64 %iv_next.5, %trip2 ; EPILOG-NEXT: %cmp_early.6 = icmp ne i64 %iv_next.5, %trip2
; EPILOG-NEXT: br i1 %cmp_early.6, label %loop_exiting_bb2.6, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.6, label %loop_exiting_bb2.6, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.6: ; EPILOG: loop_exiting_bb2.6:
; EPILOG-NEXT: br i1 %cond, label %loop_latch.6, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.6, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.6: ; EPILOG: loop_latch.6:
; EPILOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv_next.5, 1 ; EPILOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv, 7
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2 ; EPILOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2
; EPILOG-NEXT: br i1 %cmp_early.7, label %loop_exiting_bb2.7, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.7, label %loop_exiting_bb2.7, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.7: ; EPILOG: loop_exiting_bb2.7:
; EPILOG-NEXT: br i1 %cond, label %loop_latch.7, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_latch.7, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.7: ; EPILOG: loop_latch.7:
; EPILOG-NEXT: %iv_next.7 = add i64 %iv_next.6, 1 ; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit1.unr-lcssa.loopexit ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit1.unr-lcssa.loopexit
; EPILOG: exit1.unr-lcssa.loopexit: ; EPILOG: exit1.unr-lcssa.loopexit:
; EPILOG-NEXT: %iv.unr.ph = phi i64 [ %iv_next.7, %loop_latch.7 ] ; EPILOG-NEXT: %iv.unr.ph = phi i64 [ %iv_next.7, %loop_latch.7 ]
; EPILOG-NEXT: br label %exit1.unr-lcssa ; EPILOG-NEXT: br label %exit1.unr-lcssa
; EPILOG: exit1.unr-lcssa: ; EPILOG: exit1.unr-lcssa:
; EPILOG-NEXT: %iv.unr = phi i64 [ 0, %entry ], [ %iv.unr.ph, %exit1.unr-lcssa.loopexit ] ; EPILOG-NEXT: %iv.unr = phi i64 [ 0, %entry ], [ %iv.unr.ph, %exit1.unr-lcssa.loopexit ]
; EPILOG-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0 ; EPILOG-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0
Show All 38 Lines
; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.1, %loop_latch.1 ] ; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.1, %loop_latch.1 ]
; EPILOG-BLOCK-NEXT: call void @bar() ; EPILOG-BLOCK-NEXT: call void @bar()
; EPILOG-BLOCK-NEXT: %cmp_early = icmp ne i64 %iv, %trip2 ; EPILOG-BLOCK-NEXT: %cmp_early = icmp ne i64 %iv, %trip2
; EPILOG-BLOCK-NEXT: br i1 %cmp_early, label %loop_exiting_bb2, label %exit1.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cmp_early, label %loop_exiting_bb2, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_exiting_bb2: ; EPILOG-BLOCK: loop_exiting_bb2:
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch, label %exit1.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_latch: ; EPILOG-BLOCK: loop_latch:
; EPILOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1 ; EPILOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: call void @bar() ; EPILOG-BLOCK-NEXT: call void @bar()
; EPILOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2 ; EPILOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; EPILOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_exiting_bb2.1: ; EPILOG-BLOCK: loop_exiting_bb2.1:
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_latch.1: ; EPILOG-BLOCK: loop_latch.1:
; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit1.unr-lcssa.loopexit, !llvm.loop !18 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit1.unr-lcssa.loopexit, !llvm.loop !18
; EPILOG-BLOCK: exit1.unr-lcssa.loopexit: ; EPILOG-BLOCK: exit1.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: %iv.unr.ph = phi i64 [ %iv_next.1, %loop_latch.1 ] ; EPILOG-BLOCK-NEXT: %iv.unr.ph = phi i64 [ %iv_next.1, %loop_latch.1 ]
; EPILOG-BLOCK-NEXT: br label %exit1.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %exit1.unr-lcssa
; EPILOG-BLOCK: exit1.unr-lcssa: ; EPILOG-BLOCK: exit1.unr-lcssa:
; EPILOG-BLOCK-NEXT: %iv.unr = phi i64 [ 0, %entry ], [ %iv.unr.ph, %exit1.unr-lcssa.loopexit ] ; EPILOG-BLOCK-NEXT: %iv.unr = phi i64 [ 0, %entry ], [ %iv.unr.ph, %exit1.unr-lcssa.loopexit ]
; EPILOG-BLOCK-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0 ; EPILOG-BLOCK-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; PROLOG: loop_latch: ; PROLOG: loop_latch:
; PROLOG-NEXT: %iv_next = add i64 %iv, 1 ; PROLOG-NEXT: %iv_next = add i64 %iv, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2 ; PROLOG-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; PROLOG-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.1: ; PROLOG: loop_exiting_bb2.1:
; PROLOG-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.1: ; PROLOG: loop_latch.1:
; PROLOG-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; PROLOG-NEXT: %iv_next.1 = add i64 %iv, 2
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.2 = icmp ne i64 %iv_next.1, %trip2 ; PROLOG-NEXT: %cmp_early.2 = icmp ne i64 %iv_next.1, %trip2
; PROLOG-NEXT: br i1 %cmp_early.2, label %loop_exiting_bb2.2, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.2, label %loop_exiting_bb2.2, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.2: ; PROLOG: loop_exiting_bb2.2:
; PROLOG-NEXT: br i1 %cond, label %loop_latch.2, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.2, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.2: ; PROLOG: loop_latch.2:
; PROLOG-NEXT: %iv_next.2 = add i64 %iv_next.1, 1 ; PROLOG-NEXT: %iv_next.2 = add i64 %iv, 3
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.3 = icmp ne i64 %iv_next.2, %trip2 ; PROLOG-NEXT: %cmp_early.3 = icmp ne i64 %iv_next.2, %trip2
; PROLOG-NEXT: br i1 %cmp_early.3, label %loop_exiting_bb2.3, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.3, label %loop_exiting_bb2.3, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.3: ; PROLOG: loop_exiting_bb2.3:
; PROLOG-NEXT: br i1 %cond, label %loop_latch.3, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.3, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.3: ; PROLOG: loop_latch.3:
; PROLOG-NEXT: %iv_next.3 = add i64 %iv_next.2, 1 ; PROLOG-NEXT: %iv_next.3 = add i64 %iv, 4
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.4 = icmp ne i64 %iv_next.3, %trip2 ; PROLOG-NEXT: %cmp_early.4 = icmp ne i64 %iv_next.3, %trip2
; PROLOG-NEXT: br i1 %cmp_early.4, label %loop_exiting_bb2.4, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.4, label %loop_exiting_bb2.4, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.4: ; PROLOG: loop_exiting_bb2.4:
; PROLOG-NEXT: br i1 %cond, label %loop_latch.4, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.4, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.4: ; PROLOG: loop_latch.4:
; PROLOG-NEXT: %iv_next.4 = add i64 %iv_next.3, 1 ; PROLOG-NEXT: %iv_next.4 = add i64 %iv, 5
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.5 = icmp ne i64 %iv_next.4, %trip2 ; PROLOG-NEXT: %cmp_early.5 = icmp ne i64 %iv_next.4, %trip2
; PROLOG-NEXT: br i1 %cmp_early.5, label %loop_exiting_bb2.5, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.5, label %loop_exiting_bb2.5, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.5: ; PROLOG: loop_exiting_bb2.5:
; PROLOG-NEXT: br i1 %cond, label %loop_latch.5, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.5, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.5: ; PROLOG: loop_latch.5:
; PROLOG-NEXT: %iv_next.5 = add i64 %iv_next.4, 1 ; PROLOG-NEXT: %iv_next.5 = add i64 %iv, 6
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.6 = icmp ne i64 %iv_next.5, %trip2 ; PROLOG-NEXT: %cmp_early.6 = icmp ne i64 %iv_next.5, %trip2
; PROLOG-NEXT: br i1 %cmp_early.6, label %loop_exiting_bb2.6, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.6, label %loop_exiting_bb2.6, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.6: ; PROLOG: loop_exiting_bb2.6:
; PROLOG-NEXT: br i1 %cond, label %loop_latch.6, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.6, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.6: ; PROLOG: loop_latch.6:
; PROLOG-NEXT: %iv_next.6 = add i64 %iv_next.5, 1 ; PROLOG-NEXT: %iv_next.6 = add i64 %iv, 7
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2 ; PROLOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2
; PROLOG-NEXT: br i1 %cmp_early.7, label %loop_exiting_bb2.7, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.7, label %loop_exiting_bb2.7, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.7: ; PROLOG: loop_exiting_bb2.7:
; PROLOG-NEXT: br i1 %cond, label %loop_latch.7, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_latch.7, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.7: ; PROLOG: loop_latch.7:
; PROLOG-NEXT: %iv_next.7 = add i64 %iv_next.6, 1 ; PROLOG-NEXT: %iv_next.7 = add i64 %iv, 8
; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip ; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip
; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit1.unr-lcssa.loopexit
; PROLOG: exit1.unr-lcssa.loopexit: ; PROLOG: exit1.unr-lcssa.loopexit:
; PROLOG-NEXT: br label %exit1.unr-lcssa ; PROLOG-NEXT: br label %exit1.unr-lcssa
; PROLOG: exit1.unr-lcssa.loopexit1: ; PROLOG: exit1.unr-lcssa.loopexit1:
; PROLOG-NEXT: br label %exit1.unr-lcssa ; PROLOG-NEXT: br label %exit1.unr-lcssa
; PROLOG: exit1.unr-lcssa: ; PROLOG: exit1.unr-lcssa:
; PROLOG-NEXT: br label %exit1 ; PROLOG-NEXT: br label %exit1
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; PROLOG-BLOCK: loop_latch: ; PROLOG-BLOCK: loop_latch:
; PROLOG-BLOCK-NEXT: %iv_next = add i64 %iv, 1 ; PROLOG-BLOCK-NEXT: %iv_next = add i64 %iv, 1
; PROLOG-BLOCK-NEXT: call void @bar() ; PROLOG-BLOCK-NEXT: call void @bar()
; PROLOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2 ; PROLOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; PROLOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.unr-lcssa.loopexit ; PROLOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.unr-lcssa.loopexit
; PROLOG-BLOCK: loop_exiting_bb2.1: ; PROLOG-BLOCK: loop_exiting_bb2.1:
; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.unr-lcssa.loopexit ; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_latch.1, label %exit1.unr-lcssa.loopexit
; PROLOG-BLOCK: loop_latch.1: ; PROLOG-BLOCK: loop_latch.1:
; PROLOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; PROLOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit1.unr-lcssa.loopexit, !llvm.loop !18 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit1.unr-lcssa.loopexit, !llvm.loop !18
; PROLOG-BLOCK: exit1.unr-lcssa.loopexit: ; PROLOG-BLOCK: exit1.unr-lcssa.loopexit:
; PROLOG-BLOCK-NEXT: br label %exit1.unr-lcssa ; PROLOG-BLOCK-NEXT: br label %exit1.unr-lcssa
; PROLOG-BLOCK: exit1.unr-lcssa: ; PROLOG-BLOCK: exit1.unr-lcssa:
; PROLOG-BLOCK-NEXT: br label %exit1 ; PROLOG-BLOCK-NEXT: br label %exit1
; PROLOG-BLOCK: exit1: ; PROLOG-BLOCK: exit1:
; PROLOG-BLOCK-NEXT: ret void ; PROLOG-BLOCK-NEXT: ret void
Show All 39 Lines
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early = icmp ne i64 %iv, %trip2 ; EPILOG-NEXT: %cmp_early = icmp ne i64 %iv, %trip2
; EPILOG-NEXT: br i1 %cmp_early, label %loop_exiting_bb2, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early, label %loop_exiting_bb2, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2: ; EPILOG: loop_exiting_bb2:
; EPILOG-NEXT: %unknown = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown, label %loop_latch, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown, label %loop_latch, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch: ; EPILOG: loop_latch:
; EPILOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1 ; EPILOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2 ; EPILOG-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; EPILOG-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.1: ; EPILOG: loop_exiting_bb2.1:
; EPILOG-NEXT: %unknown.1 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.1 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.1: ; EPILOG: loop_latch.1:
; EPILOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1 ; EPILOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv, 2
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.2 = icmp ne i64 %iv_next.1, %trip2 ; EPILOG-NEXT: %cmp_early.2 = icmp ne i64 %iv_next.1, %trip2
; EPILOG-NEXT: br i1 %cmp_early.2, label %loop_exiting_bb2.2, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.2, label %loop_exiting_bb2.2, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.2: ; EPILOG: loop_exiting_bb2.2:
; EPILOG-NEXT: %unknown.2 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.2 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.2, label %loop_latch.2, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.2, label %loop_latch.2, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.2: ; EPILOG: loop_latch.2:
; EPILOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv_next.1, 1 ; EPILOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv, 3
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.3 = icmp ne i64 %iv_next.2, %trip2 ; EPILOG-NEXT: %cmp_early.3 = icmp ne i64 %iv_next.2, %trip2
; EPILOG-NEXT: br i1 %cmp_early.3, label %loop_exiting_bb2.3, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.3, label %loop_exiting_bb2.3, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.3: ; EPILOG: loop_exiting_bb2.3:
; EPILOG-NEXT: %unknown.3 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.3 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.3, label %loop_latch.3, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.3, label %loop_latch.3, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.3: ; EPILOG: loop_latch.3:
; EPILOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv_next.2, 1 ; EPILOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv, 4
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.4 = icmp ne i64 %iv_next.3, %trip2 ; EPILOG-NEXT: %cmp_early.4 = icmp ne i64 %iv_next.3, %trip2
; EPILOG-NEXT: br i1 %cmp_early.4, label %loop_exiting_bb2.4, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.4, label %loop_exiting_bb2.4, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.4: ; EPILOG: loop_exiting_bb2.4:
; EPILOG-NEXT: %unknown.4 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.4 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.4, label %loop_latch.4, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.4, label %loop_latch.4, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.4: ; EPILOG: loop_latch.4:
; EPILOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv_next.3, 1 ; EPILOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv, 5
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.5 = icmp ne i64 %iv_next.4, %trip2 ; EPILOG-NEXT: %cmp_early.5 = icmp ne i64 %iv_next.4, %trip2
; EPILOG-NEXT: br i1 %cmp_early.5, label %loop_exiting_bb2.5, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.5, label %loop_exiting_bb2.5, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.5: ; EPILOG: loop_exiting_bb2.5:
; EPILOG-NEXT: %unknown.5 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.5 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.5, label %loop_latch.5, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.5, label %loop_latch.5, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.5: ; EPILOG: loop_latch.5:
; EPILOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv_next.4, 1 ; EPILOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv, 6
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.6 = icmp ne i64 %iv_next.5, %trip2 ; EPILOG-NEXT: %cmp_early.6 = icmp ne i64 %iv_next.5, %trip2
; EPILOG-NEXT: br i1 %cmp_early.6, label %loop_exiting_bb2.6, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.6, label %loop_exiting_bb2.6, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.6: ; EPILOG: loop_exiting_bb2.6:
; EPILOG-NEXT: %unknown.6 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.6 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.6, label %loop_latch.6, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.6, label %loop_latch.6, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.6: ; EPILOG: loop_latch.6:
; EPILOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv_next.5, 1 ; EPILOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv, 7
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2 ; EPILOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2
; EPILOG-NEXT: br i1 %cmp_early.7, label %loop_exiting_bb2.7, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cmp_early.7, label %loop_exiting_bb2.7, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.7: ; EPILOG: loop_exiting_bb2.7:
; EPILOG-NEXT: %unknown.7 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.7 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.7, label %loop_latch.7, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.7, label %loop_latch.7, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.7: ; EPILOG: loop_latch.7:
; EPILOG-NEXT: %iv_next.7 = add i64 %iv_next.6, 1 ; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit1.unr-lcssa.loopexit ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit1.unr-lcssa.loopexit
; EPILOG: exit1.unr-lcssa.loopexit: ; EPILOG: exit1.unr-lcssa.loopexit:
; EPILOG-NEXT: %iv.unr.ph = phi i64 [ %iv_next.7, %loop_latch.7 ] ; EPILOG-NEXT: %iv.unr.ph = phi i64 [ %iv_next.7, %loop_latch.7 ]
; EPILOG-NEXT: br label %exit1.unr-lcssa ; EPILOG-NEXT: br label %exit1.unr-lcssa
; EPILOG: exit1.unr-lcssa: ; EPILOG: exit1.unr-lcssa:
; EPILOG-NEXT: %iv.unr = phi i64 [ 0, %entry ], [ %iv.unr.ph, %exit1.unr-lcssa.loopexit ] ; EPILOG-NEXT: %iv.unr = phi i64 [ 0, %entry ], [ %iv.unr.ph, %exit1.unr-lcssa.loopexit ]
; EPILOG-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0 ; EPILOG-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0
Show All 40 Lines
; EPILOG-BLOCK-NEXT: call void @bar() ; EPILOG-BLOCK-NEXT: call void @bar()
; EPILOG-BLOCK-NEXT: %cmp_early = icmp ne i64 %iv, %trip2 ; EPILOG-BLOCK-NEXT: %cmp_early = icmp ne i64 %iv, %trip2
; EPILOG-BLOCK-NEXT: br i1 %cmp_early, label %loop_exiting_bb2, label %exit1.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cmp_early, label %loop_exiting_bb2, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_exiting_bb2: ; EPILOG-BLOCK: loop_exiting_bb2:
; EPILOG-BLOCK-NEXT: %unknown = call i1 @unknown_cond() ; EPILOG-BLOCK-NEXT: %unknown = call i1 @unknown_cond()
; EPILOG-BLOCK-NEXT: br i1 %unknown, label %loop_latch, label %exit1.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %unknown, label %loop_latch, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_latch: ; EPILOG-BLOCK: loop_latch:
; EPILOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1 ; EPILOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: call void @bar() ; EPILOG-BLOCK-NEXT: call void @bar()
; EPILOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2 ; EPILOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; EPILOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_exiting_bb2.1: ; EPILOG-BLOCK: loop_exiting_bb2.1:
; EPILOG-BLOCK-NEXT: %unknown.1 = call i1 @unknown_cond() ; EPILOG-BLOCK-NEXT: %unknown.1 = call i1 @unknown_cond()
; EPILOG-BLOCK-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_latch.1: ; EPILOG-BLOCK: loop_latch.1:
; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit1.unr-lcssa.loopexit, !llvm.loop !19 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit1.unr-lcssa.loopexit, !llvm.loop !19
; EPILOG-BLOCK: exit1.unr-lcssa.loopexit: ; EPILOG-BLOCK: exit1.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: %iv.unr.ph = phi i64 [ %iv_next.1, %loop_latch.1 ] ; EPILOG-BLOCK-NEXT: %iv.unr.ph = phi i64 [ %iv_next.1, %loop_latch.1 ]
; EPILOG-BLOCK-NEXT: br label %exit1.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %exit1.unr-lcssa
; EPILOG-BLOCK: exit1.unr-lcssa: ; EPILOG-BLOCK: exit1.unr-lcssa:
; EPILOG-BLOCK-NEXT: %iv.unr = phi i64 [ 0, %entry ], [ %iv.unr.ph, %exit1.unr-lcssa.loopexit ] ; EPILOG-BLOCK-NEXT: %iv.unr = phi i64 [ 0, %entry ], [ %iv.unr.ph, %exit1.unr-lcssa.loopexit ]
; EPILOG-BLOCK-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0 ; EPILOG-BLOCK-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; PROLOG-NEXT: %iv_next = add i64 %iv, 1 ; PROLOG-NEXT: %iv_next = add i64 %iv, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2 ; PROLOG-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; PROLOG-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.1: ; PROLOG: loop_exiting_bb2.1:
; PROLOG-NEXT: %unknown.1 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.1 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.1: ; PROLOG: loop_latch.1:
; PROLOG-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; PROLOG-NEXT: %iv_next.1 = add i64 %iv, 2
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.2 = icmp ne i64 %iv_next.1, %trip2 ; PROLOG-NEXT: %cmp_early.2 = icmp ne i64 %iv_next.1, %trip2
; PROLOG-NEXT: br i1 %cmp_early.2, label %loop_exiting_bb2.2, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.2, label %loop_exiting_bb2.2, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.2: ; PROLOG: loop_exiting_bb2.2:
; PROLOG-NEXT: %unknown.2 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.2 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.2, label %loop_latch.2, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.2, label %loop_latch.2, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.2: ; PROLOG: loop_latch.2:
; PROLOG-NEXT: %iv_next.2 = add i64 %iv_next.1, 1 ; PROLOG-NEXT: %iv_next.2 = add i64 %iv, 3
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.3 = icmp ne i64 %iv_next.2, %trip2 ; PROLOG-NEXT: %cmp_early.3 = icmp ne i64 %iv_next.2, %trip2
; PROLOG-NEXT: br i1 %cmp_early.3, label %loop_exiting_bb2.3, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.3, label %loop_exiting_bb2.3, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.3: ; PROLOG: loop_exiting_bb2.3:
; PROLOG-NEXT: %unknown.3 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.3 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.3, label %loop_latch.3, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.3, label %loop_latch.3, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.3: ; PROLOG: loop_latch.3:
; PROLOG-NEXT: %iv_next.3 = add i64 %iv_next.2, 1 ; PROLOG-NEXT: %iv_next.3 = add i64 %iv, 4
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.4 = icmp ne i64 %iv_next.3, %trip2 ; PROLOG-NEXT: %cmp_early.4 = icmp ne i64 %iv_next.3, %trip2
; PROLOG-NEXT: br i1 %cmp_early.4, label %loop_exiting_bb2.4, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.4, label %loop_exiting_bb2.4, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.4: ; PROLOG: loop_exiting_bb2.4:
; PROLOG-NEXT: %unknown.4 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.4 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.4, label %loop_latch.4, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.4, label %loop_latch.4, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.4: ; PROLOG: loop_latch.4:
; PROLOG-NEXT: %iv_next.4 = add i64 %iv_next.3, 1 ; PROLOG-NEXT: %iv_next.4 = add i64 %iv, 5
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.5 = icmp ne i64 %iv_next.4, %trip2 ; PROLOG-NEXT: %cmp_early.5 = icmp ne i64 %iv_next.4, %trip2
; PROLOG-NEXT: br i1 %cmp_early.5, label %loop_exiting_bb2.5, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.5, label %loop_exiting_bb2.5, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.5: ; PROLOG: loop_exiting_bb2.5:
; PROLOG-NEXT: %unknown.5 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.5 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.5, label %loop_latch.5, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.5, label %loop_latch.5, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.5: ; PROLOG: loop_latch.5:
; PROLOG-NEXT: %iv_next.5 = add i64 %iv_next.4, 1 ; PROLOG-NEXT: %iv_next.5 = add i64 %iv, 6
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.6 = icmp ne i64 %iv_next.5, %trip2 ; PROLOG-NEXT: %cmp_early.6 = icmp ne i64 %iv_next.5, %trip2
; PROLOG-NEXT: br i1 %cmp_early.6, label %loop_exiting_bb2.6, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.6, label %loop_exiting_bb2.6, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.6: ; PROLOG: loop_exiting_bb2.6:
; PROLOG-NEXT: %unknown.6 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.6 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.6, label %loop_latch.6, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.6, label %loop_latch.6, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.6: ; PROLOG: loop_latch.6:
; PROLOG-NEXT: %iv_next.6 = add i64 %iv_next.5, 1 ; PROLOG-NEXT: %iv_next.6 = add i64 %iv, 7
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2 ; PROLOG-NEXT: %cmp_early.7 = icmp ne i64 %iv_next.6, %trip2
; PROLOG-NEXT: br i1 %cmp_early.7, label %loop_exiting_bb2.7, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp_early.7, label %loop_exiting_bb2.7, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.7: ; PROLOG: loop_exiting_bb2.7:
; PROLOG-NEXT: %unknown.7 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.7 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.7, label %loop_latch.7, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.7, label %loop_latch.7, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.7: ; PROLOG: loop_latch.7:
; PROLOG-NEXT: %iv_next.7 = add i64 %iv_next.6, 1 ; PROLOG-NEXT: %iv_next.7 = add i64 %iv, 8
; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip ; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip
; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit1.unr-lcssa.loopexit
; PROLOG: exit1.unr-lcssa.loopexit: ; PROLOG: exit1.unr-lcssa.loopexit:
; PROLOG-NEXT: br label %exit1.unr-lcssa ; PROLOG-NEXT: br label %exit1.unr-lcssa
; PROLOG: exit1.unr-lcssa.loopexit1: ; PROLOG: exit1.unr-lcssa.loopexit1:
; PROLOG-NEXT: br label %exit1.unr-lcssa ; PROLOG-NEXT: br label %exit1.unr-lcssa
; PROLOG: exit1.unr-lcssa: ; PROLOG: exit1.unr-lcssa:
; PROLOG-NEXT: br label %exit1 ; PROLOG-NEXT: br label %exit1
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; PROLOG-BLOCK-NEXT: %iv_next = add i64 %iv, 1 ; PROLOG-BLOCK-NEXT: %iv_next = add i64 %iv, 1
; PROLOG-BLOCK-NEXT: call void @bar() ; PROLOG-BLOCK-NEXT: call void @bar()
; PROLOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2 ; PROLOG-BLOCK-NEXT: %cmp_early.1 = icmp ne i64 %iv_next, %trip2
; PROLOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.unr-lcssa.loopexit ; PROLOG-BLOCK-NEXT: br i1 %cmp_early.1, label %loop_exiting_bb2.1, label %exit1.unr-lcssa.loopexit
; PROLOG-BLOCK: loop_exiting_bb2.1: ; PROLOG-BLOCK: loop_exiting_bb2.1:
; PROLOG-BLOCK-NEXT: %unknown.1 = call i1 @unknown_cond() ; PROLOG-BLOCK-NEXT: %unknown.1 = call i1 @unknown_cond()
; PROLOG-BLOCK-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.unr-lcssa.loopexit ; PROLOG-BLOCK-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.unr-lcssa.loopexit
; PROLOG-BLOCK: loop_latch.1: ; PROLOG-BLOCK: loop_latch.1:
; PROLOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; PROLOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit1.unr-lcssa.loopexit, !llvm.loop !19 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit1.unr-lcssa.loopexit, !llvm.loop !19
; PROLOG-BLOCK: exit1.unr-lcssa.loopexit: ; PROLOG-BLOCK: exit1.unr-lcssa.loopexit:
; PROLOG-BLOCK-NEXT: br label %exit1.unr-lcssa ; PROLOG-BLOCK-NEXT: br label %exit1.unr-lcssa
; PROLOG-BLOCK: exit1.unr-lcssa: ; PROLOG-BLOCK: exit1.unr-lcssa:
; PROLOG-BLOCK-NEXT: br label %exit1 ; PROLOG-BLOCK-NEXT: br label %exit1
; PROLOG-BLOCK: exit1: ; PROLOG-BLOCK: exit1:
; PROLOG-BLOCK-NEXT: ret void ; PROLOG-BLOCK-NEXT: ret void
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; EPILOG-NEXT: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.7, %loop_latch.7 ] ; EPILOG-NEXT: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.7, %loop_latch.7 ]
; EPILOG-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.7, %loop_latch.7 ] ; EPILOG-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.7, %loop_latch.7 ]
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2: ; EPILOG: loop_exiting_bb2:
; EPILOG-NEXT: %unknown = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown, label %loop_latch, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown, label %loop_latch, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch: ; EPILOG: loop_latch:
; EPILOG-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.1, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.1, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.1: ; EPILOG: loop_exiting_bb2.1:
; EPILOG-NEXT: %unknown.1 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.1 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.1: ; EPILOG: loop_latch.1:
; EPILOG-NEXT: %iv_next.1 = add nuw nsw i64 %iv_next, 1
; EPILOG-NEXT: %niter.next.1 = add nuw nsw i64 %niter.next, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.2, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.2, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.2: ; EPILOG: loop_exiting_bb2.2:
; EPILOG-NEXT: %unknown.2 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.2 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.2, label %loop_latch.2, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.2, label %loop_latch.2, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.2: ; EPILOG: loop_latch.2:
; EPILOG-NEXT: %iv_next.2 = add nuw nsw i64 %iv_next.1, 1
; EPILOG-NEXT: %niter.next.2 = add nuw nsw i64 %niter.next.1, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.3, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.3, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.3: ; EPILOG: loop_exiting_bb2.3:
; EPILOG-NEXT: %unknown.3 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.3 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.3, label %loop_latch.3, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.3, label %loop_latch.3, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.3: ; EPILOG: loop_latch.3:
; EPILOG-NEXT: %iv_next.3 = add nuw nsw i64 %iv_next.2, 1
; EPILOG-NEXT: %niter.next.3 = add nuw nsw i64 %niter.next.2, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.4, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.4, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.4: ; EPILOG: loop_exiting_bb2.4:
; EPILOG-NEXT: %unknown.4 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.4 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.4, label %loop_latch.4, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.4, label %loop_latch.4, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.4: ; EPILOG: loop_latch.4:
; EPILOG-NEXT: %iv_next.4 = add nuw nsw i64 %iv_next.3, 1
; EPILOG-NEXT: %niter.next.4 = add nuw nsw i64 %niter.next.3, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.5, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.5, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.5: ; EPILOG: loop_exiting_bb2.5:
; EPILOG-NEXT: %unknown.5 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.5 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.5, label %loop_latch.5, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.5, label %loop_latch.5, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.5: ; EPILOG: loop_latch.5:
; EPILOG-NEXT: %iv_next.5 = add nuw nsw i64 %iv_next.4, 1
; EPILOG-NEXT: %niter.next.5 = add nuw nsw i64 %niter.next.4, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.6, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.6, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.6: ; EPILOG: loop_exiting_bb2.6:
; EPILOG-NEXT: %unknown.6 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.6 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.6, label %loop_latch.6, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.6, label %loop_latch.6, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.6: ; EPILOG: loop_latch.6:
; EPILOG-NEXT: %iv_next.6 = add nuw nsw i64 %iv_next.5, 1
; EPILOG-NEXT: %niter.next.6 = add nuw nsw i64 %niter.next.5, 1
; EPILOG-NEXT: call void @bar() ; EPILOG-NEXT: call void @bar()
; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.7, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %cond, label %loop_exiting_bb2.7, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_exiting_bb2.7: ; EPILOG: loop_exiting_bb2.7:
; EPILOG-NEXT: %unknown.7 = call i1 @unknown_cond() ; EPILOG-NEXT: %unknown.7 = call i1 @unknown_cond()
; EPILOG-NEXT: br i1 %unknown.7, label %loop_latch.7, label %exit1.epilog-lcssa.loopexit ; EPILOG-NEXT: br i1 %unknown.7, label %loop_latch.7, label %exit1.epilog-lcssa.loopexit
; EPILOG: loop_latch.7: ; EPILOG: loop_latch.7:
; EPILOG-NEXT: %iv_next.7 = add i64 %iv_next.6, 1 ; EPILOG-NEXT: %iv_next.7 = add i64 %iv, 8
; EPILOG-NEXT: %niter.next.7 = add i64 %niter.next.6, 1 ; EPILOG-NEXT: %niter.next.7 = add i64 %niter, 8
; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter ; EPILOG-NEXT: %niter.ncmp.7 = icmp ne i64 %niter.next.7, %unroll_iter
; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit1.unr-lcssa.loopexit ; EPILOG-NEXT: br i1 %niter.ncmp.7, label %loop_header, label %exit1.unr-lcssa.loopexit
; EPILOG: exit1.unr-lcssa.loopexit: ; EPILOG: exit1.unr-lcssa.loopexit:
; EPILOG-NEXT: %iv.unr.ph = phi i64 [ %iv_next.7, %loop_latch.7 ] ; EPILOG-NEXT: %iv.unr.ph = phi i64 [ %iv_next.7, %loop_latch.7 ]
; EPILOG-NEXT: br label %exit1.unr-lcssa ; EPILOG-NEXT: br label %exit1.unr-lcssa
; EPILOG: exit1.unr-lcssa: ; EPILOG: exit1.unr-lcssa:
; EPILOG-NEXT: %iv.unr = phi i64 [ 0, %entry ], [ %iv.unr.ph, %exit1.unr-lcssa.loopexit ] ; EPILOG-NEXT: %iv.unr = phi i64 [ 0, %entry ], [ %iv.unr.ph, %exit1.unr-lcssa.loopexit ]
; EPILOG-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0 ; EPILOG-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0
Show All 37 Lines
; EPILOG-BLOCK-NEXT: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.1, %loop_latch.1 ] ; EPILOG-BLOCK-NEXT: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.1, %loop_latch.1 ]
; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.1, %loop_latch.1 ] ; EPILOG-BLOCK-NEXT: %niter = phi i64 [ 0, %entry.new ], [ %niter.next.1, %loop_latch.1 ]
; EPILOG-BLOCK-NEXT: call void @bar() ; EPILOG-BLOCK-NEXT: call void @bar()
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_exiting_bb2, label %exit1.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_exiting_bb2, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_exiting_bb2: ; EPILOG-BLOCK: loop_exiting_bb2:
; EPILOG-BLOCK-NEXT: %unknown = call i1 @unknown_cond() ; EPILOG-BLOCK-NEXT: %unknown = call i1 @unknown_cond()
; EPILOG-BLOCK-NEXT: br i1 %unknown, label %loop_latch, label %exit1.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %unknown, label %loop_latch, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_latch: ; EPILOG-BLOCK: loop_latch:
; EPILOG-BLOCK-NEXT: %iv_next = add nuw nsw i64 %iv, 1
; EPILOG-BLOCK-NEXT: %niter.next = add nuw nsw i64 %niter, 1
; EPILOG-BLOCK-NEXT: call void @bar() ; EPILOG-BLOCK-NEXT: call void @bar()
; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_exiting_bb2.1, label %exit1.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %cond, label %loop_exiting_bb2.1, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_exiting_bb2.1: ; EPILOG-BLOCK: loop_exiting_bb2.1:
; EPILOG-BLOCK-NEXT: %unknown.1 = call i1 @unknown_cond() ; EPILOG-BLOCK-NEXT: %unknown.1 = call i1 @unknown_cond()
; EPILOG-BLOCK-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit ; EPILOG-BLOCK-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.epilog-lcssa.loopexit
; EPILOG-BLOCK: loop_latch.1: ; EPILOG-BLOCK: loop_latch.1:
; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; EPILOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter.next, 1 ; EPILOG-BLOCK-NEXT: %niter.next.1 = add i64 %niter, 2
; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter ; EPILOG-BLOCK-NEXT: %niter.ncmp.1 = icmp ne i64 %niter.next.1, %unroll_iter
; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit1.unr-lcssa.loopexit, !llvm.loop !20 ; EPILOG-BLOCK-NEXT: br i1 %niter.ncmp.1, label %loop_header, label %exit1.unr-lcssa.loopexit, !llvm.loop !20
; EPILOG-BLOCK: exit1.unr-lcssa.loopexit: ; EPILOG-BLOCK: exit1.unr-lcssa.loopexit:
; EPILOG-BLOCK-NEXT: br label %exit1.unr-lcssa ; EPILOG-BLOCK-NEXT: br label %exit1.unr-lcssa
; EPILOG-BLOCK: exit1.unr-lcssa: ; EPILOG-BLOCK: exit1.unr-lcssa:
; EPILOG-BLOCK-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0 ; EPILOG-BLOCK-NEXT: %lcmp.mod = icmp ne i64 %xtraiter, 0
; EPILOG-BLOCK-NEXT: br i1 %lcmp.mod, label %loop_header.epil.preheader, label %exit1 ; EPILOG-BLOCK-NEXT: br i1 %lcmp.mod, label %loop_header.epil.preheader, label %exit1
; EPILOG-BLOCK: loop_header.epil.preheader: ; EPILOG-BLOCK: loop_header.epil.preheader:
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; PROLOG: loop_header: ; PROLOG: loop_header:
; PROLOG-NEXT: %iv = phi i64 [ %iv.unr, %entry.new ], [ %iv_next.7, %loop_latch.7 ] ; PROLOG-NEXT: %iv = phi i64 [ %iv.unr, %entry.new ], [ %iv_next.7, %loop_latch.7 ]
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2: ; PROLOG: loop_exiting_bb2:
; PROLOG-NEXT: %unknown = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown, label %loop_latch, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown, label %loop_latch, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch: ; PROLOG: loop_latch:
; PROLOG-NEXT: %iv_next = add i64 %iv, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.1, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.1, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.1: ; PROLOG: loop_exiting_bb2.1:
; PROLOG-NEXT: %unknown.1 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.1 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.1: ; PROLOG: loop_latch.1:
; PROLOG-NEXT: %iv_next.1 = add i64 %iv_next, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.2, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.2, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.2: ; PROLOG: loop_exiting_bb2.2:
; PROLOG-NEXT: %unknown.2 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.2 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.2, label %loop_latch.2, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.2, label %loop_latch.2, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.2: ; PROLOG: loop_latch.2:
; PROLOG-NEXT: %iv_next.2 = add i64 %iv_next.1, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.3, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.3, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.3: ; PROLOG: loop_exiting_bb2.3:
; PROLOG-NEXT: %unknown.3 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.3 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.3, label %loop_latch.3, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.3, label %loop_latch.3, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.3: ; PROLOG: loop_latch.3:
; PROLOG-NEXT: %iv_next.3 = add i64 %iv_next.2, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.4, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.4, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.4: ; PROLOG: loop_exiting_bb2.4:
; PROLOG-NEXT: %unknown.4 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.4 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.4, label %loop_latch.4, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.4, label %loop_latch.4, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.4: ; PROLOG: loop_latch.4:
; PROLOG-NEXT: %iv_next.4 = add i64 %iv_next.3, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.5, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.5, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.5: ; PROLOG: loop_exiting_bb2.5:
; PROLOG-NEXT: %unknown.5 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.5 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.5, label %loop_latch.5, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.5, label %loop_latch.5, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.5: ; PROLOG: loop_latch.5:
; PROLOG-NEXT: %iv_next.5 = add i64 %iv_next.4, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.6, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.6, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.6: ; PROLOG: loop_exiting_bb2.6:
; PROLOG-NEXT: %unknown.6 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.6 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.6, label %loop_latch.6, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.6, label %loop_latch.6, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.6: ; PROLOG: loop_latch.6:
; PROLOG-NEXT: %iv_next.6 = add i64 %iv_next.5, 1
; PROLOG-NEXT: call void @bar() ; PROLOG-NEXT: call void @bar()
; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.7, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cond, label %loop_exiting_bb2.7, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_exiting_bb2.7: ; PROLOG: loop_exiting_bb2.7:
; PROLOG-NEXT: %unknown.7 = call i1 @unknown_cond() ; PROLOG-NEXT: %unknown.7 = call i1 @unknown_cond()
; PROLOG-NEXT: br i1 %unknown.7, label %loop_latch.7, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %unknown.7, label %loop_latch.7, label %exit1.unr-lcssa.loopexit
; PROLOG: loop_latch.7: ; PROLOG: loop_latch.7:
; PROLOG-NEXT: %iv_next.7 = add i64 %iv_next.6, 1 ; PROLOG-NEXT: %iv_next.7 = add i64 %iv, 8
; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip ; PROLOG-NEXT: %cmp.7 = icmp ne i64 %iv_next.7, %trip
; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit1.unr-lcssa.loopexit ; PROLOG-NEXT: br i1 %cmp.7, label %loop_header, label %exit1.unr-lcssa.loopexit
; PROLOG: exit1.unr-lcssa.loopexit: ; PROLOG: exit1.unr-lcssa.loopexit:
; PROLOG-NEXT: br label %exit1.unr-lcssa ; PROLOG-NEXT: br label %exit1.unr-lcssa
; PROLOG: exit1.unr-lcssa.loopexit1: ; PROLOG: exit1.unr-lcssa.loopexit1:
; PROLOG-NEXT: br label %exit1.unr-lcssa ; PROLOG-NEXT: br label %exit1.unr-lcssa
; PROLOG: exit1.unr-lcssa: ; PROLOG: exit1.unr-lcssa:
; PROLOG-NEXT: br label %exit1 ; PROLOG-NEXT: br label %exit1
Show All 26 Lines
; PROLOG-BLOCK: loop_header: ; PROLOG-BLOCK: loop_header:
; PROLOG-BLOCK-NEXT: %iv = phi i64 [ %iv.unr, %entry.new ], [ %iv_next.1, %loop_latch.1 ] ; PROLOG-BLOCK-NEXT: %iv = phi i64 [ %iv.unr, %entry.new ], [ %iv_next.1, %loop_latch.1 ]
; PROLOG-BLOCK-NEXT: call void @bar() ; PROLOG-BLOCK-NEXT: call void @bar()
; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_exiting_bb2, label %exit1.unr-lcssa.loopexit ; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_exiting_bb2, label %exit1.unr-lcssa.loopexit
; PROLOG-BLOCK: loop_exiting_bb2: ; PROLOG-BLOCK: loop_exiting_bb2:
; PROLOG-BLOCK-NEXT: %unknown = call i1 @unknown_cond() ; PROLOG-BLOCK-NEXT: %unknown = call i1 @unknown_cond()
; PROLOG-BLOCK-NEXT: br i1 %unknown, label %loop_latch, label %exit1.unr-lcssa.loopexit ; PROLOG-BLOCK-NEXT: br i1 %unknown, label %loop_latch, label %exit1.unr-lcssa.loopexit
; PROLOG-BLOCK: loop_latch: ; PROLOG-BLOCK: loop_latch:
; PROLOG-BLOCK-NEXT: %iv_next = add i64 %iv, 1
; PROLOG-BLOCK-NEXT: call void @bar() ; PROLOG-BLOCK-NEXT: call void @bar()
; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_exiting_bb2.1, label %exit1.unr-lcssa.loopexit ; PROLOG-BLOCK-NEXT: br i1 %cond, label %loop_exiting_bb2.1, label %exit1.unr-lcssa.loopexit
; PROLOG-BLOCK: loop_exiting_bb2.1: ; PROLOG-BLOCK: loop_exiting_bb2.1:
; PROLOG-BLOCK-NEXT: %unknown.1 = call i1 @unknown_cond() ; PROLOG-BLOCK-NEXT: %unknown.1 = call i1 @unknown_cond()
; PROLOG-BLOCK-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.unr-lcssa.loopexit ; PROLOG-BLOCK-NEXT: br i1 %unknown.1, label %loop_latch.1, label %exit1.unr-lcssa.loopexit
; PROLOG-BLOCK: loop_latch.1: ; PROLOG-BLOCK: loop_latch.1:
; PROLOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv_next, 1 ; PROLOG-BLOCK-NEXT: %iv_next.1 = add i64 %iv, 2
; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip ; PROLOG-BLOCK-NEXT: %cmp.1 = icmp ne i64 %iv_next.1, %trip
; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit1.unr-lcssa.loopexit, !llvm.loop !20 ; PROLOG-BLOCK-NEXT: br i1 %cmp.1, label %loop_header, label %exit1.unr-lcssa.loopexit, !llvm.loop !20
; PROLOG-BLOCK: exit1.unr-lcssa.loopexit: ; PROLOG-BLOCK: exit1.unr-lcssa.loopexit:
; PROLOG-BLOCK-NEXT: br label %exit1.unr-lcssa ; PROLOG-BLOCK-NEXT: br label %exit1.unr-lcssa
; PROLOG-BLOCK: exit1.unr-lcssa: ; PROLOG-BLOCK: exit1.unr-lcssa:
; PROLOG-BLOCK-NEXT: br label %exit1 ; PROLOG-BLOCK-NEXT: br label %exit1
; PROLOG-BLOCK: exit1: ; PROLOG-BLOCK: exit1:
; PROLOG-BLOCK-NEXT: ret void ; PROLOG-BLOCK-NEXT: ret void
Show All 21 Lines

llvm/test/Transforms/LoopUnroll/runtime-loop5.ll

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; UNROLL-4: for.body: ; UNROLL-4: for.body:
; UNROLL-4-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_3:%.*]], [[FOR_BODY]] ] ; UNROLL-4-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_3:%.*]], [[FOR_BODY]] ]
; UNROLL-4-NEXT: [[SUM_02:%.*]] = phi i3 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[ADD_3:%.*]], [[FOR_BODY]] ] ; UNROLL-4-NEXT: [[SUM_02:%.*]] = phi i3 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[ADD_3:%.*]], [[FOR_BODY]] ]
; UNROLL-4-NEXT: [[NITER:%.*]] = phi i3 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_BODY]] ] ; UNROLL-4-NEXT: [[NITER:%.*]] = phi i3 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_BODY]] ]
; UNROLL-4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i3, ptr [[A:%.*]], i64 [[INDVARS_IV]] ; UNROLL-4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i3, ptr [[A:%.*]], i64 [[INDVARS_IV]]
; UNROLL-4-NEXT: [[TMP2:%.*]] = load i3, ptr [[ARRAYIDX]], align 1 ; UNROLL-4-NEXT: [[TMP2:%.*]] = load i3, ptr [[ARRAYIDX]], align 1
; UNROLL-4-NEXT: [[ADD:%.*]] = add nsw i3 [[TMP2]], [[SUM_02]] ; UNROLL-4-NEXT: [[ADD:%.*]] = add nsw i3 [[TMP2]], [[SUM_02]]
; UNROLL-4-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; UNROLL-4-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
; UNROLL-4-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i3 [[NITER]], 1
; UNROLL-4-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i3, ptr [[A]], i64 [[INDVARS_IV_NEXT]] ; UNROLL-4-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i3, ptr [[A]], i64 [[INDVARS_IV_NEXT]]
; UNROLL-4-NEXT: [[TMP3:%.*]] = load i3, ptr [[ARRAYIDX_1]], align 1 ; UNROLL-4-NEXT: [[TMP3:%.*]] = load i3, ptr [[ARRAYIDX_1]], align 1
; UNROLL-4-NEXT: [[ADD_1:%.*]] = add nsw i3 [[TMP3]], [[ADD]] ; UNROLL-4-NEXT: [[ADD_1:%.*]] = add nsw i3 [[TMP3]], [[ADD]]
; UNROLL-4-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1 ; UNROLL-4-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
; UNROLL-4-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i3 [[NITER_NEXT]], 1
; UNROLL-4-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i3, ptr [[A]], i64 [[INDVARS_IV_NEXT_1]] ; UNROLL-4-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i3, ptr [[A]], i64 [[INDVARS_IV_NEXT_1]]
; UNROLL-4-NEXT: [[TMP4:%.*]] = load i3, ptr [[ARRAYIDX_2]], align 1 ; UNROLL-4-NEXT: [[TMP4:%.*]] = load i3, ptr [[ARRAYIDX_2]], align 1
; UNROLL-4-NEXT: [[ADD_2:%.*]] = add nsw i3 [[TMP4]], [[ADD_1]] ; UNROLL-4-NEXT: [[ADD_2:%.*]] = add nsw i3 [[TMP4]], [[ADD_1]]
; UNROLL-4-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1 ; UNROLL-4-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 3
; UNROLL-4-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i3 [[NITER_NEXT_1]], 1
; UNROLL-4-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i3, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]] ; UNROLL-4-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i3, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]]
; UNROLL-4-NEXT: [[TMP5:%.*]] = load i3, ptr [[ARRAYIDX_3]], align 1 ; UNROLL-4-NEXT: [[TMP5:%.*]] = load i3, ptr [[ARRAYIDX_3]], align 1
; UNROLL-4-NEXT: [[ADD_3]] = add nsw i3 [[TMP5]], [[ADD_2]] ; UNROLL-4-NEXT: [[ADD_3]] = add nsw i3 [[TMP5]], [[ADD_2]]
; UNROLL-4-NEXT: [[INDVARS_IV_NEXT_3]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1 ; UNROLL-4-NEXT: [[INDVARS_IV_NEXT_3]] = add nuw nsw i64 [[INDVARS_IV]], 4
; UNROLL-4-NEXT: [[NITER_NEXT_3]] = add i3 [[NITER_NEXT_2]], 1 ; UNROLL-4-NEXT: [[NITER_NEXT_3]] = add i3 [[NITER]], -4
; UNROLL-4-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i3 [[NITER_NEXT_3]], [[UNROLL_ITER]] ; UNROLL-4-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i3 [[NITER_NEXT_3]], [[UNROLL_ITER]]
; UNROLL-4-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_END_LOOPEXIT_UNR_LCSSA_LOOPEXIT:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; UNROLL-4-NEXT: br i1 [[NITER_NCMP_3]], label [[FOR_END_LOOPEXIT_UNR_LCSSA_LOOPEXIT:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; UNROLL-4: for.end.loopexit.unr-lcssa.loopexit: ; UNROLL-4: for.end.loopexit.unr-lcssa.loopexit:
; UNROLL-4-NEXT: [[ADD_LCSSA_PH_PH:%.*]] = phi i3 [ [[ADD_3]], [[FOR_BODY]] ] ; UNROLL-4-NEXT: [[ADD_LCSSA_PH_PH:%.*]] = phi i3 [ [[ADD_3]], [[FOR_BODY]] ]
; UNROLL-4-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_3]], [[FOR_BODY]] ] ; UNROLL-4-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_3]], [[FOR_BODY]] ]
; UNROLL-4-NEXT: [[SUM_02_UNR_PH:%.*]] = phi i3 [ [[ADD_3]], [[FOR_BODY]] ] ; UNROLL-4-NEXT: [[SUM_02_UNR_PH:%.*]] = phi i3 [ [[ADD_3]], [[FOR_BODY]] ]
; UNROLL-4-NEXT: br label [[FOR_END_LOOPEXIT_UNR_LCSSA]] ; UNROLL-4-NEXT: br label [[FOR_END_LOOPEXIT_UNR_LCSSA]]
; UNROLL-4: for.end.loopexit.unr-lcssa: ; UNROLL-4: for.end.loopexit.unr-lcssa:
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/Transforms/LoopUnroll/runtime-multiexit-heuristic.ll

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Lines
; ENABLED: for.exiting_block: ; ENABLED: for.exiting_block:
; ENABLED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP]], label [[OTHEREXIT_LOOPEXIT:%.*]], label [[LATCH:%.*]] ; ENABLED-NEXT: br i1 [[CMP]], label [[OTHEREXIT_LOOPEXIT:%.*]], label [[LATCH:%.*]]
; ENABLED: latch: ; ENABLED: latch:
; ENABLED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV]] ; ENABLED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV]]
; ENABLED-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 ; ENABLED-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; ENABLED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[SUM_02]] ; ENABLED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[SUM_02]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
; ENABLED-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]]
; ENABLED: for.exiting_block.1: ; ENABLED: for.exiting_block.1:
; ENABLED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_1]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]] ; ENABLED-NEXT: br i1 [[CMP_1]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]]
; ENABLED: latch.1: ; ENABLED: latch.1:
; ENABLED-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]] ; ENABLED-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]]
; ENABLED-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4 ; ENABLED-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
; ENABLED-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP4]], [[ADD]] ; ENABLED-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP4]], [[ADD]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
; ENABLED-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i64 [[NITER_NEXT]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]]
; ENABLED: for.exiting_block.2: ; ENABLED: for.exiting_block.2:
; ENABLED-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_2]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]] ; ENABLED-NEXT: br i1 [[CMP_2]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]]
; ENABLED: latch.2: ; ENABLED: latch.2:
; ENABLED-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_1]] ; ENABLED-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_1]]
; ENABLED-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4 ; ENABLED-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
; ENABLED-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]] ; ENABLED-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 3
; ENABLED-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i64 [[NITER_NEXT_1]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]]
; ENABLED: for.exiting_block.3: ; ENABLED: for.exiting_block.3:
; ENABLED-NEXT: [[CMP_3:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_3:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_3]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]] ; ENABLED-NEXT: br i1 [[CMP_3]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]]
; ENABLED: latch.3: ; ENABLED: latch.3:
; ENABLED-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]] ; ENABLED-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]]
; ENABLED-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4 ; ENABLED-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
; ENABLED-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], [[ADD_2]] ; ENABLED-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], [[ADD_2]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 4
; ENABLED-NEXT: [[NITER_NEXT_3:%.*]] = add nuw nsw i64 [[NITER_NEXT_2]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]]
; ENABLED: for.exiting_block.4: ; ENABLED: for.exiting_block.4:
; ENABLED-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_4]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]] ; ENABLED-NEXT: br i1 [[CMP_4]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]]
; ENABLED: latch.4: ; ENABLED: latch.4:
; ENABLED-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_3]] ; ENABLED-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_3]]
; ENABLED-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4 ; ENABLED-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4
; ENABLED-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]] ; ENABLED-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_3]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 5
; ENABLED-NEXT: [[NITER_NEXT_4:%.*]] = add nuw nsw i64 [[NITER_NEXT_3]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]]
; ENABLED: for.exiting_block.5: ; ENABLED: for.exiting_block.5:
; ENABLED-NEXT: [[CMP_5:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_5:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_5]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]] ; ENABLED-NEXT: br i1 [[CMP_5]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]]
; ENABLED: latch.5: ; ENABLED: latch.5:
; ENABLED-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_4]] ; ENABLED-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_4]]
; ENABLED-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4 ; ENABLED-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4
; ENABLED-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP8]], [[ADD_4]] ; ENABLED-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP8]], [[ADD_4]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_4]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 6
; ENABLED-NEXT: [[NITER_NEXT_5:%.*]] = add nuw nsw i64 [[NITER_NEXT_4]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]]
; ENABLED: for.exiting_block.6: ; ENABLED: for.exiting_block.6:
; ENABLED-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_6]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]] ; ENABLED-NEXT: br i1 [[CMP_6]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]]
; ENABLED: latch.6: ; ENABLED: latch.6:
; ENABLED-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_5]] ; ENABLED-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_5]]
; ENABLED-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4 ; ENABLED-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4
; ENABLED-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]] ; ENABLED-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_5]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 7
; ENABLED-NEXT: [[NITER_NEXT_6:%.*]] = add nuw nsw i64 [[NITER_NEXT_5]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]]
; ENABLED: for.exiting_block.7: ; ENABLED: for.exiting_block.7:
; ENABLED-NEXT: [[CMP_7:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_7:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_7]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]] ; ENABLED-NEXT: br i1 [[CMP_7]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]]
; ENABLED: latch.7: ; ENABLED: latch.7:
; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]] ; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4 ; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]] ; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV_NEXT_6]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER_NEXT_6]], 1 ; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]] ; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA_LOOPEXIT:%.*]], label [[HEADER]] ; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA_LOOPEXIT:%.*]], label [[HEADER]]
; ENABLED: latchexit.unr-lcssa.loopexit: ; ENABLED: latchexit.unr-lcssa.loopexit:
; ENABLED-NEXT: [[SUM_0_LCSSA_PH_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ] ; ENABLED-NEXT: [[SUM_0_LCSSA_PH_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ]
; ENABLED-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_7]], [[LATCH_7]] ] ; ENABLED-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_7]], [[LATCH_7]] ]
; ENABLED-NEXT: [[SUM_02_UNR_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ] ; ENABLED-NEXT: [[SUM_02_UNR_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ]
; ENABLED-NEXT: br label [[LATCHEXIT_UNR_LCSSA]] ; ENABLED-NEXT: br label [[LATCHEXIT_UNR_LCSSA]]
; ENABLED: latchexit.unr-lcssa: ; ENABLED: latchexit.unr-lcssa:
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; ENABLED: for.exiting_block: ; ENABLED: for.exiting_block:
; ENABLED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP]], label [[OTHEREXIT_LOOPEXIT:%.*]], label [[LATCH:%.*]] ; ENABLED-NEXT: br i1 [[CMP]], label [[OTHEREXIT_LOOPEXIT:%.*]], label [[LATCH:%.*]]
; ENABLED: latch: ; ENABLED: latch:
; ENABLED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV]] ; ENABLED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV]]
; ENABLED-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 ; ENABLED-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; ENABLED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[SUM_02]] ; ENABLED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[SUM_02]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
; ENABLED-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]]
; ENABLED: for.exiting_block.1: ; ENABLED: for.exiting_block.1:
; ENABLED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_1]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]] ; ENABLED-NEXT: br i1 [[CMP_1]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]]
; ENABLED: latch.1: ; ENABLED: latch.1:
; ENABLED-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]] ; ENABLED-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]]
; ENABLED-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4 ; ENABLED-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
; ENABLED-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP4]], [[ADD]] ; ENABLED-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP4]], [[ADD]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
; ENABLED-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i64 [[NITER_NEXT]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]]
; ENABLED: for.exiting_block.2: ; ENABLED: for.exiting_block.2:
; ENABLED-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_2]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]] ; ENABLED-NEXT: br i1 [[CMP_2]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]]
; ENABLED: latch.2: ; ENABLED: latch.2:
; ENABLED-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_1]] ; ENABLED-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_1]]
; ENABLED-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4 ; ENABLED-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
; ENABLED-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]] ; ENABLED-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 3
; ENABLED-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i64 [[NITER_NEXT_1]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]]
; ENABLED: for.exiting_block.3: ; ENABLED: for.exiting_block.3:
; ENABLED-NEXT: [[CMP_3:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_3:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_3]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]] ; ENABLED-NEXT: br i1 [[CMP_3]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]]
; ENABLED: latch.3: ; ENABLED: latch.3:
; ENABLED-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]] ; ENABLED-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]]
; ENABLED-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4 ; ENABLED-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
; ENABLED-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], [[ADD_2]] ; ENABLED-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], [[ADD_2]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 4
; ENABLED-NEXT: [[NITER_NEXT_3:%.*]] = add nuw nsw i64 [[NITER_NEXT_2]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]]
; ENABLED: for.exiting_block.4: ; ENABLED: for.exiting_block.4:
; ENABLED-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_4]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]] ; ENABLED-NEXT: br i1 [[CMP_4]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]]
; ENABLED: latch.4: ; ENABLED: latch.4:
; ENABLED-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_3]] ; ENABLED-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_3]]
; ENABLED-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4 ; ENABLED-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4
; ENABLED-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]] ; ENABLED-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_3]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 5
; ENABLED-NEXT: [[NITER_NEXT_4:%.*]] = add nuw nsw i64 [[NITER_NEXT_3]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]]
; ENABLED: for.exiting_block.5: ; ENABLED: for.exiting_block.5:
; ENABLED-NEXT: [[CMP_5:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_5:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_5]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]] ; ENABLED-NEXT: br i1 [[CMP_5]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]]
; ENABLED: latch.5: ; ENABLED: latch.5:
; ENABLED-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_4]] ; ENABLED-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_4]]
; ENABLED-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4 ; ENABLED-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4
; ENABLED-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP8]], [[ADD_4]] ; ENABLED-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP8]], [[ADD_4]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_4]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 6
; ENABLED-NEXT: [[NITER_NEXT_5:%.*]] = add nuw nsw i64 [[NITER_NEXT_4]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]]
; ENABLED: for.exiting_block.6: ; ENABLED: for.exiting_block.6:
; ENABLED-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_6]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]] ; ENABLED-NEXT: br i1 [[CMP_6]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]]
; ENABLED: latch.6: ; ENABLED: latch.6:
; ENABLED-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_5]] ; ENABLED-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_5]]
; ENABLED-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4 ; ENABLED-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4
; ENABLED-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]] ; ENABLED-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_5]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 7
; ENABLED-NEXT: [[NITER_NEXT_6:%.*]] = add nuw nsw i64 [[NITER_NEXT_5]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]]
; ENABLED: for.exiting_block.7: ; ENABLED: for.exiting_block.7:
; ENABLED-NEXT: [[CMP_7:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_7:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_7]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]] ; ENABLED-NEXT: br i1 [[CMP_7]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]]
; ENABLED: latch.7: ; ENABLED: latch.7:
; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]] ; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4 ; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]] ; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV_NEXT_6]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER_NEXT_6]], 1 ; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]] ; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA_LOOPEXIT:%.*]], label [[HEADER]] ; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA_LOOPEXIT:%.*]], label [[HEADER]]
; ENABLED: latchexit.unr-lcssa.loopexit: ; ENABLED: latchexit.unr-lcssa.loopexit:
; ENABLED-NEXT: [[SUM_0_LCSSA_PH_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ] ; ENABLED-NEXT: [[SUM_0_LCSSA_PH_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ]
; ENABLED-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_7]], [[LATCH_7]] ] ; ENABLED-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_7]], [[LATCH_7]] ]
; ENABLED-NEXT: [[SUM_02_UNR_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ] ; ENABLED-NEXT: [[SUM_02_UNR_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ]
; ENABLED-NEXT: br label [[LATCHEXIT_UNR_LCSSA]] ; ENABLED-NEXT: br label [[LATCHEXIT_UNR_LCSSA]]
; ENABLED: latchexit.unr-lcssa: ; ENABLED: latchexit.unr-lcssa:
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; ENABLED: for.exiting_block: ; ENABLED: for.exiting_block:
; ENABLED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP]], label [[OTHEREXIT_LOOPEXIT:%.*]], label [[LATCH:%.*]] ; ENABLED-NEXT: br i1 [[CMP]], label [[OTHEREXIT_LOOPEXIT:%.*]], label [[LATCH:%.*]]
; ENABLED: latch: ; ENABLED: latch:
; ENABLED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV]] ; ENABLED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV]]
; ENABLED-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 ; ENABLED-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; ENABLED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[SUM_02]] ; ENABLED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[SUM_02]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
; ENABLED-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]]
; ENABLED: for.exiting_block.1: ; ENABLED: for.exiting_block.1:
; ENABLED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_1]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]] ; ENABLED-NEXT: br i1 [[CMP_1]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]]
; ENABLED: latch.1: ; ENABLED: latch.1:
; ENABLED-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]] ; ENABLED-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]]
; ENABLED-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4 ; ENABLED-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
; ENABLED-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP4]], [[ADD]] ; ENABLED-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP4]], [[ADD]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
; ENABLED-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i64 [[NITER_NEXT]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]]
; ENABLED: for.exiting_block.2: ; ENABLED: for.exiting_block.2:
; ENABLED-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_2]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]] ; ENABLED-NEXT: br i1 [[CMP_2]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]]
; ENABLED: latch.2: ; ENABLED: latch.2:
; ENABLED-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_1]] ; ENABLED-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_1]]
; ENABLED-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4 ; ENABLED-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
; ENABLED-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]] ; ENABLED-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 3
; ENABLED-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i64 [[NITER_NEXT_1]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]]
; ENABLED: for.exiting_block.3: ; ENABLED: for.exiting_block.3:
; ENABLED-NEXT: [[CMP_3:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_3:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_3]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]] ; ENABLED-NEXT: br i1 [[CMP_3]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]]
; ENABLED: latch.3: ; ENABLED: latch.3:
; ENABLED-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]] ; ENABLED-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]]
; ENABLED-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4 ; ENABLED-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
; ENABLED-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], [[ADD_2]] ; ENABLED-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], [[ADD_2]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 4
; ENABLED-NEXT: [[NITER_NEXT_3:%.*]] = add nuw nsw i64 [[NITER_NEXT_2]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]]
; ENABLED: for.exiting_block.4: ; ENABLED: for.exiting_block.4:
; ENABLED-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_4]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]] ; ENABLED-NEXT: br i1 [[CMP_4]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]]
; ENABLED: latch.4: ; ENABLED: latch.4:
; ENABLED-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_3]] ; ENABLED-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_3]]
; ENABLED-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4 ; ENABLED-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4
; ENABLED-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]] ; ENABLED-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_3]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 5
; ENABLED-NEXT: [[NITER_NEXT_4:%.*]] = add nuw nsw i64 [[NITER_NEXT_3]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]]
; ENABLED: for.exiting_block.5: ; ENABLED: for.exiting_block.5:
; ENABLED-NEXT: [[CMP_5:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_5:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_5]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]] ; ENABLED-NEXT: br i1 [[CMP_5]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]]
; ENABLED: latch.5: ; ENABLED: latch.5:
; ENABLED-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_4]] ; ENABLED-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_4]]
; ENABLED-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4 ; ENABLED-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4
; ENABLED-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP8]], [[ADD_4]] ; ENABLED-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP8]], [[ADD_4]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_4]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 6
; ENABLED-NEXT: [[NITER_NEXT_5:%.*]] = add nuw nsw i64 [[NITER_NEXT_4]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]]
; ENABLED: for.exiting_block.6: ; ENABLED: for.exiting_block.6:
; ENABLED-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_6]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]] ; ENABLED-NEXT: br i1 [[CMP_6]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]]
; ENABLED: latch.6: ; ENABLED: latch.6:
; ENABLED-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_5]] ; ENABLED-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_5]]
; ENABLED-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4 ; ENABLED-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4
; ENABLED-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]] ; ENABLED-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_5]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 7
; ENABLED-NEXT: [[NITER_NEXT_6:%.*]] = add nuw nsw i64 [[NITER_NEXT_5]], 1
; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]] ; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]]
; ENABLED: for.exiting_block.7: ; ENABLED: for.exiting_block.7:
; ENABLED-NEXT: [[CMP_7:%.*]] = icmp eq i64 [[N]], 42 ; ENABLED-NEXT: [[CMP_7:%.*]] = icmp eq i64 [[N]], 42
; ENABLED-NEXT: br i1 [[CMP_7]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]] ; ENABLED-NEXT: br i1 [[CMP_7]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]]
; ENABLED: latch.7: ; ENABLED: latch.7:
; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]] ; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4 ; ENABLED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]] ; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP10]], [[ADD_6]]
; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV_NEXT_6]], 1 ; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8
; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER_NEXT_6]], 1 ; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]] ; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA_LOOPEXIT:%.*]], label [[HEADER]] ; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA_LOOPEXIT:%.*]], label [[HEADER]]
; ENABLED: latchexit.unr-lcssa.loopexit: ; ENABLED: latchexit.unr-lcssa.loopexit:
; ENABLED-NEXT: [[SUM_0_LCSSA_PH_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ] ; ENABLED-NEXT: [[SUM_0_LCSSA_PH_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ]
; ENABLED-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_7]], [[LATCH_7]] ] ; ENABLED-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_7]], [[LATCH_7]] ]
; ENABLED-NEXT: [[SUM_02_UNR_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ] ; ENABLED-NEXT: [[SUM_02_UNR_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ]
; ENABLED-NEXT: br label [[LATCHEXIT_UNR_LCSSA]] ; ENABLED-NEXT: br label [[LATCHEXIT_UNR_LCSSA]]
; ENABLED: latchexit.unr-lcssa: ; ENABLED: latchexit.unr-lcssa:
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llvm/test/Transforms/LoopUnroll/runtime-small-upperbound.ll

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; UPPER-NEXT: br label [[LOOP:%.*]] ; UPPER-NEXT: br label [[LOOP:%.*]]
; UPPER: loop: ; UPPER: loop:
; UPPER-NEXT: [[IV_NEXT:%.*]] = add nuw i32 [[X]], 4 ; UPPER-NEXT: [[IV_NEXT:%.*]] = add nuw i32 [[X]], 4
; UPPER-NEXT: [[PTR_NEXT:%.*]] = getelementptr inbounds i8, ptr [[Y]], i32 1 ; UPPER-NEXT: [[PTR_NEXT:%.*]] = getelementptr inbounds i8, ptr [[Y]], i32 1
; UPPER-NEXT: store i8 [[ARG:%.*]], ptr [[PTR_NEXT]], align 1 ; UPPER-NEXT: store i8 [[ARG:%.*]], ptr [[PTR_NEXT]], align 1
; UPPER-NEXT: [[TMP1:%.*]] = icmp ult i32 [[IV_NEXT]], 17 ; UPPER-NEXT: [[TMP1:%.*]] = icmp ult i32 [[IV_NEXT]], 17
; UPPER-NEXT: br i1 [[TMP1]], label [[LOOP_1:%.*]], label [[EXIT_LOOPEXIT:%.*]] ; UPPER-NEXT: br i1 [[TMP1]], label [[LOOP_1:%.*]], label [[EXIT_LOOPEXIT:%.*]]
; UPPER: loop.1: ; UPPER: loop.1:
; UPPER-NEXT: [[IV_NEXT_1:%.*]] = add nuw i32 [[IV_NEXT]], 4 ; UPPER-NEXT: [[IV_NEXT_1:%.*]] = add nuw i32 [[X]], 8
; UPPER-NEXT: [[PTR_NEXT_1:%.*]] = getelementptr inbounds i8, ptr [[PTR_NEXT]], i32 1 ; UPPER-NEXT: [[PTR_NEXT_1:%.*]] = getelementptr inbounds i8, ptr [[PTR_NEXT]], i32 1
; UPPER-NEXT: store i8 [[ARG]], ptr [[PTR_NEXT_1]], align 1 ; UPPER-NEXT: store i8 [[ARG]], ptr [[PTR_NEXT_1]], align 1
; UPPER-NEXT: [[TMP2:%.*]] = icmp ult i32 [[IV_NEXT_1]], 17 ; UPPER-NEXT: [[TMP2:%.*]] = icmp ult i32 [[IV_NEXT_1]], 17
; UPPER-NEXT: br i1 [[TMP2]], label [[LOOP_2:%.*]], label [[EXIT_LOOPEXIT]] ; UPPER-NEXT: br i1 [[TMP2]], label [[LOOP_2:%.*]], label [[EXIT_LOOPEXIT]]
; UPPER: loop.2: ; UPPER: loop.2:
; UPPER-NEXT: [[IV_NEXT_2:%.*]] = add nuw i32 [[IV_NEXT_1]], 4 ; UPPER-NEXT: [[IV_NEXT_2:%.*]] = add nuw i32 [[X]], 12
; UPPER-NEXT: [[PTR_NEXT_2:%.*]] = getelementptr inbounds i8, ptr [[PTR_NEXT_1]], i32 1 ; UPPER-NEXT: [[PTR_NEXT_2:%.*]] = getelementptr inbounds i8, ptr [[PTR_NEXT_1]], i32 1
; UPPER-NEXT: store i8 [[ARG]], ptr [[PTR_NEXT_2]], align 1 ; UPPER-NEXT: store i8 [[ARG]], ptr [[PTR_NEXT_2]], align 1
; UPPER-NEXT: [[TMP3:%.*]] = icmp ult i32 [[IV_NEXT_2]], 17 ; UPPER-NEXT: [[TMP3:%.*]] = icmp ult i32 [[IV_NEXT_2]], 17
; UPPER-NEXT: br i1 [[TMP3]], label [[LOOP_3:%.*]], label [[EXIT_LOOPEXIT]] ; UPPER-NEXT: br i1 [[TMP3]], label [[LOOP_3:%.*]], label [[EXIT_LOOPEXIT]]
; UPPER: loop.3: ; UPPER: loop.3:
; UPPER-NEXT: [[IV_NEXT_3:%.*]] = add nuw i32 [[IV_NEXT_2]], 4 ; UPPER-NEXT: [[IV_NEXT_3:%.*]] = add nuw i32 [[X]], 16
; UPPER-NEXT: [[PTR_NEXT_3:%.*]] = getelementptr inbounds i8, ptr [[PTR_NEXT_2]], i32 1 ; UPPER-NEXT: [[PTR_NEXT_3:%.*]] = getelementptr inbounds i8, ptr [[PTR_NEXT_2]], i32 1
; UPPER-NEXT: store i8 [[ARG]], ptr [[PTR_NEXT_3]], align 1 ; UPPER-NEXT: store i8 [[ARG]], ptr [[PTR_NEXT_3]], align 1
; UPPER-NEXT: [[TMP4:%.*]] = icmp ult i32 [[IV_NEXT_3]], 17 ; UPPER-NEXT: [[TMP4:%.*]] = icmp ult i32 [[IV_NEXT_3]], 17
; UPPER-NEXT: br i1 [[TMP4]], label [[LOOP_4:%.*]], label [[EXIT_LOOPEXIT]] ; UPPER-NEXT: br i1 [[TMP4]], label [[LOOP_4:%.*]], label [[EXIT_LOOPEXIT]]
; UPPER: loop.4: ; UPPER: loop.4:
; UPPER-NEXT: [[IV_NEXT_4:%.*]] = add nuw i32 [[IV_NEXT_3]], 4
; UPPER-NEXT: [[PTR_NEXT_4:%.*]] = getelementptr inbounds i8, ptr [[PTR_NEXT_3]], i32 1 ; UPPER-NEXT: [[PTR_NEXT_4:%.*]] = getelementptr inbounds i8, ptr [[PTR_NEXT_3]], i32 1
; UPPER-NEXT: store i8 [[ARG]], ptr [[PTR_NEXT_4]], align 1 ; UPPER-NEXT: store i8 [[ARG]], ptr [[PTR_NEXT_4]], align 1
; UPPER-NEXT: [[TMP5:%.*]] = icmp ult i32 [[IV_NEXT_4]], 17 ; UPPER-NEXT: br i1 false, label [[LOOP_5:%.*]], label [[EXIT_LOOPEXIT]]
; UPPER-NEXT: br i1 [[TMP5]], label [[LOOP_5:%.*]], label [[EXIT_LOOPEXIT]]
; UPPER: loop.5: ; UPPER: loop.5:
; UPPER-NEXT: [[PTR_NEXT_5:%.*]] = getelementptr inbounds i8, ptr [[PTR_NEXT_4]], i32 1 ; UPPER-NEXT: [[PTR_NEXT_5:%.*]] = getelementptr inbounds i8, ptr [[PTR_NEXT_4]], i32 1
; UPPER-NEXT: store i8 [[ARG]], ptr [[PTR_NEXT_5]], align 1 ; UPPER-NEXT: store i8 [[ARG]], ptr [[PTR_NEXT_5]], align 1
; UPPER-NEXT: br label [[EXIT_LOOPEXIT]] ; UPPER-NEXT: br label [[EXIT_LOOPEXIT]]
; UPPER: exit.loopexit: ; UPPER: exit.loopexit:
; UPPER-NEXT: br label [[EXIT]] ; UPPER-NEXT: br label [[EXIT]]
; UPPER: exit: ; UPPER: exit:
; UPPER-NEXT: ret void ; UPPER-NEXT: ret void
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llvm/test/Transforms/LoopUnroll/runtime-unroll-assume-no-remainder.ll

Show All 27 Lines
; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i32 [[I_011]] ; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i32 [[I_011]]
; CHECK-NEXT: store i8 [[ADD]], ptr [[ARRAYIDX4]], align 1 ; CHECK-NEXT: store i8 [[ADD]], ptr [[ARRAYIDX4]], align 1
; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[I_011]], 1 ; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[I_011]], 1
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, ptr [[B]], i32 [[INC]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, ptr [[B]], i32 [[INC]]
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX_1]], align 1 ; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX_1]], align 1
; CHECK-NEXT: [[ADD_1:%.*]] = add i8 [[TMP1]], 3 ; CHECK-NEXT: [[ADD_1:%.*]] = add i8 [[TMP1]], 3
; CHECK-NEXT: [[ARRAYIDX4_1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[INC]] ; CHECK-NEXT: [[ARRAYIDX4_1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[INC]]
; CHECK-NEXT: store i8 [[ADD_1]], ptr [[ARRAYIDX4_1]], align 1 ; CHECK-NEXT: store i8 [[ADD_1]], ptr [[ARRAYIDX4_1]], align 1
; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[INC]], 1 ; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[I_011]], 2
; CHECK-NEXT: [[CMP1_1:%.*]] = icmp slt i32 [[INC_1]], [[N]] ; CHECK-NEXT: [[CMP1_1:%.*]] = icmp slt i32 [[INC_1]], [[N]]
; CHECK-NEXT: br i1 [[CMP1_1]], label [[FOR_BODY]], label [[EXIT_LOOPEXIT:%.*]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK-NEXT: br i1 [[CMP1_1]], label [[FOR_BODY]], label [[EXIT_LOOPEXIT:%.*]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: exit.loopexit: ; CHECK: exit.loopexit:
; CHECK-NEXT: br label [[EXIT]] ; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit: ; CHECK: exit:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
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; CHECK-NEXT: [[I_011:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[INC_1:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[I_011:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[INC_1:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i32 [[I_011]] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i32 [[I_011]]
; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 ; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
; CHECK-NEXT: [[ADD:%.*]] = add i8 [[TMP2]], 3 ; CHECK-NEXT: [[ADD:%.*]] = add i8 [[TMP2]], 3
; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i32 [[I_011]] ; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[A:%.*]], i32 [[I_011]]
; CHECK-NEXT: store i8 [[ADD]], ptr [[ARRAYIDX4]], align 1 ; CHECK-NEXT: store i8 [[ADD]], ptr [[ARRAYIDX4]], align 1
; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[I_011]], 1 ; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[I_011]], 1
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i32 [[NITER]], 1
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, ptr [[B]], i32 [[INC]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, ptr [[B]], i32 [[INC]]
; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX_1]], align 1 ; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX_1]], align 1
; CHECK-NEXT: [[ADD_1:%.*]] = add i8 [[TMP3]], 3 ; CHECK-NEXT: [[ADD_1:%.*]] = add i8 [[TMP3]], 3
; CHECK-NEXT: [[ARRAYIDX4_1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[INC]] ; CHECK-NEXT: [[ARRAYIDX4_1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[INC]]
; CHECK-NEXT: store i8 [[ADD_1]], ptr [[ARRAYIDX4_1]], align 1 ; CHECK-NEXT: store i8 [[ADD_1]], ptr [[ARRAYIDX4_1]], align 1
; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[INC]], 1 ; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[I_011]], 2
; CHECK-NEXT: [[NITER_NEXT_1]] = add i32 [[NITER_NEXT]], 1 ; CHECK-NEXT: [[NITER_NEXT_1]] = add i32 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp ne i32 [[NITER_NEXT_1]], [[UNROLL_ITER]] ; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp ne i32 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[FOR_BODY]], label [[EXIT_LOOPEXIT_UNR_LCSSA_LOOPEXIT:%.*]], !llvm.loop [[LOOP2:![0-9]+]] ; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[FOR_BODY]], label [[EXIT_LOOPEXIT_UNR_LCSSA_LOOPEXIT:%.*]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: exit.loopexit.unr-lcssa.loopexit: ; CHECK: exit.loopexit.unr-lcssa.loopexit:
; CHECK-NEXT: [[I_011_UNR_PH:%.*]] = phi i32 [ [[INC_1]], [[FOR_BODY]] ] ; CHECK-NEXT: [[I_011_UNR_PH:%.*]] = phi i32 [ [[INC_1]], [[FOR_BODY]] ]
; CHECK-NEXT: br label [[EXIT_LOOPEXIT_UNR_LCSSA]] ; CHECK-NEXT: br label [[EXIT_LOOPEXIT_UNR_LCSSA]]
; CHECK: exit.loopexit.unr-lcssa: ; CHECK: exit.loopexit.unr-lcssa:
; CHECK-NEXT: [[I_011_UNR:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[I_011_UNR_PH]], [[EXIT_LOOPEXIT_UNR_LCSSA_LOOPEXIT]] ] ; CHECK-NEXT: [[I_011_UNR:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[I_011_UNR_PH]], [[EXIT_LOOPEXIT_UNR_LCSSA_LOOPEXIT]] ]
; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i32 [[XTRAITER]], 0 ; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i32 [[XTRAITER]], 0
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llvm/test/Transforms/LoopUnroll/scev-invalidation-lcssa.ll

Show All 31 Lines
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[LD_LCSSA]], 7 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[LD_LCSSA]], 7
; CHECK-NEXT: br i1 [[TMP1]], label [[EXIT2_UNR_LCSSA:%.*]], label [[ENTRY2_NEW:%.*]] ; CHECK-NEXT: br i1 [[TMP1]], label [[EXIT2_UNR_LCSSA:%.*]], label [[ENTRY2_NEW:%.*]]
; CHECK: entry2.new: ; CHECK: entry2.new:
; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[TMP0]], [[XTRAITER]] ; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[TMP0]], [[XTRAITER]]
; CHECK-NEXT: br label [[LOOP2:%.*]] ; CHECK-NEXT: br label [[LOOP2:%.*]]
; CHECK: loop2: ; CHECK: loop2:
; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ 0, [[ENTRY2_NEW]] ], [ [[INC_7:%.*]], [[LOOP2]] ] ; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ 0, [[ENTRY2_NEW]] ], [ [[INC_7:%.*]], [[LOOP2]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[ENTRY2_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[LOOP2]] ] ; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[ENTRY2_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[LOOP2]] ]
; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i64 [[PHI]], 1 ; CHECK-NEXT: [[INC_7]] = add i64 [[PHI]], 8
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1 ; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8
; CHECK-NEXT: [[INC_1:%.*]] = add nuw nsw i64 [[INC]], 1
; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i64 [[NITER_NEXT]], 1
; CHECK-NEXT: [[INC_2:%.*]] = add nuw nsw i64 [[INC_1]], 1
; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i64 [[NITER_NEXT_1]], 1
; CHECK-NEXT: [[INC_3:%.*]] = add nuw nsw i64 [[INC_2]], 1
; CHECK-NEXT: [[NITER_NEXT_3:%.*]] = add nuw nsw i64 [[NITER_NEXT_2]], 1
; CHECK-NEXT: [[INC_4:%.*]] = add nuw nsw i64 [[INC_3]], 1
; CHECK-NEXT: [[NITER_NEXT_4:%.*]] = add nuw nsw i64 [[NITER_NEXT_3]], 1
; CHECK-NEXT: [[INC_5:%.*]] = add nuw nsw i64 [[INC_4]], 1
; CHECK-NEXT: [[NITER_NEXT_5:%.*]] = add nuw nsw i64 [[NITER_NEXT_4]], 1
; CHECK-NEXT: [[INC_6:%.*]] = add nuw nsw i64 [[INC_5]], 1
; CHECK-NEXT: [[NITER_NEXT_6:%.*]] = add nuw nsw i64 [[NITER_NEXT_5]], 1
; CHECK-NEXT: [[INC_7]] = add i64 [[INC_6]], 1
; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER_NEXT_6]], 1
; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]] ; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[EXIT2_UNR_LCSSA_LOOPEXIT:%.*]], label [[LOOP2]] ; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[EXIT2_UNR_LCSSA_LOOPEXIT:%.*]], label [[LOOP2]]
; CHECK: exit2.unr-lcssa.loopexit: ; CHECK: exit2.unr-lcssa.loopexit:
; CHECK-NEXT: [[PHI_UNR_PH:%.*]] = phi i64 [ [[INC_7]], [[LOOP2]] ] ; CHECK-NEXT: [[PHI_UNR_PH:%.*]] = phi i64 [ [[INC_7]], [[LOOP2]] ]
; CHECK-NEXT: br label [[EXIT2_UNR_LCSSA]] ; CHECK-NEXT: br label [[EXIT2_UNR_LCSSA]]
; CHECK: exit2.unr-lcssa: ; CHECK: exit2.unr-lcssa:
; CHECK-NEXT: [[PHI_UNR:%.*]] = phi i64 [ 0, [[ENTRY2]] ], [ [[PHI_UNR_PH]], [[EXIT2_UNR_LCSSA_LOOPEXIT]] ] ; CHECK-NEXT: [[PHI_UNR:%.*]] = phi i64 [ 0, [[ENTRY2]] ], [ [[PHI_UNR_PH]], [[EXIT2_UNR_LCSSA_LOOPEXIT]] ]
; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0 ; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0
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llvm/test/Transforms/LoopUnroll/shifted-tripcount.ll

Show All 11 Lines
; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr double, ptr [[P:%.*]], i64 [[I_013]] ; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr double, ptr [[P:%.*]], i64 [[I_013]]
; CHECK-NEXT: [[TMP16:%.*]] = add nuw nsw i64 [[I_013]], 1 ; CHECK-NEXT: [[TMP16:%.*]] = add nuw nsw i64 [[I_013]], 1
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]]
; CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX]], align 8 ; CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX]], align 8
; CHECK-NEXT: [[TMP8:%.*]] = load double, ptr [[ARRAYIDX7]], align 8 ; CHECK-NEXT: [[TMP8:%.*]] = load double, ptr [[ARRAYIDX7]], align 8
; CHECK-NEXT: [[MUL9:%.*]] = fmul double [[TMP8]], [[TMP4]] ; CHECK-NEXT: [[MUL9:%.*]] = fmul double [[TMP8]], [[TMP4]]
; CHECK-NEXT: store double [[MUL9]], ptr [[ARRAYIDX7]], align 8 ; CHECK-NEXT: store double [[MUL9]], ptr [[ARRAYIDX7]], align 8
; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]] ; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]]
; CHECK-NEXT: [[TMP16_1]] = add i64 [[TMP16]], 1 ; CHECK-NEXT: [[TMP16_1]] = add i64 [[I_013]], 2
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16_1]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16_1]]
; CHECK-NEXT: [[TMP4_1:%.*]] = load double, ptr [[ARRAYIDX_1]], align 8 ; CHECK-NEXT: [[TMP4_1:%.*]] = load double, ptr [[ARRAYIDX_1]], align 8
; CHECK-NEXT: [[TMP8_1:%.*]] = load double, ptr [[ARRAYIDX7_1]], align 8 ; CHECK-NEXT: [[TMP8_1:%.*]] = load double, ptr [[ARRAYIDX7_1]], align 8
; CHECK-NEXT: [[MUL9_1:%.*]] = fmul double [[TMP8_1]], [[TMP4_1]] ; CHECK-NEXT: [[MUL9_1:%.*]] = fmul double [[TMP8_1]], [[TMP4_1]]
; CHECK-NEXT: store double [[MUL9_1]], ptr [[ARRAYIDX7_1]], align 8 ; CHECK-NEXT: store double [[MUL9_1]], ptr [[ARRAYIDX7_1]], align 8
; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp eq i64 [[TMP16_1]], [[MUL10]] ; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp eq i64 [[TMP16_1]], [[MUL10]]
; CHECK-NEXT: br i1 [[EXITCOND_1]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK-NEXT: br i1 [[EXITCOND_1]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: for.end: ; CHECK: for.end:
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]]
; CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX]], align 8 ; CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX]], align 8
; CHECK-NEXT: [[TMP8:%.*]] = load double, ptr [[ARRAYIDX7]], align 8 ; CHECK-NEXT: [[TMP8:%.*]] = load double, ptr [[ARRAYIDX7]], align 8
; CHECK-NEXT: [[MUL9:%.*]] = fmul double [[TMP8]], [[TMP4]] ; CHECK-NEXT: [[MUL9:%.*]] = fmul double [[TMP8]], [[TMP4]]
; CHECK-NEXT: store double [[MUL9]], ptr [[ARRAYIDX7]], align 8 ; CHECK-NEXT: store double [[MUL9]], ptr [[ARRAYIDX7]], align 8
; CHECK-NEXT: br label [[LATCH:%.*]] ; CHECK-NEXT: br label [[LATCH:%.*]]
; CHECK: latch: ; CHECK: latch:
; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]] ; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]]
; CHECK-NEXT: [[TMP16_1]] = add i64 [[TMP16]], 1 ; CHECK-NEXT: [[TMP16_1]] = add i64 [[I_013]], 2
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16_1]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16_1]]
; CHECK-NEXT: [[TMP4_1:%.*]] = load double, ptr [[ARRAYIDX_1]], align 8 ; CHECK-NEXT: [[TMP4_1:%.*]] = load double, ptr [[ARRAYIDX_1]], align 8
; CHECK-NEXT: [[TMP8_1:%.*]] = load double, ptr [[ARRAYIDX7_1]], align 8 ; CHECK-NEXT: [[TMP8_1:%.*]] = load double, ptr [[ARRAYIDX7_1]], align 8
; CHECK-NEXT: [[MUL9_1:%.*]] = fmul double [[TMP8_1]], [[TMP4_1]] ; CHECK-NEXT: [[MUL9_1:%.*]] = fmul double [[TMP8_1]], [[TMP4_1]]
; CHECK-NEXT: store double [[MUL9_1]], ptr [[ARRAYIDX7_1]], align 8 ; CHECK-NEXT: store double [[MUL9_1]], ptr [[ARRAYIDX7_1]], align 8
; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp eq i64 [[TMP16_1]], [[MUL10]] ; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp eq i64 [[TMP16_1]], [[MUL10]]
; CHECK-NEXT: br i1 [[EXITCOND_1]], label [[FOR_END:%.*]], label [[LATCH_1]] ; CHECK-NEXT: br i1 [[EXITCOND_1]], label [[FOR_END:%.*]], label [[LATCH_1]]
; CHECK: latch.1: ; CHECK: latch.1:
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llvm/test/Transforms/LoopUnroll/tripcount-overflow.ll

Show All 19 Lines
; EPILOG-NEXT: br i1 [[TMP1]], label [[WHILE_END_UNR_LCSSA:%.*]], label [[ENTRY_NEW:%.*]] ; EPILOG-NEXT: br i1 [[TMP1]], label [[WHILE_END_UNR_LCSSA:%.*]], label [[ENTRY_NEW:%.*]]
; EPILOG: entry.new: ; EPILOG: entry.new:
; EPILOG-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[TMP0]], [[XTRAITER]] ; EPILOG-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[TMP0]], [[XTRAITER]]
; EPILOG-NEXT: br label [[WHILE_BODY:%.*]] ; EPILOG-NEXT: br label [[WHILE_BODY:%.*]]
; EPILOG: while.body: ; EPILOG: while.body:
; EPILOG-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[INC_1:%.*]], [[WHILE_BODY]] ] ; EPILOG-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[INC_1:%.*]], [[WHILE_BODY]] ]
; EPILOG-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[WHILE_BODY]] ] ; EPILOG-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[WHILE_BODY]] ]
; EPILOG-NEXT: [[INC:%.*]] = add nuw nsw i32 [[I]], 1 ; EPILOG-NEXT: [[INC:%.*]] = add nuw nsw i32 [[I]], 1
; EPILOG-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i32 [[NITER]], 1 ; EPILOG-NEXT: [[INC_1]] = add i32 [[I]], 2
; EPILOG-NEXT: [[INC_1]] = add i32 [[INC]], 1 ; EPILOG-NEXT: [[NITER_NEXT_1]] = add i32 [[NITER]], 2
; EPILOG-NEXT: [[NITER_NEXT_1]] = add i32 [[NITER_NEXT]], 1
; EPILOG-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i32 [[NITER_NEXT_1]], [[UNROLL_ITER]] ; EPILOG-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i32 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; EPILOG-NEXT: br i1 [[NITER_NCMP_1]], label [[WHILE_END_UNR_LCSSA_LOOPEXIT:%.*]], label [[WHILE_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; EPILOG-NEXT: br i1 [[NITER_NCMP_1]], label [[WHILE_END_UNR_LCSSA_LOOPEXIT:%.*]], label [[WHILE_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; EPILOG: while.end.unr-lcssa.loopexit: ; EPILOG: while.end.unr-lcssa.loopexit:
; EPILOG-NEXT: [[I_LCSSA_PH_PH:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ] ; EPILOG-NEXT: [[I_LCSSA_PH_PH:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ]
; EPILOG-NEXT: [[I_UNR_PH:%.*]] = phi i32 [ [[INC_1]], [[WHILE_BODY]] ] ; EPILOG-NEXT: [[I_UNR_PH:%.*]] = phi i32 [ [[INC_1]], [[WHILE_BODY]] ]
; EPILOG-NEXT: br label [[WHILE_END_UNR_LCSSA]] ; EPILOG-NEXT: br label [[WHILE_END_UNR_LCSSA]]
; EPILOG: while.end.unr-lcssa: ; EPILOG: while.end.unr-lcssa:
; EPILOG-NEXT: [[I_LCSSA_PH:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[I_LCSSA_PH_PH]], [[WHILE_END_UNR_LCSSA_LOOPEXIT]] ] ; EPILOG-NEXT: [[I_LCSSA_PH:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[I_LCSSA_PH_PH]], [[WHILE_END_UNR_LCSSA_LOOPEXIT]] ]
Show All 24 Lines
; PROLOG-NEXT: [[TMP1:%.*]] = icmp ult i32 [[N]], 1 ; PROLOG-NEXT: [[TMP1:%.*]] = icmp ult i32 [[N]], 1
; PROLOG-NEXT: br i1 [[TMP1]], label [[WHILE_END:%.*]], label [[ENTRY_NEW:%.*]] ; PROLOG-NEXT: br i1 [[TMP1]], label [[WHILE_END:%.*]], label [[ENTRY_NEW:%.*]]
; PROLOG: entry.new: ; PROLOG: entry.new:
; PROLOG-NEXT: br label [[WHILE_BODY:%.*]] ; PROLOG-NEXT: br label [[WHILE_BODY:%.*]]
; PROLOG: while.body: ; PROLOG: while.body:
; PROLOG-NEXT: [[I:%.*]] = phi i32 [ [[I_UNR]], [[ENTRY_NEW]] ], [ [[INC_1:%.*]], [[WHILE_BODY]] ] ; PROLOG-NEXT: [[I:%.*]] = phi i32 [ [[I_UNR]], [[ENTRY_NEW]] ], [ [[INC_1:%.*]], [[WHILE_BODY]] ]
; PROLOG-NEXT: [[INC:%.*]] = add i32 [[I]], 1 ; PROLOG-NEXT: [[INC:%.*]] = add i32 [[I]], 1
; PROLOG-NEXT: [[CMP_1:%.*]] = icmp eq i32 [[INC]], [[N]] ; PROLOG-NEXT: [[CMP_1:%.*]] = icmp eq i32 [[INC]], [[N]]
; PROLOG-NEXT: [[INC_1]] = add i32 [[INC]], 1 ; PROLOG-NEXT: [[INC_1]] = add i32 [[I]], 2
; PROLOG-NEXT: br i1 [[CMP_1]], label [[WHILE_END_UNR_LCSSA:%.*]], label [[WHILE_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; PROLOG-NEXT: br i1 [[CMP_1]], label [[WHILE_END_UNR_LCSSA:%.*]], label [[WHILE_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; PROLOG: while.end.unr-lcssa: ; PROLOG: while.end.unr-lcssa:
; PROLOG-NEXT: [[I_LCSSA_PH:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ] ; PROLOG-NEXT: [[I_LCSSA_PH:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ]
; PROLOG-NEXT: br label [[WHILE_END]] ; PROLOG-NEXT: br label [[WHILE_END]]
; PROLOG: while.end: ; PROLOG: while.end:
; PROLOG-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I_LCSSA_UNR]], [[WHILE_BODY_PROL_LOOPEXIT]] ], [ [[I_LCSSA_PH]], [[WHILE_END_UNR_LCSSA]] ] ; PROLOG-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I_LCSSA_UNR]], [[WHILE_BODY_PROL_LOOPEXIT]] ], [ [[I_LCSSA_PH]], [[WHILE_END_UNR_LCSSA]] ]
; PROLOG-NEXT: ret i32 [[I_LCSSA]] ; PROLOG-NEXT: ret i32 [[I_LCSSA]]
; ;
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llvm/test/Transforms/LoopUnroll/unroll-header-exiting-with-phis.ll

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; CHECK-NEXT: [[TMP3:%.*]] = call i16 @func(i16 [[DOTLCSSA10_LCSSA]]) ; CHECK-NEXT: [[TMP3:%.*]] = call i16 @func(i16 [[DOTLCSSA10_LCSSA]])
; CHECK-NEXT: ret i16 0 ; CHECK-NEXT: ret i16 0
; CHECK: for.cond.cleanup3: ; CHECK: for.cond.cleanup3:
; CHECK-NEXT: [[INC9:%.*]] = add nuw nsw i64 [[I_0]], 1 ; CHECK-NEXT: [[INC9:%.*]] = add nuw nsw i64 [[I_0]], 1
; CHECK-NEXT: [[PTR_1:%.*]] = getelementptr inbounds i16, ptr [[A:%.*]], i64 [[INC9]] ; CHECK-NEXT: [[PTR_1:%.*]] = getelementptr inbounds i16, ptr [[A:%.*]], i64 [[INC9]]
; CHECK-NEXT: [[TMP2_1]] = load i16, ptr [[PTR_1]], align 2 ; CHECK-NEXT: [[TMP2_1]] = load i16, ptr [[PTR_1]], align 2
; CHECK-NEXT: br label [[FOR_COND_CLEANUP3_1]] ; CHECK-NEXT: br label [[FOR_COND_CLEANUP3_1]]
; CHECK: for.cond.cleanup3.1: ; CHECK: for.cond.cleanup3.1:
; CHECK-NEXT: [[INC9_1:%.*]] = add nuw nsw i64 [[INC9]], 1 ; CHECK-NEXT: [[INC9_1:%.*]] = add nuw nsw i64 [[I_0]], 2
; CHECK-NEXT: [[CMP_2:%.*]] = icmp ult i64 [[INC9_1]], 200 ; CHECK-NEXT: [[CMP_2:%.*]] = icmp ult i64 [[INC9_1]], 200
; CHECK-NEXT: br i1 [[CMP_2]], label [[FOR_COND_CLEANUP3_2]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK-NEXT: br i1 [[CMP_2]], label [[FOR_COND_CLEANUP3_2]], label [[FOR_COND_CLEANUP:%.*]]
; CHECK: for.cond.cleanup3.2: ; CHECK: for.cond.cleanup3.2:
; CHECK-NEXT: [[INC9_2]] = add nuw nsw i64 [[INC9_1]], 1 ; CHECK-NEXT: [[INC9_2]] = add nuw nsw i64 [[I_0]], 3
; CHECK-NEXT: br label [[FOR_COND]] ; CHECK-NEXT: br label [[FOR_COND]]
; ;
entry: entry:
br label %for.cond br label %for.cond
for.cond: ; preds = %for.cond.cleanup3, %entry for.cond: ; preds = %for.cond.cleanup3, %entry
%.lcssa10 = phi i16 [ 123, %entry ], [ %.lcssa, %for.cond.cleanup3 ] %.lcssa10 = phi i16 [ 123, %entry ], [ %.lcssa, %for.cond.cleanup3 ]
%i.0 = phi i64 [ 0, %entry ], [ %inc9, %for.cond.cleanup3 ] %i.0 = phi i64 [ 0, %entry ], [ %inc9, %for.cond.cleanup3 ]
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llvm/test/Transforms/LoopUnroll/unroll-opt-attribute.ll

Show All 19 Linesloop:
br i1 %exitcnd, label %exit, label %loop br i1 %exitcnd, label %exit, label %loop
exit: exit:
ret void ret void
} }
; CHECK_COUNT4-LABEL: @Test1 ; CHECK_COUNT4-LABEL: @Test1
; CHECK_COUNT4: phi ; CHECK_COUNT4: phi
; CHECK_COUNT4-NEXT: add ; CHECK_COUNT4-NEXT: add{{.*}}, 4
; CHECK_COUNT4-NEXT: add
; CHECK_COUNT4-NEXT: add
; CHECK_COUNT4-NEXT: add
; CHECK_COUNT4-NEXT: icmp ; CHECK_COUNT4-NEXT: icmp
;///////////////////// TEST 2 ////////////////////////////// ;///////////////////// TEST 2 //////////////////////////////
; This test shows that with optnone attribute, the loop is not unrolled ; This test shows that with optnone attribute, the loop is not unrolled
; even if an unroll factor was specified. ; even if an unroll factor was specified.
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llvm/test/Transforms/LoopUnrollAndJam/dependencies_visit_order.ll

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; CHECK: bb.new: ; CHECK: bb.new:
; CHECK-NEXT: br label [[BB5_PREHEADER:%.*]] ; CHECK-NEXT: br label [[BB5_PREHEADER:%.*]]
; CHECK: bb5.preheader: ; CHECK: bb5.preheader:
; CHECK-NEXT: [[I10:%.*]] = phi i16 [ 0, [[BB_NEW]] ], [ [[I42_3:%.*]], [[BB38:%.*]] ] ; CHECK-NEXT: [[I10:%.*]] = phi i16 [ 0, [[BB_NEW]] ], [ [[I42_3:%.*]], [[BB38:%.*]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i16 [ 0, [[BB_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[BB38]] ] ; CHECK-NEXT: [[NITER:%.*]] = phi i16 [ 0, [[BB_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[BB38]] ]
; CHECK-NEXT: [[I4017:%.*]] = zext i16 [[I10]] to i64 ; CHECK-NEXT: [[I4017:%.*]] = zext i16 [[I10]] to i64
; CHECK-NEXT: [[I13_I:%.*]] = add nuw nsw i64 [[I4017]], 1 ; CHECK-NEXT: [[I13_I:%.*]] = add nuw nsw i64 [[I4017]], 1
; CHECK-NEXT: [[I42:%.*]] = trunc i64 [[I13_I]] to i16 ; CHECK-NEXT: [[I42:%.*]] = trunc i64 [[I13_I]] to i16
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i16 [[NITER]], 1
; CHECK-NEXT: [[I4017_1:%.*]] = zext i16 [[I42]] to i64 ; CHECK-NEXT: [[I4017_1:%.*]] = zext i16 [[I42]] to i64
; CHECK-NEXT: [[I13_I_1:%.*]] = add nuw nsw i64 [[I4017_1]], 1 ; CHECK-NEXT: [[I13_I_1:%.*]] = add nuw nsw i64 [[I4017_1]], 1
; CHECK-NEXT: [[I42_1:%.*]] = trunc i64 [[I13_I_1]] to i16 ; CHECK-NEXT: [[I42_1:%.*]] = trunc i64 [[I13_I_1]] to i16
; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i16 [[NITER_NEXT]], 1
; CHECK-NEXT: [[I4017_2:%.*]] = zext i16 [[I42_1]] to i64 ; CHECK-NEXT: [[I4017_2:%.*]] = zext i16 [[I42_1]] to i64
; CHECK-NEXT: [[I13_I_2:%.*]] = add nuw nsw i64 [[I4017_2]], 1 ; CHECK-NEXT: [[I13_I_2:%.*]] = add nuw nsw i64 [[I4017_2]], 1
; CHECK-NEXT: [[I42_2:%.*]] = trunc i64 [[I13_I_2]] to i16 ; CHECK-NEXT: [[I42_2:%.*]] = trunc i64 [[I13_I_2]] to i16
; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i16 [[NITER_NEXT_1]], 1
; CHECK-NEXT: [[I4017_3:%.*]] = zext i16 [[I42_2]] to i64 ; CHECK-NEXT: [[I4017_3:%.*]] = zext i16 [[I42_2]] to i64
; CHECK-NEXT: [[I13_I_3:%.*]] = add nuw nsw i64 [[I4017_3]], 1 ; CHECK-NEXT: [[I13_I_3:%.*]] = add nuw nsw i64 [[I4017_3]], 1
; CHECK-NEXT: [[I42_3]] = trunc i64 [[I13_I_3]] to i16 ; CHECK-NEXT: [[I42_3]] = trunc i64 [[I13_I_3]] to i16
; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw i16 [[NITER_NEXT_2]], 1 ; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw i16 [[NITER]], 4
; CHECK-NEXT: br label [[BB10_PREHEADER:%.*]] ; CHECK-NEXT: br label [[BB10_PREHEADER:%.*]]
; CHECK: bb10.preheader: ; CHECK: bb10.preheader:
; CHECK-NEXT: br i1 true, label [[BB38]], label [[BB10_PREHEADER]] ; CHECK-NEXT: br i1 true, label [[BB38]], label [[BB10_PREHEADER]]
; CHECK: bb38: ; CHECK: bb38:
; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i16 [[NITER_NEXT_3]], -28 ; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i16 [[NITER_NEXT_3]], -28
; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[BB1_BB43_CRIT_EDGE_UNR_LCSSA_LOOPEXIT:%.*]], label [[BB5_PREHEADER]], !llvm.loop [[LOOP1:![0-9]+]] ; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label [[BB1_BB43_CRIT_EDGE_UNR_LCSSA_LOOPEXIT:%.*]], label [[BB5_PREHEADER]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: bb1.bb43_crit_edge.unr-lcssa.loopexit: ; CHECK: bb1.bb43_crit_edge.unr-lcssa.loopexit:
; CHECK-NEXT: [[I10_UNR_PH:%.*]] = phi i16 [ [[I42_3]], [[BB38]] ] ; CHECK-NEXT: [[I10_UNR_PH:%.*]] = phi i16 [ [[I42_3]], [[BB38]] ]
; CHECK-NEXT: br label [[BB1_BB43_CRIT_EDGE_UNR_LCSSA]] ; CHECK-NEXT: br label [[BB1_BB43_CRIT_EDGE_UNR_LCSSA]]
; CHECK: bb1.bb43_crit_edge.unr-lcssa: ; CHECK: bb1.bb43_crit_edge.unr-lcssa:
; CHECK-NEXT: [[I10_UNR:%.*]] = phi i16 [ 0, [[BB:%.*]] ], [ [[I10_UNR_PH]], [[BB1_BB43_CRIT_EDGE_UNR_LCSSA_LOOPEXIT]] ] ; CHECK-NEXT: [[I10_UNR:%.*]] = phi i16 [ 0, [[BB:%.*]] ], [ [[I10_UNR_PH]], [[BB1_BB43_CRIT_EDGE_UNR_LCSSA_LOOPEXIT]] ]
; CHECK-NEXT: br i1 true, label [[BB5_PREHEADER_EPIL_PREHEADER:%.*]], label [[BB1_BB43_CRIT_EDGE:%.*]] ; CHECK-NEXT: br i1 true, label [[BB5_PREHEADER_EPIL_PREHEADER:%.*]], label [[BB1_BB43_CRIT_EDGE:%.*]]
; CHECK: bb5.preheader.epil.preheader: ; CHECK: bb5.preheader.epil.preheader:
; CHECK-NEXT: br label [[BB5_PREHEADER_EPIL:%.*]] ; CHECK-NEXT: br label [[BB5_PREHEADER_EPIL:%.*]]
; CHECK: bb5.preheader.epil: ; CHECK: bb5.preheader.epil:
; CHECK-NEXT: [[I10_EPIL:%.*]] = phi i16 [ [[I10_UNR]], [[BB5_PREHEADER_EPIL_PREHEADER]] ], [ [[I42_EPIL:%.*]], [[BB38_EPIL:%.*]] ] ; CHECK-NEXT: [[I10_EPIL:%.*]] = phi i16 [ [[I10_UNR]], [[BB5_PREHEADER_EPIL_PREHEADER]] ], [ [[I42_EPIL:%.*]], [[BB38_EPIL:%.*]] ]
; CHECK-NEXT: [[EPIL_ITER:%.*]] = phi i16 [ 0, [[BB5_PREHEADER_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], [[BB38_EPIL]] ] ; CHECK-NEXT: [[EPIL_ITER:%.*]] = phi i16 [ 0, [[BB5_PREHEADER_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], [[BB38_EPIL]] ]
; CHECK-NEXT: br label [[BB10_PREHEADER_EPIL:%.*]] ; CHECK-NEXT: br label [[BB10_PREHEADER_EPIL:%.*]]
; CHECK: bb10.preheader.epil: ; CHECK: bb10.preheader.epil:
; CHECK-NEXT: br i1 true, label [[BB38_EPIL]], label [[BB10_PREHEADER_EPIL]] ; CHECK-NEXT: br i1 true, label [[BB38_EPIL]], label [[BB10_PREHEADER_EPIL]]
; CHECK: bb38.epil: ; CHECK: bb38.epil:
; CHECK-NEXT: [[I4017_EPIL:%.*]] = zext i16 [[I10_EPIL]] to i64 ; CHECK-NEXT: [[I4017_EPIL:%.*]] = zext i16 [[I10_EPIL]] to i64
; CHECK-NEXT: [[I13_I_EPIL:%.*]] = add i64 [[I4017_EPIL]], 1 ; CHECK-NEXT: [[I13_I_EPIL:%.*]] = add i64 [[I4017_EPIL]], 1
; CHECK-NEXT: [[I14_I_EPIL:%.*]] = select i1 true, i64 [[I13_I_EPIL]], i64 [[I4017_EPIL]] ; CHECK-NEXT: [[I14_I_EPIL:%.*]] = select i1 true, i64 [[I13_I_EPIL]], i64 [[I4017_EPIL]]
; CHECK-NEXT: [[I42_EPIL]] = trunc i64 [[I14_I_EPIL]] to i16 ; CHECK-NEXT: [[I42_EPIL]] = trunc i64 [[I14_I_EPIL]] to i16
; CHECK-NEXT: [[I3_NOT_EPIL:%.*]] = icmp eq i16 [[I10_EPIL]], -27 ; CHECK-NEXT: [[I3_NOT_EPIL:%.*]] = icmp eq i16 [[I10_EPIL]], -27
; CHECK-NEXT: [[EPIL_ITER_NEXT]] = add i16 [[EPIL_ITER]], 1 ; CHECK-NEXT: [[EPIL_ITER_NEXT]] = add i16 [[EPIL_ITER]], 1
; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i16 [[EPIL_ITER_NEXT]], 2 ; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i16 [[EPIL_ITER_NEXT]], 2
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[BB5_PREHEADER_EPIL]], label [[BB1_BB43_CRIT_EDGE_EPILOG_LCSSA:%.*]], !llvm.loop [[LOOP3:![0-9]+]] ; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[BB5_PREHEADER_EPIL]], label [[BB1_BB43_CRIT_EDGE_EPILOG_LCSSA:%.*]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: bb1.bb43_crit_edge.epilog-lcssa: ; CHECK: bb1.bb43_crit_edge.epilog-lcssa:
; CHECK-NEXT: br label [[BB1_BB43_CRIT_EDGE]] ; CHECK-NEXT: br label [[BB1_BB43_CRIT_EDGE]]
; CHECK: bb1.bb43_crit_edge: ; CHECK: bb1.bb43_crit_edge:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
bb: bb:
br label %bb5.preheader br label %bb5.preheader
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llvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll

Show All 18 Lines
; CHECK-NEXT: br i1 [[TMP1]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_OUTER_PREHEADER_NEW:%.*]] ; CHECK-NEXT: br i1 [[TMP1]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_OUTER_PREHEADER_NEW:%.*]]
; CHECK: for.outer.preheader.new: ; CHECK: for.outer.preheader.new:
; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[I]], [[XTRAITER]] ; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[I]], [[XTRAITER]]
; CHECK-NEXT: br label [[FOR_OUTER:%.*]] ; CHECK-NEXT: br label [[FOR_OUTER:%.*]]
; CHECK: for.outer: ; CHECK: for.outer:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD8_3:%.*]], [[FOR_LATCH:%.*]] ], [ 0, [[FOR_OUTER_PREHEADER_NEW]] ] ; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD8_3:%.*]], [[FOR_LATCH:%.*]] ], [ 0, [[FOR_OUTER_PREHEADER_NEW]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_OUTER_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_LATCH]] ] ; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_OUTER_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_LATCH]] ]
; CHECK-NEXT: [[ADD8:%.*]] = add nuw nsw i32 [[I]], 1 ; CHECK-NEXT: [[ADD8:%.*]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i32 [[NITER]], 1 ; CHECK-NEXT: [[ADD8_1:%.*]] = add nuw nsw i32 [[I]], 2
; CHECK-NEXT: [[ADD8_1:%.*]] = add nuw nsw i32 [[ADD8]], 1 ; CHECK-NEXT: [[ADD8_2:%.*]] = add nuw nsw i32 [[I]], 3
; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i32 [[NITER_NEXT]], 1 ; CHECK-NEXT: [[ADD8_3]] = add nuw i32 [[I]], 4
; CHECK-NEXT: [[ADD8_2:%.*]] = add nuw nsw i32 [[ADD8_1]], 1 ; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER]], 4
; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i32 [[NITER_NEXT_1]], 1
; CHECK-NEXT: [[ADD8_3]] = add nuw i32 [[ADD8_2]], 1
; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER_NEXT_2]], 1
; CHECK-NEXT: br label [[FOR_INNER:%.*]] ; CHECK-NEXT: br label [[FOR_INNER:%.*]]
; CHECK: for.inner: ; CHECK: for.inner:
; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[J_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_1:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[J_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_1:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD_1:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD_1:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[J_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_2:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[J_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_2:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[SUM_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD_2:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[SUM_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD_2:%.*]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[ADD_EPIL_1]] = add i32 [[TMP7]], [[SUM_EPIL_1]] ; CHECK-NEXT: [[ADD_EPIL_1]] = add i32 [[TMP7]], [[SUM_EPIL_1]]
; CHECK-NEXT: [[INC_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1 ; CHECK-NEXT: [[INC_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1
; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[INC_EPIL_1]], [[E]] ; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[INC_EPIL_1]], [[E]]
; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label [[FOR_LATCH_EPIL_1:%.*]], label [[FOR_INNER_EPIL_1]] ; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label [[FOR_LATCH_EPIL_1:%.*]], label [[FOR_INNER_EPIL_1]]
; CHECK: for.latch.epil.1: ; CHECK: for.latch.epil.1:
; CHECK-NEXT: [[ADD_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], [[FOR_INNER_EPIL_1]] ] ; CHECK-NEXT: [[ADD_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], [[FOR_INNER_EPIL_1]] ]
; CHECK-NEXT: [[ARRAYIDX6_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD8_EPIL]] ; CHECK-NEXT: [[ARRAYIDX6_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD8_EPIL]]
; CHECK-NEXT: store i32 [[ADD_LCSSA_EPIL_1]], ptr [[ARRAYIDX6_EPIL_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 [[ADD_LCSSA_EPIL_1]], ptr [[ARRAYIDX6_EPIL_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD8_EPIL_1:%.*]] = add nuw i32 [[ADD8_EPIL]], 1 ; CHECK-NEXT: [[ADD8_EPIL_1:%.*]] = add nuw i32 [[I_UNR]], 2
; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]] ; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]]
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_OUTER_EPIL_2:%.*]], label [[FOR_END_LOOPEXIT_EPILOG_LCSSA]] ; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_OUTER_EPIL_2:%.*]], label [[FOR_END_LOOPEXIT_EPILOG_LCSSA]]
; CHECK: for.outer.epil.2: ; CHECK: for.outer.epil.2:
; CHECK-NEXT: br label [[FOR_INNER_EPIL_2:%.*]] ; CHECK-NEXT: br label [[FOR_INNER_EPIL_2:%.*]]
; CHECK: for.inner.epil.2: ; CHECK: for.inner.epil.2:
; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[INC_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ] ; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[INC_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ]
; CHECK-NEXT: [[SUM_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[ADD_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ] ; CHECK-NEXT: [[SUM_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[ADD_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ]
; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_2]] ; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_2]]
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; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[I]], [[XTRAITER]] ; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[I]], [[XTRAITER]]
; CHECK-NEXT: br label [[FOR_OUTER:%.*]] ; CHECK-NEXT: br label [[FOR_OUTER:%.*]]
; CHECK: for.outer: ; CHECK: for.outer:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD9_3:%.*]], [[FOR_LATCH:%.*]] ], [ 0, [[FOR_OUTER_PREHEADER_NEW]] ] ; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD9_3:%.*]], [[FOR_LATCH:%.*]] ], [ 0, [[FOR_OUTER_PREHEADER_NEW]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_OUTER_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_LATCH]] ] ; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_OUTER_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_LATCH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i32 [[I]] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i32 [[I]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD9:%.*]] = add nuw nsw i32 [[I]], 1 ; CHECK-NEXT: [[ADD9:%.*]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i32 [[NITER]], 1
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD9_1:%.*]] = add nuw nsw i32 [[ADD9]], 1 ; CHECK-NEXT: [[ADD9_1:%.*]] = add nuw nsw i32 [[I]], 2
; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i32 [[NITER_NEXT]], 1
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9_1]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9_1]]
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD9_2:%.*]] = add nuw nsw i32 [[ADD9_1]], 1 ; CHECK-NEXT: [[ADD9_2:%.*]] = add nuw nsw i32 [[I]], 3
; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i32 [[NITER_NEXT_1]], 1
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9_2]] ; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9_2]]
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD9_3]] = add nuw i32 [[ADD9_2]], 1 ; CHECK-NEXT: [[ADD9_3]] = add nuw i32 [[I]], 4
; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER_NEXT_2]], 1 ; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER]], 4
; CHECK-NEXT: br label [[FOR_INNER:%.*]] ; CHECK-NEXT: br label [[FOR_INNER:%.*]]
; CHECK: for.inner: ; CHECK: for.inner:
; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[TMP2]], [[FOR_OUTER]] ], [ [[ADD:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[TMP2]], [[FOR_OUTER]] ], [ [[ADD:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[J_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_1:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[J_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_1:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ [[TMP3]], [[FOR_OUTER]] ], [ [[ADD_1:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ [[TMP3]], [[FOR_OUTER]] ], [ [[ADD_1:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[J_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_2:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[J_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_2:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[SUM_2:%.*]] = phi i32 [ [[TMP4]], [[FOR_OUTER]] ], [ [[ADD_2:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[SUM_2:%.*]] = phi i32 [ [[TMP4]], [[FOR_OUTER]] ], [ [[ADD_2:%.*]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX6_EPIL_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX6_EPIL_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD_EPIL_1]] = add i32 [[TMP13]], [[SUM_EPIL_1]] ; CHECK-NEXT: [[ADD_EPIL_1]] = add i32 [[TMP13]], [[SUM_EPIL_1]]
; CHECK-NEXT: [[INC_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1 ; CHECK-NEXT: [[INC_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1
; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[INC_EPIL_1]], [[E]] ; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[INC_EPIL_1]], [[E]]
; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label [[FOR_LATCH_EPIL_1:%.*]], label [[FOR_INNER_EPIL_1]] ; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label [[FOR_LATCH_EPIL_1:%.*]], label [[FOR_INNER_EPIL_1]]
; CHECK: for.latch.epil.1: ; CHECK: for.latch.epil.1:
; CHECK-NEXT: [[ADD_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], [[FOR_INNER_EPIL_1]] ] ; CHECK-NEXT: [[ADD_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], [[FOR_INNER_EPIL_1]] ]
; CHECK-NEXT: store i32 [[ADD_LCSSA_EPIL_1]], ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 [[ADD_LCSSA_EPIL_1]], ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD9_EPIL_1:%.*]] = add nuw i32 [[ADD9_EPIL]], 1 ; CHECK-NEXT: [[ADD9_EPIL_1:%.*]] = add nuw i32 [[I_UNR]], 2
; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]] ; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]]
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_OUTER_EPIL_2:%.*]], label [[FOR_END10_LOOPEXIT_EPILOG_LCSSA]] ; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_OUTER_EPIL_2:%.*]], label [[FOR_END10_LOOPEXIT_EPILOG_LCSSA]]
; CHECK: for.outer.epil.2: ; CHECK: for.outer.epil.2:
; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9_EPIL_1]] ; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9_EPIL_1]]
; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX_EPIL_2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX_EPIL_2]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: br label [[FOR_INNER_EPIL_2:%.*]] ; CHECK-NEXT: br label [[FOR_INNER_EPIL_2:%.*]]
; CHECK: for.inner.epil.2: ; CHECK: for.inner.epil.2:
; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[INC_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ] ; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[INC_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ]
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; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[F_PROMOTED10:%.*]] = load i32, ptr @f, align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: [[F_PROMOTED10:%.*]] = load i32, ptr @f, align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: br i1 false, label [[FOR_END_UNR_LCSSA:%.*]], label [[ENTRY_NEW:%.*]] ; CHECK-NEXT: br i1 false, label [[FOR_END_UNR_LCSSA:%.*]], label [[ENTRY_NEW:%.*]]
; CHECK: entry.new: ; CHECK: entry.new:
; CHECK-NEXT: br label [[FOR_OUTER:%.*]] ; CHECK-NEXT: br label [[FOR_OUTER:%.*]]
; CHECK: for.outer: ; CHECK: for.outer:
; CHECK-NEXT: [[INC5_SINK9:%.*]] = phi i32 [ 2, [[ENTRY_NEW]] ], [ [[INC5_3:%.*]], [[FOR_LATCH:%.*]] ] ; CHECK-NEXT: [[INC5_SINK9:%.*]] = phi i32 [ 2, [[ENTRY_NEW]] ], [ [[INC5_3:%.*]], [[FOR_LATCH:%.*]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_LATCH]] ] ; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_LATCH]] ]
; CHECK-NEXT: [[INC5:%.*]] = add nuw nsw i32 [[INC5_SINK9]], 1 ; CHECK-NEXT: [[INC5_3]] = add nuw nsw i32 [[INC5_SINK9]], 4
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i32 [[NITER]], 1 ; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw nsw i32 [[NITER]], 4
; CHECK-NEXT: [[INC5_1:%.*]] = add nuw nsw i32 [[INC5]], 1
; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i32 [[NITER_NEXT]], 1
; CHECK-NEXT: [[INC5_2:%.*]] = add nuw nsw i32 [[INC5_1]], 1
; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i32 [[NITER_NEXT_1]], 1
; CHECK-NEXT: [[INC5_3]] = add nuw nsw i32 [[INC5_2]], 1
; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw nsw i32 [[NITER_NEXT_2]], 1
; CHECK-NEXT: br label [[FOR_INNER:%.*]] ; CHECK-NEXT: br label [[FOR_INNER:%.*]]
; CHECK: for.inner: ; CHECK: for.inner:
; CHECK-NEXT: [[INC_SINK8:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[INC_SINK8:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[INC_SINK8_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_1:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[INC_SINK8_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_1:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[INC_SINK8_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_2:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[INC_SINK8_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_2:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[INC_SINK8_3:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_3:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[INC_SINK8_3:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_3:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[INC_SINK8]], 1 ; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[INC_SINK8]], 1
; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[INC_SINK8_1]], 1 ; CHECK-NEXT: [[INC_1]] = add nuw nsw i32 [[INC_SINK8_1]], 1
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; CHECK: for.outer: ; CHECK: for.outer:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD_3:%.*]], [[FOR_LATCH:%.*]] ], [ 0, [[FOR_PREHEADER_NEW]] ] ; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD_3:%.*]], [[FOR_LATCH:%.*]] ], [ 0, [[FOR_PREHEADER_NEW]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_LATCH]] ] ; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_LATCH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i32 [[I]] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i32 [[I]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[I]], 1 ; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD]] ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD]]
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i32 [[NITER]], 1
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[ADD]], 1 ; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[I]], 2
; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_1]] ; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_1]]
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i32 [[NITER_NEXT]], 1
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_1]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_1]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_2]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[ADD_1]], 1 ; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[I]], 3
; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_2]] ; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_2]]
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_2]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i32 [[NITER_NEXT_1]], 1
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_2]] ; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_2]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_3]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_3]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD_3]] = add nuw i32 [[ADD_2]], 1 ; CHECK-NEXT: [[ADD_3]] = add nuw i32 [[I]], 4
; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_3]] ; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_3]]
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_3]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_3]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER_NEXT_2]], 1 ; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER]], 4
; CHECK-NEXT: br label [[FOR_INNER:%.*]] ; CHECK-NEXT: br label [[FOR_INNER:%.*]]
; CHECK: for.latch: ; CHECK: for.latch:
; CHECK-NEXT: [[ADD9_LCSSA:%.*]] = phi i32 [ [[ADD9:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[ADD9_LCSSA:%.*]] = phi i32 [ [[ADD9:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[ADD9_LCSSA_1:%.*]] = phi i32 [ [[ADD9_1:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[ADD9_LCSSA_1:%.*]] = phi i32 [ [[ADD9_1:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[ADD9_LCSSA_2:%.*]] = phi i32 [ [[ADD9_2:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[ADD9_LCSSA_2:%.*]] = phi i32 [ [[ADD9_2:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[ADD9_LCSSA_3:%.*]] = phi i32 [ [[ADD9_3:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[ADD9_LCSSA_3:%.*]] = phi i32 [ [[ADD9_3:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: store i32 [[ADD9_LCSSA]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 [[ADD9_LCSSA]], ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: store i32 [[ADD9_LCSSA_1]], ptr [[ARRAYIDX_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 [[ADD9_LCSSA_1]], ptr [[ARRAYIDX_1]], align 4, !tbaa [[TBAA0]]
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; CHECK: for.latch.epil: ; CHECK: for.latch.epil:
; CHECK-NEXT: [[ADD9_LCSSA_EPIL:%.*]] = phi i32 [ [[ADD9_EPIL]], [[FOR_INNER_EPIL]] ] ; CHECK-NEXT: [[ADD9_LCSSA_EPIL:%.*]] = phi i32 [ [[ADD9_EPIL]], [[FOR_INNER_EPIL]] ]
; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL]], ptr [[ARRAYIDX_EPIL]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL]], ptr [[ARRAYIDX_EPIL]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 1, [[XTRAITER]] ; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 1, [[XTRAITER]]
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[FOR_OUTER_EPIL_1:%.*]], label [[FOR_END_LOOPEXIT_EPILOG_LCSSA:%.*]] ; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[FOR_OUTER_EPIL_1:%.*]], label [[FOR_END_LOOPEXIT_EPILOG_LCSSA:%.*]]
; CHECK: for.outer.epil.1: ; CHECK: for.outer.epil.1:
; CHECK-NEXT: [[ARRAYIDX_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL]] ; CHECK-NEXT: [[ARRAYIDX_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add nuw i32 [[ADD_EPIL]], 1 ; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add nuw i32 [[I_UNR]], 2
; CHECK-NEXT: [[ARRAYIDX2_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_1]] ; CHECK-NEXT: [[ARRAYIDX2_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_1]]
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_EPIL_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_EPIL_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: br label [[FOR_INNER_EPIL_1:%.*]] ; CHECK-NEXT: br label [[FOR_INNER_EPIL_1:%.*]]
; CHECK: for.inner.epil.1: ; CHECK: for.inner.epil.1:
; CHECK-NEXT: [[SUM_EPIL_1:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_1]] ], [ [[ADD9_EPIL_1:%.*]], [[FOR_INNER_EPIL_1]] ] ; CHECK-NEXT: [[SUM_EPIL_1:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_1]] ], [ [[ADD9_EPIL_1:%.*]], [[FOR_INNER_EPIL_1]] ]
; CHECK-NEXT: [[J_EPIL_1:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_1]] ], [ [[ADD10_EPIL_1:%.*]], [[FOR_INNER_EPIL_1]] ] ; CHECK-NEXT: [[J_EPIL_1:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_1]] ], [ [[ADD10_EPIL_1:%.*]], [[FOR_INNER_EPIL_1]] ]
; CHECK-NEXT: [[ARRAYIDX7_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_1]] ; CHECK-NEXT: [[ARRAYIDX7_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_1]]
; CHECK-NEXT: [[L1_EPIL_1:%.*]] = load i32, ptr [[ARRAYIDX7_EPIL_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: [[L1_EPIL_1:%.*]] = load i32, ptr [[ARRAYIDX7_EPIL_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD9_EPIL_1]] = add i32 [[L1_EPIL_1]], [[SUM_EPIL_1]] ; CHECK-NEXT: [[ADD9_EPIL_1]] = add i32 [[L1_EPIL_1]], [[SUM_EPIL_1]]
; CHECK-NEXT: [[ADD10_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1 ; CHECK-NEXT: [[ADD10_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1
; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[ADD10_EPIL_1]], [[E]] ; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[ADD10_EPIL_1]], [[E]]
; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label [[FOR_LATCH_EPIL_1:%.*]], label [[FOR_INNER_EPIL_1]] ; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label [[FOR_LATCH_EPIL_1:%.*]], label [[FOR_INNER_EPIL_1]]
; CHECK: for.latch.epil.1: ; CHECK: for.latch.epil.1:
; CHECK-NEXT: [[ADD9_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD9_EPIL_1]], [[FOR_INNER_EPIL_1]] ] ; CHECK-NEXT: [[ADD9_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD9_EPIL_1]], [[FOR_INNER_EPIL_1]] ]
; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL_1]], ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL_1]], ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]] ; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]]
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_OUTER_EPIL_2:%.*]], label [[FOR_END_LOOPEXIT_EPILOG_LCSSA]] ; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_OUTER_EPIL_2:%.*]], label [[FOR_END_LOOPEXIT_EPILOG_LCSSA]]
; CHECK: for.outer.epil.2: ; CHECK: for.outer.epil.2:
; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_1]] ; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_1]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL_2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL_2]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD_EPIL_2:%.*]] = add nuw i32 [[ADD_EPIL_1]], 1 ; CHECK-NEXT: [[ADD_EPIL_2:%.*]] = add nuw i32 [[I_UNR]], 3
; CHECK-NEXT: [[ARRAYIDX2_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_2]] ; CHECK-NEXT: [[ARRAYIDX2_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_2]]
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_EPIL_2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_EPIL_2]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: br label [[FOR_INNER_EPIL_2:%.*]] ; CHECK-NEXT: br label [[FOR_INNER_EPIL_2:%.*]]
; CHECK: for.inner.epil.2: ; CHECK: for.inner.epil.2:
; CHECK-NEXT: [[SUM_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[ADD9_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ] ; CHECK-NEXT: [[SUM_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[ADD9_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ]
; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[ADD10_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ] ; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[ADD10_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ]
; CHECK-NEXT: [[ARRAYIDX7_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_2]] ; CHECK-NEXT: [[ARRAYIDX7_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_2]]
; CHECK-NEXT: [[L1_EPIL_2:%.*]] = load i32, ptr [[ARRAYIDX7_EPIL_2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: [[L1_EPIL_2:%.*]] = load i32, ptr [[ARRAYIDX7_EPIL_2]], align 4, !tbaa [[TBAA0]]
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; CHECK: for.outer: ; CHECK: for.outer:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD_3:%.*]], [[FOR_LATCH:%.*]] ], [ 0, [[FOR_OUTEST_NEW]] ] ; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD_3:%.*]], [[FOR_LATCH:%.*]] ], [ 0, [[FOR_OUTEST_NEW]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_OUTEST_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_LATCH]] ] ; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_OUTEST_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_LATCH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i32 [[I]] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i32 [[I]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[I]], 1 ; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD]] ; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD]]
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i32 [[NITER]], 1
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD]] ; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[ADD]], 1 ; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[I]], 2
; CHECK-NEXT: [[ARRAYIDX6_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_1]] ; CHECK-NEXT: [[ARRAYIDX6_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_1]]
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i32 [[NITER_NEXT]], 1
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_1]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_1]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_2]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[ADD_1]], 1 ; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[I]], 3
; CHECK-NEXT: [[ARRAYIDX6_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_2]] ; CHECK-NEXT: [[ARRAYIDX6_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_2]]
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_2]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i32 [[NITER_NEXT_1]], 1
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_2]] ; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_2]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_3]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_3]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD_3]] = add nuw i32 [[ADD_2]], 1 ; CHECK-NEXT: [[ADD_3]] = add nuw i32 [[I]], 4
; CHECK-NEXT: [[ARRAYIDX6_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_3]] ; CHECK-NEXT: [[ARRAYIDX6_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_3]]
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_3]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_3]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER_NEXT_2]], 1 ; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER]], 4
; CHECK-NEXT: br label [[FOR_INNER:%.*]] ; CHECK-NEXT: br label [[FOR_INNER:%.*]]
; CHECK: for.inner: ; CHECK: for.inner:
; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD9:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD9:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD10:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD10:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD9_1:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD9_1:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[J_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD10_1:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[J_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD10_1:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[SUM_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD9_2:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[SUM_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD9_2:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[J_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD10_2:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[J_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD10_2:%.*]], [[FOR_INNER]] ]
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; CHECK: for.latch.epil: ; CHECK: for.latch.epil:
; CHECK-NEXT: [[ADD9_LCSSA_EPIL:%.*]] = phi i32 [ [[ADD9_EPIL]], [[FOR_INNER_EPIL]] ] ; CHECK-NEXT: [[ADD9_LCSSA_EPIL:%.*]] = phi i32 [ [[ADD9_EPIL]], [[FOR_INNER_EPIL]] ]
; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL]], ptr [[ARRAYIDX_EPIL]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL]], ptr [[ARRAYIDX_EPIL]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 1, [[XTRAITER]] ; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 1, [[XTRAITER]]
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[FOR_OUTER_EPIL_1:%.*]], label [[FOR_CLEANUP_EPILOG_LCSSA:%.*]] ; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[FOR_OUTER_EPIL_1:%.*]], label [[FOR_CLEANUP_EPILOG_LCSSA:%.*]]
; CHECK: for.outer.epil.1: ; CHECK: for.outer.epil.1:
; CHECK-NEXT: [[ARRAYIDX_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL]] ; CHECK-NEXT: [[ARRAYIDX_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add nuw i32 [[ADD_EPIL]], 1 ; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add nuw i32 [[I_UNR]], 2
; CHECK-NEXT: [[ARRAYIDX6_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_1]] ; CHECK-NEXT: [[ARRAYIDX6_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_1]]
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_EPIL_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_EPIL_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: br label [[FOR_INNER_EPIL_1:%.*]] ; CHECK-NEXT: br label [[FOR_INNER_EPIL_1:%.*]]
; CHECK: for.inner.epil.1: ; CHECK: for.inner.epil.1:
; CHECK-NEXT: [[SUM_EPIL_1:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_1]] ], [ [[ADD9_EPIL_1:%.*]], [[FOR_INNER_EPIL_1]] ] ; CHECK-NEXT: [[SUM_EPIL_1:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_1]] ], [ [[ADD9_EPIL_1:%.*]], [[FOR_INNER_EPIL_1]] ]
; CHECK-NEXT: [[J_EPIL_1:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_1]] ], [ [[ADD10_EPIL_1:%.*]], [[FOR_INNER_EPIL_1]] ] ; CHECK-NEXT: [[J_EPIL_1:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_1]] ], [ [[ADD10_EPIL_1:%.*]], [[FOR_INNER_EPIL_1]] ]
; CHECK-NEXT: [[ARRAYIDX11_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_1]] ; CHECK-NEXT: [[ARRAYIDX11_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_1]]
; CHECK-NEXT: [[L1_EPIL_1:%.*]] = load i32, ptr [[ARRAYIDX11_EPIL_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: [[L1_EPIL_1:%.*]] = load i32, ptr [[ARRAYIDX11_EPIL_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD9_EPIL_1]] = add i32 [[L1_EPIL_1]], [[SUM_EPIL_1]] ; CHECK-NEXT: [[ADD9_EPIL_1]] = add i32 [[L1_EPIL_1]], [[SUM_EPIL_1]]
; CHECK-NEXT: [[ADD10_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1 ; CHECK-NEXT: [[ADD10_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1
; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[ADD10_EPIL_1]], [[E]] ; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[ADD10_EPIL_1]], [[E]]
; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label [[FOR_LATCH_EPIL_1:%.*]], label [[FOR_INNER_EPIL_1]] ; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label [[FOR_LATCH_EPIL_1:%.*]], label [[FOR_INNER_EPIL_1]]
; CHECK: for.latch.epil.1: ; CHECK: for.latch.epil.1:
; CHECK-NEXT: [[ADD9_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD9_EPIL_1]], [[FOR_INNER_EPIL_1]] ] ; CHECK-NEXT: [[ADD9_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD9_EPIL_1]], [[FOR_INNER_EPIL_1]] ]
; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL_1]], ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL_1]], ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]] ; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]]
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_OUTER_EPIL_2:%.*]], label [[FOR_CLEANUP_EPILOG_LCSSA]] ; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_OUTER_EPIL_2:%.*]], label [[FOR_CLEANUP_EPILOG_LCSSA]]
; CHECK: for.outer.epil.2: ; CHECK: for.outer.epil.2:
; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_1]] ; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_1]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL_2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL_2]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD_EPIL_2:%.*]] = add nuw i32 [[ADD_EPIL_1]], 1 ; CHECK-NEXT: [[ADD_EPIL_2:%.*]] = add nuw i32 [[I_UNR]], 3
; CHECK-NEXT: [[ARRAYIDX6_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_2]] ; CHECK-NEXT: [[ARRAYIDX6_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_2]]
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_EPIL_2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_EPIL_2]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: br label [[FOR_INNER_EPIL_2:%.*]] ; CHECK-NEXT: br label [[FOR_INNER_EPIL_2:%.*]]
; CHECK: for.inner.epil.2: ; CHECK: for.inner.epil.2:
; CHECK-NEXT: [[SUM_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[ADD9_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ] ; CHECK-NEXT: [[SUM_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[ADD9_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ]
; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[ADD10_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ] ; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[ADD10_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ]
; CHECK-NEXT: [[ARRAYIDX11_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_2]] ; CHECK-NEXT: [[ARRAYIDX11_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_2]]
; CHECK-NEXT: [[L1_EPIL_2:%.*]] = load i32, ptr [[ARRAYIDX11_EPIL_2]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: [[L1_EPIL_2:%.*]] = load i32, ptr [[ARRAYIDX11_EPIL_2]], align 4, !tbaa [[TBAA0]]
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; CHECK-NEXT: br i1 [[TMP1]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_OUTER_PREHEADER_NEW:%.*]] ; CHECK-NEXT: br i1 [[TMP1]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_OUTER_PREHEADER_NEW:%.*]]
; CHECK: for.outer.preheader.new: ; CHECK: for.outer.preheader.new:
; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[I]], [[XTRAITER]] ; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[I]], [[XTRAITER]]
; CHECK-NEXT: br label [[FOR_OUTER:%.*]] ; CHECK-NEXT: br label [[FOR_OUTER:%.*]]
; CHECK: for.outer: ; CHECK: for.outer:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD8_3:%.*]], [[FOR_LATCH:%.*]] ], [ 0, [[FOR_OUTER_PREHEADER_NEW]] ] ; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD8_3:%.*]], [[FOR_LATCH:%.*]] ], [ 0, [[FOR_OUTER_PREHEADER_NEW]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_OUTER_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_LATCH]] ] ; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_OUTER_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_LATCH]] ]
; CHECK-NEXT: [[ADD8:%.*]] = add nuw nsw i32 [[I]], 1 ; CHECK-NEXT: [[ADD8:%.*]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i32 [[NITER]], 1 ; CHECK-NEXT: [[ADD8_1:%.*]] = add nuw nsw i32 [[I]], 2
; CHECK-NEXT: [[ADD8_1:%.*]] = add nuw nsw i32 [[ADD8]], 1 ; CHECK-NEXT: [[ADD8_2:%.*]] = add nuw nsw i32 [[I]], 3
; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i32 [[NITER_NEXT]], 1 ; CHECK-NEXT: [[ADD8_3]] = add nuw i32 [[I]], 4
; CHECK-NEXT: [[ADD8_2:%.*]] = add nuw nsw i32 [[ADD8_1]], 1 ; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER]], 4
; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i32 [[NITER_NEXT_1]], 1
; CHECK-NEXT: [[ADD8_3]] = add nuw i32 [[ADD8_2]], 1
; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER_NEXT_2]], 1
; CHECK-NEXT: br label [[FOR_INNER:%.*]] ; CHECK-NEXT: br label [[FOR_INNER:%.*]]
; CHECK: for.inner: ; CHECK: for.inner:
; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[J_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_1:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[J_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_1:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD_1:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD_1:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[J_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_2:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[J_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_2:%.*]], [[FOR_INNER]] ]
; CHECK-NEXT: [[SUM_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD_2:%.*]], [[FOR_INNER]] ] ; CHECK-NEXT: [[SUM_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD_2:%.*]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[ADD_EPIL_1]] = add i32 [[SEXT_EPIL_1]], [[SUM_EPIL_1]] ; CHECK-NEXT: [[ADD_EPIL_1]] = add i32 [[SEXT_EPIL_1]], [[SUM_EPIL_1]]
; CHECK-NEXT: [[INC_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1 ; CHECK-NEXT: [[INC_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1
; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[INC_EPIL_1]], [[E]] ; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[INC_EPIL_1]], [[E]]
; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label [[FOR_LATCH_EPIL_1:%.*]], label [[FOR_INNER_EPIL_1]] ; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label [[FOR_LATCH_EPIL_1:%.*]], label [[FOR_INNER_EPIL_1]]
; CHECK: for.latch.epil.1: ; CHECK: for.latch.epil.1:
; CHECK-NEXT: [[ADD_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], [[FOR_INNER_EPIL_1]] ] ; CHECK-NEXT: [[ADD_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], [[FOR_INNER_EPIL_1]] ]
; CHECK-NEXT: [[ARRAYIDX6_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD8_EPIL]] ; CHECK-NEXT: [[ARRAYIDX6_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD8_EPIL]]
; CHECK-NEXT: store i32 [[ADD_LCSSA_EPIL_1]], ptr [[ARRAYIDX6_EPIL_1]], align 4, !tbaa [[TBAA0]] ; CHECK-NEXT: store i32 [[ADD_LCSSA_EPIL_1]], ptr [[ARRAYIDX6_EPIL_1]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[ADD8_EPIL_1:%.*]] = add nuw i32 [[ADD8_EPIL]], 1 ; CHECK-NEXT: [[ADD8_EPIL_1:%.*]] = add nuw i32 [[I_UNR]], 2
; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]] ; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]]
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_OUTER_EPIL_2:%.*]], label [[FOR_END_LOOPEXIT_EPILOG_LCSSA]] ; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_OUTER_EPIL_2:%.*]], label [[FOR_END_LOOPEXIT_EPILOG_LCSSA]]
; CHECK: for.outer.epil.2: ; CHECK: for.outer.epil.2:
; CHECK-NEXT: br label [[FOR_INNER_EPIL_2:%.*]] ; CHECK-NEXT: br label [[FOR_INNER_EPIL_2:%.*]]
; CHECK: for.inner.epil.2: ; CHECK: for.inner.epil.2:
; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[INC_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ] ; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[INC_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ]
; CHECK-NEXT: [[SUM_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[ADD_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ] ; CHECK-NEXT: [[SUM_EPIL_2:%.*]] = phi i32 [ 0, [[FOR_OUTER_EPIL_2]] ], [ [[ADD_EPIL_2:%.*]], [[FOR_INNER_EPIL_2]] ]
; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i16, ptr [[B]], i32 [[J_EPIL_2]] ; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i16, ptr [[B]], i32 [[J_EPIL_2]]
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[TOBOOL9:%.*]] = icmp eq i8 [[TMP0]], 0 ; CHECK-NEXT: [[TOBOOL9:%.*]] = icmp eq i8 [[TMP0]], 0
; CHECK-NEXT: [[TOBOOL13:%.*]] = icmp ne i32 [[K:%.*]], 0 ; CHECK-NEXT: [[TOBOOL13:%.*]] = icmp ne i32 [[K:%.*]], 0
; CHECK-NEXT: br i1 false, label [[FOR_END26_UNR_LCSSA:%.*]], label [[ENTRY_NEW:%.*]] ; CHECK-NEXT: br i1 false, label [[FOR_END26_UNR_LCSSA:%.*]], label [[ENTRY_NEW:%.*]]
; CHECK: entry.new: ; CHECK: entry.new:
; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body: ; CHECK: for.body:
; CHECK-NEXT: [[STOREMERGE82:%.*]] = phi i64 [ 0, [[ENTRY_NEW]] ], [ [[INC25_3:%.*]], [[FOR_INC24:%.*]] ] ; CHECK-NEXT: [[STOREMERGE82:%.*]] = phi i64 [ 0, [[ENTRY_NEW]] ], [ [[INC25_3:%.*]], [[FOR_INC24:%.*]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_INC24]] ] ; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_INC24]] ]
; CHECK-NEXT: [[INC25:%.*]] = add nuw nsw i64 [[STOREMERGE82]], 1 ; CHECK-NEXT: [[INC25_3]] = add nuw nsw i64 [[STOREMERGE82]], 4
; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1 ; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw nsw i64 [[NITER]], 4
; CHECK-NEXT: [[INC25_1:%.*]] = add nuw nsw i64 [[INC25]], 1
; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i64 [[NITER_NEXT]], 1
; CHECK-NEXT: [[INC25_2:%.*]] = add nuw nsw i64 [[INC25_1]], 1
; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i64 [[NITER_NEXT_1]], 1
; CHECK-NEXT: [[INC25_3]] = add nuw nsw i64 [[INC25_2]], 1
; CHECK-NEXT: [[NITER_NEXT_3]] = add nuw nsw i64 [[NITER_NEXT_2]], 1
; CHECK-NEXT: br label [[FOR_BODY2:%.*]] ; CHECK-NEXT: br label [[FOR_BODY2:%.*]]
; CHECK: for.body2: ; CHECK: for.body2:
; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i64 [ 4, [[FOR_BODY]] ], [ [[DEC:%.*]], [[FOR_INC21_3:%.*]] ] ; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i64 [ 4, [[FOR_BODY]] ], [ [[DEC:%.*]], [[FOR_INC21_3:%.*]] ]
; CHECK-NEXT: [[STOREMERGE_14:%.*]] = phi i64 [ 4, [[FOR_BODY]] ], [ [[DEC_1:%.*]], [[FOR_INC21_3]] ] ; CHECK-NEXT: [[STOREMERGE_14:%.*]] = phi i64 [ 4, [[FOR_BODY]] ], [ [[DEC_1:%.*]], [[FOR_INC21_3]] ]
; CHECK-NEXT: [[STOREMERGE_25:%.*]] = phi i64 [ 4, [[FOR_BODY]] ], [ [[DEC_2:%.*]], [[FOR_INC21_3]] ] ; CHECK-NEXT: [[STOREMERGE_25:%.*]] = phi i64 [ 4, [[FOR_BODY]] ], [ [[DEC_2:%.*]], [[FOR_INC21_3]] ]
; CHECK-NEXT: [[STOREMERGE_36:%.*]] = phi i64 [ 4, [[FOR_BODY]] ], [ [[DEC_3:%.*]], [[FOR_INC21_3]] ] ; CHECK-NEXT: [[STOREMERGE_36:%.*]] = phi i64 [ 4, [[FOR_BODY]] ], [ [[DEC_3:%.*]], [[FOR_INC21_3]] ]
; CHECK-NEXT: br i1 [[TOBOOL9]], label [[FOR_BODY2_SPLIT:%.*]], label [[FOR_BODY2_SPLIT2:%.*]] ; CHECK-NEXT: br i1 [[TOBOOL9]], label [[FOR_BODY2_SPLIT:%.*]], label [[FOR_BODY2_SPLIT2:%.*]]
; CHECK: for.body2.split2: ; CHECK: for.body2.split2:
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