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Differential D153479

[NFC] Tests for future commit in DAGCombiner
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Authored by kmitropoulou on Jun 21 2023, 3:55 PM.

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arsenm
foad
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rG11cd92a70f26: [NFC] Tests for future commit in DAGCombiner

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kmitropoulou created this revision.Jun 21 2023, 3:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 21 2023, 3:55 PM
Herald added subscribers: kerbowa, jvesely. · View Herald Transcript
kmitropoulou requested review of this revision.Jun 21 2023, 3:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 21 2023, 3:55 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
arsenm added a subscriber: arsenm.Jun 21 2023, 4:07 PM
arsenm added inline comments.
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
2

Why use mir for this?

23

Should also do some SGPR tests

Harbormaster completed remote builds in B240368: Diff 533426.Jun 21 2023, 4:46 PM
kmitropoulou updated this revision to Diff 533443.Jun 21 2023, 5:48 PM

Updating D153479: [NFC] Add tests for future commit in DAGCombiner

kmitropoulou updated this revision to Diff 533448.Jun 21 2023, 6:12 PM

Updating D153479: [NFC] Add tests for future commit in DAGCombiner

kmitropoulou marked 2 inline comments as done.Jun 21 2023, 6:18 PM
kmitropoulou added inline comments.
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
2

CSE changes my optimization. Therefore, I need to do the checking earlier.

For example, the following test:

define i1 @test1(i32 %arg1, i32 %arg2) #0 {

%cmp1 = icmp slt i32 %arg1, 1000
%cmp2 = icmp slt i32 %arg2, 1000
%or  = or i1 %cmp1, %cmp2
ret i1 %or

}

will be optimized as follows with my optimization:

bb.0 (%ir-block.0):
  liveins: $vgpr0, $vgpr1
  %1:vgpr_32 = COPY $vgpr1
  %0:vgpr_32 = COPY $vgpr0
  %2:vgpr_32 = V_MIN_I32_e64 %0, %1, implicit $exec
  %3:sreg_32 = S_MOV_B32 1000
  %4:sreg_32_xm0_xexec = V_CMP_LT_I32_e64 killed %2, killed %3, implicit $exec
  %5:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %4, implicit $exec
  $vgpr0 = COPY %5
  SI_RETURN implicit $vgpr0

This is the output after the instruction selection. After CSE, the predicate of the compare instruction changes:

; %bb.0:

s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
v_min_i32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
s_setpc_b64 s[30:31]
kmitropoulou added reviewers: arsenm, foad.Jun 21 2023, 6:19 PM
Herald added subscribers: StephenFan, wdng. · View Herald TranscriptJun 21 2023, 6:19 PM
kmitropoulou retitled this revision from [NFC] Add tests for future commit in DAGCombiner to [NFC] Tests for future commit in DAGCombiner.Jun 21 2023, 6:21 PM
kmitropoulou marked an inline comment as done.
kmitropoulou added a subscriber: Restricted Project.
arsenm added inline comments.Jun 21 2023, 6:45 PM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
2

I don't understand. I assume you mean MachineCSE? Is your patch not actually a DAG combine as the description states?

Can you stop somewhere after SIFixSGPRCopies instead?

Harbormaster completed remote builds in B240387: Diff 533448.Jun 21 2023, 6:48 PM
kmitropoulou updated this revision to Diff 533458.Jun 21 2023, 7:45 PM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

kmitropoulou added inline comments.Jun 21 2023, 7:48 PM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
2

I am sorry I meant MachineCSE. The patch will upload implements is in DAGCombiner.
The new checks are generated after amdgpu-isel .

kmitropoulou added inline comments.Jun 21 2023, 7:50 PM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
2

*The patch that I will upload implements the optimization in DAGCombiner.

Harbormaster completed remote builds in B240396: Diff 533458.Jun 21 2023, 8:35 PM
kmitropoulou updated this revision to Diff 533466.Jun 21 2023, 9:42 PM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

kmitropoulou added inline comments.Jun 21 2023, 9:43 PM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
2

I am sorry I did not understand your comment earlier :) I update the test.

Harbormaster completed remote builds in B240403: Diff 533466.Jun 21 2023, 10:15 PM
kmitropoulou updated this revision to Diff 533483.Jun 21 2023, 11:56 PM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

Harbormaster completed remote builds in B240416: Diff 533483.Jun 22 2023, 12:46 AM
arsenm added inline comments.Jun 22 2023, 6:41 AM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
2

My original point still stands. Why can't you test the end ISA? In general optimization patches are better of testing end to end unless you specifically need to check some intermediate state

kmitropoulou updated this revision to Diff 533855.Jun 22 2023, 9:25 PM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

kmitropoulou added inline comments.Jun 22 2023, 10:01 PM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
2

Lets' say we have the following test:

define i1 @test1(i32 %arg1, i32 %arg2) #0 {

%cmp1 = icmp slt i32 %arg1, 1000
%cmp2 = icmp slt i32 %arg2, 1000
%or  = or i1 %cmp1, %cmp2
ret i1 %or

}

The dump after SI Fix SGPR copies is:

bb.0 (%ir-block.0):
  liveins: $vgpr0, $vgpr1
  %1:vgpr_32 = COPY $vgpr1
  %0:vgpr_32 = COPY $vgpr0
  %2:vgpr_32 = V_MIN_I32_e64 %0, %1, implicit $exec
  %3:sreg_32 = S_MOV_B32 1000
  %4:sreg_32_xm0_xexec = V_CMP_LT_I32_e64 killed %2, killed %3, implicit $exec
  %5:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %4, implicit $exec
  $vgpr0 = COPY %5
  SI_RETURN implicit $vgpr0

The final output is:

%bb.0:

s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
v_min_i32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
s_setpc_b64 s[30:31]

So, it is easier to check the correctness of the optimization after SI Fix SGPR copies.

If you do not like it, then I can change it.

Harbormaster completed remote builds in B240689: Diff 533855.Jun 22 2023, 10:26 PM
kmitropoulou updated this revision to Diff 533862.Jun 22 2023, 11:03 PM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

Harbormaster completed remote builds in B240696: Diff 533862.Jun 22 2023, 11:48 PM
kmitropoulou updated this revision to Diff 534578.Jun 26 2023, 8:40 AM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

Harbormaster completed remote builds in B241194: Diff 534578.Jun 26 2023, 9:30 AM
arsenm added inline comments.Jun 26 2023, 9:47 AM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
2

You don't actually care about the MIR here, so just go to ISA. You can disable the s_delay_salu insertion for gfx11 with the flag

950

amdgpu_gfx with inreg is less noisy

kmitropoulou added inline comments.Jun 26 2023, 10:28 AM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
2

Which flag?

foad added inline comments.Jun 26 2023, 10:47 AM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
2

-amdgpu-enable-delay-alu=0

kmitropoulou updated this revision to Diff 534739.Jun 26 2023, 1:45 PM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

kmitropoulou marked 3 inline comments as done.Jun 26 2023, 1:47 PM

Thank you all :)

Harbormaster completed remote builds in B241304: Diff 534739.Jun 26 2023, 3:15 PM
kmitropoulou updated this revision to Diff 534783.Jun 26 2023, 4:39 PM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

kmitropoulou added a child revision: D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns.Jun 26 2023, 5:12 PM
Harbormaster completed remote builds in B241331: Diff 534783.Jun 26 2023, 5:50 PM
arsenm accepted this revision.Jun 27 2023, 11:27 AM
This revision is now accepted and ready to land.Jun 27 2023, 11:27 AM
kmitropoulou updated this revision to Diff 537891.Jul 6 2023, 2:53 PM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

arsenm added inline comments.Jul 6 2023, 2:57 PM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
19–20

Do you need tests where these use different constants?

275–276

Some tests where the compare types don't match?

1101

Don't need these attributes

kmitropoulou updated this revision to Diff 537899.Jul 6 2023, 3:23 PM
kmitropoulou marked 3 inline comments as done.

Updating D153479: [NFC] Tests for future commit in DAGCombiner

llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
275–276

In test62, the predicates are different and in test63, the compare types are different.

kmitropoulou added inline comments.Jul 6 2023, 3:32 PM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
19–20

I added test65.

Harbormaster completed remote builds in B243591: Diff 537899.Jul 6 2023, 5:55 PM
kmitropoulou updated this revision to Diff 540253.Jul 13 2023, 7:47 PM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

kmitropoulou updated this revision to Diff 540263.Jul 13 2023, 9:12 PM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

Harbormaster completed remote builds in B245278: Diff 540263.Jul 13 2023, 9:57 PM
kmitropoulou added a child revision: D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points..Jul 14 2023, 1:10 AM
arsenm added inline comments.Jul 14 2023, 5:15 AM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
1875

Also test f16 and v2f16

kmitropoulou updated this revision to Diff 540590.Jul 14 2023, 4:08 PM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

kmitropoulou marked an inline comment as done.Jul 14 2023, 4:08 PM
kmitropoulou added inline comments.Jul 14 2023, 4:11 PM
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
1875

I added tests: test84, test85, test86, test87, test88, test89, tes90 and test91.

Harbormaster completed remote builds in B245513: Diff 540590.Jul 14 2023, 4:55 PM
kmitropoulou updated this revision to Diff 541135.Jul 17 2023, 10:46 AM

Updating D153479: [NFC] Tests for future commit in DAGCombiner

Harbormaster completed remote builds in B245930: Diff 541135.Jul 17 2023, 4:46 PM
This revision was landed with ongoing or failed builds.Jul 17 2023, 5:09 PM
Closed by commit rG11cd92a70f26: [NFC] Tests for future commit in DAGCombiner (authored by kmitropoulou). · Explain Why
This revision was automatically updated to reflect the committed changes.
kmitropoulou added a commit: rG11cd92a70f26: [NFC] Tests for future commit in DAGCombiner.
kmitropoulou removed a child revision: D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points..Aug 2 2023, 1:26 PM

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
742 lines

Diff 533426

llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -stop-after=finalize-isel < %s | FileCheck %s
arsenmUnsubmitted
Done
ReplyInline Actions

Why use mir for this?

arsenm: Why use mir for this?
kmitropoulouAuthorUnsubmitted
Done
ReplyInline Actions

CSE changes my optimization. Therefore, I need to do the checking earlier.

For example, the following test:

define i1 @test1(i32 %arg1, i32 %arg2) #0 {

%cmp1 = icmp slt i32 %arg1, 1000
%cmp2 = icmp slt i32 %arg2, 1000
%or  = or i1 %cmp1, %cmp2
ret i1 %or

}

will be optimized as follows with my optimization:

bb.0 (%ir-block.0):
  liveins: $vgpr0, $vgpr1
  %1:vgpr_32 = COPY $vgpr1
  %0:vgpr_32 = COPY $vgpr0
  %2:vgpr_32 = V_MIN_I32_e64 %0, %1, implicit $exec
  %3:sreg_32 = S_MOV_B32 1000
  %4:sreg_32_xm0_xexec = V_CMP_LT_I32_e64 killed %2, killed %3, implicit $exec
  %5:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %4, implicit $exec
  $vgpr0 = COPY %5
  SI_RETURN implicit $vgpr0

This is the output after the instruction selection. After CSE, the predicate of the compare instruction changes:

; %bb.0:

s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
v_min_i32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
s_setpc_b64 s[30:31]
kmitropoulou: CSE changes my optimization. Therefore, I need to do the checking earlier. For example, the…
arsenmUnsubmitted
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I don't understand. I assume you mean MachineCSE? Is your patch not actually a DAG combine as the description states?

Can you stop somewhere after SIFixSGPRCopies instead?

arsenm: I don't understand. I assume you mean MachineCSE? Is your patch not actually a DAG combine as…
kmitropoulouAuthorUnsubmitted
Done
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I am sorry I meant MachineCSE. The patch will upload implements is in DAGCombiner.
The new checks are generated after amdgpu-isel .

kmitropoulou: I am sorry I meant MachineCSE. The patch will upload implements is in DAGCombiner. The new…
kmitropoulouAuthorUnsubmitted
Done
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*The patch that I will upload implements the optimization in DAGCombiner.

kmitropoulou: *The patch that I will upload implements the optimization in DAGCombiner.
kmitropoulouAuthorUnsubmitted
Done
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I am sorry I did not understand your comment earlier :) I update the test.

kmitropoulou: I am sorry I did not understand your comment earlier :) I update the test.
arsenmUnsubmitted
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My original point still stands. Why can't you test the end ISA? In general optimization patches are better of testing end to end unless you specifically need to check some intermediate state

arsenm: My original point still stands. Why can't you test the end ISA? In general optimization patches…
kmitropoulouAuthorUnsubmitted
Done
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Lets' say we have the following test:

define i1 @test1(i32 %arg1, i32 %arg2) #0 {

%cmp1 = icmp slt i32 %arg1, 1000
%cmp2 = icmp slt i32 %arg2, 1000
%or  = or i1 %cmp1, %cmp2
ret i1 %or

}

The dump after SI Fix SGPR copies is:

bb.0 (%ir-block.0):
  liveins: $vgpr0, $vgpr1
  %1:vgpr_32 = COPY $vgpr1
  %0:vgpr_32 = COPY $vgpr0
  %2:vgpr_32 = V_MIN_I32_e64 %0, %1, implicit $exec
  %3:sreg_32 = S_MOV_B32 1000
  %4:sreg_32_xm0_xexec = V_CMP_LT_I32_e64 killed %2, killed %3, implicit $exec
  %5:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %4, implicit $exec
  $vgpr0 = COPY %5
  SI_RETURN implicit $vgpr0

The final output is:

%bb.0:

s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
v_min_i32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
s_setpc_b64 s[30:31]

So, it is easier to check the correctness of the optimization after SI Fix SGPR copies.

If you do not like it, then I can change it.

kmitropoulou: Lets' say we have the following test: define i1 @test1(i32 %arg1, i32 %arg2) #0 { %cmp1 =…
arsenmUnsubmitted
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You don't actually care about the MIR here, so just go to ISA. You can disable the s_delay_salu insertion for gfx11 with the flag

arsenm: You don't actually care about the MIR here, so just go to ISA. You can disable the s_delay_salu…
kmitropoulouAuthorUnsubmitted
Done
ReplyInline Actions

Which flag?

kmitropoulou: Which flag?
foadUnsubmitted
Done
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-amdgpu-enable-delay-alu=0

foad: `-amdgpu-enable-delay-alu=0`
define i1 @test1(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test1
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1000
; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_LT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_LT_I32_e64_]], killed [[V_CMP_LT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp slt i32 %arg1, 1000
%cmp2 = icmp slt i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
arsenmUnsubmitted
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Do you need tests where these use different constants?

arsenm: Do you need tests where these use different constants?
kmitropoulouAuthorUnsubmitted
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I added test65.

kmitropoulou: I added test65.
ret i1 %or
}
arsenmUnsubmitted
Done
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Should also do some SGPR tests

arsenm: Should also do some SGPR tests
define i1 @test2(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test2
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1000
; CHECK-NEXT: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_U32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_LT_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_U32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_LT_U32_e64_]], killed [[V_CMP_LT_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ult i32 %arg1, 1000
%cmp2 = icmp ult i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test3(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test3
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1001
; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_LT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_LT_I32_e64_]], killed [[V_CMP_LT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp sle i32 %arg1, 1000
%cmp2 = icmp sle i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test4(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test4
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1001
; CHECK-NEXT: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_U32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_LT_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_U32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_LT_U32_e64_]], killed [[V_CMP_LT_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ule i32 %arg1, 1000
%cmp2 = icmp ule i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test5(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test5
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1000
; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_GT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_GT_I32_e64_]], killed [[V_CMP_GT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp sgt i32 %arg1, 1000
%cmp2 = icmp sgt i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test6(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test6
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1000
; CHECK-NEXT: [[V_CMP_GT_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_U32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_GT_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GT_U32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_GT_U32_e64_]], killed [[V_CMP_GT_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ugt i32 %arg1, 1000
%cmp2 = icmp ugt i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test7(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test7
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 999
; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_GT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_GT_I32_e64_]], killed [[V_CMP_GT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp sge i32 %arg1, 1000
%cmp2 = icmp sge i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test8(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test8
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 999
; CHECK-NEXT: [[V_CMP_GT_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_U32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_GT_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GT_U32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_GT_U32_e64_]], killed [[V_CMP_GT_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp uge i32 %arg1, 1000
%cmp2 = icmp uge i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test9(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test9
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_LT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_LT_I32_e64_]], killed [[V_CMP_LT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp slt i32 %arg1, %arg3
%cmp2 = icmp slt i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test10(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test10
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_U32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_LT_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_U32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_LT_U32_e64_]], killed [[V_CMP_LT_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ult i32 %arg1, %arg3
%cmp2 = icmp ult i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test11(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test11
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_LE_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_I32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_LE_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LE_I32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_LE_I32_e64_]], killed [[V_CMP_LE_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp sle i32 %arg1, %arg3
%cmp2 = icmp sle i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test12(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test12
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_LE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_U32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_LE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LE_U32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_LE_U32_e64_]], killed [[V_CMP_LE_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ule i32 %arg1, %arg3
%cmp2 = icmp ule i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test13(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test13
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_GT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_GT_I32_e64_]], killed [[V_CMP_GT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp sgt i32 %arg1, %arg3
%cmp2 = icmp sgt i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test14(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test14
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_GT_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_U32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_GT_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GT_U32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_GT_U32_e64_]], killed [[V_CMP_GT_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
arsenmUnsubmitted
Done
ReplyInline Actions

Some tests where the compare types don't match?

arsenm: Some tests where the compare types don't match?
kmitropoulouAuthorUnsubmitted
Done
ReplyInline Actions

In test62, the predicates are different and in test63, the compare types are different.

kmitropoulou: In test62, the predicates are different and in test63, the compare types are different.
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ugt i32 %arg1, %arg3
%cmp2 = icmp ugt i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test15(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test15
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_GE_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_I32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_GE_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GE_I32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_GE_I32_e64_]], killed [[V_CMP_GE_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp sge i32 %arg1, %arg3
%cmp2 = icmp sge i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test16(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test16
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_GE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_U32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_GE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GE_U32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_GE_U32_e64_]], killed [[V_CMP_GE_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp uge i32 %arg1, %arg3
%cmp2 = icmp uge i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test17(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test17
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1000
; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_LT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_LT_I32_e64_]], killed [[V_CMP_LT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp slt i32 %arg1, 1000
%cmp2 = icmp slt i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test18(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test18
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1000
; CHECK-NEXT: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_U32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_LT_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_U32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_LT_U32_e64_]], killed [[V_CMP_LT_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ult i32 %arg1, 1000
%cmp2 = icmp ult i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test19(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test19
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1001
; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_LT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_LT_I32_e64_]], killed [[V_CMP_LT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp sle i32 %arg1, 1000
%cmp2 = icmp sle i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test20(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test20
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1001
; CHECK-NEXT: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_U32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_LT_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_U32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_LT_U32_e64_]], killed [[V_CMP_LT_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ule i32 %arg1, 1000
%cmp2 = icmp ule i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test21(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test21
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1000
; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_GT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_GT_I32_e64_]], killed [[V_CMP_GT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp sgt i32 %arg1, 1000
%cmp2 = icmp sgt i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test22(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test22
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1000
; CHECK-NEXT: [[V_CMP_GT_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_U32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_GT_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GT_U32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_GT_U32_e64_]], killed [[V_CMP_GT_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ugt i32 %arg1, 1000
%cmp2 = icmp ugt i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test23(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test23
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 999
; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_GT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_GT_I32_e64_]], killed [[V_CMP_GT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp sge i32 %arg1, 1000
%cmp2 = icmp sge i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test24(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test24
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 999
; CHECK-NEXT: [[V_CMP_GT_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_U32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[V_CMP_GT_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GT_U32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_GT_U32_e64_]], killed [[V_CMP_GT_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp uge i32 %arg1, 1000
%cmp2 = icmp uge i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test25(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test25
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_LT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_LT_I32_e64_]], killed [[V_CMP_LT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp slt i32 %arg1, %arg3
%cmp2 = icmp slt i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test26(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test26
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_U32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_LT_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_U32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_LT_U32_e64_]], killed [[V_CMP_LT_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ult i32 %arg1, %arg3
%cmp2 = icmp ult i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test27(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test27
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_LE_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_I32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_LE_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LE_I32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_LE_I32_e64_]], killed [[V_CMP_LE_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp sle i32 %arg1, %arg3
%cmp2 = icmp sle i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test28(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test28
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_LE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_U32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_LE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LE_U32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_LE_U32_e64_]], killed [[V_CMP_LE_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ule i32 %arg1, %arg3
%cmp2 = icmp ule i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test29(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test29
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_GT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_GT_I32_e64_]], killed [[V_CMP_GT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp sgt i32 %arg1, %arg3
%cmp2 = icmp sgt i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test30(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test30
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_GT_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_U32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_GT_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GT_U32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_GT_U32_e64_]], killed [[V_CMP_GT_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ugt i32 %arg1, %arg3
%cmp2 = icmp ugt i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test31(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test31
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_GE_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_I32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_GE_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GE_I32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_GE_I32_e64_]], killed [[V_CMP_GE_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp sge i32 %arg1, %arg3
%cmp2 = icmp sge i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test32(i32 %arg1, i32 %arg2, i32 %arg3) #0 {
; CHECK-LABEL: name: test32
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_GE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_U32_e64 [[COPY2]], [[COPY]], implicit $exec
; CHECK-NEXT: [[V_CMP_GE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_GE_U32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_GE_U32_e64_]], killed [[V_CMP_GE_U32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_AND_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp uge i32 %arg1, %arg3
%cmp2 = icmp uge i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
ret i1 %and
}
define i1 @test33(i32 %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: test33
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY1]], [[COPY]], implicit $exec
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1000
; CHECK-NEXT: [[V_CMP_LT_I32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY1]], killed [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_LT_I32_e64_]], killed [[V_CMP_LT_I32_e64_1]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp slt i32 %arg1, %arg2
%cmp2 = icmp slt i32 %arg1, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test34(i32 %arg1, i64 %arg2) #0 {
; CHECK-LABEL: name: test34
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1000
; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[COPY2]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, killed [[S_MOV_B32_1]], %subreg.sub1
; CHECK-NEXT: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I64_e64 killed [[REG_SEQUENCE]], killed [[REG_SEQUENCE1]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_LT_I32_e64_]], killed [[V_CMP_LT_I64_e64_]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp slt i32 %arg1, 1000
%cmp2 = icmp slt i64 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test35(i32 %arg1, i64 %arg2) #0 {
; CHECK-LABEL: name: test35
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1000
; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY2]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, killed [[S_MOV_B32_1]], %subreg.sub1
; CHECK-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U64_e64 killed [[REG_SEQUENCE]], killed [[REG_SEQUENCE1]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_EQ_U32_e64_]], killed [[V_CMP_EQ_U64_e64_]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp eq i32 %arg1, 1000
%cmp2 = icmp eq i64 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
define i1 @test36(i32 %arg1, i64 %arg2) #0 {
; CHECK-LABEL: name: test36
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1000
; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY2]], [[S_MOV_B32_]], implicit $exec
; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, killed [[S_MOV_B32_1]], %subreg.sub1
; CHECK-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U64_e64 killed [[REG_SEQUENCE]], killed [[REG_SEQUENCE1]], implicit $exec
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 killed [[V_CMP_NE_U32_e64_]], killed [[V_CMP_NE_U64_e64_]], implicit-def dead $scc
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B32_]], implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%cmp1 = icmp ne i32 %arg1, 1000
%cmp2 = icmp ne i64 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
attributes #0 = { nounwind readnone }
arsenmUnsubmitted
Done
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amdgpu_gfx with inreg is less noisy

arsenm: amdgpu_gfx with inreg is less noisy
arsenmUnsubmitted
Done
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Don't need these attributes

arsenm: Don't need these attributes
arsenmUnsubmitted
Done
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Also test f16 and v2f16

arsenm: Also test f16 and v2f16
kmitropoulouAuthorUnsubmitted
Done
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I added tests: test84, test85, test86, test87, test88, test89, tes90 and test91.

kmitropoulou: I added tests: test84, test85, test86, test87, test88, test89, tes90 and test91.