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Differential D152797

[AMDGPU][ValueTracking] Precommit tests for amdgcn intrinsics that cannot create poison
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Authored by foad on Jun 13 2023, 3:37 AM.

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nhaehnle
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Restricted Project

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foad created this revision.Jun 13 2023, 3:37 AM
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foad requested review of this revision.Jun 13 2023, 3:37 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 13 2023, 3:37 AM
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foad added a child revision: D152798: [AMDGPU][ValueTracking] Handle amdgcn intrinsics that cannot create poison.Jun 13 2023, 3:51 AM
Harbormaster completed remote builds in B238446: Diff 530848.Jun 13 2023, 5:44 AM
nhaehnle accepted this revision.Jun 13 2023, 8:00 AM
This revision is now accepted and ready to land.Jun 13 2023, 8:00 AM

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
AMDGPU/
224 lines

Diff 530848

llvm/test/Transforms/InstCombine/AMDGPU/freeze.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -march=amdgcn -S -passes=instcombine < %s | FileCheck %s
define float @fmed3(float noundef %x, float noundef %y, float noundef %z) {
; CHECK-LABEL: define float @fmed3
; CHECK-SAME: (float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[X]], float [[Y]], float [[Z]])
; CHECK-NEXT: [[FRZ:%.*]] = freeze float [[VAL]]
; CHECK-NEXT: ret float [[FRZ]]
;
%val = call float @llvm.amdgcn.fmed3.f32(float %x, float %y, float %z)
%frz = freeze float %val
ret float %frz
}
define float @fmul.legacy(float noundef %x, float noundef %y) {
; CHECK-LABEL: define float @fmul.legacy
; CHECK-SAME: (float noundef [[X:%.*]], float noundef [[Y:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.fmul.legacy(float [[X]], float [[Y]])
; CHECK-NEXT: [[FRZ:%.*]] = freeze float [[VAL]]
; CHECK-NEXT: ret float [[FRZ]]
;
%val = call float @llvm.amdgcn.fmul.legacy(float %x, float %y)
%frz = freeze float %val
ret float %frz
}
define float @fract(float noundef %x) {
; CHECK-LABEL: define float @fract
; CHECK-SAME: (float noundef [[X:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; CHECK-NEXT: [[FRZ:%.*]] = freeze float [[VAL]]
; CHECK-NEXT: ret float [[FRZ]]
;
%val = call float @llvm.amdgcn.fract.f32(float %x)
%frz = freeze float %val
ret float %frz
}
define i32 @icmp(i32 noundef %x, i32 noundef %y) {
; CHECK-LABEL: define i32 @icmp
; CHECK-SAME: (i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.icmp.i32.i32(i32 [[X]], i32 [[Y]], i32 0)
; CHECK-NEXT: [[FRZ:%.*]] = freeze i32 [[VAL]]
; CHECK-NEXT: ret i32 [[FRZ]]
;
%val = call i32 @llvm.amdgcn.icmp.i32(i32 %x, i32 %y, i32 0)
%frz = freeze i32 %val
ret i32 %frz
}
define float @interp.p1(float noundef %x) {
; CHECK-LABEL: define float @interp.p1
; CHECK-SAME: (float noundef [[X:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.interp.p1(float [[X]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[FRZ:%.*]] = freeze float [[VAL]]
; CHECK-NEXT: ret float [[FRZ]]
;
%val = call float @llvm.amdgcn.interp.p1(float %x, i32 0, i32 0, i32 0)
%frz = freeze float %val
ret float %frz
}
define float @interp.p1.f16(float noundef %x) {
; CHECK-LABEL: define float @interp.p1.f16
; CHECK-SAME: (float noundef [[X:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.interp.p1.f16(float [[X]], i32 0, i32 0, i1 false, i32 0)
; CHECK-NEXT: [[FRZ:%.*]] = freeze float [[VAL]]
; CHECK-NEXT: ret float [[FRZ]]
;
%val = call float @llvm.amdgcn.interp.p1.f16(float %x, i32 0, i32 0, i1 false, i32 0)
%frz = freeze float %val
ret float %frz
}
define float @interp.p2(float noundef %x, float noundef %y) {
; CHECK-LABEL: define float @interp.p2
; CHECK-SAME: (float noundef [[X:%.*]], float noundef [[Y:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.interp.p2(float [[X]], float [[Y]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[FRZ:%.*]] = freeze float [[VAL]]
; CHECK-NEXT: ret float [[FRZ]]
;
%val = call float @llvm.amdgcn.interp.p2(float %x, float %y, i32 0, i32 0, i32 0)
%frz = freeze float %val
ret float %frz
}
define half @interp.p2.f16(float noundef %x, float noundef %y) {
; CHECK-LABEL: define half @interp.p2.f16
; CHECK-SAME: (float noundef [[X:%.*]], float noundef [[Y:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.interp.p2.f16(float [[X]], float [[Y]], i32 0, i32 0, i1 false, i32 0)
; CHECK-NEXT: [[FRZ:%.*]] = freeze half [[VAL]]
; CHECK-NEXT: ret half [[FRZ]]
;
%val = call half @llvm.amdgcn.interp.p2.f16(float %x, float %y, i32 0, i32 0, i1 false, i32 0)
%frz = freeze half %val
ret half %frz
}
define i32 @mbcnt.hi(i32 noundef %x) {
; CHECK-LABEL: define i32 @mbcnt.hi
; CHECK-SAME: (i32 noundef [[X:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[X]], i32 0)
; CHECK-NEXT: [[FRZ:%.*]] = freeze i32 [[VAL]]
; CHECK-NEXT: ret i32 [[FRZ]]
;
%val = call i32 @llvm.amdgcn.mbcnt.hi(i32 %x, i32 0)
%frz = freeze i32 %val
ret i32 %frz
}
define i32 @mbcnt.lo(i32 noundef %x) {
; CHECK-LABEL: define i32 @mbcnt.lo
; CHECK-SAME: (i32 noundef [[X:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[X]], i32 0)
; CHECK-NEXT: [[FRZ:%.*]] = freeze i32 [[VAL]]
; CHECK-NEXT: ret i32 [[FRZ]]
;
%val = call i32 @llvm.amdgcn.mbcnt.hi(i32 %x, i32 0)
%frz = freeze i32 %val
ret i32 %frz
}
define float @rcp(float noundef %x) {
; CHECK-LABEL: define float @rcp
; CHECK-SAME: (float noundef [[X:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[X]])
; CHECK-NEXT: [[FRZ:%.*]] = freeze float [[VAL]]
; CHECK-NEXT: ret float [[FRZ]]
;
%val = call float @llvm.amdgcn.rcp.f32(float %x)
%frz = freeze float %val
ret float %frz
}
define i32 @readfirstlane(i32 noundef %x) {
; CHECK-LABEL: define i32 @readfirstlane
; CHECK-SAME: (i32 noundef [[X:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.readfirstlane(i32 [[X]])
; CHECK-NEXT: [[FRZ:%.*]] = freeze i32 [[VAL]]
; CHECK-NEXT: ret i32 [[FRZ]]
;
%val = call i32 @llvm.amdgcn.readfirstlane(i32 %x)
%frz = freeze i32 %val
ret i32 %frz
}
define i32 @readlane(i32 noundef %x) {
; CHECK-LABEL: define i32 @readlane
; CHECK-SAME: (i32 noundef [[X:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[X]], i32 7)
; CHECK-NEXT: [[FRZ:%.*]] = freeze i32 [[VAL]]
; CHECK-NEXT: ret i32 [[FRZ]]
;
%val = call i32 @llvm.amdgcn.readlane(i32 %x, i32 7)
%frz = freeze i32 %val
ret i32 %frz
}
define float @rsq(float noundef %x) {
; CHECK-LABEL: define float @rsq
; CHECK-SAME: (float noundef [[X:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.rsq.f32(float [[X]])
; CHECK-NEXT: [[FRZ:%.*]] = freeze float [[VAL]]
; CHECK-NEXT: ret float [[FRZ]]
;
%val = call float @llvm.amdgcn.rsq.f32(float %x)
%frz = freeze float %val
ret float %frz
}
define i32 @softwqm(i32 noundef %x) {
; CHECK-LABEL: define i32 @softwqm
; CHECK-SAME: (i32 noundef [[X:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.softwqm.i32(i32 [[X]])
; CHECK-NEXT: [[FRZ:%.*]] = freeze i32 [[VAL]]
; CHECK-NEXT: ret i32 [[FRZ]]
;
%val = call i32 @llvm.amdgcn.softwqm.i32(i32 %x)
%frz = freeze i32 %val
ret i32 %frz
}
define i32 @wqm(i32 noundef %x) {
; CHECK-LABEL: define i32 @wqm
; CHECK-SAME: (i32 noundef [[X:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.wqm.i32(i32 [[X]])
; CHECK-NEXT: [[FRZ:%.*]] = freeze i32 [[VAL]]
; CHECK-NEXT: ret i32 [[FRZ]]
;
%val = call i32 @llvm.amdgcn.wqm.i32(i32 %x)
%frz = freeze i32 %val
ret i32 %frz
}
define i32 @wwm(i32 noundef %x) {
; CHECK-LABEL: define i32 @wwm
; CHECK-SAME: (i32 noundef [[X:%.*]]) {
; CHECK-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[X]])
; CHECK-NEXT: [[FRZ:%.*]] = freeze i32 [[VAL]]
; CHECK-NEXT: ret i32 [[FRZ]]
;
%val = call i32 @llvm.amdgcn.wwm.i32(i32 %x)
%frz = freeze i32 %val
ret i32 %frz
}
declare float @llvm.amdgcn.fmed3.f32(float, float, float)
declare float @llvm.amdgcn.fmul.legacy(float, float)
declare float @llvm.amdgcn.fract.f32(float)
declare i32 @llvm.amdgcn.icmp.i32(i32, i32, i32)
declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32)
declare float @llvm.amdgcn.interp.p1.f16(float, i32, i32, i1, i32)
declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32)
declare half @llvm.amdgcn.interp.p2.f16(float, float, i32, i32, i1, i32)
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32)
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32)
declare float @llvm.amdgcn.rcp.f32(float)
declare i32 @llvm.amdgcn.readfirstlane(i32)
declare i32 @llvm.amdgcn.readlane(i32, i32)
declare float @llvm.amdgcn.rsq.f32(float)
declare i32 @llvm.amdgcn.softwqm.i32(i32)
declare i32 @llvm.amdgcn.wqm.i32(i32)
declare i32 @llvm.amdgcn.wwm.i32(i32)