[AVR] Optimize 8-bit rotation when rotation bits >= 4

[benshi001]

Summary

Fixes https://github.com/llvm/llvm-project/issues/63100

[jacquesguan]

LGTM.

[benshi001]

@aykevl How about your thoughts on this change ?

llvm/lib/Target/AVR/AVRISelLowering.cpp

if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
       Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
                            DAG.getConstant(6, dl, VT));
       ShiftAmount = 0;
     } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
       // Optimize ASR when ShiftAmount == 7.
       Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
                            DAG.getConstant(7, dl, VT));
       ShiftAmount = 0;
+    } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 7) {
+      // Optimize left rotation 7 bits to right rotation 1 bit.
+      Victim =
+          DAG.getNode(AVRISD::ROR, dl, VT, Victim, DAG.getConstant(1, dl, VT));
+      ShiftAmount = 0;
+    } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 7) {
+      // Optimize right rotation 7 bits to left rotation 1 bit.
+      Victim =
+          DAG.getNode(AVRISD::ROL, dl, VT, Victim, DAG.getConstant(1, dl, VT));
+      ShiftAmount = 0;
+    } else if ((Op.getOpcode() == ISD::ROTR || Op.getOpcode() == ISD::ROTL) &&
+               ShiftAmount >= 4) {
+      // Optimize left/right rotation with the SWAP instruction.
+      Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
+      ShiftAmount -= 4;
     }
   } else if (VT.getSizeInBits() == 16) {
     if (Op.getOpcode() == ISD::SRA)
       // Special optimization for int16 arithmetic right shift.
       switch (ShiftAmount) {
       case 15:
         Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
                              DAG.getConstant(15, dl, VT));

llvm/test/CodeGen/AVR/rotate.ll

 start:
   %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
   ret i8 %0
 }
 
 define i8 @rotl8_5(i8 %x) {
 ; CHECK-LABEL: rotl8_5:
 ; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
+; CHECK-NEXT:    swap r24
 ; CHECK-NEXT:    lsl r24
 ; CHECK-NEXT:    adc r24, r1
 ; CHECK-NEXT:    ret
 start:
   %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 5)
   ret i8 %0
 }
 
 define i8 @rotl8_7(i8 %x) {
 ; CHECK-LABEL: rotl8_7:
 ; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
+; CHECK-NEXT:    bst r24, 0
+; CHECK-NEXT:    ror r24
+; CHECK-NEXT:    bld r24, 7
 ; CHECK-NEXT:    ret
 start:
   %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 7)
   ret i8 %0
 }
 
 define i8 @rotl8_dyn(i8 %x, i8 %y) {
 ; CHECK-LABEL: rotl8_dyn:

 start:
   %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
   ret i8 %0
 }
 
 define i8 @rotr8_5(i8 %x) {
 ; CHECK-LABEL: rotr8_5:
 ; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
+; CHECK-NEXT:    swap r24
 ; CHECK-NEXT:    bst r24, 0
 ; CHECK-NEXT:    ror r24
 ; CHECK-NEXT:    bld r24, 7
 ; CHECK-NEXT:    ret
 start:
   %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 5)
   ret i8 %0
 }
 
 define i8 @rotr8_7(i8 %x) {
 ; CHECK-LABEL: rotr8_7:
 ; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
+; CHECK-NEXT:    lsl r24
+; CHECK-NEXT:    adc r24, r1
 ; CHECK-NEXT:    ret
 start:
   %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 7)
   ret i8 %0
 }
 
 define i8 @rotr8_dyn(i8 %x, i8 %y) {
 ; CHECK-LABEL: rotr8_dyn: