[AVR] Fix incorrect expansion of pseudo instruction ROLBRd

[benshi001]

Summary

Since ROLBRd needs an implicit R1 (on AVR) or an implicit R17 (on AVRTiny),
we split ROLBRd to ROLBRdR1 (on AVR) and ROLBRdR17 (on AVRTiny).

[Patryk27]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1505

Hmm, this feels kinda excessive - wouldn't adding let Uses = [R1] to ROLBRd be sufficient?

let Uses = [R1] in
def ROLBRd : Pseudo<(outs GPR8
                     : $rd),
                    (ins GPR8
                     : $src),
                    "rolb\t$rd",
                    [(set i8
                      : $rd, (AVRrol i8
                              : $src)),
                     (implicit SREG)]>;

[benshi001]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1505

Because it maybe R17 on AVRTINY.

[benshi001]

llvm/test/CodeGen/AVR/rotate.ll

67 ↗

(On Diff #528747)

We need not worry this, since I have made optimization for that, https://reviews.llvm.org/D152130

[Patryk27]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1505

ah, true, true

[Patryk27]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1505

Maybe we could have two separate instructions, then?

Something like:

diff --git a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
index 726ed7303746..94cabb4e1387 100644
--- a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
@@ -1481,7 +1481,48 @@ bool AVRExpandPseudo::expand<AVR::POPWRd>(Block &MBB, BlockIt MBBI) {
 }
 
 template <>
-bool AVRExpandPseudo::expand<AVR::ROLBRd>(Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expand<AVR::ROLBRdNT>(Block &MBB, BlockIt MBBI) {
+  // In AVR, the rotate instructions behave quite unintuitively. They rotate
+  // bits through the carry bit in SREG, effectively rotating over 9 bits,
+  // instead of 8. This is useful when we are dealing with numbers over
+  // multiple registers, but when we actually need to rotate stuff, we have
+  // to explicitly add the carry bit.
+
+  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
+
+  MachineInstr &MI = *MBBI;
+  unsigned OpShift, OpCarry;
+  Register DstReg = MI.getOperand(0).getReg();
+  Register ZeroReg = STI.getZeroRegister();
+  bool DstIsDead = MI.getOperand(0).isDead();
+  bool DstIsKill = MI.getOperand(1).isKill();
+  OpShift = AVR::ADDRdRr;
+  OpCarry = AVR::ADCRdRr;
+
+  // add r16, r16
+  // adc r16, r1
+
+  // Shift part
+  buildMI(MBB, MBBI, OpShift)
+      .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
+
+  // Add the carry bit
+  auto MIB = buildMI(MBB, MBBI, OpCarry)
+                 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+                 .addReg(DstReg, getKillRegState(DstIsKill))
+                 .addReg(ZeroReg);
+
+  MIB->getOperand(3).setIsDead(); // SREG is always dead
+  MIB->getOperand(4).setIsKill(); // SREG is always implicitly killed
+
+  MI.eraseFromParent();
+  return true;
+}
+
+template <>
+bool AVRExpandPseudo::expand<AVR::ROLBRdT>(Block &MBB, BlockIt MBBI) {
   // In AVR, the rotate instructions behave quite unintuitively. They rotate
   // bits through the carry bit in SREG, effectively rotating over 9 bits,
   // instead of 8. This is useful when we are dealing with numbers over
@@ -2605,7 +2646,8 @@ bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
     EXPAND(AVR::OUTWARr);
     EXPAND(AVR::PUSHWRr);
     EXPAND(AVR::POPWRd);
-    EXPAND(AVR::ROLBRd);
+    EXPAND(AVR::ROLBRdNT);
+    EXPAND(AVR::ROLBRdT);
     EXPAND(AVR::RORBRd);
     EXPAND(AVR::LSLWRd);
     EXPAND(AVR::LSRWRd);
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index e44ef51ab3a8..d97b02681f2e 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -1758,6 +1758,7 @@ MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
   MachineFunction *F = BB->getParent();
   MachineRegisterInfo &RI = F->getRegInfo();
   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
+  const AVRSubtarget &STI = F->getSubtarget<AVRSubtarget>();
   DebugLoc dl = MI.getDebugLoc();
 
   switch (MI.getOpcode()) {
@@ -1789,7 +1790,7 @@ MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
     RC = &AVR::DREGSRegClass;
     break;
   case AVR::Rol8:
-    Opc = AVR::ROLBRd;
+    Opc = STI.hasTinyEncoding() ? AVR::ROLBRdT : AVR::ROLBRdNT;
     RC = &AVR::GPR8RegClass;
     break;
   case AVR::Rol16:
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td
index d0e75733114a..630369d2d25e 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -2029,7 +2029,8 @@ let Constraints = "$src = $rd", Defs = [SREG] in {
   def ASRWLoRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "asrwlo\t$rd",
                         [(set i16:$rd, (AVRasrlo i16:$src)), (implicit SREG)]>;
 
-  def ROLBRd : Pseudo<(outs GPR8
+  let Uses = [R1] in
+  def ROLBRdNT : Pseudo<(outs GPR8
                        : $rd),
                       (ins GPR8
                        : $src),
@@ -2037,7 +2038,20 @@ let Constraints = "$src = $rd", Defs = [SREG] in {
                       [(set i8
                         : $rd, (AVRrol i8
                                 : $src)),
-                       (implicit SREG)]>;
+                       (implicit SREG)]>,
+                       Requires<[HasNonTinyEncoding]>;
+
+  let Uses = [R17] in
+  def ROLBRdT : Pseudo<(outs GPR8
+                       : $rd),
+                      (ins GPR8
+                       : $src),
+                      "rolb\t$rd",
+                      [(set i8
+                        : $rd, (AVRrol i8
+                                : $src)),
+                       (implicit SREG)]>,
+                       Requires<[HasTinyEncoding]>;
 
   def RORBRd : Pseudo<(outs GPR8
                        : $rd),

Of course, this naive approach copy-pastes the code responsible for expanding the pseudo-instruction, but that could should be pretty easy to de-duplicate.

[aykevl]

This looks correct at first glance, but of course a bit inefficient.

I see two options to make this efficient:

1. As proposed by @Patryk27, using two different instructions to differentiate between R1 and R17. This most likely works just fine.
2. Custom lowering for ROLB that adds the zero register. There are many custom lowered instructions, this could be one of them.

I have a slight preference for option 1 (as it's perhaps a little bit more explicit), but either way would work.

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1500

Nit: this is eor, not xor.

1505

You can use this:

buildMI(MBB, MBBI, AVR::EORRdRr, TmpReg)
      .addReg(TmpReg)
      .addReg(TmpReg);

The third parameter to buildMI is the register to define.

[benshi001]

Thanks for both of your suggestion, I have split ROLBRd to ROLBRdR1 and ROLBRdR17.

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

private:
   bool expandLSRW12Rd(Block &MBB, BlockIt MBBI);
   bool expandASRW14Rd(Block &MBB, BlockIt MBBI);
   bool expandASRW15Rd(Block &MBB, BlockIt MBBI);
 
   // Common implementation of LPMWRdZ and ELPMWRdZ.
   bool expandLPMWELPMW(Block &MBB, BlockIt MBBI, bool IsELPM);
   // Common implementation of LPMBRdZ and ELPMBRdZ.
   bool expandLPMBELPMB(Block &MBB, BlockIt MBBI, bool IsELPM);
+  // Common implementation of ROLBRdR1 and ROLBRdR17.
+  bool expandROLBRd(Block &MBB, BlockIt MBBI);
 };
 
 char AVRExpandPseudo::ID = 0;
 
 bool AVRExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
   bool Modified = false;
 
   BlockIt MBBI = MBB.begin(), E = MBB.end();
bool AVRExpandPseudo::expand<AVR::POPWRd>(Block &MBB, BlockIt MBBI) {
 
   buildMI(MBB, MBBI, OpHi, DstHiReg).setMIFlags(Flags); // High
   buildMI(MBB, MBBI, OpLo, DstLoReg).setMIFlags(Flags); // Low
 
   MI.eraseFromParent();
   return true;
 }
 
-template <>
-bool AVRExpandPseudo::expand<AVR::ROLBRd>(Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expandROLBRd(Block &MBB, BlockIt MBBI) {
   // In AVR, the rotate instructions behave quite unintuitively. They rotate
   // bits through the carry bit in SREG, effectively rotating over 9 bits,
   // instead of 8. This is useful when we are dealing with numbers over
   // multiple registers, but when we actually need to rotate stuff, we have
   // to explicitly add the carry bit.
 
-  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
-
   MachineInstr &MI = *MBBI;
   unsigned OpShift, OpCarry;
   Register DstReg = MI.getOperand(0).getReg();
-  Register ZeroReg = STI.getZeroRegister();
+  Register ZeroReg = MI.getOperand(3).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
   OpShift = AVR::ADDRdRr;
   OpCarry = AVR::ADCRdRr;
 
   // add r16, r16
   // adc r16, r1
 
   // Shift part
   buildMI(MBB, MBBI, OpShift)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstReg, RegState::Kill)
       .addReg(DstReg, RegState::Kill);
 
   // Add the carry bit
   auto MIB = buildMI(MBB, MBBI, OpCarry)
                  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
                  .addReg(DstReg, getKillRegState(DstIsKill))
                  .addReg(ZeroReg);
 
   MIB->getOperand(3).setIsDead(); // SREG is always dead
   MIB->getOperand(4).setIsKill(); // SREG is always implicitly killed
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
+bool AVRExpandPseudo::expand<AVR::ROLBRdR1>(Block &MBB, BlockIt MBBI) {
+  return expandROLBRd(MBB, MBBI);
+}
+
+template <>
+bool AVRExpandPseudo::expand<AVR::ROLBRdR17>(Block &MBB, BlockIt MBBI) {
+  return expandROLBRd(MBB, MBBI);
+}
+
+template <>
 bool AVRExpandPseudo::expand<AVR::RORBRd>(Block &MBB, BlockIt MBBI) {
   // In AVR, the rotate instructions behave quite unintuitively. They rotate
   // bits through the carry bit in SREG, effectively rotating over 9 bits,
   // instead of 8. This is useful when we are dealing with numbers over
   // multiple registers, but when we actually need to rotate stuff, we have
   // to explicitly add the carry bit.
 
   MachineInstr &MI = *MBBI;
case AVR::LDDWRdYQ: //: FIXME: remove this once PR13375 gets fixed
     EXPAND(AVR::STWPtrPdRr);
     EXPAND(AVR::STDWPtrQRr);
     EXPAND(AVR::STDSPQRr);
     EXPAND(AVR::STDWSPQRr);
     EXPAND(AVR::INWRdA);
     EXPAND(AVR::OUTWARr);
     EXPAND(AVR::PUSHWRr);
     EXPAND(AVR::POPWRd);
-    EXPAND(AVR::ROLBRd);
+    EXPAND(AVR::ROLBRdR1);
+    EXPAND(AVR::ROLBRdR17);
     EXPAND(AVR::RORBRd);
     EXPAND(AVR::LSLWRd);
     EXPAND(AVR::LSRWRd);
     EXPAND(AVR::RORWRd);
     EXPAND(AVR::ROLWRd);
     EXPAND(AVR::ASRWRd);
     EXPAND(AVR::LSLWHiRd);
     EXPAND(AVR::LSRWLoRd);

llvm/lib/Target/AVR/AVRISelLowering.h

SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
                           const SmallVectorImpl<ISD::InputArg> &Ins,
                           const SDLoc &dl, SelectionDAG &DAG,
                           SmallVectorImpl<SDValue> &InVals) const;
 
 protected:
   const AVRSubtarget &Subtarget;
 
 private:
-  MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
+  MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB,
+                                 bool Tiny) const;
   MachineBasicBlock *insertWideShift(MachineInstr &MI,
                                      MachineBasicBlock *BB) const;
   MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
   MachineBasicBlock *insertCopyZero(MachineInstr &MI,
                                     MachineBasicBlock *BB) const;
   MachineBasicBlock *insertAtomicArithmeticOp(MachineInstr &MI,
                                               MachineBasicBlock *BB,
                                               unsigned Opcode, int Width) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_AVR_ISEL_LOWERING_H

llvm/lib/Target/AVR/AVRISelLowering.cpp

AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
   return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
 }
 
 //===----------------------------------------------------------------------===//
 //  Custom Inserters
 //===----------------------------------------------------------------------===//
 
 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
-                                                  MachineBasicBlock *BB) const {
+                                                  MachineBasicBlock *BB,
+                                                  bool Tiny) const {
   unsigned Opc;
   const TargetRegisterClass *RC;
   bool HasRepeatedOperand = false;
   MachineFunction *F = BB->getParent();
   MachineRegisterInfo &RI = F->getRegInfo();
   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
   DebugLoc dl = MI.getDebugLoc();
 
case AVR::Lsr8:
     Opc = AVR::LSRRd;
     RC = &AVR::GPR8RegClass;
     break;
   case AVR::Lsr16:
     Opc = AVR::LSRWRd;
     RC = &AVR::DREGSRegClass;
     break;
   case AVR::Rol8:
-    Opc = AVR::ROLBRd;
+    Opc = Tiny ? AVR::ROLBRdR17 : AVR::ROLBRdR1;
     RC = &AVR::GPR8RegClass;
     break;
   case AVR::Rol16:
     Opc = AVR::ROLWRd;
     RC = &AVR::DREGSRegClass;
     break;
   case AVR::Ror8:
     Opc = AVR::RORBRd;
MachineBasicBlock *AVRTargetLowering::insertAtomicArithmeticOp(
   MI.eraseFromParent();
   return BB;
 }
 
 MachineBasicBlock *
 AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                                                MachineBasicBlock *MBB) const {
   int Opc = MI.getOpcode();
+  const AVRSubtarget &STI = MBB->getParent()->getSubtarget<AVRSubtarget>();
 
   // Pseudo shift instructions with a non constant shift amount are expanded
   // into a loop.
   switch (Opc) {
   case AVR::Lsl8:
   case AVR::Lsl16:
   case AVR::Lsr8:
   case AVR::Lsr16:
   case AVR::Rol8:
   case AVR::Rol16:
   case AVR::Ror8:
   case AVR::Ror16:
   case AVR::Asr8:
   case AVR::Asr16:
-    return insertShift(MI, MBB);
+    return insertShift(MI, MBB, STI.hasTinyEncoding());
   case AVR::Lsl32:
   case AVR::Lsr32:
   case AVR::Asr32:
     return insertWideShift(MI, MBB);
   case AVR::MULRdRr:
   case AVR::MULSRdRr:
     return insertMul(MI, MBB);
   case AVR::CopyZero:

llvm/lib/Target/AVR/AVRInstrInfo.td

def ASRWRd : Pseudo<(outs DREGS
                       "asrw\t$rd",
                       [(set i16
                         : $rd, (AVRasr i16
                                 : $src)),
                        (implicit SREG)]>;
 
   def ASRWLoRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "asrwlo\t$rd",
                         [(set i16:$rd, (AVRasrlo i16:$src)), (implicit SREG)]>;
+  let Uses = [R1] in
+  def ROLBRdR1 : Pseudo<(outs GPR8:$rd),
+                        (ins GPR8:$src),
+                        "rolb\t$rd",
+                        [(set i8:$rd, (AVRrol i8:$src)),
+                        (implicit SREG)]>,
+                 Requires<[HasNonTinyEncoding]>;
 
-  def ROLBRd : Pseudo<(outs GPR8
-                       : $rd),
-                      (ins GPR8
-                       : $src),
+  let Uses = [R17] in
+  def ROLBRdR17 : Pseudo<(outs GPR8:$rd),
+                         (ins GPR8:$src),
                          "rolb\t$rd",
-                      [(set i8
-                        : $rd, (AVRrol i8
-                                : $src)),
-                       (implicit SREG)]>;
+                         [(set i8:$rd, (AVRrol i8:$src)),
+                         (implicit SREG)]>,
+                  Requires<[HasTinyEncoding]>;
 
   def RORBRd : Pseudo<(outs GPR8
                        : $rd),
                       (ins GPR8
                        : $src),
                       "rorb\t$rd",
                       [(set i8
                         : $rd, (AVRror i8

llvm/test/CodeGen/AVR/pseudo/ROLBRdR1.mir

 
 ---
 name:            test_rolbrd
 body: |
   bb.0.entry:
     liveins: $r14
 
     ; CHECK-LABEL: test_rolbrd
-
-    ; CHECK:      $r14 = ADDRdRr killed $r14, killed $r14, implicit-def $sreg
-    ; CHECK-NEXT: $r14 = ADCRdRr $r14, $r1, implicit-def dead $sreg, implicit killed $sreg
-    $r14 = ROLBRd $r14, implicit-def $sreg
+    ; CHECK:         $r14 = ADDRdRr killed $r14, killed $r14, implicit-def $sreg
+    ; CHECK-NEXT:    $r14 = ADCRdRr $r14, $r1, implicit-def dead $sreg, implicit killed $sreg
+
+    $r14 = ROLBRdR1  $r14, implicit-def $sreg, implicit $r1
 ...

llvm/test/CodeGen/AVR/pseudo/ROLBRdR17.mir

+# RUN: llc -O0 -run-pass=avr-expand-pseudo -mattr=+avrtiny %s -o - | FileCheck %s
+
+# This test checks the expansion of the 8-bit ROLB (rotate) pseudo instruction
+# on AVRTiny.
+
+--- |
+  target triple = "avr--"
+  define void @test_rolbrd() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_rolbrd
+body: |
+  bb.0.entry:
+    liveins: $r24
+
+    ; CHECK-LABEL: test_rolbrd
+    ; CHECK:         $r24 = ADDRdRr killed $r24, killed $r24, implicit-def $sreg
+    ; CHECK-NEXT:    $r24 = ADCRdRr $r24, $r17, implicit-def dead $sreg, implicit killed $sreg
+    $r24 = ROLBRdR17 $r24, implicit-def $sreg, implicit $r17
+...

llvm/test/CodeGen/AVR/rot.ll

-; RUN: llc < %s -march=avr | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mattr=+avrtiny | FileCheck --check-prefix=TINY %s
 
-; Bit rotation tests.
-
-; CHECK-LABEL: rol8:
 define i8 @rol8(i8 %val, i8 %amt) {
-  ; CHECK:      andi r22, 7
-
-  ; CHECK-NEXT: dec r22
-  ; CHECK-NEXT: brmi .LBB0_2
-
-; CHECK-NEXT: .LBB0_1:
-  ; CHECK-NEXT: lsl r24
-  ; CHECK-NEXT: adc r24, r1
-  ; CHECK-NEXT: dec r22
-  ; CHECK-NEXT: brpl .LBB0_1
-
-; CHECK-NEXT: .LBB0_2:
-  ; CHECK-NEXT: ret
+; CHECK-LABEL: rol8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    andi r22, 7
+; CHECK-NEXT:    dec r22
+; CHECK-NEXT:    brmi .LBB0_2
+; CHECK-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    lsl r24
+; CHECK-NEXT:    adc r24, r1
+; CHECK-NEXT:    dec r22
+; CHECK-NEXT:    brpl .LBB0_1
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    ret
+;
+; TINY-LABEL: rol8:
+; TINY:       ; %bb.0:
+; TINY-NEXT:    andi r22, 7
+; TINY-NEXT:    dec r22
+; TINY-NEXT:    brmi .LBB0_2
+; TINY-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; TINY-NEXT:    lsl r24
+; TINY-NEXT:    adc r24, r17
+; TINY-NEXT:    dec r22
+; TINY-NEXT:    brpl .LBB0_1
+; TINY-NEXT:  .LBB0_2:
+; TINY-NEXT:    ret
   %mod = urem i8 %amt, 8
-
   %inv = sub i8 8, %mod
   %parta = shl i8 %val, %mod
   %partb = lshr i8 %val, %inv
-
   %rotl = or i8 %parta, %partb
-
   ret i8 %rotl
 }
 
 
-; CHECK-LABEL: ror8:
 define i8 @ror8(i8 %val, i8 %amt) {
-  ; CHECK:      andi r22, 7
-
-  ; CHECK-NEXT: dec r22
-  ; CHECK-NEXT: brmi .LBB1_2
-
-; CHECK-NEXT: .LBB1_1:
-  ; CHECK-NEXT: bst r24, 0
-  ; CHECK-NEXT: ror r24
-  ; CHECK-NEXT: bld r24, 7
-  ; CHECK-NEXT: dec r22
-  ; CHECK-NEXT: brpl .LBB1_1
-
-; CHECK-NEXT: .LBB1_2:
-  ; CHECK-NEXT: ret
+; CHECK-LABEL: ror8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    andi r22, 7
+; CHECK-NEXT:    dec r22
+; CHECK-NEXT:    brmi .LBB1_2
+; CHECK-NEXT:  .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    bst r24, 0
+; CHECK-NEXT:    ror r24
+; CHECK-NEXT:    bld r24, 7
+; CHECK-NEXT:    dec r22
+; CHECK-NEXT:    brpl .LBB1_1
+; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    ret
+;
+; TINY-LABEL: ror8:
+; TINY:       ; %bb.0:
+; TINY-NEXT:    andi r22, 7
+; TINY-NEXT:    dec r22
+; TINY-NEXT:    brmi .LBB1_2
+; TINY-NEXT:  .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; TINY-NEXT:    bst r24, 0
+; TINY-NEXT:    ror r24
+; TINY-NEXT:    bld r24, 7
+; TINY-NEXT:    dec r22
+; TINY-NEXT:    brpl .LBB1_1
+; TINY-NEXT:  .LBB1_2:
+; TINY-NEXT:    ret
   %mod = urem i8 %amt, 8
-
   %inv = sub i8 8, %mod
   %parta = lshr i8 %val, %mod
   %partb = shl i8 %val, %inv
-
   %rotr = or i8 %parta, %partb
-
   ret i8 %rotr
 }