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[clang-format] Parse the Verilog language option in configuration
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Authored by sstwcw on May 28 2023, 8:38 AM.

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rymiel
HazardyKnusperkeks
owenpan
MyDeveloperDay

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rG24231df9b8ef: [clang-format] Parse the Verilog language option in configuration

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Repository: rG LLVM Github Monorepo

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sstwcw created this revision.May 28 2023, 8:38 AM

Herald added projects: Restricted Project, Restricted Project, Restricted Project. · View Herald TranscriptMay 28 2023, 8:38 AM

Herald added reviewers: rymiel, HazardyKnusperkeks, owenpan, MyDeveloperDay. · View Herald Transcript

Herald added a subscriber: cfe-commits. · View Herald Transcript

sstwcw requested review of this revision.May 28 2023, 8:38 AM

MyDeveloperDay accepted this revision.May 28 2023, 9:23 AM

This revision is now accepted and ready to land.May 28 2023, 9:23 AM

Harbormaster completed remote builds in B235075: Diff 526337.May 28 2023, 10:27 AM

HazardyKnusperkeks accepted this revision.May 29 2023, 10:11 AM

Closed by commit rG24231df9b8ef: [clang-format] Parse the Verilog language option in configuration (authored by sstwcw). · Explain WhyJun 2 2023, 8:00 AM

This revision was automatically updated to reflect the committed changes.

sstwcw added a commit: rG24231df9b8ef: [clang-format] Parse the Verilog language option in configuration.

Revision Contents
Changeset List

Path

Size

clang/

lib/

Format/

Format.cpp

1 line

unittests/

Format/

ConfigParseTest.cpp

17 lines

Diff 527862

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clang/lib/Format/Format.cpp