[CodeGen] Make use of MachineInstr::all_defs and all_uses. NFCI.

[qcolombet]

I like the improved readability.
Thanks!

[nikic]

It looks like this causes a major compile-time regression: https://llvm-compile-time-tracker.com/compare.php?from=2de54b919ba5fd9ccf37038cddfc36e97eb480af&to=5022fc2ad31b5e3211e2458347c89412b8c5ec1b&stat=instructions:u

The implementation of these methods looks somewhat suspect: https://github.com/llvm/llvm-project/blob/7f374b6902fad9caed41284a57d573abe9ada9d1/llvm/include/llvm/CodeGen/MachineInstr.h#L732 Not sure why this is creating an std::function.

[foad]

In D151424#4388971, @nikic wrote:

It looks like this causes a major compile-time regression: https://llvm-compile-time-tracker.com/compare.php?from=2de54b919ba5fd9ccf37038cddfc36e97eb480af&to=5022fc2ad31b5e3211e2458347c89412b8c5ec1b&stat=instructions:u

The implementation of these methods looks somewhat suspect: https://github.com/llvm/llvm-project/blob/7f374b6902fad9caed41284a57d573abe9ada9d1/llvm/include/llvm/CodeGen/MachineInstr.h#L732 Not sure why this is creating an std::function.

Thanks/sorry. I won't be able to look at this for a few days. Feel free to revert if you want.

[foad]

It looks like this causes a major compile-time regression: https://llvm-compile-time-tracker.com/compare.php?from=2de54b919ba5fd9ccf37038cddfc36e97eb480af&to=5022fc2ad31b5e3211e2458347c89412b8c5ec1b&stat=instructions:u

Could you please add https://github.com/jayfoad/llvm-project to the compile time tracker?

The implementation of these methods looks somewhat suspect: https://github.com/llvm/llvm-project/blob/7f374b6902fad9caed41284a57d573abe9ada9d1/llvm/include/llvm/CodeGen/MachineInstr.h#L732 Not sure why this is creating an std::function.

That was part of my attempt at getting sane(ish) declared return types for the new functions. The first versions of this patch used auto and did not use std::function. What's so bad about std::function anyway?

[nikic]

In D151424#4390174, @foad wrote:

It looks like this causes a major compile-time regression: https://llvm-compile-time-tracker.com/compare.php?from=2de54b919ba5fd9ccf37038cddfc36e97eb480af&to=5022fc2ad31b5e3211e2458347c89412b8c5ec1b&stat=instructions:u

Could you please add https://github.com/jayfoad/llvm-project to the compile time tracker?

Done!

The implementation of these methods looks somewhat suspect: https://github.com/llvm/llvm-project/blob/7f374b6902fad9caed41284a57d573abe9ada9d1/llvm/include/llvm/CodeGen/MachineInstr.h#L732 Not sure why this is creating an std::function.

That was part of my attempt at getting sane(ish) declared return types for the new functions. The first versions of this patch used auto and did not use std::function. What's so bad about std::function anyway?

I've landed https://github.com/llvm/llvm-project/commit/1efbef4085fbe7098af4bb7013c6295ed3682cdf to remove the std::function use, which does seem to fully mitigate the regression. Not sure what exactly about std::function is so slow/unoptimizable, but it's a "well known" performance footgun (like so many things in the STL ... sigh)

[foad]

In D151424#4390193, @nikic wrote:

In D151424#4390174, @foad wrote:

It looks like this causes a major compile-time regression: https://llvm-compile-time-tracker.com/compare.php?from=2de54b919ba5fd9ccf37038cddfc36e97eb480af&to=5022fc2ad31b5e3211e2458347c89412b8c5ec1b&stat=instructions:u

Could you please add https://github.com/jayfoad/llvm-project to the compile time tracker?

Done!

The implementation of these methods looks somewhat suspect: https://github.com/llvm/llvm-project/blob/7f374b6902fad9caed41284a57d573abe9ada9d1/llvm/include/llvm/CodeGen/MachineInstr.h#L732 Not sure why this is creating an std::function.

That was part of my attempt at getting sane(ish) declared return types for the new functions. The first versions of this patch used auto and did not use std::function. What's so bad about std::function anyway?

I've landed https://github.com/llvm/llvm-project/commit/1efbef4085fbe7098af4bb7013c6295ed3682cdf to remove the std::function use, which does seem to fully mitigate the regression. Not sure what exactly about std::function is so slow/unoptimizable, but it's a "well known" performance footgun (like so many things in the STL ... sigh)

Thanks and thanks!

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

void AggressiveAntiDepBreaker::PrescanInstruction(
   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
     RegRefs = State->GetRegRefs();
 
   // Handle dead defs by simulating a last-use of the register just
   // after the def. A dead def can occur because the def is truly
   // dead, or because only a subregister is live at the def. If we
   // don't do this the dead def will be incorrectly merged into the
   // previous def.
-  for (const MachineOperand &MO : MI.operands()) {
-    if (!MO.isReg() || !MO.isDef()) continue;
+  for (const MachineOperand &MO : MI.all_defs()) {
     Register Reg = MO.getReg();
     if (Reg == 0) continue;
 
     HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
   }
 
   LLVM_DEBUG(dbgs() << "\tDef Groups:");
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {

llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

static void interpretValues(const MachineInstr *CurMI,
   // If the MI is an instruction defining one or more parameters' forwarding
   // registers, add those defines.
   ClobberedRegSet NewClobberedRegUnits;
   auto getForwardingRegsDefinedByMI = [&](const MachineInstr &MI,
                                           SmallSetVector<unsigned, 4> &Defs) {
     if (MI.isDebugInstr())
       return;
 
-    for (const MachineOperand &MO : MI.operands()) {
-      if (MO.isReg() && MO.isDef() && MO.getReg().isPhysical()) {
+    for (const MachineOperand &MO : MI.all_defs()) {
+      if (MO.getReg().isPhysical()) {
         for (auto &FwdReg : ForwardedRegWorklist)
           if (TRI.regsOverlap(FwdReg.first, MO.getReg()))
             Defs.insert(FwdReg.first);
         for (MCRegUnitIterator Units(MO.getReg(), &TRI); Units.isValid(); ++Units)
           NewClobberedRegUnits.insert(*Units);
       }
     }
   };

llvm/lib/CodeGen/BranchFolding.cpp

while (TIB != TIE && FIB != FIE) {
     if (!IsSafe)
       break;
 
     bool DontMoveAcrossStore = true;
     if (!TIB->isSafeToMove(nullptr, DontMoveAcrossStore))
       break;
 
     // Remove kills from ActiveDefsSet, these registers had short live ranges.
-    for (const MachineOperand &MO : TIB->operands()) {
-      if (!MO.isReg() || !MO.isUse() || !MO.isKill())
+    for (const MachineOperand &MO : TIB->all_uses()) {
+      if (!MO.isKill())
         continue;
       Register Reg = MO.getReg();
       if (!Reg)
         continue;
       if (!AllDefsSet.count(Reg)) {
         continue;
       }
       if (Reg.isPhysical()) {
         for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
           ActiveDefsSet.erase(*AI);
       } else {
         ActiveDefsSet.erase(Reg);
       }
     }
 
     // Track local defs so we can update liveins.
-    for (const MachineOperand &MO : TIB->operands()) {
-      if (!MO.isReg() || !MO.isDef() || MO.isDead())
+    for (const MachineOperand &MO : TIB->all_defs()) {
+      if (MO.isDead())
         continue;
       Register Reg = MO.getReg();
       if (!Reg || Reg.isVirtual())
         continue;
       addRegAndItsAliases(Reg, TRI, ActiveDefsSet);
       addRegAndItsAliases(Reg, TRI, AllDefsSet);
     }
 

llvm/lib/CodeGen/BreakFalseDeps.cpp

bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
 
   // Get the undef operand's register class
   const TargetRegisterClass *OpRC =
     TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF);
   assert(OpRC && "Not a valid register class");
 
   // If the instruction has a true dependency, we can hide the false depdency
   // behind it.
-  for (MachineOperand &CurrMO : MI->operands()) {
-    if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() ||
-      !OpRC->contains(CurrMO.getReg()))
+  for (MachineOperand &CurrMO : MI->all_uses()) {
+    if (CurrMO.isUndef() || !OpRC->contains(CurrMO.getReg()))
       continue;
     // We found a true dependency - replace the undef register with the true
     // dependency.
     MO.setReg(CurrMO.getReg());
     return true;
   }
 
   // Go over all registers in the register class and find the register with

llvm/lib/CodeGen/DeadMachineInstructionElim.cpp

if (MI->getOpcode() == TargetOpcode::LOCAL_ESCAPE)
     return false;
 
   // Don't delete instructions with side effects.
   bool SawStore = false;
   if (!MI->isSafeToMove(nullptr, SawStore) && !MI->isPHI())
     return false;
 
   // Examine each operand.
-  for (const MachineOperand &MO : MI->operands()) {
-    if (MO.isReg() && MO.isDef()) {
-      Register Reg = MO.getReg();
-      if (Reg.isPhysical()) {
-        // Don't delete live physreg defs, or any reserved register defs.
-        if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
-          return false;
-      } else {
-        if (MO.isDead()) {
+  for (const MachineOperand &MO : MI->all_defs()) {
 #ifndef NDEBUG
-          // Basic check on the register. All of them should be 'undef'.
-          for (auto &U : MRI->use_nodbg_operands(Reg))
-            assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");
 #endif
-          continue;
-        }
-        for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
-          if (&Use != MI)
-            // This def has a non-debug use. Don't delete the instruction!
-            return false;
-        }
-      }
-    }
-  }
 
   // If there are no defs with uses, the instruction is dead.
   return true;
 }
 
 bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
   if (skipFunction(MF.getFunction()))
     return false;

llvm/lib/CodeGen/GlobalISel/Utils.cpp

bool llvm::isTriviallyDead(const MachineInstr &MI,
 
   // If we can move an instruction, we can remove it.  Otherwise, it has
   // a side-effect of some sort.
   bool SawStore = false;
   if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI())
     return false;
 
   // Instructions without side-effects are dead iff they only define dead vregs.
-  for (const auto &MO : MI.operands()) {
-    if (!MO.isReg() || !MO.isDef())
-      continue;
-
+  for (const auto &MO : MI.all_defs()) {
     Register Reg = MO.getReg();
     if (Reg.isPhysical() || !MRI.use_nodbg_empty(Reg))
       return false;
   }
   return true;
 }
 
 static void reportGISelDiagnostic(DiagnosticSeverity Severity,

llvm/lib/CodeGen/ImplicitNullChecks.cpp

for (const auto &NC : NullCheckList) {
     // since we haven't changed control flow, we've just made it implicit.
     MachineInstr *FaultingInstr = insertFaultingInstr(
         NC.getMemOperation(), NC.getCheckBlock(), NC.getNullSucc());
     // Now the values defined by MemOperation, if any, are live-in of
     // the block of MemOperation.
     // The original operation may define implicit-defs alongside
     // the value.
     MachineBasicBlock *MBB = NC.getMemOperation()->getParent();
-    for (const MachineOperand &MO : FaultingInstr->operands()) {
-      if (!MO.isReg() || !MO.isDef())
-        continue;
+    for (const MachineOperand &MO : FaultingInstr->all_defs()) {
       Register Reg = MO.getReg();
       if (!Reg || MBB->isLiveIn(Reg))
         continue;
       MBB->addLiveIn(Reg);
     }
 
     if (auto *DepMI = NC.getOnlyDependency()) {
-      for (auto &MO : DepMI->operands()) {
-        if (!MO.isReg() || !MO.getReg() || !MO.isDef() || MO.isDead())
+      for (auto &MO : DepMI->all_defs()) {
+        if (!MO.getReg() || MO.isDead())
           continue;
         if (!NC.getNotNullSucc()->isLiveIn(MO.getReg()))
           NC.getNotNullSucc()->addLiveIn(MO.getReg());
       }
     }
 
     NC.getMemOperation()->eraseFromParent();
     if (auto *CheckOp = NC.getCheckOperation())

llvm/lib/CodeGen/InlineSpiller.cpp

static Register isFullCopyOf(const MachineInstr &MI, Register Reg) {
   if (MI.getOperand(0).getReg() == Reg)
     return MI.getOperand(1).getReg();
   if (MI.getOperand(1).getReg() == Reg)
     return MI.getOperand(0).getReg();
   return Register();
 }
 
 static void getVDefInterval(const MachineInstr &MI, LiveIntervals &LIS) {
-  for (const MachineOperand &MO : MI.operands())
-    if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
+  for (const MachineOperand &MO : MI.all_defs())
+    if (MO.getReg().isVirtual())
       LIS.getInterval(MO.getReg());
 }
 
 /// isSnippet - Identify if a live interval is a snippet that should be spilled.
 /// It is assumed that SnipLI is a virtual register with the same original as
 /// Edit->getReg().
 bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
   Register Reg = Edit->getReg();
bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
   if (!RI.Reads)
     return false;
 
   SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
   VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
 
   if (!ParentVNI) {
     LLVM_DEBUG(dbgs() << "\tadding <undef> flags: ");
-    for (MachineOperand &MO : MI.operands())
-      if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg())
+    for (MachineOperand &MO : MI.all_uses())
+      if (MO.getReg() == VirtReg.reg())
         MO.setIsUndef();
     LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI);
     return true;
   }
 
   if (SnippetCopies.count(&MI))
     return false;
 

llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp

if (Expr->getNumElements() > 0 && !Expr->isDeref())
     return false;
 
   return true;
 }
 
 /// Collect all register defines (including aliases) for the given instruction.
 static void collectRegDefs(const MachineInstr &MI, DefinedRegsSet &Regs,
                            const TargetRegisterInfo *TRI) {
-  for (const MachineOperand &MO : MI.operands()) {
-    if (MO.isReg() && MO.isDef() && MO.getReg() && MO.getReg().isPhysical()) {
+  for (const MachineOperand &MO : MI.all_defs()) {
+    if (MO.getReg() && MO.getReg().isPhysical()) {
       Regs.insert(MO.getReg());
       for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
         Regs.insert(*AI);
     }
   }
 }
 
 /// This routine records the entry values of function parameters. The values

llvm/lib/CodeGen/LiveVariables.cpp

if (Dist > LastDefDist) {
       LastDefDist = Dist;
     }
   }
 
   if (!LastDef)
     return nullptr;
 
   PartDefRegs.insert(LastDefReg);
-  for (MachineOperand &MO : LastDef->operands()) {
-    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
+  for (MachineOperand &MO : LastDef->all_defs()) {
+    if (MO.getReg() == 0)
       continue;
     Register DefReg = MO.getReg();
     if (TRI->isSubRegister(Reg, DefReg)) {
       for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg))
         PartDefRegs.insert(SubReg);
     }
   }
   return LastDef;

llvm/lib/CodeGen/MachineBasicBlock.cpp

MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
   // terminators.
   LiveVariables *LV = P.getAnalysisIfAvailable<LiveVariables>();
 
   // Collect a list of virtual registers killed by the terminators.
   SmallVector<Register, 4> KilledRegs;
   if (LV)
     for (MachineInstr &MI :
          llvm::make_range(getFirstInstrTerminator(), instr_end())) {
-      for (MachineOperand &MO : MI.operands()) {
-        if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse() || !MO.isKill() ||
-            MO.isUndef())
+      for (MachineOperand &MO : MI.all_uses()) {
+        if (MO.getReg() == 0 || !MO.isKill() || MO.isUndef())
           continue;
         Register Reg = MO.getReg();
         if (Reg.isPhysical() || LV->getVarInfo(Reg).removeKill(MI)) {
           KilledRegs.push_back(Reg);
           LLVM_DEBUG(dbgs() << "Removing terminator kill: " << MI);
           MO.setIsKill(false);
         }
       }

llvm/lib/CodeGen/MachineCSE.cpp

 
 /// The source register of a COPY machine instruction can be propagated to all
 /// its users, and this propagation could increase the probability of finding
 /// common subexpressions. If the COPY has only one user, the COPY itself can
 /// be removed.
 bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
                                                MachineBasicBlock *MBB) {
   bool Changed = false;
-  for (MachineOperand &MO : MI->operands()) {
-    if (!MO.isReg() || !MO.isUse())
-      continue;
+  for (MachineOperand &MO : MI->all_uses()) {
     Register Reg = MO.getReg();
     if (!Reg.isVirtual())
       continue;
     bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
     MachineInstr *DefMI = MRI->getVRegDef(Reg);
     if (!DefMI->isCopy())
       continue;
     Register SrcReg = DefMI->getOperand(1).getReg();

 /// returns the physical register def by reference if it's the only one and the
 /// instruction does not uses a physical register.
 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
                                        const MachineBasicBlock *MBB,
                                        SmallSet<MCRegister, 8> &PhysRefs,
                                        PhysDefVector &PhysDefs,
                                        bool &PhysUseDef) const {
   // First, add all uses to PhysRefs.
-  for (const MachineOperand &MO : MI->operands()) {
-    if (!MO.isReg() || MO.isDef())
-      continue;
+  for (const MachineOperand &MO : MI->all_uses()) {
     Register Reg = MO.getReg();
     if (!Reg)
       continue;
     if (Reg.isVirtual())
       continue;
     // Reading either caller preserved or constant physregs is ok.
     if (!isCallerPreservedOrConstPhysReg(Reg.asMCReg(), MO, *MI->getMF(), *TRI,
                                          *TII))
if (TII->isAsCheapAsAMove(*MI)) {
     MachineBasicBlock *BB = MI->getParent();
     if (CSBB != BB && !CSBB->isSuccessor(BB))
       return false;
   }
 
   // Heuristics #2: If the expression doesn't not use a vr and the only use
   // of the redundant computation are copies, do not cse.
   bool HasVRegUse = false;
-  for (const MachineOperand &MO : MI->operands()) {
-    if (MO.isReg() && MO.isUse() && MO.getReg().isVirtual()) {
+  for (const MachineOperand &MO : MI->all_uses()) {
+    if (MO.getReg().isVirtual()) {
       HasVRegUse = true;
       break;
     }
   }
   if (!HasVRegUse) {
     bool HasNonCopyUse = false;
     for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
       // Ignore copies.

llvm/lib/CodeGen/MachineCombiner.cpp

MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
                           MachineTraceMetrics::Trace BlockTrace,
                           const MachineBasicBlock &MBB) {
   SmallVector<unsigned, 16> InstrDepth;
   // For each instruction in the new sequence compute the depth based on the
   // operands. Use the trace information when possible. For new operands which
   // are tracked in the InstrIdxForVirtReg map depth is looked up in InstrDepth
   for (auto *InstrPtr : InsInstrs) { // for each Use
     unsigned IDepth = 0;
-    for (const MachineOperand &MO : InstrPtr->operands()) {
+    for (const MachineOperand &MO : InstrPtr->all_uses()) {
       // Check for virtual register operand.
-      if (!(MO.isReg() && MO.getReg().isVirtual()))
-        continue;
-      if (!MO.isUse())
+      if (!MO.getReg().isVirtual())
         continue;
       unsigned DepthOp = 0;
       unsigned LatencyOp = 0;
       DenseMap<unsigned, unsigned>::iterator II =
           InstrIdxForVirtReg.find(MO.getReg());
       if (II != InstrIdxForVirtReg.end()) {
         // Operand is new virtual register not in trace
         assert(II->second < InstrDepth.size() && "Bad Index");

 /// \param BlockTrace is a trace of machine instructions
 ///
 /// \returns Latency of \p NewRoot
 unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot,
                                      MachineTraceMetrics::Trace BlockTrace) {
   // Check each definition in NewRoot and compute the latency
   unsigned NewRootLatency = 0;
 
-  for (const MachineOperand &MO : NewRoot->operands()) {
+  for (const MachineOperand &MO : NewRoot->all_defs()) {
     // Check for virtual register operand.
-    if (!(MO.isReg() && MO.getReg().isVirtual()))
-      continue;
-    if (!MO.isDef())
+    if (!MO.getReg().isVirtual())
       continue;
     // Get the first instruction that uses MO
     MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(MO.getReg());
     RI++;
     if (RI == MRI->reg_end())
       continue;
     MachineInstr *UseMO = RI->getParent();
     unsigned LatencyOp = 0;

llvm/lib/CodeGen/MachineDebugify.cpp

for (auto I = MBB.begin(), E = MBB.end(); I != E;) {
       if (!Line2Var.count(Line))
         Line = EarliestDVI->getDebugLoc().getLine();
       DILocalVariable *LocalVar = Line2Var[Line];
       assert(LocalVar && "No variable for current line?");
       VarSet.insert(LocalVar);
 
       // Emit DBG_VALUEs for register definitions.
       SmallVector<MachineOperand *, 4> RegDefs;
-      for (MachineOperand &MO : MI.operands())
-        if (MO.isReg() && MO.isDef() && MO.getReg())
+      for (MachineOperand &MO : MI.all_defs())
+        if (MO.getReg())
           RegDefs.push_back(&MO);
       for (MachineOperand *MO : RegDefs)
         BuildMI(MBB, InsertBeforeIt, MI.getDebugLoc(), DbgValDesc,
                 /*IsIndirect=*/false, *MO, LocalVar, Expr);
 
       // OK, failing that, emit a constant DBG_VALUE.
       if (RegDefs.empty()) {
         auto ImmOp = MachineOperand::CreateImm(NextImm++);

llvm/lib/CodeGen/MachineFunction.cpp

auto ApplySubregisters =
     return P;
   };
 
   // If we managed to find the defining instruction after COPYs, return an
   // instruction / operand pair after adding subregister qualifiers.
   if (State.first.isVirtual()) {
     // Virtual register def -- we can just look up where this happens.
     MachineInstr *Inst = MRI.def_begin(State.first)->getParent();
-    for (auto &MO : Inst->operands()) {
-      if (!MO.isReg() || !MO.isDef() || MO.getReg() != State.first)
+    for (auto &MO : Inst->all_defs()) {
+      if (MO.getReg() != State.first)
         continue;
       return ApplySubregisters({Inst->getDebugInstrNum(), MO.getOperandNo()});
     }
 
     llvm_unreachable("Vreg def with no corresponding operand?");
   }
 
   // Our search ended in a copy from a physreg: walk back up the function
   // looking for whatever defines the physreg.
   assert(CurInst->isCopyLike() || TII.isCopyInstr(*CurInst));
   State = GetRegAndSubreg(*CurInst);
   Register RegToSeek = State.first;
 
   auto RMII = CurInst->getReverseIterator();
   auto PrevInstrs = make_range(RMII, CurInst->getParent()->instr_rend());
   for (auto &ToExamine : PrevInstrs) {
-    for (auto &MO : ToExamine.operands()) {
+    for (auto &MO : ToExamine.all_defs()) {
       // Test for operand that defines something aliasing RegToSeek.
-      if (!MO.isReg() || !MO.isDef() ||
-          !TRI.regsOverlap(RegToSeek, MO.getReg()))
+      if (!TRI.regsOverlap(RegToSeek, MO.getReg()))
         continue;
 
       return ApplySubregisters(
           {ToExamine.getDebugInstrNum(), MO.getOperandNo()});
     }
   }
 
   MachineBasicBlock &InsertBB = *CurInst->getParent();

llvm/lib/CodeGen/MachineLICM.cpp

for (CandidateInfo &Candidate : Candidates) {
     if (Candidate.FI != std::numeric_limits<int>::min() &&
         StoredFIs.count(Candidate.FI))
       continue;
 
     unsigned Def = Candidate.Def;
     if (!PhysRegClobbers.test(Def) && !TermRegs.test(Def)) {
       bool Safe = true;
       MachineInstr *MI = Candidate.MI;
-      for (const MachineOperand &MO : MI->operands()) {
-        if (!MO.isReg() || MO.isDef() || !MO.getReg())
+      for (const MachineOperand &MO : MI->all_uses()) {
+        if (!MO.getReg())
           continue;
         Register Reg = MO.getReg();
         if (PhysRegDefs.test(Reg) ||
             PhysRegClobbers.test(Reg)) {
           // If it's using a non-loop-invariant register, then it's obviously
           // not safe to hoist.
           Safe = false;
           break;
         }
       }
       if (Safe)
         HoistPostRA(MI, Candidate.Def);
     }
   }
 }
 
 /// Add register 'Reg' to the livein sets of BBs in the current loop, and make
 /// sure it is not killed by any instructions in the loop.
 void MachineLICMBase::AddToLiveIns(MCRegister Reg) {
   for (MachineBasicBlock *BB : CurLoop->getBlocks()) {
     if (!BB->isLiveIn(Reg))
       BB->addLiveIn(Reg);
     for (MachineInstr &MI : *BB) {
-      for (MachineOperand &MO : MI.operands()) {
-        if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
+      for (MachineOperand &MO : MI.all_uses()) {
+        if (!MO.getReg())
+          continue;
         if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
           MO.setIsKill(false);
       }
     }
   }
 }
 
 /// When an instruction is found to only use loop invariant operands that is

 /// virtual register uses. Even though rematerializable RA might not actually
 /// rematerialize it in this scenario. In that case we do not want to hoist such
 /// instruction out of the loop in a belief RA will sink it back if needed.
 bool MachineLICMBase::isTriviallyReMaterializable(
     const MachineInstr &MI) const {
   if (!TII->isTriviallyReMaterializable(MI))
     return false;
 
-  for (const MachineOperand &MO : MI.operands()) {
-    if (MO.isReg() && MO.isUse() && MO.getReg().isVirtual())
+  for (const MachineOperand &MO : MI.all_uses()) {
+    if (MO.getReg().isVirtual())
       return false;
   }
 
   return true;
 }
 
 void MachineLICMBase::EnterScope(MachineBasicBlock *MBB) {
   LLVM_DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n');

 }
 
 /// Return true if the specified instruction is used by a phi node and hoisting
 /// it could cause a copy to be inserted.
 bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI) const {
   SmallVector<const MachineInstr*, 8> Work(1, MI);
   do {
     MI = Work.pop_back_val();
-    for (const MachineOperand &MO : MI->operands()) {
-      if (!MO.isReg() || !MO.isDef())
-        continue;
+    for (const MachineOperand &MO : MI->all_defs()) {
       Register Reg = MO.getReg();
       if (!Reg.isVirtual())
         continue;
       for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
         // A PHI may cause a copy to be inserted.
         if (UseMI.isPHI()) {
           // A PHI inside the loop causes a copy because the live range of Reg is
           // extended across the PHI.
if (!EliminateCSE(MI, CI)) {
     MI->setDebugLoc(DebugLoc());
 
     // Update register pressure for BBs from header to this block.
     UpdateBackTraceRegPressure(MI);
 
     // Clear the kill flags of any register this instruction defines,
     // since they may need to be live throughout the entire loop
     // rather than just live for part of it.
-    for (MachineOperand &MO : MI->operands())
-      if (MO.isReg() && MO.isDef() && !MO.isDead())
+    for (MachineOperand &MO : MI->all_defs())
+      if (!MO.isDead())
         MRI->clearKillFlags(MO.getReg());
 
     // Add to the CSE map.
     if (CI != CSEMap.end())
       CI->second.push_back(MI);
     else
       CSEMap[Opcode].push_back(MI);
   }

llvm/lib/CodeGen/MachinePipeliner.cpp

static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   SmallVector<RegisterMaskPair, 8> LiveOutRegs;
   SmallSet<unsigned, 4> Uses;
   for (SUnit *SU : NS) {
     const MachineInstr *MI = SU->getInstr();
     if (MI->isPHI())
       continue;
-    for (const MachineOperand &MO : MI->operands())
-      if (MO.isReg() && MO.isUse()) {
-        Register Reg = MO.getReg();
-        if (Reg.isVirtual())
-          Uses.insert(Reg);
-        else if (MRI.isAllocatable(Reg))
-          for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
-               ++Units)
-            Uses.insert(*Units);
-      }
+    for (const MachineOperand &MO : MI->all_uses()) {
   }
   for (SUnit *SU : NS)
-    for (const MachineOperand &MO : SU->getInstr()->operands())
-      if (MO.isReg() && MO.isDef() && !MO.isDead()) {
+    for (const MachineOperand &MO : SU->getInstr()->all_defs())
+      if (!MO.isDead()) {
         Register Reg = MO.getReg();
         if (Reg.isVirtual()) {
           if (!Uses.count(Reg))
             LiveOutRegs.push_back(RegisterMaskPair(Reg,
                                                    LaneBitmask::getNone()));
         } else if (MRI.isAllocatable(Reg)) {
           for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
                ++Units)
bool SMSchedule::isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD,
   if (Def->isPHI())
     return false;
   MachineInstr *Phi = MRI.getVRegDef(MO.getReg());
   if (!Phi || !Phi->isPHI() || Phi->getParent() != Def->getParent())
     return false;
   if (!isLoopCarried(SSD, *Phi))
     return false;
   unsigned LoopReg = getLoopPhiReg(*Phi, Phi->getParent());
-  for (MachineOperand &DMO : Def->operands()) {
-    if (!DMO.isReg() || !DMO.isDef())
-      continue;
+  for (MachineOperand &DMO : Def->all_defs()) {
     if (DMO.getReg() == LoopReg)
       return true;
   }
   return false;
 }
 
 /// Determine transitive dependences of unpipelineable instructions
 SmallSet<SUnit *, 8> SMSchedule::computeUnpipelineableNodes(

llvm/lib/CodeGen/MachineSSAContext.cpp

void MachineSSAContext::appendBlockTerms(
     const MachineBasicBlock &block) {
   for (auto &T : block.terminators())
     terms.push_back(&T);
 }
 
 void MachineSSAContext::appendBlockDefs(SmallVectorImpl<Register> &defs,
                                         const MachineBasicBlock &block) {
   for (const MachineInstr &instr : block.instrs()) {
-    for (const MachineOperand &op : instr.operands()) {
-      if (op.isReg() && op.isDef())
-        defs.push_back(op.getReg());
-    }
-  }
-}
+    for (const MachineOperand &op : instr.all_defs())
 
 /// Get the defining block of a value.
 MachineBasicBlock *MachineSSAContext::getDefBlock(Register value) const {
   if (!value)
     return nullptr;
   return RegInfo->getVRegDef(value)->getParent();
 }
 

llvm/lib/CodeGen/MachineScheduler.cpp

for (const MachineOperand &MO : MI.operands()) {
 
     Register Reg = MO.getReg();
     if (!Reg.isVirtual())
       continue;
 
     // Ignore re-defs.
     if (TrackLaneMasks) {
       bool FoundDef = false;
-      for (const MachineOperand &MO2 : MI.operands()) {
-        if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
+      for (const MachineOperand &MO2 : MI.all_defs()) {
+        if (MO2.getReg() == Reg && !MO2.isDead()) {
           FoundDef = true;
           break;
         }
       }
       if (FoundDef)
         continue;
     }
 

llvm/lib/CodeGen/MachineSink.cpp

bool MachineSinking::isWorthBreakingCriticalEdge(MachineInstr &MI,
 
   if (From->isSuccessor(To) && MBPI->getEdgeProbability(From, To) <=
       BranchProbability(SplitEdgeProbabilityThreshold, 100))
     return true;
 
   // MI is cheap, we probably don't want to break the critical edge for it.
   // However, if this would allow some definitions of its source operands
   // to be sunk then it's probably worth it.
-  for (const MachineOperand &MO : MI.operands()) {
-    if (!MO.isReg() || !MO.isUse())
-      continue;
+  for (const MachineOperand &MO : MI.all_uses()) {
     Register Reg = MO.getReg();
     if (Reg == 0)
       continue;
 
     // We don't move live definitions of physical registers,
     // so sinking their uses won't enable any opportunities.
     if (Reg.isPhysical())
       continue;
bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
 
   // If there are no outputs, it must have side-effects.
   if (!SuccToSinkTo)
     return false;
 
   // If the instruction to move defines a dead physical register which is live
   // when leaving the basic block, don't move it because it could turn into a
   // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
-  for (const MachineOperand &MO : MI.operands()) {
-    if (!MO.isReg() || MO.isUse())
-      continue;
+  for (const MachineOperand &MO : MI.all_defs()) {
     Register Reg = MO.getReg();
     if (Reg == 0 || !Reg.isPhysical())
       continue;
     if (SuccToSinkTo->isLiveIn(Reg))
       return false;
   }
 
   LLVM_DEBUG(dbgs() << "Sink instr " << MI << "\tinto block " << *SuccToSinkTo);
MachineBasicBlock::iterator InsertPos =
       SuccToSinkTo->SkipPHIsAndLabels(SuccToSinkTo->begin());
   if (blockPrologueInterferes(SuccToSinkTo, InsertPos, MI, TRI, TII, MRI)) {
     LLVM_DEBUG(dbgs() << " *** Not sinking: prologue interference\n");
     return false;
   }
 
   // Collect debug users of any vreg that this inst defines.
   SmallVector<MIRegs, 4> DbgUsersToSink;
-  for (auto &MO : MI.operands()) {
-    if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
+  for (auto &MO : MI.all_defs()) {
+    if (!MO.getReg().isVirtual())
       continue;
     if (!SeenDbgUsers.count(MO.getReg()))
       continue;
 
     // Sink any users that don't pass any other DBG_VALUEs for this variable.
     auto &Users = SeenDbgUsers[MO.getReg()];
     for (auto &User : Users) {
       MachineInstr *DbgMI = User.getPointer();
bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
 
   performSink(MI, *SuccToSinkTo, InsertPos, DbgUsersToSink);
 
   // Conservatively, clear any kill flags, since it's possible that they are no
   // longer correct.
   // Note that we have to clear the kill flags for any register this instruction
   // uses as we may sink over another instruction which currently kills the
   // used registers.
-  for (MachineOperand &MO : MI.operands()) {
-    if (MO.isReg() && MO.isUse())
-      RegsToClearKillFlags.insert(MO.getReg()); // Remember to clear kill flags.
-  }
+  for (MachineOperand &MO : MI.all_uses())
 
   return true;
 }
 
 void MachineSinking::SalvageUnsunkDebugUsersOfCopy(
     MachineInstr &MI, MachineBasicBlock *TargetBlock) {
   assert(MI.isCopy());
   assert(MI.getOperand(1).isReg());
 
   // Enumerate all users of vreg operands that are def'd. Skip those that will
   // be sunk. For the rest, if they are not dominated by the block we will sink
   // MI into, propagate the copy source to them.
   SmallVector<MachineInstr *, 4> DbgDefUsers;
   SmallVector<Register, 4> DbgUseRegs;
   const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
-  for (auto &MO : MI.operands()) {
-    if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
+  for (auto &MO : MI.all_defs()) {
+    if (!MO.getReg().isVirtual())
       continue;
     DbgUseRegs.push_back(MO.getReg());
     for (auto &User : MRI.use_instructions(MO.getReg())) {
       if (!User.isDebugValue() || DT->dominates(TargetBlock, User.getParent()))
         continue;
 
       // If is in same block, will either sink or be use-before-def.
       if (User.getParent() == MI.getParent())
for (MachineInstr &MI : llvm::make_early_inc_range(llvm::reverse(CurBB))) {
     }
     assert((SuccBB->pred_size() == 1 && *SuccBB->pred_begin() == &CurBB) &&
            "Unexpected predecessor");
 
     // Collect DBG_VALUEs that must sink with this copy. We've previously
     // recorded which reg units that DBG_VALUEs read, if this instruction
     // writes any of those units then the corresponding DBG_VALUEs must sink.
     MapVector<MachineInstr *, MIRegs::second_type> DbgValsToSinkMap;
-    for (auto &MO : MI.operands()) {
-      if (!MO.isReg() || !MO.isDef())
-        continue;
-
+    for (auto &MO : MI.all_defs()) {
       for (auto RI = MCRegUnitIterator(MO.getReg(), TRI); RI.isValid(); ++RI) {
         for (const auto &MIRegs : SeenDbgInstrs.lookup(*RI)) {
           auto &Regs = DbgValsToSinkMap[MIRegs.first];
           for (unsigned Reg : MIRegs.second)
             Regs.push_back(Reg);
         }
       }
     }

llvm/lib/CodeGen/MachineUniformityAnalysis.cpp

 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/InitializePasses.h"
 
 using namespace llvm;
 
 template <>
 bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::hasDivergentDefs(
     const MachineInstr &I) const {
-  for (auto &op : I.operands()) {
-    if (!op.isReg() || !op.isDef())
-      continue;
+  for (auto &op : I.all_defs()) {
     if (isDivergent(op.getReg()))
       return true;
   }
   return false;
 }
 
 template <>
 bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::markDefsDivergent(
     const MachineInstr &Instr) {
   bool insertedDivergent = false;
   const auto &MRI = F.getRegInfo();
   const auto &RBI = *F.getSubtarget().getRegBankInfo();
   const auto &TRI = *MRI.getTargetRegisterInfo();
-  for (auto &op : Instr.operands()) {
-    if (!op.isReg() || !op.isDef())
-      continue;
+  for (auto &op : Instr.all_defs()) {
     if (!op.getReg().isVirtual())
       continue;
     assert(!op.getSubReg());
     if (TRI.isUniformReg(MRI, RBI, op.getReg()))
       continue;
     insertedDivergent |= markDivergent(op.getReg());
   }
   return insertedDivergent;

 }
 
 template <>
 void llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::pushUsers(
     const MachineInstr &Instr) {
   assert(!isAlwaysUniform(Instr));
   if (Instr.isTerminator())
     return;
-  for (const MachineOperand &op : Instr.operands()) {
-    if (!op.isReg() || !op.isDef())
-      continue;
+  for (const MachineOperand &op : Instr.all_defs()) {
     auto Reg = op.getReg();
     if (isDivergent(Reg))
       pushUsers(Reg);
   }
 }
 
 template <>
 bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::usesValueFromCycle(
bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::usesValueFromCycle(
   return false;
 }
 
 template <>
 void llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::
     propagateTemporalDivergence(const MachineInstr &I,
                                 const MachineCycle &DefCycle) {
   const auto &RegInfo = F.getRegInfo();
-  for (auto &Op : I.operands()) {
-    if (!Op.isReg() || !Op.isDef())
-      continue;
+  for (auto &Op : I.all_defs()) {
     if (!Op.getReg().isVirtual())
       continue;
     auto Reg = Op.getReg();
     if (isDivergent(Reg))
       continue;
     for (MachineInstr &UserInstr : RegInfo.use_instructions(Reg)) {
       if (DefCycle.contains(UserInstr.getParent()))
         continue;

llvm/lib/CodeGen/ModuloSchedule.cpp

void ModuloScheduleExpander::expand() {
   Preheader = *BB->pred_begin();
   if (Preheader == BB)
     Preheader = *std::next(BB->pred_begin());
 
   // Iterate over the definitions in each instruction, and compute the
   // stage difference for each use.  Keep the maximum value.
   for (MachineInstr *MI : Schedule.getInstructions()) {
     int DefStage = Schedule.getStage(MI);
-    for (const MachineOperand &Op : MI->operands()) {
-      if (!Op.isReg() || !Op.isDef())
-        continue;
-
+    for (const MachineOperand &Op : MI->all_defs()) {
       Register Reg = Op.getReg();
       unsigned MaxDiff = 0;
       bool PhiIsSwapped = false;
       for (MachineOperand &UseOp : MRI.use_operands(Reg)) {
         MachineInstr *UseMI = UseOp.getParent();
         int UseStage = Schedule.getStage(UseMI);
         unsigned Diff = 0;
         if (UseStage != -1 && UseStage >= DefStage)
for (MachineBasicBlock::reverse_instr_iterator MI = MBB->instr_rbegin(),
       bool SawStore = false;
       // Check if it's safe to remove the instruction due to side effects.
       // We can, and want to, remove Phis here.
       if (!MI->isSafeToMove(nullptr, SawStore) && !MI->isPHI()) {
         ++MI;
         continue;
       }
       bool used = true;
-      for (const MachineOperand &MO : MI->operands()) {
-        if (!MO.isReg() || !MO.isDef())
-          continue;
+      for (const MachineOperand &MO : MI->all_defs()) {
         Register reg = MO.getReg();
         // Assume physical registers are used, unless they are marked dead.
         if (reg.isPhysical()) {
           used = !MO.isDead();
           if (used)
             break;
           continue;
         }

llvm/lib/CodeGen/ProcessImplicitDefs.cpp

 }
 
 bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
   if (!MI->isCopyLike() &&
       !MI->isInsertSubreg() &&
       !MI->isRegSequence() &&
       !MI->isPHI())
     return false;
-  for (const MachineOperand &MO : MI->operands())
-    if (MO.isReg() && MO.isUse() && MO.readsReg())
+  for (const MachineOperand &MO : MI->all_uses())
+    if (MO.readsReg())
       return false;
   return true;
 }
 
 void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
   LLVM_DEBUG(dbgs() << "Processing " << *MI);
   Register Reg = MI->getOperand(0).getReg();
 

llvm/lib/CodeGen/RDFGraph.cpp

if (In.isBranch()) {
         return true;
     }
     return false;
   };
 
   auto isDefUndef = [this] (const MachineInstr &In, RegisterRef DR) -> bool {
     // This instruction defines DR. Check if there is a use operand that
     // would make DR live on entry to the instruction.
-    for (const MachineOperand &Op : In.operands()) {
-      if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef())
+    for (const MachineOperand &Op : In.all_uses()) {
+      if (Op.getReg() == 0 || Op.isUndef())
         continue;
       RegisterRef UR = makeRegRef(Op);
       if (PRI.alias(DR, UR))
         return false;
     }
     return true;
   };
 

llvm/lib/CodeGen/RDFLiveness.cpp

void Liveness::resetKills(MachineBasicBlock *B) {
   for (auto *SI : B->successors())
     CopyLiveIns(SI, Live);
 
   for (MachineInstr &MI : llvm::reverse(*B)) {
     if (MI.isDebugInstr())
       continue;
 
     MI.clearKillInfo();
-    for (auto &Op : MI.operands()) {
+    for (auto &Op : MI.all_defs()) {
       // An implicit def of a super-register may not necessarily start a
       // live range of it, since an implicit use could be used to keep parts
       // of it live. Instead of analyzing the implicit operands, ignore
       // implicit defs.
-      if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
+      if (Op.isImplicit())
         continue;
       Register R = Op.getReg();
       if (!R.isPhysical())
         continue;
       for (MCPhysReg SR : TRI.subregs_inclusive(R))
         Live.reset(SR);
     }
-    for (auto &Op : MI.operands()) {
-      if (!Op.isReg() || !Op.isUse() || Op.isUndef())
+    for (auto &Op : MI.all_uses()) {
+      if (Op.isUndef())
         continue;
       Register R = Op.getReg();
       if (!R.isPhysical())
         continue;
       bool IsLive = false;
       for (MCRegAliasIterator AR(R, &TRI, true); AR.isValid(); ++AR) {
         if (!Live[*AR])
           continue;

llvm/lib/CodeGen/RegAllocFast.cpp

for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
         break;
     }
   }
 
   // Allocate undef operands. This is a separate step because in a situation
   // like  ` = OP undef %X, %X`    both operands need the same register assign
   // so we should perform the normal assignment first.
   if (HasUndefUse) {
-    for (MachineOperand &MO : MI.uses()) {
-      if (!MO.isReg() || !MO.isUse())
-        continue;
+    for (MachineOperand &MO : MI.all_uses()) {
       Register Reg = MO.getReg();
       if (!Reg.isVirtual() || !shouldAllocateRegister(Reg))
         continue;
 
       assert(MO.isUndef() && "Should only have undef virtreg uses left");
       allocVirtRegUndef(MO);
     }
   }
 
   // Free early clobbers.
   if (HasEarlyClobber) {
-    for (MachineOperand &MO : llvm::reverse(MI.operands())) {
-      if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber())
+    for (MachineOperand &MO : llvm::reverse(MI.all_defs())) {
+      if (!MO.isEarlyClobber())
         continue;
       assert(!MO.getSubReg() && "should be already handled in def processing");
 
       Register Reg = MO.getReg();
       if (!Reg)
         continue;
       if (Reg.isVirtual()) {
         assert(!shouldAllocateRegister(Reg));

llvm/lib/CodeGen/RegisterCoalescer.cpp

bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
   return true;
 }
 
 /// Returns true if @p MI defines the full vreg @p Reg, as opposed to just
 /// defining a subregister.
 static bool definesFullReg(const MachineInstr &MI, Register Reg) {
   assert(!Reg.isPhysical() && "This code cannot handle physreg aliasing");
 
-  for (const MachineOperand &Op : MI.operands()) {
-    if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
+  for (const MachineOperand &Op : MI.all_defs()) {
+    if (Op.getReg() != Reg)
       continue;
     // Return true if we define the full register or don't care about the value
     // inside other subregisters.
     if (Op.getSubReg() == 0 || Op.isUndef())
       return true;
   }
   return false;
 }
for (MachineOperand &MO : MRI->reg_nodbg_operands(DstReg)) {
     LLVM_DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI);
   }
 
   // A def of a subregister may be a use of the other subregisters, so
   // deleting a def of a subregister may also remove uses. Since CopyMI
   // is still part of the function (but about to be erased), mark all
   // defs of DstReg in it as <undef>, so that shrinkToUses would
   // ignore them.
-  for (MachineOperand &MO : CopyMI->operands())
-    if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
+  for (MachineOperand &MO : CopyMI->all_defs())
+    if (MO.getReg() == DstReg)
       MO.setIsUndef(true);
   LIS->shrinkToUses(&DstLI);
 
   return CopyMI;
 }
 
 void RegisterCoalescer::addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
                                      MachineOperand &MO, unsigned SubRegIdx) {
public:
   }
 };
 
 } // end anonymous namespace
 
 LaneBitmask JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
   const {
   LaneBitmask L;
-  for (const MachineOperand &MO : DefMI->operands()) {
-    if (!MO.isReg() || MO.getReg() != Reg || !MO.isDef())
+  for (const MachineOperand &MO : DefMI->all_defs()) {
+    if (MO.getReg() != Reg)
       continue;
     L |= TRI->getSubRegIndexLaneMask(
            TRI->composeSubRegIndices(SubIdx, MO.getSubReg()));
     if (MO.readsReg())
       Redef = true;
   }
   return L;
 }
taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
   } while (TaintedLanes.any());
   return true;
 }
 
 bool JoinVals::usesLanes(const MachineInstr &MI, Register Reg, unsigned SubIdx,
                          LaneBitmask Lanes) const {
   if (MI.isDebugOrPseudoInstr())
     return false;
-  for (const MachineOperand &MO : MI.operands()) {
-    if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
+  for (const MachineOperand &MO : MI.all_uses()) {
+    if (MO.getReg() != Reg)
       continue;
     if (!MO.readsReg())
       continue;
     unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg());
     if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any())
       return true;
   }
   return false;

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

 void ScheduleDAGInstrs::addSchedBarrierDeps() {
   MachineInstr *ExitMI =
       RegionEnd != BB->end()
           ? &*skipDebugInstructionsBackward(RegionEnd, RegionBegin)
           : nullptr;
   ExitSU.setInstr(ExitMI);
   // Add dependencies on the defs and uses of the instruction.
   if (ExitMI) {
-    for (const MachineOperand &MO : ExitMI->operands()) {
-      if (!MO.isReg() || MO.isDef()) continue;
+    for (const MachineOperand &MO : ExitMI->all_uses()) {
       Register Reg = MO.getReg();
       if (Reg.isPhysical()) {
         Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
       } else if (Reg.isVirtual() && MO.readsReg()) {
         addVRegUseDeps(&ExitSU, MO.getOperandNo());
       }
     }
   }

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

#endif
     // by SubRegB is compatible with RegA with no subregister. So regardless of
     // whether the dest oper writes a subreg, the source oper should not.
     MO.setSubReg(0);
   }
 
   if (AllUsesCopied) {
     LaneBitmask RemainingUses = LaneBitmask::getNone();
     // Replace other (un-tied) uses of regB with LastCopiedReg.
-    for (MachineOperand &MO : MI->operands()) {
-      if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
+    for (MachineOperand &MO : MI->all_uses()) {
+      if (MO.getReg() == RegB) {
         if (MO.getSubReg() == SubRegB && !IsEarlyClobber) {
           if (MO.isKill()) {
             MO.setIsKill(false);
             RemovedKillFlag = true;
           }
           MO.setReg(LastCopiedReg);
           MO.setSubReg(0);
         } else {
if (LIS) {
       if (ShrinkLI)
         Shrink(LI, LaneBitmask::getAll());
     }
   } else if (RemovedKillFlag) {
     // Some tied uses of regB matched their destination registers, so
     // regB is still used in this instruction, but a kill flag was
     // removed from a different tied use of regB, so now we need to add
     // a kill flag to one of the remaining uses of regB.
-    for (MachineOperand &MO : MI->operands()) {
-      if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
+    for (MachineOperand &MO : MI->all_uses()) {
+      if (MO.getReg() == RegB) {
         MO.setIsKill(true);
         break;
       }
     }
   }
 }
 
 // For every tied operand pair this function transforms statepoint from