[AArch64] Predicate for ROR immediate

[evandro]

Summary

Add a common predicate for when the ROR immediate or "Bitfield extract, one register" idiom is used for EXTR or "Bitfield extract, two registers".

[dmgreen]

Sounds good to me.

[dmgreen]

Do you have any details where you are planning to use this? Just to make sure we dont end up doing similar work. Thanks

[evandro]

@dmgreen, I am working on a scheduling model that will use this change and also noticed that other processors, like Neoverse N1, N2, V1, etc, besides Exynos, could benefit from it too.

llvm/lib/Target/AArch64/AArch64SchedExynosM3.td

def M3WriteAV : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
                                    SchedVar<ExynosArithPred, [M3WriteA1]>,
                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 def M3WriteAW : SchedWriteVariant<[SchedVar<IsZeroIdiomPred, [M3WriteZ0]>,
                                    SchedVar<ExynosLogicPred, [M3WriteA1]>,
                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>,
                                    SchedVar<ExynosLogicPred, [M3WriteA1]>,
                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
-def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>,
-                                   SchedVar<NoSchedPred,              [M3WriteAA]>]>;
+def M3WriteAY : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M3WriteA1]>,
+                                   SchedVar<NoSchedPred,       [M3WriteAA]>]>;
 
 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
 def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>,
                                    SchedVar<NoSchedPred,            [M3WriteAB]>]>;
 
 def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; }
 def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; }
 def M3WriteLA : SchedWriteRes<[M3UnitL,

llvm/lib/Target/AArch64/AArch64SchedExynosM4.td

def M4WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred,   [M4WriteZ0]>,
                                    SchedVar<NoSchedPred,       [M4WriteAA]>]>;
 def M4WriteAV : SchedWriteVariant<[SchedVar<ExynosResetPred,   [M4WriteZ0]>,
                                    SchedVar<ExynosArithPred,   [M4WriteA1]>,
                                    SchedVar<ExynosLogicExPred, [M4WriteA1]>,
                                    SchedVar<NoSchedPred,       [M4WriteAA]>]>;
 def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M4WriteA1]>,
                                    SchedVar<ExynosLogicExPred, [M4WriteA1]>,
                                    SchedVar<NoSchedPred,       [M4WriteAA]>]>;
-def M4WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M4WriteA1]>,
-                                   SchedVar<NoSchedPred,              [M4WriteAF]>]>;
+def M4WriteAY : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M4WriteA1]>,
+                                   SchedVar<NoSchedPred,       [M4WriteAF]>]>;
 
 def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; }
 def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>,
                                    SchedVar<NoSchedPred,            [M4WriteAB]>]>;
 
 def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; }
 def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; }
 def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;

llvm/lib/Target/AArch64/AArch64SchedExynosM5.td

def M5WriteAVX : SchedWriteVariant<[SchedVar<ExynosResetPred,   [M5WriteZ0]>,
                                     SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
                                     SchedVar<NoSchedPred,       [M5WriteAAX]>]>;
 def M5WriteAXW : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M5WriteA1W]>,
                                     SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
                                     SchedVar<NoSchedPred,       [M5WriteAAW]>]>;
 def M5WriteAXX : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M5WriteA1X]>,
                                     SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
                                     SchedVar<NoSchedPred,       [M5WriteAAX]>]>;
-def M5WriteAYW : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M5WriteA1W]>,
-                                    SchedVar<NoSchedPred,              [M5WriteAFW]>]>;
-def M5WriteAYX : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M5WriteA1X]>,
-                                    SchedVar<NoSchedPred,              [M5WriteAFX]>]>;
+def M5WriteAYW : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M5WriteA1W]>,
+                                    SchedVar<NoSchedPred,       [M5WriteAFW]>]>;
+def M5WriteAYX : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M5WriteA1X]>,
+                                    SchedVar<NoSchedPred,       [M5WriteAFX]>]>;
 
 def M5WriteB1 : SchedWriteRes<[M5UnitB]> { let Latency = 1; }
 def M5WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M5WriteAC]>,
                                    SchedVar<NoSchedPred,            [M5WriteAB]>]>;
 
 def M5WriteC1 : SchedWriteRes<[M5UnitC]> { let Latency = 1; }
 def M5WriteC2 : SchedWriteRes<[M5UnitC]> { let Latency = 2; }
 def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3;

llvm/lib/Target/AArch64/AArch64SchedPredExynos.td

def ExynosResetFn   : TIIPredicate<
                                     [CheckRegOperand<1, WZR>,
                                      CheckRegOperand<1, XZR>]>]>>>],
                           MCReturnStatement<
                             CheckAny<
                               [IsCopyIdiomFn,
                                IsZeroFPIdiomFn]>>>>;
 def ExynosResetPred : MCSchedPredicate<ExynosResetFn>;
 
-// Identify EXTR as the alias for ROR (immediate).
-def ExynosRotateRightImmPred : MCSchedPredicate<
-                                 CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
-                                           CheckSameRegOperand<1, 2>]>>;
-
 // Identify cheap arithmetic and logic immediate instructions.
 def ExynosCheapFn : TIIPredicate<
                       "isExynosCheapAsMove",
                       MCOpcodeSwitchStatement<
                         [MCOpcodeSwitchCase<
                            IsArithLogicImmOp.ValidOpcodes,
                            MCReturnStatement<TruePred>>],
                         MCReturnStatement<
                           CheckAny<
                             [ExynosArithFn, ExynosResetFn, ExynosLogicFn]>>>>;

llvm/lib/Target/AArch64/AArch64SchedPredicates.td

def IsZeroIdiomFn     : TIIPredicate<"isZeroIdiom",
                                            CheckAll<
                                              [CheckIsRegOperand<1>,
                                               CheckAny<
                                                 [CheckRegOperand<1, WZR>,
                                                  CheckRegOperand<1, XZR>]>,
                                               CheckZeroOperand<2>]>>>],
                                       MCReturnStatement<FalsePred>>>;
 def IsZeroIdiomPred   : MCSchedPredicate<IsZeroIdiomFn>;
+
+// Identify EXTR as the alias for ROR (immediate).
+def IsRORImmIdiomPred : MCSchedPredicate<
+                          CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
+                                    CheckSameRegOperand<1, 2>]>>;