[GlobalIsel][x86] Legalize G_AND, G_OR, and G_XOR for AVX2

[tschuett]

Summary

check plan: ninja check-llvm-codegen-x86

[arsenm]

LGTM with nit

If you're picking up x86 legality rules I think step 1 is to remove all this legacy rule stuff

llvm/test/CodeGen/X86/GlobalISel/legalize-and-or-xor.mir

120

Formatting is consistently off, missing space before x

131–137

Can drop all this stuff

[tschuett]

address review comments

llvm/lib/Target/X86/X86LegalizerInfo.cpp

for (const auto &Ty : {v64s8, v32s16, v16s32, v8s64}) {
     LegacyInfo.setAction({G_UNMERGE_VALUES, 1, Ty},
                          LegacyLegalizeActions::Legal);
   }
   for (const auto &Ty : {v32s8, v16s16, v8s32, v4s64}) {
     LegacyInfo.setAction({G_CONCAT_VECTORS, 1, Ty},
                          LegacyLegalizeActions::Legal);
     LegacyInfo.setAction({G_UNMERGE_VALUES, Ty}, LegacyLegalizeActions::Legal);
   }
+
+  getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
+    .legalFor({v8s32, v4s64});
 }
 
 void X86LegalizerInfo::setLegalizerInfoAVX512() {
   if (!Subtarget.hasAVX512())
     return;
 
   const LLT v16s8 = LLT::fixed_vector(16, 8);
   const LLT v8s16 = LLT::fixed_vector(8, 16);

llvm/test/CodeGen/X86/GlobalISel/legalize-and-or-xor.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -O0 -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s
+
+# test vpand
+
+---
+name:            test_and_v8s32
+alignment:       16
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+body:             |
+  bb.1:
+
+    ; CHECK-LABEL: name: test_and_v8s32
+    ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s32>) = G_AND [[DEF]], [[DEF]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[AND]](<8 x s32>)
+    ; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
+    %0:_(<8 x s32>) = IMPLICIT_DEF
+    %1:_(<8 x s32>) = G_AND %0, %0
+    %2:_(<8 x s32>) = COPY %1(<8 x s32>)
+    RET 0, implicit %2
+...
+---
+name:            test_and_v4s64
+alignment:       16
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+body:             |
+  bb.1:
+
+    ; CHECK-LABEL: name: test_and_v4s64
+    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s64>) = G_AND [[DEF]], [[DEF]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[AND]](<4 x s64>)
+    ; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
+    %0:_(<4 x s64>) = IMPLICIT_DEF
+    %1:_(<4 x s64>) = G_AND %0, %0
+    %2:_(<4 x s64>) = COPY %1(<4 x s64>)
+    RET 0, implicit %2
+...
+---
+name:            test_xor_v4s64
+alignment:       16
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: test_xor_v4s64
+    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s64>) = G_XOR [[DEF]], [[DEF]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[XOR]](<4 x s64>)
+    ; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
+    %0:_(<4 x s64>) = IMPLICIT_DEF
+    %1:_(<4 x s64>) = G_XOR %0, %0
+    %2:_(<4 x s64>) = COPY %1(<4 x s64>)
+    RET 0, implicit %2
+
+...
+---
+name:            test_xor_v8s32
+alignment:       16
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: test_xor_v8s32
+    ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<8 x s32>) = G_XOR [[DEF]], [[DEF]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[XOR]](<8 x s32>)
+    ; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
+    %0:_(<8 x s32>) = IMPLICIT_DEF
+    %1:_(<8 x s32>) = G_XOR %0, %0
+    %2:_(<8 x s32>) = COPY %1(<8 x s32>)
+    RET 0, implicit %2
+
+...
+---
+name:            test_or_v4s64
+alignment:       16
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: test_or_v4s64
+    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s64>) = G_OR [[DEF]], [[DEF]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[OR]](<4 x s64>)
+    ; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
+    %0:_(<4x s64>) = IMPLICIT_DEF
+    %1:_(<4x s64>) = G_OR %0, %0
+    %2:_(<4x s64>) = COPY %1(<4x s64>)
+    RET 0, implicit %2
+
+...
+---
+name:            test_or_v8s32
+alignment:       16
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: test_or_v8s32
+    ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s32>) = G_OR [[DEF]], [[DEF]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[OR]](<8 x s32>)
+    ; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
+    %0:_(<8x s32>) = IMPLICIT_DEF
+    %1:_(<8x s32>) = G_OR %0, %0
+    %2:_(<8x s32>) = COPY %1(<8x s32>)
+    RET 0, implicit %2
+
+...