[Lanai] Use backwards scavenging in frame index elimination

[foad]

Summary

This is preferred because it does not rely on accurate kill flags.

[jpienaar]

Would a difference show up on a small test?

[jpienaar]

Looks good in general.

[foad]

In D150600#4344440, @jpienaar wrote:

Would a difference show up on a small test?

If you have a small test that relies on scavenging then we can run it with -stop-before=prologepilog to get a MIR test, and then manually add/remove some kill flags to show that forward scavenging is affected by that but backwards scavenging is not.

Currently if I disable the scavenging part of LanaiRegisterInfo::eliminateFrameIndex then all the codegen tests still pass :(

[foad]

Switch to scavengeRegisterBackwards.

llvm/lib/Target/Lanai/LanaiRegisterInfo.h

struct LanaiRegisterInfo : public LanaiGenRegisterInfo {
   // Code Generation virtual methods.
   const uint16_t *
   getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
+  bool supportsBackwardScavenger() const override { return true; }
+
   bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   // Debug information queries.
   unsigned getRARegister() const;
   Register getFrameRegister(const MachineFunction &MF) const override;
   Register getBaseRegister() const;
   bool hasBasePointer(const MachineFunction &MF) const;
 
   int getDwarfRegNum(unsigned RegNum, bool IsEH) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LANAI_LANAIREGISTERINFO_H

llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp

bool LanaiRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   // If the offset is small enough to fit in the immediate field, directly
   // encode it.
   // Otherwise scavenge a register and encode it into a MOVHI, OR_I_LO sequence.
   if ((isSPLSOpcode(MI.getOpcode()) && !isInt<10>(Offset)) ||
       !isInt<16>(Offset)) {
     assert(RS && "Register scavenging must be on");
     Register Reg = RS->FindUnusedReg(&Lanai::GPRRegClass);
     if (!Reg)
-      Reg = RS->scavengeRegister(&Lanai::GPRRegClass, II, SPAdj);
+      Reg = RS->scavengeRegisterBackwards(Lanai::GPRRegClass, II, false, SPAdj);
     assert(Reg && "Register scavenger failed");
 
     bool HasNegOffset = false;
     // ALU ops have unsigned immediate values. If the Offset is negative, we
     // negate it here and reverse the opcode later.
     if (Offset < 0) {
       HasNegOffset = true;
       Offset = -Offset;
if ((Offset < 0) && isALUArithLoOpcode(MI.getOpcode())) {
     // 0: destination register
     // 1: source register (frame register)
     // 2: immediate
     BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode),
             MI.getOperand(0).getReg())
         .addReg(FrameReg)
         .addImm(-Offset);
     MI.eraseFromParent();
-  } else {
-    MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
-    MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
-  }
+    return true;
+  }
+
   return false;
 }
 
 bool LanaiRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   // When we need stack realignment and there are dynamic allocas, we can't
   // reference off of the stack pointer, so we reserve a base pointer.
   if (hasStackRealignment(MF) && MFI.hasVarSizedObjects())