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[AMDGPU] Add implicit uses to AGPR copy MIR tests
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Authored by foad on May 15 2023, 6:47 AM.

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Reviewers
arsenm
Group Reviewers
Restricted Project
Commits
rGaf0121fb8f79: [AMDGPU] Add implicit uses to AGPR copy MIR tests
Summary

Some tests were using liveins or IMPLICIT_DEFs to add fake live
registers, but that only works if you track liveness forwards. Add some
implicit uses too, so that it also works if you track liveness
backwards.

Some of these tests were using the regmask amdgpu_allvgprs but that is a
clobber not a use.

Diff Detail

Event Timeline

foad created this revision.May 15 2023, 6:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 15 2023, 6:47 AM
foad requested review of this revision.May 15 2023, 6:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 15 2023, 6:47 AM
Pierre-vh added inline comments.
llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
75–76

nit: Why is there two nops now?

foad added inline comments.May 16 2023, 12:11 AM
llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
75–76

s_nop x means delay for x+1 cycles so the code is equivalent. I assumed the reason was that the hazard recognizer added the second nop (and was not clever enough to combine it into the first one) but I did not look too closely.

arsenm added a subscriber: arsenm.May 16 2023, 12:16 AM
arsenm added inline comments.
llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
75–76

I thought there was a nop run cleanup in SIShrinkInstructions but it looks like that was removed in ebdcef20ce2921d1b6e8463ecf4031396cef79dc

arsenm accepted this revision.May 16 2023, 12:17 AM
This revision is now accepted and ready to land.May 16 2023, 12:17 AM
This revision was landed with ongoing or failed builds.May 16 2023, 1:13 AM
This revision was automatically updated to reflect the committed changes.