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[AArch64] Add ARMv8.2-A FP16 scalar instructions
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Authored by olista01 on Nov 26 2015, 5:08 AM.

Details

Summary

ARMv8.2-A adds 16-bit floating point versions of all existing VFP
floating-point instructions. This is an optional extension, so all of
these instructions require the FeatureFullFP16 subtarget feature.

Most of these instructions are the same as the 32- and 64-bit versions,
but with the type field (bits 23-22) set to 0b11. Previously the top bit
of the size field was always 0, so the instruction classes only provided
a 1-bit size field, which I have widened to 2 bits.

Diff Detail

Repository
rL LLVM

Event Timeline

olista01 updated this revision to Diff 41235.Nov 26 2015, 5:08 AM
olista01 retitled this revision from to [AArch64] Add ARMv8.2-A FP16 scalar instructions.
olista01 updated this object.
olista01 added a reviewer: t.p.northover.
olista01 set the repository for this revision to rL LLVM.
olista01 added a subscriber: llvm-commits.
ab accepted this revision.Nov 27 2015, 3:19 AM
ab added a reviewer: ab.
ab added a subscriber: ab.

LGTM

I'll submit a patch for fccmp if you don't have one already. Thanks!

lib/Target/AArch64/AArch64InstrFormats.td
4195 ↗(On Diff #41235)

Redundant with 4175?

This revision is now accepted and ready to land.Nov 27 2015, 3:19 AM
This revision was automatically updated to reflect the committed changes.