[SelectionDAG] Use `computeKnownBits` if `Op` is not recognized by `isKnownNeverZero`

[goldstein.w.n]

Summary

The current logic is pretty limitted unless the Op is a
constant. This at least covers more obvious cases.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

5020

I think you want Depth -1 here to counteract the increment earlier. The switch in computeKnownBits should be the same depth as the switch in this function.

[goldstein.w.n]

Depth - 1

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

5020

return computeKnownBits(Op, Depth - 1).isNonZero(). KnownBits already has a wrapper so we don't have to reference the One field directly.

[goldstein.w.n]

use isNonZero

[craig.topper]

LGTM

[foad]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

5020

It would be less confusing overall to *not* increment Depth.

[goldstein.w.n]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

5020

I think in this case is but it makes it so that in all the recursive cases you can just copy Depth rather than Depth + 1. Its also what we do in ValueTracking to think it makes sense to keep it similiar.

[goldstein.w.n]

Rebase

[goldstein.w.n]

Rebase

[goldstein.w.n]

Rebase

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
   default: break;
   case ISD::OR:
     if (isKnownNeverZero(Op.getOperand(1)) ||
         isKnownNeverZero(Op.getOperand(0)))
       return true;
     break;
   }
 
-  return false;
+  return !computeKnownBits(Op, Depth).One.isZero();
 }
 
 bool SelectionDAG::isEqualTo(SDValue A, SDValue B) const {
   // Check the obvious case.
   if (A == B) return true;
 
   // For for negative and positive zero.
   if (const ConstantFPSDNode *CA = dyn_cast<ConstantFPSDNode>(A))

llvm/test/CodeGen/ARM/cttz_vector.ll

; CHECK-NEXT:    bx lr
   store <2 x i8> %tmp, ptr %p
   ret void
 }
 
 define void @test_v4i8(ptr %p) {
 ; CHECK-LABEL: test_v4i8:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vld1.32 {d16[0]}, [r0:32]
-; CHECK-NEXT:    vmov.i16 d19, #0x1
 ; CHECK-NEXT:    vmovl.u8 q8, d16
 ; CHECK-NEXT:    vorr.i16 d16, #0x100
 ; CHECK-NEXT:    vneg.s16 d18, d16
 ; CHECK-NEXT:    vand d16, d16, d18
-; CHECK-NEXT:    vsub.i16 d16, d16, d19
-; CHECK-NEXT:    vcnt.8 d16, d16
-; CHECK-NEXT:    vpaddl.u8 d16, d16
+; CHECK-NEXT:    vmov.i16 d17, #0xf
+; CHECK-NEXT:    vclz.i16 d16, d16
+; CHECK-NEXT:    vsub.i16 d16, d17, d16
 ; CHECK-NEXT:    vuzp.8 d16, d17
 ; CHECK-NEXT:    vst1.32 {d16[0]}, [r0:32]
 ; CHECK-NEXT:    bx lr
   %a = load <4 x i8>, ptr %p
   %tmp = call <4 x i8> @llvm.cttz.v4i8(<4 x i8> %a, i1 false)
   store <4 x i8> %tmp, ptr %p
   ret void
 }