Fix uninitialized scalar members in CodeGen

[akshaykhadse]

Summary

This change fixes some static code analysis warnings.

[LuoYuanke]

LGTM.

llvm/include/llvm/CodeGen/AccelTable.h

 protected:
   /// Allocator for HashData and Values.
   BumpPtrAllocator Allocator;
 
   using StringEntries = StringMap<HashData, BumpPtrAllocator &>;
   StringEntries Entries;
 
   HashFn *Hash;
-  uint32_t BucketCount;
-  uint32_t UniqueHashCount;
+  uint32_t BucketCount = 0;
+  uint32_t UniqueHashCount = 0;
 
   HashList Hashes;
   BucketList Buckets;
 
   void computeBucketCount();
 
   AccelTableBase(HashFn *Hash) : Entries(Allocator), Hash(Hash) {}
 

llvm/include/llvm/CodeGen/MachineModuleInfo.h

class MachineModuleInfo {
   /// MachineModuleInfoImpl, which lets targets accumulate whatever info they
   /// want.
   MachineModuleInfoImpl *ObjFileMMI;
 
   /// \name Exception Handling
   /// \{
 
   /// The current call site index being processed, if any. 0 if none.
-  unsigned CurCallSite;
+  unsigned CurCallSite = 0;
 
   /// \}
 
   // TODO: Ideally, what we'd like is to have a switch that allows emitting
   // synchronous (precise at call-sites only) CFA into .eh_frame. However,
   // even under this switch, we'd like .debug_frame to be precise when using
   // -g. At this moment, there's no way to specify that some CFI directives
   // go into .eh_frame only, while others go into .debug_frame only.
 
   /// True if debugging information is available in this module.
-  bool DbgInfoAvailable;
+  bool DbgInfoAvailable = false;
 
   /// True if this module is being built for windows/msvc, and uses floating
   /// point.  This is used to emit an undefined reference to _fltused.
-  bool UsesMSVCFloatingPoint;
+  bool UsesMSVCFloatingPoint = false;
 
   /// Maps IR Functions to their corresponding MachineFunctions.
   DenseMap<const Function*, std::unique_ptr<MachineFunction>> MachineFunctions;
   /// Next unique number available for a MachineFunction.
   unsigned NextFnNum = 0;
   const Function *LastRequest = nullptr; ///< Used for shortcut/cache.
   MachineFunction *LastResult = nullptr; ///< Used for shortcut/cache.
 

llvm/include/llvm/CodeGen/MachinePipeliner.h

class SwingSchedulerDAG : public ScheduleDAGInstrs {
   class Circuits {
     std::vector<SUnit> &SUnits;
     SetVector<SUnit *> Stack;
     BitVector Blocked;
     SmallVector<SmallPtrSet<SUnit *, 4>, 10> B;
     SmallVector<SmallVector<int, 4>, 16> AdjK;
     // Node to Index from ScheduleDAGTopologicalSort
     std::vector<int> *Node2Idx;
-    unsigned NumPaths;
+    unsigned NumPaths = 0u;
     static unsigned MaxPaths;
 
   public:
     Circuits(std::vector<SUnit> &SUs, ScheduleDAGTopologicalSort &Topo)
         : SUnits(SUs), Blocked(SUs.size()), B(SUs.size()), AdjK(SUs.size()) {
       Node2Idx = new std::vector<int>(SUs.size());
       unsigned Idx = 0;
       for (const auto &NodeNum : Topo)
private:
   /// are assumed to be scheduled one per cycle, starting with the cycle in
   /// which the instruction is scheduled.
   llvm::SmallVector<int> NumScheduledMops;
   /// Each processor resource is associated with a so-called processor resource
   /// mask. This vector allows to correlate processor resource IDs with
   /// processor resource masks. There is exactly one element per each processor
   /// resource declared by the scheduling model.
   llvm::SmallVector<uint64_t, DefaultProcResSize> ProcResourceMasks;
-  int InitiationInterval;
+  int InitiationInterval = 0;
   /// The number of micro operations that can be scheduled at a cycle.
   int IssueWidth;
 
   int calculateResMIIDFA() const;
   /// Check if MRT is overbooked
   bool isOverbooked() const;
   /// Reserve resources on MRT
   void reserveResources(const MCSchedClassDesc *SCDesc, int Cycle);

llvm/include/llvm/CodeGen/RegisterPressure.h

struct IndexMaskPair {
 
     unsigned getSparseSetIndex() const {
       return Index;
     }
   };
 
   using RegSet = SparseSet<IndexMaskPair>;
   RegSet Regs;
-  unsigned NumRegUnits;
+  unsigned NumRegUnits = 0u;
 
   unsigned getSparseIndexFromReg(Register Reg) const {
     if (Reg.isVirtual())
       return Register::virtReg2Index(Reg) + NumRegUnits;
     assert(Reg < NumRegUnits);
     return Reg;
   }
 

llvm/include/llvm/CodeGen/ScheduleDAG.h

union {
 
       /// Additional information about Order dependencies.
       unsigned OrdKind; // enum OrderKind
     } Contents;
 
     /// The time associated with this edge. Often this is just the value of the
     /// Latency field of the predecessor, however advanced models may provide
     /// additional information about specific edges.
-    unsigned Latency;
+    unsigned Latency = 0u;
 
   public:
     /// Constructs a null SDep. This is only for use by container classes which
     /// require default constructors. SUnits may not/ have null SDep edges.
     SDep() : Dep(nullptr, Data) {}
 
     /// Constructs an SDep with the specified values.
     SDep(SUnit *S, Kind kind, unsigned Reg)

llvm/include/llvm/CodeGen/SelectionDAGNodes.h

private:
   /// The operation that this node performs.
   int32_t NodeType;
 
 public:
   /// Unique and persistent id per SDNode in the DAG. Used for debug printing.
   /// We do not place that under `#if LLVM_ENABLE_ABI_BREAKING_CHECKS`
   /// intentionally because it adds unneeded complexity without noticeable
   /// benefits (see discussion with @thakis in D120714).
-  uint16_t PersistentId;
+  uint16_t PersistentId = 0xffff;
 
 protected:
   // We define a set of mini-helper classes to help us interpret the bits in our
   // SubclassData.  These are designed to fit within a uint16_t so they pack
   // with PersistentId.
 
 #if defined(_AIX) && (!defined(__GNUC__) || defined(__clang__))
 // Except for GCC; by default, AIX compilers store bit-fields in 4-byte words

llvm/include/llvm/CodeGen/TileShapeInfo.h

void deduceImm(const MachineRegisterInfo *MRI) {
     RowImm = GetImm(Row->getReg());
     ColImm = GetImm(Col->getReg());
   }
 
 private:
   static constexpr int64_t InvalidImmShape = -1;
   MachineOperand *Row;
   MachineOperand *Col;
-  int64_t RowImm;
-  int64_t ColImm;
+  int64_t RowImm = -1;
+  int64_t ColImm = -1;
 };
 
 } // namespace llvm
 
 #endif

llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp

 template <typename DataT>
 class Dwarf5AccelTableWriter : public AccelTableWriter {
   struct Header {
     uint16_t Version = 5;
     uint16_t Padding = 0;
     uint32_t CompUnitCount;
     uint32_t LocalTypeUnitCount = 0;
     uint32_t ForeignTypeUnitCount = 0;
-    uint32_t BucketCount;
-    uint32_t NameCount;
+    uint32_t BucketCount = 0;
+    uint32_t NameCount = 0;
     uint32_t AbbrevTableSize = 0;
     uint32_t AugmentationStringSize = sizeof(AugmentationString);
     char AugmentationString[8] = {'L', 'L', 'V', 'M', '0', '7', '0', '0'};
 
     Header(uint32_t CompUnitCount, uint32_t BucketCount, uint32_t NameCount)
         : CompUnitCount(CompUnitCount), BucketCount(BucketCount),
           NameCount(NameCount) {}
 

llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp

private:
   using NodePtr = std::shared_ptr<ComplexDeinterleavingCompositeNode>;
   using RawNodePtr = ComplexDeinterleavingCompositeNode *;
 
 public:
   ComplexDeinterleavingOperation Operation;
   Instruction *Real;
   Instruction *Imag;
 
-  ComplexDeinterleavingRotation Rotation;
+  ComplexDeinterleavingRotation Rotation =
+      ComplexDeinterleavingRotation::Rotation_0;
   SmallVector<RawNodePtr> Operands;
   Value *ReplacementNode = nullptr;
 
   void addOperand(NodePtr Node) { Operands.push_back(Node.get()); }
 
   void dump() { dump(dbgs()); }
   void dump(raw_ostream &OS) {
     auto PrintValue = [&](Value *V) {

llvm/lib/CodeGen/GlobalMerge.cpp

class GlobalMerge : public FunctionPass {
     /// Currently, this applies a dead simple heuristic: only consider globals
     /// used in minsize functions for merging.
     /// FIXME: This could learn about optsize, and be used in the cost model.
     bool OnlyOptimizeForSize = false;
 
     /// Whether we should merge global variables that have external linkage.
     bool MergeExternalGlobals = false;
 
-    bool IsMachO;
+    bool IsMachO = false;
 
     bool doMerge(SmallVectorImpl<GlobalVariable*> &Globals,
                  Module &M, bool isConst, unsigned AddrSpace) const;
 
     /// Merge everything in \p Globals for which the corresponding bit
     /// in \p GlobalSet is set.
     bool doMerge(const SmallVectorImpl<GlobalVariable *> &Globals,
                  const BitVector &GlobalSet, Module &M, bool isConst,

llvm/lib/CodeGen/InterleavedAccessPass.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
   }
 
 private:
   DominatorTree *DT = nullptr;
   const TargetLowering *TLI = nullptr;
 
   /// The maximum supported interleave factor.
-  unsigned MaxFactor;
+  unsigned MaxFactor = 0u;
 
   /// Transform an interleaved load into target specific intrinsics.
   bool lowerInterleavedLoad(LoadInst *LI,
                             SmallVector<Instruction *, 32> &DeadInsts);
 
   /// Transform an interleaved store into target specific intrinsics.
   bool lowerInterleavedStore(StoreInst *SI,
                              SmallVector<Instruction *, 32> &DeadInsts);

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

 class ScheduleDAGFast : public ScheduleDAGSDNodes {
 private:
   /// AvailableQueue - The priority queue to use for the available SUnits.
   FastPriorityQueue AvailableQueue;
 
   /// LiveRegDefs - A set of physical registers and their definition
   /// that are "live". These nodes must be scheduled before any other nodes that
   /// modifies the registers can be scheduled.
-  unsigned NumLiveRegs;
+  unsigned NumLiveRegs = 0u;
   std::vector<SUnit*> LiveRegDefs;
   std::vector<unsigned> LiveRegCycles;
 
 public:
   ScheduleDAGFast(MachineFunction &mf)
     : ScheduleDAGSDNodes(mf) {}
 
   void Schedule() override;

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

private:
 
   /// HazardRec - The hazard recognizer to use.
   ScheduleHazardRecognizer *HazardRec;
 
   /// CurCycle - The current scheduler state corresponds to this cycle.
   unsigned CurCycle = 0;
 
   /// MinAvailableCycle - Cycle of the soonest available instruction.
-  unsigned MinAvailableCycle;
+  unsigned MinAvailableCycle = ~0u;
 
   /// IssueCount - Count instructions issued in this cycle
   /// Currently valid only for bottom-up scheduling.
-  unsigned IssueCount;
+  unsigned IssueCount = 0u;
 
   /// LiveRegDefs - A set of physical registers and their definition
   /// that are "live". These nodes must be scheduled before any other nodes that
   /// modifies the registers can be scheduled.
-  unsigned NumLiveRegs;
+  unsigned NumLiveRegs = 0u;
   std::unique_ptr<SUnit*[]> LiveRegDefs;
   std::unique_ptr<SUnit*[]> LiveRegGens;
 
   // Collect interferences between physical register use/defs.
   // Each interference is an SUnit and set of physical registers.
   SmallVector<SUnit*, 4> Interferences;
 
   using LRegsMapT = DenseMap<SUnit *, SmallVector<unsigned, 4>>;

llvm/lib/CodeGen/SplitKit.h

private:
   // Sorted slot indexes of using instructions.
   SmallVector<SlotIndex, 8> UseSlots;
 
   /// UseBlocks - Blocks where CurLI has uses.
   SmallVector<BlockInfo, 8> UseBlocks;
 
   /// NumGapBlocks - Number of duplicate entries in UseBlocks for blocks where
   /// the live range has a gap.
-  unsigned NumGapBlocks;
+  unsigned NumGapBlocks = 0u;
 
   /// ThroughBlocks - Block numbers where CurLI is live through without uses.
   BitVector ThroughBlocks;
 
   /// NumThroughBlocks - Number of live-through blocks.
-  unsigned NumThroughBlocks;
+  unsigned NumThroughBlocks = 0u;
 
   // Sumarize statistics by counting instructions using CurLI.
   void analyzeUses();
 
   /// calcLiveBlockInfo - Compute per-block information about CurLI.
   void calcLiveBlockInfo();
 
 public: