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Differential D147734

[LV][NFC] Precommit test for a follow-up patch that introduces uniformity for a specific VF.
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Authored by vporpo on Apr 6 2023, 12:49 PM.

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fhahn
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rG95539186c826: [LV][NFC] Precommit test for a follow-up patch that introduces uniformity for a…

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vporpo created this revision.Apr 6 2023, 12:49 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 6 2023, 12:49 PM
vporpo requested review of this revision.Apr 6 2023, 12:49 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 6 2023, 12:49 PM
Herald added subscribers: llvm-commits, • pcwang-thead. · View Herald Transcript
vporpo added a child revision: D147735: [LV] Adds simple analysis that improves VF-aware uniformity checks..Apr 6 2023, 12:51 PM
Harbormaster completed remote builds in B224084: Diff 511504.Apr 6 2023, 1:27 PM
fhahn added a subscriber: fhahn.Apr 20 2023, 1:38 PM

I think it would be good to extend test coverage by adding tests with 1) multiple inductions, 2) different induction start values (different constants, maybe a function argument), 3) different divisors (including a non-power-of-2 one)

llvm/test/Transforms/LoopVectorize/X86/uniform_across_vf.ll
2

Does the test have to be X86 specific or could it be generic?

vporpo added a comment.Apr 20 2023, 2:58 PM

OK let me add more tests.

llvm/test/Transforms/LoopVectorize/X86/uniform_across_vf.ll
2

Yeah I can move it one directory up.

vporpo updated this revision to Diff 515521.Apr 20 2023, 4:15 PM

Added more tests. Testing all combinations of: start from 0 to 1, step from 1 to 3 and div from 1 to 3.
Added a separate file for the same tests but with 2 inductions.

Harbormaster completed remote builds in B227011: Diff 515521.Apr 20 2023, 5:27 PM
vporpo added a reviewer: fhahn.Apr 21 2023, 10:15 AM
Herald added a subscriber: StephenFan. · View Herald TranscriptApr 21 2023, 10:15 AM
vporpo added a comment.Apr 21 2023, 10:18 AM

Do you think I should add a couple of tests with a left-shift too , instead of a div (like i << 1 instead of i / 2 ? Though the SCEV implementation should cover both.

vporpo added a comment.Apr 21 2023, 10:19 AM

*I meant right shifts (i >> 1)

fhahn added a comment.Apr 22 2023, 1:38 PM

Thanks for adding all the extra tests! For the multi-induction tests, I think it would be good to have the additional iv2 also used in the loop body (besides incrementing it) in some of the tests, as suggested inline.

llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
54 ↗(On Diff #515521)

for those tests, it would probably be good to use %iv2 as well, possibly some cases where the index is %iv /C + iv2 / C.

vporpo updated this revision to Diff 516441.Apr 24 2023, 9:28 AM

Use iv2 in the index calculation: iv/C + iv2/C.

Harbormaster completed remote builds in B227754: Diff 516441.Apr 24 2023, 10:12 AM
fhahn accepted this revision.Apr 25 2023, 1:34 PM

LGTM, thanks for adding the extensive test coverage. It would be good to extend wit other patterns in the future, like shifts.

In D147734#4292778, @vporpo wrote:

Use iv2 in the index calculation: iv/C + iv2/C.

Excellent! This should also be handled by D148841 automatically.

llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
1494 ↗(On Diff #516441)

nit: stray newline.

This revision is now accepted and ready to land.Apr 25 2023, 1:34 PM
fhahn mentioned this in D148841: [LV] Use SCEV for uniformity analysis across VF.Apr 25 2023, 1:42 PM
This revision was landed with ongoing or failed builds.Apr 25 2023, 2:14 PM
Closed by commit rG95539186c826: [LV][NFC] Precommit test for a follow-up patch that introduces uniformity for a… (authored by vporpo). · Explain Why
This revision was automatically updated to reflect the committed changes.
vporpo added a commit: rG95539186c826: [LV][NFC] Precommit test for a follow-up patch that introduces uniformity for a….

Revision Contents

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llvm/
test/
Transforms/
LoopVectorize/
X86/
331 lines

Diff 511504

llvm/test/Transforms/LoopVectorize/X86/uniform_across_vf.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -mtriple=x86_64-unknown-linux -mcpu=skx -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=2 %s -S | FileCheck %s
fhahnUnsubmitted
Not Done
ReplyInline Actions

Does the test have to be X86 specific or could it be generic?

fhahn: Does the test have to be X86 specific or could it be generic?
vporpoAuthorUnsubmitted
Done
ReplyInline Actions

Yeah I can move it one directory up.

vporpo: Yeah I can move it one directory up.
; This is for division by 1, step 1
define void @ld_div1_step1(ptr noalias %src, ptr noalias %dst) {
; CHECK-LABEL: define void @ld_div1_step1
; CHECK-SAME: (ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], 1
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 0
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP3]], align 8
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <2 x i64> [[WIDE_LOAD]], <i64 42, i64 42>
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP5]], i32 0
; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr [[TMP6]], align 8
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000
; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: middle.block:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1000, 1000
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[IV]], 1
; CHECK-NEXT: [[GEP_LD:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[DIV]]
; CHECK-NEXT: [[LD:%.*]] = load i64, ptr [[GEP_LD]], align 8
; CHECK-NEXT: [[CALC:%.*]] = add nsw i64 [[LD]], 42
; CHECK-NEXT: [[GEP_ST:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[IV]]
; CHECK-NEXT: store i64 [[CALC]], ptr [[GEP_ST]], align 8
; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[IV_NEXT]], 1000
; CHECK-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i64 [ 0, %entry ], [ %iv_next, %loop ]
%div = udiv i64 %iv, 1
%gep_ld = getelementptr inbounds i64, ptr %src, i64 %div
%ld = load i64, ptr %gep_ld, align 8
%calc = add nsw i64 %ld, 42
%gep_st = getelementptr inbounds i64, ptr %dst, i64 %iv
store i64 %calc, ptr %gep_st, align 8
%iv_next = add nsw i64 %iv, 1
%cond = icmp eq i64 %iv_next, 1000
br i1 %cond, label %exit, label %loop
exit:
ret void
}
; This is for division by 2 step 1
define void @ld_div2_step1(ptr noalias %src, ptr noalias %dst) {
; CHECK-LABEL: define void @ld_div2_step1
; CHECK-SAME: (ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
; CHECK-NEXT: [[TMP1:%.*]] = udiv <2 x i64> [[VEC_IND]], <i64 2, i64 2>
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP3]], align 8
; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP5]], align 8
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> poison, i64 [[TMP6]], i32 0
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i64> [[TMP8]], i64 [[TMP7]], i32 1
; CHECK-NEXT: [[TMP10:%.*]] = add nsw <2 x i64> [[TMP9]], <i64 42, i64 42>
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP11]], i32 0
; CHECK-NEXT: store <2 x i64> [[TMP10]], ptr [[TMP12]], align 8
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], <i64 2, i64 2>
; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000
; CHECK-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK: middle.block:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1000, 1000
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[IV]], 2
; CHECK-NEXT: [[GEP_LD:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[DIV]]
; CHECK-NEXT: [[LD:%.*]] = load i64, ptr [[GEP_LD]], align 8
; CHECK-NEXT: [[CALC:%.*]] = add nsw i64 [[LD]], 42
; CHECK-NEXT: [[GEP_ST:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[IV]]
; CHECK-NEXT: store i64 [[CALC]], ptr [[GEP_ST]], align 8
; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[IV_NEXT]], 1000
; CHECK-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i64 [ 0, %entry ], [ %iv_next, %loop ]
%div = udiv i64 %iv, 2
%gep_ld = getelementptr inbounds i64, ptr %src, i64 %div
%ld = load i64, ptr %gep_ld, align 8
%calc = add nsw i64 %ld, 42
%gep_st = getelementptr inbounds i64, ptr %dst, i64 %iv
store i64 %calc, ptr %gep_st, align 8
%iv_next = add nsw i64 %iv, 1
%cond = icmp eq i64 %iv_next, 1000
br i1 %cond, label %exit, label %loop
exit:
ret void
}
; This is for division by 3 step 1
define void @ld_div3_step1(ptr noalias %src, ptr noalias %dst) {
; CHECK-LABEL: define void @ld_div3_step1
; CHECK-SAME: (ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
; CHECK-NEXT: [[TMP1:%.*]] = udiv <2 x i64> [[VEC_IND]], <i64 3, i64 3>
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP3]], align 8
; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP5]], align 8
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> poison, i64 [[TMP6]], i32 0
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i64> [[TMP8]], i64 [[TMP7]], i32 1
; CHECK-NEXT: [[TMP10:%.*]] = add nsw <2 x i64> [[TMP9]], <i64 42, i64 42>
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP11]], i32 0
; CHECK-NEXT: store <2 x i64> [[TMP10]], ptr [[TMP12]], align 8
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], <i64 2, i64 2>
; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000
; CHECK-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: middle.block:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1000, 1000
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[IV]], 3
; CHECK-NEXT: [[GEP_LD:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[DIV]]
; CHECK-NEXT: [[LD:%.*]] = load i64, ptr [[GEP_LD]], align 8
; CHECK-NEXT: [[CALC:%.*]] = add nsw i64 [[LD]], 42
; CHECK-NEXT: [[GEP_ST:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[IV]]
; CHECK-NEXT: store i64 [[CALC]], ptr [[GEP_ST]], align 8
; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[IV_NEXT]], 1000
; CHECK-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i64 [ 0, %entry ], [ %iv_next, %loop ]
%div = udiv i64 %iv, 3
%gep_ld = getelementptr inbounds i64, ptr %src, i64 %div
%ld = load i64, ptr %gep_ld, align 8
%calc = add nsw i64 %ld, 42
%gep_st = getelementptr inbounds i64, ptr %dst, i64 %iv
store i64 %calc, ptr %gep_st, align 8
%iv_next = add nsw i64 %iv, 1
%cond = icmp eq i64 %iv_next, 1000
br i1 %cond, label %exit, label %loop
exit:
ret void
}
; This is for division by 2 step 2
define void @ld_div2_step2(ptr noalias %src, ptr noalias %dst) {
; CHECK-LABEL: define void @ld_div2_step2
; CHECK-SAME: (ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 2
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 2
; CHECK-NEXT: [[TMP2:%.*]] = udiv i64 [[TMP0]], 2
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP3]], i32 0
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP4]], align 8
; CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i64> [[WIDE_LOAD]], <i64 42, i64 42>
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]]
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP1]]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP5]], i32 0
; CHECK-NEXT: store i64 [[TMP8]], ptr [[TMP6]], align 8
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP5]], i32 1
; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP7]], align 8
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 500
; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK: middle.block:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 500, 500
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[IV]], 2
; CHECK-NEXT: [[GEP_LD:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[DIV]]
; CHECK-NEXT: [[LD:%.*]] = load i64, ptr [[GEP_LD]], align 8
; CHECK-NEXT: [[CALC:%.*]] = add nsw i64 [[LD]], 42
; CHECK-NEXT: [[GEP_ST:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[IV]]
; CHECK-NEXT: store i64 [[CALC]], ptr [[GEP_ST]], align 8
; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 2
; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[IV_NEXT]], 1000
; CHECK-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i64 [ 0, %entry ], [ %iv_next, %loop ]
%div = udiv i64 %iv, 2
%gep_ld = getelementptr inbounds i64, ptr %src, i64 %div
%ld = load i64, ptr %gep_ld, align 8
%calc = add nsw i64 %ld, 42
%gep_st = getelementptr inbounds i64, ptr %dst, i64 %iv
store i64 %calc, ptr %gep_st, align 8
%iv_next = add nsw i64 %iv, 2
%cond = icmp eq i64 %iv_next, 1000
br i1 %cond, label %exit, label %loop
exit:
ret void
}
; Same as before but with a uniform store, divisor 2 and step 1.
define void @store_div2_step1(ptr noalias %src, ptr noalias %dst) {
; CHECK-LABEL: define void @store_div2_step1
; CHECK-SAME: (ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = udiv <2 x i64> [[VEC_IND]], <i64 2, i64 2>
; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i64> [[TMP0]], <i64 42, i64 42>
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP0]], i32 0
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP0]], i32 1
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
; CHECK-NEXT: store i64 [[TMP6]], ptr [[TMP3]], align 8
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
; CHECK-NEXT: store i64 [[TMP7]], ptr [[TMP5]], align 8
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], <i64 2, i64 2>
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000
; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK: middle.block:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1000, 1000
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[IV]], 2
; CHECK-NEXT: [[VAL:%.*]] = add nsw i64 [[DIV]], 42
; CHECK-NEXT: [[GEP_ST:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[DIV]]
; CHECK-NEXT: store i64 [[VAL]], ptr [[GEP_ST]], align 8
; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[IV_NEXT]], 1000
; CHECK-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i64 [ 0, %entry ], [ %iv_next, %loop ]
%div = udiv i64 %iv, 2
%val = add nsw i64 %div, 42
%gep_st = getelementptr inbounds i64, ptr %dst, i64 %div
store i64 %val, ptr %gep_st, align 8
%iv_next = add nsw i64 %iv, 1
%cond = icmp eq i64 %iv_next, 1000
br i1 %cond, label %exit, label %loop
exit:
ret void
}