[AArch64][SME] Fix LDR and STR asm parser

[CarolineConcatto]

Summary

The LDR and STR instructions must have the same value for imm4(second operand)
and offset(fourth operand).
The disassembly guarantees that happens, but the Asm parser was not checking that.
This patch fixes that by checking if the second operand and fourth operand are
immediate and have the same value.

[david-arm]

Nice fix @CarolineConcatto! Just one minor comment ...

llvm/test/MC/AArch64/SME/ldr-diagnostics.s

56

If it's not too much trouble, could you also add a similar test for str as well?

[CarolineConcatto]

• Add missing str test

[CarolineConcatto]

llvm/test/MC/AArch64/SME/ldr-diagnostics.s

56

Sorry, I totally missed that. Now it is done

[david-arm]

LGTM! Thanks @CarolineConcatto. :)

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

case AArch64::LDPXpre: {
     if (RI->isSubRegisterEq(Rn, Rt))
       return Error(Loc[0], "unpredictable LDP instruction, writeback base "
                            "is also a destination");
     if (RI->isSubRegisterEq(Rn, Rt2))
       return Error(Loc[1], "unpredictable LDP instruction, writeback base "
                            "is also a destination");
     [[fallthrough]];
   }
+  case AArch64::LDR_ZA:
+  case AArch64::STR_ZA: {
+    if (Inst.getOperand(2).isImm() && Inst.getOperand(4).isImm() &&
+        Inst.getOperand(2).getImm() != Inst.getOperand(4).getImm())
+      return Error(Loc[1],
+                   "unpredictable instruction, immediate and offset mismatch.");
+    break;
+  }
   case AArch64::LDPDi:
   case AArch64::LDPQi:
   case AArch64::LDPSi:
   case AArch64::LDPSWi:
   case AArch64::LDPWi:
   case AArch64::LDPXi: {
     unsigned Rt = Inst.getOperand(0).getReg();
     unsigned Rt2 = Inst.getOperand(1).getReg();

llvm/test/MC/AArch64/SME/ldr-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
 // CHECK-NEXT: ldr za[w12, #0], [x0, #16, mul vl]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldr za[w12, #0], [x0, #0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: ldr za[w12, #0], [x0, #0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Mismatch between offset and immediate
+ldr     za[w14, 6], [x10, #5, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, immediate and offset mismatch.
+// CHECK-NEXT: ldr     za[w14, 6], [x10, #5, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/str-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
 // CHECK-NEXT: str za[w12, #0], [x0, #16, mul vl]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 str za[w12, #0], [x0, #0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: str za[w12, #0], [x0, #0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Mismatch between offset and immediate
+str     za[w14, 6], [x10, #5, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, immediate and offset mismatch.
+// CHECK-NEXT: str     za[w14, 6], [x10, #5, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: