[M68k] Add subtarget features for M68881/2 FPU

[myhsu]

Summary

Note that technically both M68000/010 can use M68881, despite the fact that usually only M68020 and newer ISAs are equipped with M68881/2. M68040 and newer processors have builtin M68882.

[0x59616e]

llvm/lib/Target/M68k/M68k.td

47

nit: need a space to align with the current style.

[myhsu]

minor formatting.

llvm/lib/Target/M68k/M68k.td

: SubtargetFeature<"isa-68020", "SubtargetKind", "M20",
                      "Is M68020 ISA supported",
                      [ FeatureISA10 ]>;
 
 def FeatureISA30
   : SubtargetFeature<"isa-68030", "SubtargetKind", "M30",
                      "Is M68030 ISA supported",
                      [ FeatureISA20 ]>;
 
+def FeatureISA881
+  : SubtargetFeature<"isa-68881", "FPUKind", "M881",
+                     "Is M68881 (FPU) ISA supported">;
+
+def FeatureISA882
+  : SubtargetFeature<"isa-68882", "FPUKind", "M882",
+                     "Is M68882 (FPU) ISA supported",
+                     [ FeatureISA881 ]>;
+
 def FeatureISA40
   : SubtargetFeature<"isa-68040", "SubtargetKind", "M40",
                      "Is M68040 ISA supported",
-                     [ FeatureISA30 ]>;
+                     [ FeatureISA30, FeatureISA882 ]>;
 
 def FeatureISA60
   : SubtargetFeature<"isa-68060", "SubtargetKind", "M60",
                      "Is M68060 ISA supported",
                      [ FeatureISA40 ]>;
 
 foreach i = {0-6} in
   def FeatureReserveA#i :

llvm/lib/Target/M68k/M68kInstrInfo.td

 def IsPIC        : Predicate<"TM.isPositionIndependent()">;
 def IsNotPIC     : Predicate<"!TM.isPositionIndependent()">;
 
 // ISA versions
 foreach i = [0,1,2,4,6] in
 def AtLeastM680 # i # "0" : Predicate<"Subtarget->atLeastM680"#i#"0()">,
                             AssemblerPredicate<(all_of
                                                 !cast<SubtargetFeature>("FeatureISA"#i#"0"))>;
+def AtLeastM68881 : Predicate<"Subtarget->atLeastM68881()">,
+                    AssemblerPredicate<(all_of FeatureISA881)>;
+def AtLeastM68882 : Predicate<"Subtarget->atLeastM68882()">,
+                    AssemblerPredicate<(all_of FeatureISA882)>;
 
 //===----------------------------------------------------------------------===//
 // Condition Codes
 //
 // These MUST be kept in sync with codes enum in M68kInstrInfo.h
 //===----------------------------------------------------------------------===//
 
 def MxCONDt   : PatLeaf<(i8 0)>;  // True

llvm/lib/Target/M68k/M68kSubtarget.h

 
 protected:
   // These define which ISA is supported. Since each Motorola M68k ISA is
   // built on top of the previous one whenever an ISA is selected the previous
   // selected as well.
   enum SubtargetEnum { M00, M10, M20, M30, M40, M60 };
   SubtargetEnum SubtargetKind = M00;
 
+  enum FPKindEnum { M881, M882 };
+  std::optional<FPKindEnum> FPUKind;
+
   std::bitset<M68k::NUM_TARGET_REGS> UserReservedRegister;
 
   InstrItineraryData InstrItins;
 
   /// Small section is used.
   bool UseSmallSection = true;
 
   const M68kTargetMachine &TM;
public:
 
   bool atLeastM68000() const { return SubtargetKind >= M00; }
   bool atLeastM68010() const { return SubtargetKind >= M10; }
   bool atLeastM68020() const { return SubtargetKind >= M20; }
   bool atLeastM68030() const { return SubtargetKind >= M30; }
   bool atLeastM68040() const { return SubtargetKind >= M40; }
   bool atLeastM68060() const { return SubtargetKind >= M60; }
 
-  bool useSmallSection() const { return UseSmallSection; }
+  /// Floating point support
+  bool hasFPU() const { return FPUKind.has_value(); }
+  bool atLeastM68881() const { return hasFPU() && *FPUKind >= M881; }
+  bool atLeastM68882() const { return hasFPU() && *FPUKind >= M882; }
 
-  bool abiUsesSoftFloat() const;
+  bool useSmallSection() const { return UseSmallSection; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
 
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
 
   /// Return true if the subtarget allows calls to immediate address.
   bool isLegalToCallImmediateAddr() const;
 

llvm/lib/Target/M68k/M68kSubtarget.cpp

 }
 
 bool M68kSubtarget::isPositionIndependent() const {
   return TM.isPositionIndependent();
 }
 
 bool M68kSubtarget::isLegalToCallImmediateAddr() const { return true; }
 
-bool M68kSubtarget::abiUsesSoftFloat() const { return true; }
-
 M68kSubtarget &M68kSubtarget::initializeSubtargetDependencies(
     StringRef CPU, Triple TT, StringRef FS, const M68kTargetMachine &TM) {
   std::string CPUName = selectM68kCPU(TT, CPU).str();
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, CPUName, FS);
 
   // Initialize scheduling itinerary for the specified CPU.

llvm/test/CodeGen/M68k/m6888x-features.ll

+; RUN: llc -mtriple=m68k -mattr="+isa-68881" %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=m68k -mattr="+isa-68882" %s -o - 2>&1 | FileCheck %s
+
+define dso_local i32 @f() {
+entry:
+  ret i32 0
+}
+
+; Make sure that all of the features listed are recognized.
+; CHECK-NOT:    is not a recognized feature for this target