[LoongArch] Optimize multiplication with immediates

[benshi001]

Summary

Optimize 'x * c' to (ALSL x, (SLLI x, i0), i1) in which
c = (1 << i0) | (1 << i1).

[xen0n]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

3143

Do you mean Imm - 8 and Imm - 16 instead?

[benshi001]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

3143

Yes. Sorry for such a mistake. Has fixed.

[benshi001]

llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll

1158

This is not optimized due to the immiedate is used twice, by mul.w and mulh.w.

[xen0n]

llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll

1032–1035

Kind of interesting why this didn't get optimized into the same form as LA32, but there may be a deeper reason. I don't currently have time to look into this though.

[benshi001]

llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll

1032–1035

I will take a look later, however this is still a win, since total 4 instructions are reduced to 3 ones.

[benshi001]

llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll

1032–1035

Maybe we can accept current form, and I will submit another patch for this further optimization.

[xen0n]

llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll

1032–1035

Fine with me, thanks!

[SixWeining]

LGTM. Thanks.

[benshi001]

llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll

1032–1035

I have fixed that issue in https://reviews.llvm.org/D147423 .

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

bool LoongArchTargetLowering::decomposeMulByConstant(LLVMContext &Context,
   // TODO: Support vectors.
   if (!VT.isScalarInteger())
     return false;
 
   // Omit the optimization if the data size exceeds GRLen.
   if (VT.getSizeInBits() > Subtarget.getGRLen())
     return false;
 
-  // Break MUL into (SLLI + ADD/SUB) or ALSL.
   if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {
     const APInt &Imm = ConstNode->getAPIntValue();
+    // Break MUL into (SLLI + ADD/SUB) or ALSL.
     if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() ||
         (1 - Imm).isPowerOf2() || (-1 - Imm).isPowerOf2())
       return true;
+    // Break MUL into (ALSL x, (SLLI x, imm0), imm1).
+    if (ConstNode->hasOneUse() &&
+        ((Imm - 2).isPowerOf2() || (Imm - 4).isPowerOf2() ||
+         (Imm - 8).isPowerOf2() || (Imm - 16).isPowerOf2()))
+      return true;
   }
 
   return false;
 }
 
 bool LoongArchTargetLowering::isLegalAddressingMode(const DataLayout &DL,
                                                     const AddrMode &AM,
                                                     Type *Ty, unsigned AS,

llvm/test/CodeGen/LoongArch/alsl.ll

entry:
   %mul = mul nsw i8 %a, 3
   %add = add nsw i8 %b, %mul
   ret i8 %add
 }
 
 define i16 @mul_add_i16(i16 signext %a, i16 signext %b) nounwind {
 ; LA32-LABEL: mul_add_i16:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    ori $a2, $zero, 10
-; LA32-NEXT:    mul.w $a0, $a0, $a2
+; LA32-NEXT:    slli.w $a2, $a0, 3
+; LA32-NEXT:    alsl.w $a0, $a0, $a2, 1
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_add_i16:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    ori $a2, $zero, 10
-; LA64-NEXT:    mul.d $a0, $a0, $a2
+; LA64-NEXT:    slli.d $a2, $a0, 3
+; LA64-NEXT:    alsl.d $a0, $a0, $a2, 1
 ; LA64-NEXT:    add.d $a0, $a1, $a0
 ; LA64-NEXT:    ret
 entry:
   %mul = mul nsw i16 %a, 10
   %add = add nsw i16 %b, %mul
   ret i16 %add
 }
 
 define i32 @mul_add_i32(i32 signext %a, i32 signext %b) nounwind {
 ; LA32-LABEL: mul_add_i32:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    ori $a2, $zero, 12
-; LA32-NEXT:    mul.w $a0, $a0, $a2
+; LA32-NEXT:    slli.w $a2, $a0, 3
+; LA32-NEXT:    alsl.w $a0, $a0, $a2, 2
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_add_i32:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    ori $a2, $zero, 12
-; LA64-NEXT:    mul.d $a0, $a0, $a2
+; LA64-NEXT:    slli.d $a2, $a0, 3
+; LA64-NEXT:    alsl.d $a0, $a0, $a2, 2
 ; LA64-NEXT:    add.d $a0, $a1, $a0
 ; LA64-NEXT:    ret
 entry:
   %mul = mul nsw i32 %a, 12
   %add = add nsw i32 %b, %mul
   ret i32 %add
 }
 

llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll

 ; LA64-NEXT:    ret
   %b = mul i64 %a, 289
   ret i64 %b
 }
 
 define signext i32 @mul_i32_4098(i32 %a) {
 ; LA32-LABEL: mul_i32_4098:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    lu12i.w $a1, 1
-; LA32-NEXT:    ori $a1, $a1, 2
-; LA32-NEXT:    mul.w $a0, $a0, $a1
+; LA32-NEXT:    slli.w $a1, $a0, 12
+; LA32-NEXT:    alsl.w $a0, $a0, $a1, 1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i32_4098:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 1
-; LA64-NEXT:    ori $a1, $a1, 2
-; LA64-NEXT:    mul.d $a0, $a0, $a1
-; LA64-NEXT:    addi.w $a0, $a0, 0
+; LA64-NEXT:    slli.d $a1, $a0, 1
+; LA64-NEXT:    slli.d $a0, $a0, 12
+; LA64-NEXT:    add.w $a0, $a0, $a1
 ; LA64-NEXT:    ret
   %b = mul i32 %a, 4098
   ret i32 %b
 }
 
 define signext i32 @mul_i32_4100(i32 %a) {
 ; LA32-LABEL: mul_i32_4100:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    lu12i.w $a1, 1
-; LA32-NEXT:    ori $a1, $a1, 4
-; LA32-NEXT:    mul.w $a0, $a0, $a1
+; LA32-NEXT:    slli.w $a1, $a0, 12
+; LA32-NEXT:    alsl.w $a0, $a0, $a1, 2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i32_4100:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 1
-; LA64-NEXT:    ori $a1, $a1, 4
-; LA64-NEXT:    mul.d $a0, $a0, $a1
-; LA64-NEXT:    addi.w $a0, $a0, 0
+; LA64-NEXT:    slli.d $a1, $a0, 2
+; LA64-NEXT:    slli.d $a0, $a0, 12
+; LA64-NEXT:    add.w $a0, $a0, $a1
 ; LA64-NEXT:    ret
   %b = mul i32 %a, 4100
   ret i32 %b
 }
 
 define signext i32 @mul_i32_4104(i32 %a) {
 ; LA32-LABEL: mul_i32_4104:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    lu12i.w $a1, 1
-; LA32-NEXT:    ori $a1, $a1, 8
-; LA32-NEXT:    mul.w $a0, $a0, $a1
+; LA32-NEXT:    slli.w $a1, $a0, 12
+; LA32-NEXT:    alsl.w $a0, $a0, $a1, 3
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i32_4104:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 1
-; LA64-NEXT:    ori $a1, $a1, 8
-; LA64-NEXT:    mul.d $a0, $a0, $a1
-; LA64-NEXT:    addi.w $a0, $a0, 0
+; LA64-NEXT:    slli.d $a1, $a0, 3
+; LA64-NEXT:    slli.d $a0, $a0, 12
+; LA64-NEXT:    add.w $a0, $a0, $a1
 ; LA64-NEXT:    ret
   %b = mul i32 %a, 4104
   ret i32 %b
 }
 
 define signext i32 @mul_i32_4112(i32 %a) {
 ; LA32-LABEL: mul_i32_4112:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    lu12i.w $a1, 1
-; LA32-NEXT:    ori $a1, $a1, 16
-; LA32-NEXT:    mul.w $a0, $a0, $a1
+; LA32-NEXT:    slli.w $a1, $a0, 12
+; LA32-NEXT:    alsl.w $a0, $a0, $a1, 4
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i32_4112:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 1
-; LA64-NEXT:    ori $a1, $a1, 16
-; LA64-NEXT:    mul.d $a0, $a0, $a1
-; LA64-NEXT:    addi.w $a0, $a0, 0
+; LA64-NEXT:    slli.d $a1, $a0, 4
+; LA64-NEXT:    slli.d $a0, $a0, 12
+; LA64-NEXT:    add.w $a0, $a0, $a1
 ; LA64-NEXT:    ret
   %b = mul i32 %a, 4112
   ret i32 %b
 }
 
 define i64 @mul_i64_4098(i64 %a) {
 ; LA32-LABEL: mul_i64_4098:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, 1
 ; LA32-NEXT:    ori $a2, $a2, 2
 ; LA32-NEXT:    mul.w $a1, $a1, $a2
 ; LA32-NEXT:    mulh.wu $a3, $a0, $a2
 ; LA32-NEXT:    add.w $a1, $a3, $a1
 ; LA32-NEXT:    mul.w $a0, $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i64_4098:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 1
-; LA64-NEXT:    ori $a1, $a1, 2
-; LA64-NEXT:    mul.d $a0, $a0, $a1
+; LA64-NEXT:    slli.d $a1, $a0, 12
+; LA64-NEXT:    alsl.d $a0, $a0, $a1, 1
 ; LA64-NEXT:    ret
   %b = mul i64 %a, 4098
   ret i64 %b
 }
 
 define i64 @mul_i64_4100(i64 %a) {
 ; LA32-LABEL: mul_i64_4100:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, 1
 ; LA32-NEXT:    ori $a2, $a2, 4
 ; LA32-NEXT:    mul.w $a1, $a1, $a2
 ; LA32-NEXT:    mulh.wu $a3, $a0, $a2
 ; LA32-NEXT:    add.w $a1, $a3, $a1
 ; LA32-NEXT:    mul.w $a0, $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i64_4100:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 1
-; LA64-NEXT:    ori $a1, $a1, 4
-; LA64-NEXT:    mul.d $a0, $a0, $a1
+; LA64-NEXT:    slli.d $a1, $a0, 12
+; LA64-NEXT:    alsl.d $a0, $a0, $a1, 2
 ; LA64-NEXT:    ret
   %b = mul i64 %a, 4100
   ret i64 %b
 }
 
 define i64 @mul_i64_4104(i64 %a) {
 ; LA32-LABEL: mul_i64_4104:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, 1
 ; LA32-NEXT:    ori $a2, $a2, 8
 ; LA32-NEXT:    mul.w $a1, $a1, $a2
 ; LA32-NEXT:    mulh.wu $a3, $a0, $a2
 ; LA32-NEXT:    add.w $a1, $a3, $a1
 ; LA32-NEXT:    mul.w $a0, $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i64_4104:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 1
-; LA64-NEXT:    ori $a1, $a1, 8
-; LA64-NEXT:    mul.d $a0, $a0, $a1
+; LA64-NEXT:    slli.d $a1, $a0, 12
+; LA64-NEXT:    alsl.d $a0, $a0, $a1, 3
 ; LA64-NEXT:    ret
   %b = mul i64 %a, 4104
   ret i64 %b
 }
 
 define i64 @mul_i64_4112(i64 %a) {
 ; LA32-LABEL: mul_i64_4112:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, 1
 ; LA32-NEXT:    ori $a2, $a2, 16
 ; LA32-NEXT:    mul.w $a1, $a1, $a2
 ; LA32-NEXT:    mulh.wu $a3, $a0, $a2
 ; LA32-NEXT:    add.w $a1, $a3, $a1
 ; LA32-NEXT:    mul.w $a0, $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i64_4112:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 1
-; LA64-NEXT:    ori $a1, $a1, 16
-; LA64-NEXT:    mul.d $a0, $a0, $a1
+; LA64-NEXT:    slli.d $a1, $a0, 12
+; LA64-NEXT:    alsl.d $a0, $a0, $a1, 4
 ; LA64-NEXT:    ret
   %b = mul i64 %a, 4112
   ret i64 %b
 }