[AMDGPU][GFX940] Simplify definitions of GLOBAL_ATOMIC

[mariusz-sikora-at-amd]

Summary

This change aims to remove unnecessary SubtargetPredicate override
for Flat_Global_Atomics for gfx940.

In current implementation we override SubtargetPredicate twice.
First time when creating definition for Pseudo Instruction in which
SubtargetPredicate is changed to 'isGFX90APlus' and later when
creating Real instruction SubtargetPredicate is changed to 'isGFX940Plus'.
This should not be needed because multiclass 'FLAT_Global_Atomic_Pseudo'
sets up SubtargetPredicate to 'HasFlatGlobalInsts' and all ASICs Generations
should add this feature if they support it.

Additionaly FLAT_Global_Real_Atomics_gfx940 sets up AssemblerPredicate to
'isGFX940Plus' which later is added to final list of all Predicates
for Real instructions in 'list<Predicate> Predicates'

[foad]

llvm/lib/Target/AMDGPU/FLATInstructions.td

725–728

Can you also remove the predicate for these FLAT Reals? Or is there some reason why that would not work?

[rampitec]

llvm/lib/Target/AMDGPU/FLATInstructions.td

730

I do not understand this. These were only added in gfx90a.

[mariusz-sikora-at-amd]

llvm/lib/Target/AMDGPU/FLATInstructions.td

730

This patch is only removing 'complexity' from gfx940. For gfx90A we still have Real Instruction under SubtargetPredicate = IsGFX90APlus.
I will add test for gfx908.

[mariusz-sikora-at-amd]

Add tests for gfx908 with unsupported instructions.

[rampitec]

llvm/lib/Target/AMDGPU/FLATInstructions.td

730

This patch is only removing 'complexity' from gfx940. For gfx90A we still have Real Instruction under SubtargetPredicate = IsGFX90APlus.
I will add test for gfx908.

But isn't pseudo still need a predicate too, not just real instruction?

llvm/lib/Target/AMDGPU/FLATInstructions.td

defm FLAT_ATOMIC_FMIN_X2     : FLAT_Atomic_Pseudo <"flat_atomic_fmin_x2",
                                 VReg_64, f64>;
 
 defm FLAT_ATOMIC_FMAX_X2     : FLAT_Atomic_Pseudo <"flat_atomic_fmax_x2",
                                 VReg_64, f64>;
 
 } // End SubtargetPredicate = isGFX7GFX10
 
 let SubtargetPredicate = isGFX90APlus in {
   defm FLAT_ATOMIC_ADD_F64   : FLAT_Atomic_Pseudo<"flat_atomic_add_f64", VReg_64, f64>;
   defm FLAT_ATOMIC_MIN_F64   : FLAT_Atomic_Pseudo<"flat_atomic_min_f64", VReg_64, f64>;
   defm FLAT_ATOMIC_MAX_F64   : FLAT_Atomic_Pseudo<"flat_atomic_max_f64", VReg_64, f64>;
-  defm GLOBAL_ATOMIC_ADD_F64 : FLAT_Global_Atomic_Pseudo<"global_atomic_add_f64", VReg_64, f64>;
-  defm GLOBAL_ATOMIC_MIN_F64 : FLAT_Global_Atomic_Pseudo<"global_atomic_min_f64", VReg_64, f64>;
-  defm GLOBAL_ATOMIC_MAX_F64 : FLAT_Global_Atomic_Pseudo<"global_atomic_max_f64", VReg_64, f64>;
-} // End SubtargetPredicate = isGFX90APlus
+} // End SubtargetPredicate = isGFX90APlus
+
 
 let SubtargetPredicate = HasAtomicFlatPkAdd16Insts in {
   defm FLAT_ATOMIC_PK_ADD_F16    : FLAT_Atomic_Pseudo<"flat_atomic_pk_add_f16",  VGPR_32, v2f16>;
   let FPAtomic = 1 in
     defm FLAT_ATOMIC_PK_ADD_BF16   : FLAT_Atomic_Pseudo<"flat_atomic_pk_add_bf16", VGPR_32, v2i16>;
 } // End SubtargetPredicate = HasAtomicFlatPkAdd16Insts
 
 let SubtargetPredicate = HasAtomicGlobalPkAddBF16Inst, FPAtomic = 1 in

 
 multiclass FLAT_Global_Real_Atomics_gfx940<bits<7> op> :
   FLAT_Real_AllAddr_gfx940<op> {
   def _RTN_gfx940       : FLAT_Real_gfx940 <op, !cast<FLAT_Pseudo>(NAME#"_RTN")>;
   def _SADDR_RTN_gfx940 : FLAT_Real_gfx940 <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN")>;
 }
 
 let SubtargetPredicate = isGFX940Plus in {
-  // These instructions are encoded differently on gfx90* and gfx940.
-  defm GLOBAL_ATOMIC_ADD_F32     : FLAT_Global_Real_Atomics_gfx940 <0x04d>;
-  defm GLOBAL_ATOMIC_PK_ADD_F16  : FLAT_Global_Real_Atomics_gfx940 <0x04e>;
 
   defm FLAT_ATOMIC_ADD_F64       : FLAT_Real_Atomics_gfx940<0x4f, FLAT_ATOMIC_ADD_F64>;
   defm FLAT_ATOMIC_MIN_F64       : FLAT_Real_Atomics_gfx940<0x50, FLAT_ATOMIC_MIN_F64>;
   defm FLAT_ATOMIC_MAX_F64       : FLAT_Real_Atomics_gfx940<0x51, FLAT_ATOMIC_MAX_F64>;
-  defm GLOBAL_ATOMIC_ADD_F64     : FLAT_Global_Real_Atomics_gfx940<0x4f>;
-  defm GLOBAL_ATOMIC_MIN_F64     : FLAT_Global_Real_Atomics_gfx940<0x50>;
-  defm GLOBAL_ATOMIC_MAX_F64     : FLAT_Global_Real_Atomics_gfx940<0x51>;
   defm FLAT_ATOMIC_ADD_F32       : FLAT_Real_Atomics_vi<0x4d, FLAT_ATOMIC_ADD_F32>;
   defm FLAT_ATOMIC_PK_ADD_F16    : FLAT_Real_Atomics_vi<0x4e, FLAT_ATOMIC_PK_ADD_F16>;
   defm FLAT_ATOMIC_PK_ADD_BF16   : FLAT_Real_Atomics_vi<0x52, FLAT_ATOMIC_PK_ADD_BF16>;
   defm GLOBAL_ATOMIC_PK_ADD_BF16 : FLAT_Global_Real_Atomics_vi<0x52>;
 } // End SubtargetPredicate = isGFX940Plus
 
+// These instructions are encoded differently on gfx90* and gfx940.
+defm GLOBAL_ATOMIC_ADD_F32     : FLAT_Global_Real_Atomics_gfx940<0x04d>;
+defm GLOBAL_ATOMIC_PK_ADD_F16  : FLAT_Global_Real_Atomics_gfx940<0x04e>;
+
+defm GLOBAL_ATOMIC_ADD_F64     : FLAT_Global_Real_Atomics_gfx940<0x4f>;
+defm GLOBAL_ATOMIC_MIN_F64     : FLAT_Global_Real_Atomics_gfx940<0x50>;
+defm GLOBAL_ATOMIC_MAX_F64     : FLAT_Global_Real_Atomics_gfx940<0x51>;
+
 //===----------------------------------------------------------------------===//
 // GFX10.
 //===----------------------------------------------------------------------===//
 
 class FLAT_Real_gfx10<bits<7> op, FLAT_Pseudo ps> :
     FLAT_Real<op, ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX10> {
   let AssemblerPredicate = isGFX10Only;
   let DecoderNamespace = "GFX10";

llvm/test/MC/AMDGPU/gfx908_unsupported.s

+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+
+global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off glc
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+global_atomic_min_f64 v[0:1], v[0:1], v[2:3], off glc
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+global_atomic_max_f64 v[0:1], v[0:1], v[2:3], off glc
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU