[M68k] Enable returning pointer in address register.

[0x59616e]

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[0x59616e]

update diff

[0x59616e]

I was confused with the absence of some of my fix in the test after rebasing to master. It turns out that this has been done by Min.

llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp

bool M68kCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                    Register SwiftErrorVReg) const {
 
   auto MIB = MIRBuilder.buildInstrNoInsert(M68k::RTS);
   bool Success = true;
   MachineFunction &MF = MIRBuilder.getMF();
   const Function &F = MF.getFunction();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const M68kTargetLowering &TLI = *getTLI<M68kTargetLowering>();
-  CCAssignFn *AssignFn =
-      TLI.getCCAssignFn(F.getCallingConv(), true, F.isVarArg());
+  CCAssignFn *AssignFn = TLI.getCCAssignFn(F.getCallingConv(), true,
+                                           F.isVarArg(), F.getReturnType());
   auto &DL = F.getParent()->getDataLayout();
   if (!VRegs.empty()) {
     SmallVector<ArgInfo, 8> SplitArgs;
     ArgInfo OrigArg{VRegs, Val->getType(), 0};
     setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
     splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
     OutgoingValueAssigner ArgAssigner(AssignFn);
     M68kOutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB);
bool M68kCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
   unsigned I = 0;
   for (const auto &Arg : F.args()) {
     ArgInfo OrigArg{VRegs[I], Arg.getType(), I};
     setArgFlags(OrigArg, I + AttributeList::FirstArgIndex, DL, F);
     splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
     ++I;
   }
 
-  CCAssignFn *AssignFn =
-      TLI.getCCAssignFn(F.getCallingConv(), false, F.isVarArg());
+  CCAssignFn *AssignFn = TLI.getCCAssignFn(F.getCallingConv(), false,
+                                           F.isVarArg(), F.getReturnType());
   IncomingValueAssigner ArgAssigner(AssignFn);
   FormalArgHandler ArgHandler(MIRBuilder, MRI);
   return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
                                        MIRBuilder, F.getCallingConv(),
                                        F.isVarArg());
 }
 
 void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
bool M68kCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
   unsigned Opc = TLI.getTargetMachine().isPositionIndependent() ? M68k::CALLq
                  : Info.Callee.isReg()                          ? M68k::CALLj
                                                                 : M68k::CALLb;
 
   auto MIB = MIRBuilder.buildInstrNoInsert(Opc)
                  .add(Info.Callee)
                  .addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
 
-  CCAssignFn *AssignFn = TLI.getCCAssignFn(Info.CallConv, false, Info.IsVarArg);
+  CCAssignFn *AssignFn =
+      TLI.getCCAssignFn(Info.CallConv, false, Info.IsVarArg, nullptr);
   OutgoingValueAssigner Assigner(AssignFn);
   M68kOutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
   if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
                                      Info.CallConv, Info.IsVarArg))
     return false;
 
   if (Info.Callee.isReg())
     constrainOperandRegClass(MF, *TRI, MRI, *STI.getInstrInfo(),
                              *STI.getRegBankInfo(), *MIB, MIB->getDesc(),
                              Info.Callee, 0);
 
   MIRBuilder.insertInstr(MIB);
 
   if (!Info.OrigRet.Ty->isVoidTy()) {
     CCAssignFn *RetAssignFn =
-        TLI.getCCAssignFn(Info.CallConv, true, Info.IsVarArg);
+        TLI.getCCAssignFn(Info.CallConv, true, Info.IsVarArg, Info.OrigRet.Ty);
 
     OutgoingValueAssigner Assigner(RetAssignFn, RetAssignFn);
     CallReturnHandler Handler(MIRBuilder, MRI, MIB);
     if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
                                        Info.CallConv, Info.IsVarArg))
       return false;
   }
 

llvm/lib/Target/M68k/M68kCallingConv.td

 def RetCC_M68k_C : CallingConv<[
   CCIfPtr<CCAssignToReg<[A0]>>,
   CCIfType<[i1],   CCPromoteToType<i8>>,
   CCIfType<[i8],   CCAssignToReg<[BD0, BD1]>>,
   CCIfType<[i16],  CCAssignToReg<[WD0, WD1]>>,
   CCIfType<[i32],  CCAssignToReg<[D0, D1]>>,
 ]>;
 
+def RetCC_M68k_C_PTRRET : CallingConv<[
+  CCIfType<[i32], CCAssignToReg<[A0]>>,
+  CCDelegateTo<RetCC_M68kCommon>
+]>;
+
 /// M68k fastcc return convention.
 /// This convention allows to return up to 16 bytes in registers which can be
 /// split among 16 1-byte values or used for a single 16-byte value.
 /// TODO: Verify its functionality and write tests
 def RetCC_M68k_Fast : CallingConv<[
   CCIfPtr<CCAssignToReg<[A0]>>,
   CCIfType<[i1],   CCPromoteToType<i8>>,
   CCIfType<[i8],   CCAssignToReg<[BD0, BD1]>>,

llvm/lib/Target/M68k/M68kISelLowering.h

public:
   void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                     std::vector<SDValue> &Ops,
                                     SelectionDAG &DAG) const override;
 
   MachineBasicBlock *
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *MBB) const override;
 
-  CCAssignFn *getCCAssignFn(CallingConv::ID CC, bool Return,
-                            bool IsVarArg) const;
+  CCAssignFn *getCCAssignFn(CallingConv::ID CC, bool IsReturn, bool IsVarArg,
+                            Type *ReturnType) const;
 
   AtomicExpansionKind
   shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const override;
 
   /// If a physical register, this returns the register that receives the
   /// exception address on entry to an EH pad.
   Register
   getExceptionPointerRegister(const Constant *PersonalityFn) const override;
private:
   SDValue LowerGlobalAddress(const GlobalValue *GV, const SDLoc &DL,
                              int64_t Offset, SelectionDAG &DAG) const;
   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
 
-  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
+  SDValue LowerCallResult(CallLoweringInfo &CLI, SDValue Chain, SDValue InFlag,
                           CallingConv::ID CallConv, bool IsVarArg,
                           const SmallVectorImpl<ISD::InputArg> &Ins,
                           const SDLoc &DL, SelectionDAG &DAG,
                           SmallVectorImpl<SDValue> &InVals) const;
 
   /// LowerFormalArguments - transform physical registers into virtual
   /// registers and generate load operations for arguments places on the stack.
   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CCID,

llvm/lib/Target/M68k/M68kISelLowering.cpp

SDValue M68kTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
   if (!IsSibcall) {
     Chain = DAG.getCALLSEQ_END(Chain, NumBytesToPop, NumBytesForCalleeToPop,
                                InFlag, DL);
     InFlag = Chain.getValue(1);
   }
 
   // Handle result values, copying them out of physregs into vregs that we
   // return.
-  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
+  return LowerCallResult(CLI, Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
                          InVals);
 }
 
 SDValue M68kTargetLowering::LowerCallResult(
-    SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
+    CallLoweringInfo &CLI, SDValue Chain, SDValue InFlag,
+    CallingConv::ID CallConv, bool IsVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 
+  MachineFunction &MF = DAG.getMachineFunction();
   // Assign locations to each value returned by this call.
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
                  *DAG.getContext());
-  CCInfo.AnalyzeCallResult(Ins, RetCC_M68k);
+
+  CCInfo.AnalyzeCallResult(
+      Ins, getCCAssignFn(CallConv, /*IsReturn=*/true, IsVarArg, CLI.RetTy));
 
   // Copy all of the result registers out of their specified physreg.
   for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
     CCValAssign &VA = RVLocs[i];
     EVT CopyVT = VA.getLocVT();
 
     /// ??? is this correct?
     Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), CopyVT, InFlag)
M68kTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CCID,
                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
                                 const SmallVectorImpl<SDValue> &OutVals,
                                 const SDLoc &DL, SelectionDAG &DAG) const {
   MachineFunction &MF = DAG.getMachineFunction();
   M68kMachineFunctionInfo *MFI = MF.getInfo<M68kMachineFunctionInfo>();
 
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CCID, IsVarArg, MF, RVLocs, *DAG.getContext());
-  CCInfo.AnalyzeReturn(Outs, RetCC_M68k);
+
+  CCInfo.AnalyzeReturn(Outs, getCCAssignFn(CCID, /*IsReturn=*/true, IsVarArg,
+                                           MF.getFunction().getReturnType()));
 
   SDValue Flag;
   SmallVector<SDValue, 6> RetOps;
   // Operand #0 = Chain (updated below)
   RetOps.push_back(Chain);
   // Operand #1 = Bytes To Pop
   RetOps.push_back(
       DAG.getTargetConstant(MFI->getBytesToPopOnReturn(), DL, MVT::i32));
case M68kISD::WrapperPC:
     return "M68kISD::WrapperPC";
   case M68kISD::SEG_ALLOCA:
     return "M68kISD::SEG_ALLOCA";
   default:
     return NULL;
   }
 }
 
-CCAssignFn *M68kTargetLowering::getCCAssignFn(CallingConv::ID CC, bool Return,
-                                              bool IsVarArg) const {
-  if (Return)
-    return RetCC_M68k_C;
-  else
-    return CC_M68k_C;
+CCAssignFn *M68kTargetLowering::getCCAssignFn(CallingConv::ID CC, bool IsReturn,
+                                              bool IsVarArg,
+                                              Type *ReturnType) const {
+  if (IsReturn)
+    return isa<PointerType>(ReturnType) ? RetCC_M68k_C_PTRRET : RetCC_M68k_C;
+
 }

llvm/test/CodeGen/M68k/CConv/ret-addr-reg.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k -o - %s | FileCheck %s
+
+
+define ptr @get_addr() {
+; CHECK-LABEL: get_addr:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0:
+; CHECK-NEXT:    move.l #0, %a0
+; CHECK-NEXT:    rts
+  ret ptr null
+}
+
+define i32 @foo() {
+; CHECK-LABEL: foo:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0:
+; CHECK-NEXT:    suba.l #4, %sp
+; CHECK-NEXT:    .cfi_def_cfa_offset -8
+; CHECK-NEXT:    jsr get_addr@PLT
+; CHECK-NEXT:    move.l (%a0), %d0
+; CHECK-NEXT:    adda.l #4, %sp
+; CHECK-NEXT:    rts
+  %call = call ptr @get_addr()
+  %1 = load i32, ptr %call, align 4
+  ret i32 %1
+}