[libc] Implement memory fences on NVPTX

[jhuber6]

Summary

Memory fences are not handled by the NVPTX backend. We need to replace
them with a memory barrier intrinsic function. This doesn't include the
ordering, but should perform the necessary functionality, albeit slower.

[tianshilei1992]

Does it have to be sys? Does gl (kernel level) work?

[jhuber6]

In D146725#4216704, @tianshilei1992 wrote:

Does it have to be sys? Does gl (kernel level) work?

It should be sys as far as I understand because this is intended to be used on the Nvidia USM to implement RPC. Also I believe __atomic_thread_fence defaults to system scope on AMDPGU as well.

[tianshilei1992]

In D146725#4216706, @jhuber6 wrote:

In D146725#4216704, @tianshilei1992 wrote:

Does it have to be sys? Does gl (kernel level) work?

It should be sys as far as I understand because this is intended to be used on the Nvidia USM to implement RPC. Also I believe __atomic_thread_fence defaults to system scope on AMDPGU as well.

Oh I see. That's for shared memory. LG.

libc/src/__support/CPP/atomic.h

 //===-- A simple equivalent of std::atomic ----------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIBC_SRC_SUPPORT_CPP_ATOMIC_H
 #define LLVM_LIBC_SRC_SUPPORT_CPP_ATOMIC_H
 
 #include "src/__support/macros/attributes.h"
+#include "src/__support/macros/properties/architectures.h"
 
 #include "type_traits.h"
 
 namespace __llvm_libc {
 namespace cpp {
 
 enum class MemoryOrder : int {
   RELAXED = __ATOMIC_RELAXED,
public:
 
   // Set the value without using an atomic operation. This is useful
   // in initializing atomic values without a constructor.
   void set(T rhs) { val = rhs; }
 };
 
 // Issue a thread fence with the given memory ordering.
 LIBC_INLINE void atomic_thread_fence(MemoryOrder mem_ord) {
+// The NVPTX backend currently does not support atomic thread fences so we use a
+// full system fence instead.
+#ifdef LIBC_TARGET_ARCH_IS_NVPTX
+  (void)mem_ord;
+  __nvvm_membar_sys();
+#else
   __atomic_thread_fence(int(mem_ord));
+#endif
 }
 
 } // namespace cpp
 } // namespace __llvm_libc
 
 #endif // LLVM_LIBC_SRC_SUPPORT_CPP_ATOMIC_H