Mark widenable condition as noundef

[mkazantsev]

Summary

This corresponds to its description in LangRef:
The intrinsic @llvm.experimental.widenable.condition() returns either true or false.

[skatkov]

Look pretty straightforward to Lang Ref.

[nikic]

LGTM

llvm/include/llvm/IR/Intrinsics.td

def int_experimental_deoptimize : Intrinsic<[llvm_any_ty], [llvm_vararg_ty],
                                             [Throws]>;
 
 // Support for speculative runtime guards
 def int_experimental_guard : DefaultAttrsIntrinsic<[], [llvm_i1_ty, llvm_vararg_ty],
                                        [Throws]>;
 
 // Supports widenable conditions for guards represented as explicit branches.
 def int_experimental_widenable_condition : DefaultAttrsIntrinsic<[llvm_i1_ty], [],
-        [IntrInaccessibleMemOnly, IntrWillReturn, IntrSpeculatable]>;
+        [IntrInaccessibleMemOnly, IntrWillReturn, IntrSpeculatable, NoUndef<RetIndex>]>;
 
 // NOP: calls/invokes to this intrinsic are removed by codegen
 def int_donothing : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrWillReturn]>;
 
 // This instruction has no actual effect, though it is treated by the optimizer
 // has having opaque side effects. This may be inserted into loops to ensure
 // that they are not removed even if they turn out to be empty, for languages
 // which specify that infinite loops must be preserved.

llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll

;
   %call = call <vscale x 2 x i32> @llvm.sshl.sat.nxv2i32(<vscale x 2 x i32> %arg0, <vscale x 2 x i32> zeroinitializer)
   %freeze = freeze <vscale x 2 x i32> %call
   ret <vscale x 2 x i32> %freeze
 }
 
 define i1 @widenable_condition() {
 ; CHECK-LABEL: @widenable_condition(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[FREEZE:%.*]] = freeze i1 [[WC]]
-; CHECK-NEXT:    ret i1 [[FREEZE]]
+; CHECK-NEXT:    ret i1 [[WC]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %freeze = freeze i1 %wc
   ret i1 %freeze
 }
 
 declare i32 @llvm.ctlz.i32(i32, i1 immarg)
 declare i32 @llvm.cttz.i32(i32, i1 immarg)

llvm/test/Transforms/InstCombine/widenable-conditions.ll

;
   %lhs = and i1 %b, %wc
   %and = and i1 %lhs, %a
   ret i1 %and
 }
 
 define i1 @test1_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test1_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[B:%.*]], i1 [[WC]], i1 false
+; CHECK-NEXT:    [[LHS:%.*]] = and i1 [[WC]], [[B:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[A:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %lhs = select i1 %b, i1 %wc, i1 false
   %and = select i1 %lhs, i1 %a, i1 false
   ret i1 %and
 }
;
   call void @use(i1 %lhs)
   %and = and i1 %lhs, %a
   ret i1 %and
 }
 
 define i1 @test1b_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test1b_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[B:%.*]], i1 [[WC]], i1 false
+; CHECK-NEXT:    [[LHS:%.*]] = and i1 [[WC]], [[B:%.*]]
 ; CHECK-NEXT:    call void @use(i1 [[LHS]])
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[A:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %lhs = select i1 %b, i1 %wc, i1 false
   call void @use(i1 %lhs)
   %and = select i1 %lhs, i1 %a, i1 false

 }
 
 define i1 @test1c_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test1c_logical(
 ; CHECK-NEXT:    call void @use(i1 [[A:%.*]])
 ; CHECK-NEXT:    call void @use(i1 [[B:%.*]])
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    call void @use(i1 [[WC]])
-; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[B]], i1 [[WC]], i1 false
+; CHECK-NEXT:    [[LHS:%.*]] = and i1 [[WC]], [[B]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[A]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   call void @use(i1 %a)
   call void @use(i1 %b)
   %wc = call i1 @llvm.experimental.widenable.condition()
   call void @use(i1 %wc)
   %lhs = select i1 %b, i1 %wc, i1 false
;
   %and = and i1 %lhs, %rhs
   ret i1 %and
 }
 
 define i1 @test3_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @test3_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[LHS]], i1 [[C:%.*]], i1 false
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i1 [[WC]], i1 false
+; CHECK-NEXT:    [[RHS:%.*]] = and i1 [[WC]], [[C:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[RHS]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %lhs = select i1 %a, i1 %b, i1 false
   %rhs = select i1 %c, i1 %wc, i1 false
   %and = select i1 %lhs, i1 %rhs, i1 false
   ret i1 %and
 }
;
   %and = and i1 %lhs, %rhs
   ret i1 %and
 }
 
 define i1 @test4_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @test4_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[LHS]], i1 [[WC]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[LHS]], [[WC]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i1 [[C:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %lhs = select i1 %a, i1 %b, i1 false
   %rhs = select i1 %wc, i1 %c, i1 false
   %and = select i1 %lhs, i1 %rhs, i1 false
   ret i1 %and
;
   %and = and i1 %wc, %wc2
   ret i1 %and
 }
 
 define i1 @test6_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test6_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    [[WC2:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[WC]], i1 [[WC2]], i1 false
+; CHECK-NEXT:    [[AND:%.*]] = and i1 [[WC]], [[WC2]]
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %wc2 = call i1 @llvm.experimental.widenable.condition()
   %and = select i1 %wc, i1 %wc2, i1 false
   ret i1 %and
 }
 
;
   ret i1 %and
 }
 
 define i1 @test7_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test7_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    call void @use(i1 [[WC]])
 ; CHECK-NEXT:    [[WC2:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[WC]], i1 [[WC2]], i1 false
+; CHECK-NEXT:    [[AND:%.*]] = and i1 [[WC]], [[WC2]]
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   call void @use(i1 %wc)
   %wc2 = call i1 @llvm.experimental.widenable.condition()
   %and = select i1 %wc, i1 %wc2, i1 false
   ret i1 %and
 }
;
   ret i1 %and
 }
 
 define i1 @test8_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test8_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    [[WC2:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    call void @use(i1 [[WC2]])
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[WC]], i1 [[WC2]], i1 false
+; CHECK-NEXT:    [[AND:%.*]] = and i1 [[WC]], [[WC2]]
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %wc2 = call i1 @llvm.experimental.widenable.condition()
   call void @use(i1 %wc2)
   %and = select i1 %wc, i1 %wc2, i1 false
   ret i1 %and
 }
 
 
 declare void @use(i1)
 declare i1 @llvm.experimental.widenable.condition()

llvm/test/Transforms/SimpleLoopUnswitch/pr60736.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simple-loop-unswitch-inject-invariant-conditions=true -passes='loop(simple-loop-unswitch<nontrivial>,loop-instsimplify)' -S | FileCheck %s
 
 define void @test() {
 ; CHECK-LABEL: @test(
 ; CHECK-NEXT:  bb:
 ; CHECK-NEXT:    [[TMP:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    [[TMP1:%.*]] = load atomic i32, ptr addrspace(1) poison unordered, align 8
 ; CHECK-NEXT:    [[TMP2:%.*]] = load atomic i32, ptr addrspace(1) poison unordered, align 8
+; CHECK-NEXT:    br i1 [[TMP]], label [[BB_SPLIT:%.*]], label [[BB3_SPLIT_US:%.*]]
+; CHECK:       bb.split:
 ; CHECK-NEXT:    br label [[BB3:%.*]]
 ; CHECK:       bb3:
-; CHECK-NEXT:    [[TMP_FR:%.*]] = freeze i1 [[TMP]]
-; CHECK-NEXT:    br i1 [[TMP_FR]], label [[BB3_SPLIT:%.*]], label [[BB3_SPLIT_US:%.*]]
+; CHECK-NEXT:    br label [[BB3_SPLIT:%.*]]
 ; CHECK:       bb3.split.us:
 ; CHECK-NEXT:    br label [[BB4_US:%.*]]
 ; CHECK:       bb4.us:
 ; CHECK-NEXT:    [[TMP5_US:%.*]] = phi i32 [ poison, [[BB3_SPLIT_US]] ]
 ; CHECK-NEXT:    [[TMP6_US:%.*]] = phi i32 [ poison, [[BB3_SPLIT_US]] ]
 ; CHECK-NEXT:    [[TMP7_US:%.*]] = add nuw nsw i32 [[TMP6_US]], 2
 ; CHECK-NEXT:    [[TMP8_US:%.*]] = icmp ult i32 [[TMP7_US]], [[TMP2]]
 ; CHECK-NEXT:    br i1 [[TMP8_US]], label [[BB9_US:%.*]], label [[BB16_SPLIT_US:%.*]], !prof [[PROF0:![0-9]+]]