[RISCV] Make Zfh PseudoQuietFCMP definitions predicated on HasStdExtZfh

[asb]

Summary

These were previously in a Predicates = [HasStdExtZfhOrZfhmin] block, but Zfhmin has no fcmp instructions so the definition makes no sense for Zfhmin.

@craig.topper pretty sure this is just a merging / copy and paste issue based on similar logic on F and D, but thought I'd quickly double check I've not missed something here.

[craig.topper]

LGTM. I guess maybe I focused on the FLH/FSH and didn't notice the block needed to be split.

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

 def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>;
 
 // fgt.h/fge.h are recognised by the GNU assembler but the canonical
 // flt.h/fle.h forms will always be printed. Therefore, set a zero weight.
 def : InstAlias<"fgt.h $rd, $rs, $rt",
                 (FLT_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 def : InstAlias<"fge.h $rd, $rs, $rt",
                 (FLE_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
-} // Predicates = [HasStdExtZfh]
 
-let Predicates = [HasStdExtZfhOrZfhmin] in {
-def PseudoFLH  : PseudoFloatLoad<"flh", FPR16>;
-def PseudoFSH  : PseudoStore<"fsh", FPR16>;
 let usesCustomInserter = 1 in {
 def PseudoQuietFLE_H : PseudoQuietFCMP<FPR16>;
 def PseudoQuietFLT_H : PseudoQuietFCMP<FPR16>;
 }
+} // Predicates = [HasStdExtZfh]
+
+let Predicates = [HasStdExtZfhOrZfhmin] in {
+def PseudoFLH  : PseudoFloatLoad<"flh", FPR16>;
+def PseudoFSH  : PseudoStore<"fsh", FPR16>;
 } // Predicates = [HasStdExtZfhOrZfhmin]
 
 let Predicates = [HasStdExtZhinx] in {
 def : InstAlias<"fmv.h $rd, $rs",  (FSGNJ_H_INX  FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;
 def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;
 def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;
 
 def : InstAlias<"fgt.h $rd, $rs, $rt",