[AMDGPU] Avoid constant bus limitation on V_BFE GISel pattern

[Pierre-vh]

Summary

For D141247 - if that pattern was used by GISel it could cause constant bus limitation failures.
Just use inline immediates instead of S_MOV to avoid the issue.

[arsenm]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir

170

Can you also add and end to end test that shows the same issue

[Pierre-vh]

comment

[Pierre-vh]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir

170

I think those get folded out later because out of all the tests affected by the constant bus limit assert, none had any regression other than the MIR tests (because they just run ISel)

[build] Failed Tests (6):
[build]   LLVM :: CodeGen/AMDGPU/GlobalISel/bswap.ll
[build]   LLVM :: CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
[build]   LLVM :: CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
[build]   LLVM :: CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
[build]   LLVM :: CodeGen/AMDGPU/GlobalISel/mul.ll
[build]   LLVM :: CodeGen/AMDGPU/mad-mix-hi.ll

I still added a small test case to show it's indeed folded out, but that one wasn't affected by the constant bus violation so not sure if it's that useful

[Pierre-vh]

Move test to GISel folder

[arsenm]

llvm/lib/Target/AMDGPU/VOP3Instructions.td

266

These are both inline immediate so you could just directly put the immediate in the output operands

[Pierre-vh]

Use inline imm

llvm/lib/Target/AMDGPU/VOP3Instructions.td

let SchedRW = [Write64Bit] in {
   defm V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, clshr_rev_64>;
   defm V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, cashr_rev_64>;
   } // End SubtargetPredicate = isGFX8Plus
 } // End SchedRW = [Write64Bit]
 } // End isReMaterializable = 1
 
 def : GCNPat<
   (i32 (DivergentUnaryFrag<sext> i16:$src)),
-  (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10))))
+  (i32 (V_BFE_I32_e64 i16:$src, (V_MOV_B32_e32 (i32 0)), (V_MOV_B32_e32 (i32 0x10))))
 >;
 
 let isReMaterializable = 1 in {
 let SubtargetPredicate = isGFX6GFX7GFX10Plus in {
 defm V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
 } // End SubtargetPredicate = isGFX6GFX7GFX10Plus
 
 let SchedRW = [Write32Bit] in {

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir

 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GCN-LABEL: name: sext_vgpr_s16_to_vgpr_s32
     ; GCN: liveins: $vgpr0
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], 0, 16, implicit $exec
+    ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
+    ; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], implicit $exec
     ; GCN-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s32) = G_SEXT %1
     $vgpr0 = COPY %2
 
 ...
 

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir

body: |
   bb.0:
     liveins: $vgpr0
 
     ; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s16
     ; GCN: liveins: $vgpr0
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
-    ; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[V_AND_B32_e32_]], 0, 16, implicit $exec
+    ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
+    ; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[V_AND_B32_e32_]], [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], implicit $exec
     ; GCN-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s1) = G_TRUNC %0
     %2:vgpr(s16) = G_ZEXT %1
     %3:vgpr(s32) = G_SEXT %2
     $vgpr0 = COPY %3
 ...
 

llvm/test/CodeGen/AMDGPU/v_bfe_i32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --global-isel -verify-machineinstrs < %s | FileCheck --check-prefix=PREGFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --global-isel -mcpu=hawaii -verify-machineinstrs < %s | FileCheck --check-prefix=PREGFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --global-isel -mcpu=fiji -verify-machineinstrs < %s | FileCheck --check-prefix=PREGFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --global-isel -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck --check-prefix=PREGFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --global-isel -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10PLUS %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --global-isel -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10PLUS %s
+
+define i32 @check_v_bfe(i16 %a) {
+; PREGFX9-LABEL: check_v_bfe:
+; PREGFX9:       ; %bb.0: ; %entry
+; PREGFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; PREGFX9-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; PREGFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-LABEL: check_v_bfe:
+; GFX10PLUS:       ; %bb.0: ; %entry
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %res = sext i16 %a to i32
+  ret i32 %res
+}