[SystemZ] Allow fp/int casting into inline assembly operands

[jonpa]

Summary

Allow bitcasting of fp/vec values into inline assembly 'r' operands, int/vec operands into 'f' operands, and int/fp operands into 'v' operands. This now matches GCCs behavior.

For the 'f' constraint, I changed the register class assigned for 128-bit to depend on the vector facility (using getRegClassFor()). This was needed to match GCCs behavior, but I am now a little surprised that this was always FP128BitRegClass..?

The casting between i128 and f128 required some extra work as i128 is untyped.

[iii]

llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting.ll

44

Did this work for you in GCC? I tried:

__int128 foo(__int128 bar) {
    asm("" : "+f" (bar));
    return bar;
}

and got:

error: inconsistent operand constraints in an ‘asm’

I wanted to give it a try, because I would expect ld/std here, like for long double.

[iii]

I can't really comment on the implementation, but the examples in the testcase look good to me.

llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting.ll

44

My bad, I should have specified -march=z13.

[uweigand]

The 128-bit logic doesn't look quite right to me. I think what should be used there is:

• "r" constraint - GPR register pair
• "f" constraint - FPR register pair if hard-float, error if soft-float
• "v" constraint - single VR if vector support enabled, error otherwise

In particular, for "f" I believe this should *not* depend on the -march level, that would be very confusing. (I'm actually not sure GCC is getting this right in all cases either.) In any case, we definitely need tests verifying this for pre-z13, z13, and z14/later.

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

1110

All this CW_Default stuff is confusing - isn't this, well, the default?

[jonpa]

Updated patch per review.

Added more tests, but left this one out for zEC12 as it failed (not sure exactly why):

define <4 x i32> @vec128_and_r(<4 x i32> %cc_dep1) {
entry:

%0 = tail call <4 x i32> asm sideeffect "", "=r,0"(<4 x i32> %cc_dep1)
ret <4 x i32> %0

}

llc: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:733: void getCopyToPartsVector(llvm::SelectionDAG&, const llvm::SDLoc&, llvm::SDValue, llvm::SDValue*, unsigned int, llvm::MVT, const llvm::Value*, std:\
:optional<unsigned int>): Assertion `RegisterVT == PartVT && "Part type doesn't match vector breakdown!"' failed.

Is this expected to fail?

[jonpa]

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

1110

Yeah, I was just following the pattern in use, but I guess it's more readable this way.

[uweigand]

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

1110

Ah, sorry - I overlooked the default was CW_Invalid, not CW_Default. And in fact the default has to be CW_Invalid, since this is critical for the various constant constraints like 'I'. If the argument is not an in-range constant, this has to be refused.

1114

Also, this makes me wonder now if we should return CW_Invalid here if soft-float (and similarly for 'v' and no-vector).

llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting.ll

39

This difference between z15 and z13 is a bit weird. Both instruction sequences would be correct and available on both architectures, so I'm not sure why it chooses a different one. (Also, I'm not actually sure which one performs better ...) - That may be something to look at as a follow-on.

llvm/test/CodeGen/SystemZ/soft-float-inline-asm-01.ll

10 ↗

(On Diff #507047)

Hmm, I think the previous error (reported via emitInlineAsmError) is better - this is not an LLVM bug (which is what report_fatal_error is primarily for), but rather a user error.

[jonpa]

Patch updated per review - see inline comments.

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

1110

ouch - yeah, I guess it needs to handle those cases as well.

1114

IIUC, the multiple-alternative decision is the same for all operands, and if one of the operands is invalid in that alternative, the search continues still in other alternatives. So I guess it would make sense to return CW_Invalid and then perhaps end up with a legal alternative, rather than giving the error message in case it would end up with the illegal alternative.

llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting.ll

39

The i128 load is bitcasted into f128, and becomes a f128 load. So I guess this then relates to the fact that for z13 we use FP128BitRegClass for f128, and with z14 and later instead the VR128BitRegClass. I guess VectorEnhancements1 is the difference and that makes it worthwhile to use VR128. Yeah, it seems actually better to have two independent instructions and maybe that could be worth trying on z15 as well.

llvm/test/CodeGen/SystemZ/soft-float-inline-asm-01.ll

10 ↗

(On Diff #507047)

It seems the easy thing to do is to return nullptr for the register class. This diagnostic is not quite as informative, though... (not sure we could do like emitInlineAsmError() and call LLVMContext::emitError() with a better message as the DAG pointer/LLVMContext is not available here).

[uweigand]

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

1199

Isn't this the same the original code (base class) already does? I don't think we need to change this here at all.

1216

However, I'm wondering if we shouldn't also make the same set of changes in this block, so enable the same logic for explicitly named register constraints like {f0}.

1463

Maybe we should just merge the two if blocks into a something like:

if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) {
      if (ValueVT != MVT::i128)
         Val = DAG.getNode(ISD::BITCAST, SDLoc(Val), MVT::i128, Val);
      Parts[0] = lowerI128ToGR128(DAG, Val);
}

and similarly below.

1485

It's a bit confusing that this accepts any type with getSizeInBits 128, but then hardcodes MVT::f128 as result type. Shouldn't this simply bitcast to ValueVT then?

[jonpa]

Patch updated per review.

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

1199

ok

1463

Yes - and the getBitcast() has the type check so even better.

I removed the assertions because they didn't seem to be of much use anymore now that we are bitcasting ValueVT and also checking carefully in the if statement.

1485

Makes sense.

[uweigand]

OK; this version LGTM now. Thanks!

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

getSingleConstraintMatchWeight(AsmOperandInfo &info,
   default:
     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
     break;
 
   case 'a': // Address register
   case 'd': // Data register (equivalent to 'r')
   case 'h': // High-part register
   case 'r': // General-purpose register
-    if (CallOperandVal->getType()->isIntegerTy())
-      weight = CW_Register;
+    weight = CallOperandVal->getType()->isIntegerTy() ? CW_Register : CW_Default;
     break;
 
   case 'f': // Floating-point register
-    if (type->isFloatingPointTy())
-      weight = CW_Register;
+    if (!useSoftFloat())
+      weight = type->isFloatingPointTy() ? CW_Register : CW_Default;
     break;
 
   case 'v': // Vector register
-    if ((type->isVectorTy() || type->isFloatingPointTy()) &&
-        Subtarget.hasVector())
-      weight = CW_Register;
+    if (Subtarget.hasVector())
+      weight = (type->isVectorTy() || type->isFloatingPointTy()) ? CW_Register
+                                                                 : CW_Default;
     break;
 
   case 'I': // Unsigned 8-bit constant
     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
       if (isUInt<8>(C->getZExtValue()))
         weight = CW_Constant;
     break;
 

 SystemZTargetLowering::getRegForInlineAsmConstraint(
     const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
   if (Constraint.size() == 1) {
     // GCC Constraint Letters
     switch (Constraint[0]) {
     default: break;
     case 'd': // Data register (equivalent to 'r')
     case 'r': // General-purpose register
-      if (VT == MVT::i64)
+      if (VT.getSizeInBits() == 64)
         return std::make_pair(0U, &SystemZ::GR64BitRegClass);
-      else if (VT == MVT::i128)
+      else if (VT.getSizeInBits() == 128)
         return std::make_pair(0U, &SystemZ::GR128BitRegClass);
       return std::make_pair(0U, &SystemZ::GR32BitRegClass);
 
     case 'a': // Address register
       if (VT == MVT::i64)
         return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
       else if (VT == MVT::i128)
         return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
       return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
 
     case 'h': // High-part register (an LLVM extension)
       return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
 
     case 'f': // Floating-point register
-      if (!useSoftFloat()) {
-        if (VT == MVT::f64)
-          return std::make_pair(0U, &SystemZ::FP64BitRegClass);
-        else if (VT == MVT::f128)
-          return std::make_pair(0U, &SystemZ::FP128BitRegClass);
-        return std::make_pair(0U, &SystemZ::FP32BitRegClass);
-      }
-      break;
+      if (useSoftFloat())
+        return std::make_pair(0U, nullptr);
+      if (VT.getSizeInBits() == 64)
+      else if (VT.getSizeInBits() == 128)
+
     case 'v': // Vector register
-      if (Subtarget.hasVector()) {
-        if (VT == MVT::f32)
-          return std::make_pair(0U, &SystemZ::VR32BitRegClass);
-        if (VT == MVT::f64)
-          return std::make_pair(0U, &SystemZ::VR64BitRegClass);
-        return std::make_pair(0U, &SystemZ::VR128BitRegClass);
-      }
-      break;
-    }
+      if (!Subtarget.hasVector())
+        return std::make_pair(0U, nullptr);
+      if (VT.getSizeInBits() == 32)
+      if (VT.getSizeInBits() == 64)
   }
   if (Constraint.size() > 0 && Constraint[0] == '{') {
     // We need to override the default register parsing for GPRs and FPRs
     // because the interpretation depends on VT.  The internal names of
     // the registers are also different from the external names
     // (F0D and F0S instead of F0, etc.).
     if (Constraint[1] == 'r') {
       if (VT == MVT::i32)
         return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
                                    SystemZMC::GR32Regs, 16);
assert((ValueVT != MVT::i128 ||
           ((NumParts == 1 && PartVT == MVT::Untyped) ||
            (NumParts == 2 && PartVT == MVT::i64))) &&
          "Unknown handling of i128 value.");
   if (ValueVT == MVT::i128 && NumParts == 1) {
     // Inline assembly operand.
     Parts[0] = lowerI128ToGR128(DAG, Val);
     return true;
   }
+  if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) {
+    // Inline assmebly operand: f128 -> i128
+    SDValue Val_i128 = DAG.getNode(ISD::BITCAST, SDLoc(Val), MVT::i128, Val);
+    Parts[0] = lowerI128ToGR128(DAG, Val_i128);
+    return true;
+  }
   return false;
 }
 
 SDValue SystemZTargetLowering::joinRegisterPartsIntoValue(
     SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
     MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const {
   assert((ValueVT != MVT::i128 ||
           ((NumParts == 1 && PartVT == MVT::Untyped) ||
            (NumParts == 2 && PartVT == MVT::i64))) &&
          "Unknown handling of i128 value.");
   if (ValueVT == MVT::i128 && NumParts == 1)
     // Inline assembly operand.
     return lowerGR128ToI128(DAG, Parts[0]);
+  if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) {
+    // Inline assmebly operand: i128 -> f128
+    SDValue Val_i128 = lowerGR128ToI128(DAG, Parts[0]);
+    return DAG.getNode(ISD::BITCAST, SDLoc(Val_i128), MVT::f128, Val_i128);
+  }
   return SDValue();
 }
 
 SDValue SystemZTargetLowering::LowerFormalArguments(
     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
   MachineFunction &MF = DAG.getMachineFunction();

llvm/test/CodeGen/SystemZ/inline-asm-f-constraint-softfloat.ll

+; RUN: not llc -mtriple=s390x-linux-gnu -mcpu=z15 -mattr=soft-float < %s 2>&1 | FileCheck %s
+
+; CHECK: error: couldn't allocate output register for constraint 'f'
+
+define signext i32 @int_and_f(i32 signext %cc_dep1) {
+entry:
+  %0 = tail call i32 asm sideeffect "", "=f,0"(i32 %cc_dep1)
+  ret i32 %0
+}

llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-zEC12.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=zEC12 < %s | FileCheck %s
+;
+; Test inline assembly where the operand is bitcasted.
+
+define signext i32 @int_and_f(i32 signext %cc_dep1) {
+; CHECK-LABEL: int_and_f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    risbhg %r0, %r2, 0, 159, 32
+; CHECK-NEXT:    ldgr %f0, %r0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lgdr %r0, %f0
+; CHECK-NEXT:    risblg %r0, %r0, 0, 159, 32
+; CHECK-NEXT:    lgfr %r2, %r0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call i32 asm sideeffect "", "=f,0"(i32 %cc_dep1)
+  ret i32 %0
+}
+
+define i64 @long_and_f(i64 %cc_dep1) {
+; CHECK-LABEL: long_and_f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ldgr %f0, %r2
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lgdr %r2, %f0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call i64 asm sideeffect "", "=f,0"(i64 %cc_dep1)
+  ret i64 %0
+}
+
+define void @__int128_and_f(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) {
+; CHECK-LABEL: __int128_and_f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ld %f0, 0(%r3)
+; CHECK-NEXT:    ld %f2, 8(%r3)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    std %f0, 0(%r2)
+; CHECK-NEXT:    std %f2, 8(%r2)
+; CHECK-NEXT:    br %r14
+entry:
+  %cc_dep1 = load i128, ptr %0, align 8
+  %1 = tail call i128 asm sideeffect "", "=f,0"(i128 %cc_dep1)
+  store i128 %1, ptr %agg.result, align 8
+  ret void
+}
+
+define float @float_and_r(float %cc_dep1) {
+; CHECK-LABEL: float_and_r:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $f0s killed $f0s def $f0d
+; CHECK-NEXT:    lgdr %r0, %f0
+; CHECK-NEXT:    risblg %r0, %r0, 0, 159, 32
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    risbhg %r0, %r0, 0, 159, 32
+; CHECK-NEXT:    ldgr %f0, %r0
+; CHECK-NEXT:    # kill: def $f0s killed $f0s killed $f0d
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call float asm sideeffect "", "=r,0"(float %cc_dep1)
+  ret float %0
+}
+
+define double @double_and_r(double %cc_dep1) {
+; CHECK-LABEL: double_and_r:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lgdr %r0, %f0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    ldgr %f0, %r0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call double asm sideeffect "", "=r,0"(double %cc_dep1)
+  ret double %0
+}
+
+define void @longdouble_and_r(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) {
+; CHECK-LABEL: longdouble_and_r:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lg %r1, 8(%r3)
+; CHECK-NEXT:    lg %r0, 0(%r3)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    stg %r1, 8(%r2)
+; CHECK-NEXT:    stg %r0, 0(%r2)
+; CHECK-NEXT:    br %r14
+entry:
+  %cc_dep1 = load fp128, ptr %0, align 8
+  %1 = tail call fp128 asm sideeffect "", "=r,0"(fp128 %cc_dep1)
+  store fp128 %1, ptr %agg.result, align 8
+  ret void
+}
+
+define <2 x i16> @vec32_and_r(<2 x i16> %cc_dep1) {
+; CHECK-LABEL: vec32_and_r:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $r3l killed $r3l def $r3d
+; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT:    risbgn %r3, %r2, 32, 47, 16
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    srlk %r2, %r3, 16
+; CHECK-NEXT:    # kill: def $r3l killed $r3l killed $r3d
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call <2 x i16> asm sideeffect "", "=r,0"(<2 x i16> %cc_dep1)
+  ret <2 x i16> %0
+}
+
+define <2 x i32> @vec64_and_r(<2 x i32> %cc_dep1) {
+; CHECK-LABEL: vec64_and_r:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT:    sllg %r0, %r2, 32
+; CHECK-NEXT:    lr %r0, %r3
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lr %r3, %r0
+; CHECK-NEXT:    srlg %r2, %r0, 32
+; CHECK-NEXT:    # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call <2 x i32> asm sideeffect "", "=r,0"(<2 x i32> %cc_dep1)
+  ret <2 x i32> %0
+}
+
+define <2 x i16> @vec32_and_f(<2 x i16> %cc_dep1) {
+; CHECK-LABEL: vec32_and_f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $r3l killed $r3l def $r3d
+; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT:    risbgn %r3, %r2, 32, 47, 16
+; CHECK-NEXT:    risbhg %r0, %r3, 0, 159, 32
+; CHECK-NEXT:    ldgr %f0, %r0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lgdr %r0, %f0
+; CHECK-NEXT:    risblg %r3, %r0, 0, 159, 32
+; CHECK-NEXT:    srlk %r2, %r3, 16
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call <2 x i16> asm sideeffect "", "=f,0"(<2 x i16> %cc_dep1)
+  ret <2 x i16> %0
+}
+
+define <2 x i32> @vec64_and_f(<2 x i32> %cc_dep1) {
+; CHECK-LABEL: vec64_and_f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT:    sllg %r0, %r2, 32
+; CHECK-NEXT:    lr %r0, %r3
+; CHECK-NEXT:    ldgr %f0, %r0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lgdr %r3, %f0
+; CHECK-NEXT:    srlg %r2, %r3, 32
+; CHECK-NEXT:    # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT:    # kill: def $r3l killed $r3l killed $r3d
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call <2 x i32> asm sideeffect "", "=f,0"(<2 x i32> %cc_dep1)
+  ret <2 x i32> %0
+}
+
+define <4 x i32> @vec128_and_f(<4 x i32> %cc_dep1) {
+; CHECK-LABEL: vec128_and_f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    aghi %r15, -176
+; CHECK-NEXT:    .cfi_def_cfa_offset 336
+; CHECK-NEXT:    # kill: def $r4l killed $r4l def $r4d
+; CHECK-NEXT:    sllg %r0, %r4, 32
+; CHECK-NEXT:    lr %r0, %r5
+; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT:    stg %r0, 168(%r15)
+; CHECK-NEXT:    sllg %r0, %r2, 32
+; CHECK-NEXT:    lr %r0, %r3
+; CHECK-NEXT:    stg %r0, 160(%r15)
+; CHECK-NEXT:    ld %f0, 160(%r15)
+; CHECK-NEXT:    ld %f2, 168(%r15)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lgdr %r3, %f0
+; CHECK-NEXT:    lgdr %r5, %f2
+; CHECK-NEXT:    srlg %r2, %r3, 32
+; CHECK-NEXT:    srlg %r4, %r5, 32
+; CHECK-NEXT:    # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT:    # kill: def $r3l killed $r3l killed $r3d
+; CHECK-NEXT:    # kill: def $r4l killed $r4l killed $r4d
+; CHECK-NEXT:    # kill: def $r5l killed $r5l killed $r5d
+; CHECK-NEXT:    aghi %r15, 176
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call <4 x i32> asm sideeffect "", "=f,0"(<4 x i32> %cc_dep1)
+  ret <4 x i32> %0
+}
+

llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 < %s | FileCheck %s --check-prefixes=CHECK,Z15
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s --check-prefixes=CHECK,Z13
+;
+; Test inline assembly where the operand is bitcasted.
+
+define signext i32 @int_and_f(i32 signext %cc_dep1) {
+; CHECK-LABEL: int_and_f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vlvgf %v0, %r2, 0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vlgvf %r0, %v0, 0
+; CHECK-NEXT:    lgfr %r2, %r0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call i32 asm sideeffect "", "=f,0"(i32 %cc_dep1)
+  ret i32 %0
+}
+
+define i64 @long_and_f(i64 %cc_dep1) {
+; CHECK-LABEL: long_and_f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ldgr %f0, %r2
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lgdr %r2, %f0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call i64 asm sideeffect "", "=f,0"(i64 %cc_dep1)
+  ret i64 %0
+}
+
+define void @__int128_and_f(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) {
+; Z15-LABEL: __int128_and_f:
+; Z15:       # %bb.0: # %entry
+; Z15-NEXT:    vl %v0, 0(%r3), 3
+; Z15-NEXT:    vrepg %v2, %v0, 1
+; Z15-NEXT:    #APP
+; Z15-NEXT:    #NO_APP
+; Z15-NEXT:    vmrhg %v0, %v0, %v2
+; Z15-NEXT:    vst %v0, 0(%r2), 3
+; Z15-NEXT:    br %r14
+;
+; Z13-LABEL: __int128_and_f:
+; Z13:       # %bb.0: # %entry
+; Z13-NEXT:    ld %f0, 0(%r3)
+; Z13-NEXT:    ld %f2, 8(%r3)
+; Z13-NEXT:    #APP
+; Z13-NEXT:    #NO_APP
+; Z13-NEXT:    std %f0, 0(%r2)
+; Z13-NEXT:    std %f2, 8(%r2)
+; Z13-NEXT:    br %r14
+entry:
+  %cc_dep1 = load i128, ptr %0, align 8
+  %1 = tail call i128 asm sideeffect "", "=f,0"(i128 %cc_dep1)
+  store i128 %1, ptr %agg.result, align 8
+  ret void
+}
+
+define signext i32 @int_and_v(i32 signext %cc_dep1) {
+; CHECK-LABEL: int_and_v:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vlvgf %v0, %r2, 0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vlgvf %r0, %v0, 0
+; CHECK-NEXT:    lgfr %r2, %r0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call i32 asm sideeffect "", "=v,0"(i32 %cc_dep1)
+  ret i32 %0
+}
+
+define i64 @long_and_v(i64 %cc_dep1) {
+; CHECK-LABEL: long_and_v:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ldgr %f0, %r2
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lgdr %r2, %f0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call i64 asm sideeffect "", "=v,0"(i64 %cc_dep1)
+  ret i64 %0
+}
+
+define void @__int128_and_v(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) {
+; CHECK-LABEL: __int128_and_v:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vl %v0, 0(%r3), 3
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vst %v0, 0(%r2), 3
+; CHECK-NEXT:    br %r14
+entry:
+  %cc_dep1 = load i128, ptr %0, align 8
+  %1 = tail call i128 asm sideeffect "", "=v,0"(i128 %cc_dep1)
+  store i128 %1, ptr %agg.result, align 8
+  ret void
+}
+
+define float @float_and_r(float %cc_dep1) {
+; CHECK-LABEL: float_and_r:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vlgvf %r0, %v0, 0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vlvgf %v0, %r0, 0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call float asm sideeffect "", "=r,0"(float %cc_dep1)
+  ret float %0
+}
+
+define double @double_and_r(double %cc_dep1) {
+; CHECK-LABEL: double_and_r:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lgdr %r0, %f0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    ldgr %f0, %r0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call double asm sideeffect "", "=r,0"(double %cc_dep1)
+  ret double %0
+}
+
+define void @longdouble_and_r(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) {
+; CHECK-LABEL: longdouble_and_r:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lg %r1, 8(%r3)
+; CHECK-NEXT:    lg %r0, 0(%r3)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    stg %r1, 8(%r2)
+; CHECK-NEXT:    stg %r0, 0(%r2)
+; CHECK-NEXT:    br %r14
+entry:
+  %cc_dep1 = load fp128, ptr %0, align 8
+  %1 = tail call fp128 asm sideeffect "", "=r,0"(fp128 %cc_dep1)
+  store fp128 %1, ptr %agg.result, align 8
+  ret void
+}
+
+define float @float_and_v(float %cc_dep1) {
+; CHECK-LABEL: float_and_v:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call float asm sideeffect "", "=v,0"(float %cc_dep1)
+  ret float %0
+}
+
+define double @double_and_v(double %cc_dep1) {
+; CHECK-LABEL: double_and_v:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call double asm sideeffect "", "=v,0"(double %cc_dep1)
+  ret double %0
+}
+
+define void @longdouble_and_v(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) {
+; CHECK-LABEL: longdouble_and_v:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vl %v0, 0(%r3), 3
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vst %v0, 0(%r2), 3
+; CHECK-NEXT:    br %r14
+entry:
+  %cc_dep1 = load fp128, ptr %0, align 8
+  %1 = tail call fp128 asm sideeffect "", "=v,0"(fp128 %cc_dep1)
+  store fp128 %1, ptr %agg.result, align 8
+  ret void
+}
+
+define <2 x i16> @vec32_and_r(<2 x i16> %cc_dep1) {
+; CHECK-LABEL: vec32_and_r:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vlgvf %r0, %v24, 0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vlvgf %v24, %r0, 0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call <2 x i16> asm sideeffect "", "=r,0"(<2 x i16> %cc_dep1)
+  ret <2 x i16> %0
+}
+
+define <2 x i32> @vec64_and_r(<2 x i32> %cc_dep1) {
+; CHECK-LABEL: vec64_and_r:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vlgvg %r0, %v24, 0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vlvgg %v24, %r0, 0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call <2 x i32> asm sideeffect "", "=r,0"(<2 x i32> %cc_dep1)
+  ret <2 x i32> %0
+}
+
+define <4 x i32> @vec128_and_r(<4 x i32> %cc_dep1) {
+; CHECK-LABEL: vec128_and_r:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vlgvg %r1, %v24, 1
+; CHECK-NEXT:    vlgvg %r0, %v24, 0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vlvgp %v24, %r0, %r1
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call <4 x i32> asm sideeffect "", "=r,0"(<4 x i32> %cc_dep1)
+  ret <4 x i32> %0
+}
+
+define <2 x i16> @vec32_and_f(<2 x i16> %cc_dep1) {
+; CHECK-LABEL: vec32_and_f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vlr %v0, %v24
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vlr %v24, %v0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call <2 x i16> asm sideeffect "", "=f,0"(<2 x i16> %cc_dep1)
+  ret <2 x i16> %0
+}
+
+define <2 x i32> @vec64_and_f(<2 x i32> %cc_dep1) {
+; CHECK-LABEL: vec64_and_f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vlr %v0, %v24
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vlr %v24, %v0
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call <2 x i32> asm sideeffect "", "=f,0"(<2 x i32> %cc_dep1)
+  ret <2 x i32> %0
+}
+
+define <4 x i32> @vec128_and_f(<4 x i32> %cc_dep1) {
+; CHECK-LABEL: vec128_and_f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vrepg %v2, %v24, 1
+; CHECK-NEXT:    vlr %v0, %v24
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vmrhg %v24, %v0, %v2
+; CHECK-NEXT:    br %r14
+entry:
+  %0 = tail call <4 x i32> asm sideeffect "", "=f,0"(<4 x i32> %cc_dep1)
+  ret <4 x i32> %0
+}
+

llvm/test/CodeGen/SystemZ/inline-asm-v-constraint-novecfacility.ll

+; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 2>&1 | FileCheck %s
+
+; CHECK: error: couldn't allocate output register for constraint 'v'
+
+define signext i32 @int_and_v(i32 signext %cc_dep1) {
+entry:
+  %0 = tail call i32 asm sideeffect "", "=v,0"(i32 %cc_dep1)
+  ret i32 %0
+}