[BOLT][NFC] Provide default impl for MIB methods that are only overridden on X86

[Amir]

Summary

Simplifies D145687

[rafauler]

LGTM

[Amir]

clang-format

bolt/include/bolt/Core/MCPlusBuilder.h

virtual bool isNoop(const MCInst &Inst) const {
     return false;
   }
 
   virtual bool isBreakpoint(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
-  virtual bool isPrefix(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
+  virtual bool isPrefix(const MCInst &Inst) const { return false; }
 
-  virtual bool isRep(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
+  virtual bool isRep(const MCInst &Inst) const { return false; }
 
   virtual bool deleteREPPrefix(MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
   virtual bool isEHLabel(const MCInst &Inst) const {
     return Inst.getOpcode() == TargetOpcode::EH_LABEL;
   }
 
-  virtual bool isPop(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
+  virtual bool isPop(const MCInst &Inst) const { return false; }
 
   /// Return true if the instruction is used to terminate an indirect branch.
   virtual bool isTerminateBranch(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
   /// Return the width, in bytes, of the memory access performed by \p Inst, if
virtual bool isSUB(const MCInst &Inst) const {
     return false;
   }
 
   virtual bool isLEA64r(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
-  virtual bool isLeave(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
+  virtual bool isLeave(const MCInst &Inst) const { return false; }
 
   virtual bool isADRP(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
   virtual bool isADR(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
   virtual void getADRReg(const MCInst &Inst, MCPhysReg &RegName) const {
     llvm_unreachable("not implemented");
   }
 
-  virtual bool isMoveMem2Reg(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
+  virtual bool isMoveMem2Reg(const MCInst &Inst) const { return false; }
 
   virtual bool isLoad(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
   virtual bool isStore(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
public:
   /// Return a number of the operand representing a memory.
   /// Return -1 if the instruction doesn't have an explicit memory field.
   virtual int getMemoryOperandNo(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return -1;
   }
 
   /// Return true if the instruction is encoded using EVEX (AVX-512).
-  virtual bool hasEVEXEncoding(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
+  virtual bool hasEVEXEncoding(const MCInst &Inst) const { return false; }
 
   /// Return true if a pair of instructions represented by \p Insts
   /// could be fused into a single uop.
   virtual bool isMacroOpFusionPair(ArrayRef<MCInst> Insts) const {
     llvm_unreachable("not implemented");
     return false;
   }
 

bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp

bool equals(const MCTargetExpr &A, const MCTargetExpr &B,
     const auto &AArch64ExprB = cast<AArch64MCExpr>(B);
     if (AArch64ExprA.getKind() != AArch64ExprB.getKind())
       return false;
 
     return MCPlusBuilder::equals(*AArch64ExprA.getSubExpr(),
                                  *AArch64ExprB.getSubExpr(), Comp);
   }
 
-  bool hasEVEXEncoding(const MCInst &) const override { return false; }
-
   bool isMacroOpFusionPair(ArrayRef<MCInst> Insts) const override {
     return false;
   }
 
   bool shortenInstruction(MCInst &, const MCSubtargetInfo &) const override {
     return false;
   }
 
bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
     Inst.setOpcode(AArch64::B);
     Inst.clear();
     Inst.addOperand(MCOperand::createExpr(getTargetExprFor(
         Inst, MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx),
         *Ctx, 0)));
     return true;
   }
 
-  bool isMoveMem2Reg(const MCInst &Inst) const override { return false; }
-
-  bool isLeave(const MCInst &Inst) const override { return false; }
-
-  bool isPop(const MCInst &Inst) const override { return false; }
-
-  bool isPrefix(const MCInst &Inst) const override { return false; }
-
   bool createReturn(MCInst &Inst) const override {
     Inst.setOpcode(AArch64::RET);
     Inst.clear();
     Inst.addOperand(MCOperand::createReg(AArch64::LR));
     return true;
   }
 
   InstructionListType materializeAddress(const MCSymbol *Target, MCContext *Ctx,