[clang-format] Fix non-case colons in Verilog case lines

[sstwcw]

Summary

Back in D128714, we should have replaced the old rule about colons when
we added the new one. Because we didn't, all colons got mistaken as
case colons as long as the line began with case or default.

[MyDeveloperDay]

clang/lib/Format/TokenAnnotator.cpp

4424

Hmm.. this is going to impact others, did you make a change here before and break something for c++? or was this a bug in the C++ code, is there not a unit test for setting SpaceBeforeCaseColon?

[sstwcw]

clang/lib/Format/TokenAnnotator.cpp

4424

You can see that the previous rule already covers what this one covers. This rule doesn't change the behavior for C++.

clang/lib/Format/TokenAnnotator.cpp

return Style.BitFieldColonSpacing == FormatStyle::BFCS_Both ||
            Style.BitFieldColonSpacing == FormatStyle::BFCS_After;
   }
   if (Right.is(tok::colon)) {
     if (Right.is(TT_GotoLabelColon) ||
         (!Style.isVerilog() &&
          Line.First->isOneOf(tok::kw_default, tok::kw_case))) {
       return Style.SpaceBeforeCaseColon;
     }
-    if (Line.First->isOneOf(tok::kw_default, tok::kw_case))
-      return Style.SpaceBeforeCaseColon;
     const FormatToken *Next = Right.getNextNonComment();
     if (!Next || Next->is(tok::semi))
       return false;
     if (Right.is(TT_ObjCMethodExpr))
       return false;
     if (Left.is(tok::question))
       return false;
     if (Right.is(TT_InlineASMColon) && Left.is(tok::coloncolon))

clang/unittests/Format/FormatTestVerilog.cpp

verifyFormat("case (data)\n"
                "endcase",
                Style);
   verifyFormat("case (data)\n"
                "  16'd0: begin\n"
                "    result = 10'b0111111111;\n"
                "  end\n"
                "endcase",
                Style);
+  // Other colons should not be mistaken as case colons.
+  Style = getLLVMStyle(FormatStyle::LK_Verilog);
+  Style.BitFieldColonSpacing = FormatStyle::BFCS_None;
+  verifyFormat("case (x[1:0])\n"
+               "endcase", Style);
+  verifyFormat("default:\n"
+               "  x[1:0] = x[1:0];", Style);
+  Style.BitFieldColonSpacing = FormatStyle::BFCS_Both;
+  verifyFormat("case (x[1 : 0])\n"
+               "endcase", Style);
+  verifyFormat("default:\n"
+               "  x[1 : 0] = x[1 : 0];", Style);
+  Style = getLLVMStyle(FormatStyle::LK_Verilog);
+  Style.SpacesInContainerLiterals = true;
+  verifyFormat("case ('{x : x, default : 9})\n"
+               "endcase", Style);
+  verifyFormat("x = '{x : x, default : 9};\n", Style);
+  verifyFormat("default:\n"
+               "  x = '{x : x, default : 9};\n",
+               Style);
+  Style.SpacesInContainerLiterals = false;
+  verifyFormat("case ('{x: x, default: 9})\n"
+               "endcase", Style);
+  verifyFormat("x = '{x: x, default: 9};\n", Style);
+  verifyFormat("default:\n"
+               "  x = '{x: x, default: 9};\n",
+               Style);
 }
 
 TEST_F(FormatTestVerilog, Declaration) {
   verifyFormat("wire mynet;");
   verifyFormat("wire mynet, mynet1;");
   verifyFormat("wire mynet, //\n"
                "     mynet1;");
   verifyFormat("wire mynet = enable;");