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Differential D145632

[test] Remove occurences of br undef in CodeGen/PowerPC tests
Needs RevisionPublic

Authored by kritgpt on Mar 8 2023, 4:35 PM.

Details

Reviewers
nlopes
nemanjai
Summary

This patch removes br undef as suggested by https://discourse.llvm.org/t/please-dont-use-br-undef-in-tests-aka-please-avoid-test-cases-with-ub/63115. Script used: https://gist.github.com/kritgpt/69bfc7ef78e1784716c693d531a58adf.

Diff Detail

Unit TestsFailed

TimeTest
60 msx64 debian > LLVM.CodeGen/PowerPC::aix-vsx-splatimm.ll
80 msx64 debian > LLVM.CodeGen/PowerPC::bdzlr.ll
80 msx64 debian > LLVM.CodeGen/PowerPC::expand-foldable-isel.ll
80 msx64 debian > LLVM.CodeGen/PowerPC::mma-phi-accs.ll
50 msx64 debian > LLVM.CodeGen/PowerPC::optimize-andiso.ll
View Full Test Results (16 Failed)

Event Timeline

kritgpt created this revision.Mar 8 2023, 4:35 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 8 2023, 4:35 PM
Herald added subscribers: shchenz, asbirlea, arphaman and 4 others. · View Herald Transcript
kritgpt requested review of this revision.Mar 8 2023, 4:35 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 8 2023, 4:35 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
kritgpt added a reviewer: nlopes.Mar 8 2023, 4:35 PM
lkail added a reviewer: nemanjai.Mar 8 2023, 4:47 PM
lkail added a subscriber: lkail.
Harbormaster completed remote builds in B218246: Diff 503563.Mar 8 2023, 5:26 PM
nlopes requested changes to this revision.Mar 9 2023, 12:05 AM

tests are failing. please run all the tests before submitting patches.

This revision now requires changes to proceed.Mar 9 2023, 12:05 AM
kritgpt added a comment.Mar 9 2023, 4:24 AM
In D145632#4180536, @nlopes wrote:

tests are failing. please run all the tests before submitting patches.

I checked these files with ninja check-llvm and all tests passed, but some fail here. Is there other checks I can perform before submitting a patch?

nlopes added a comment.Mar 9 2023, 4:39 AM
In D145632#4181185, @kritgpt wrote:
In D145632#4180536, @nlopes wrote:

tests are failing. please run all the tests before submitting patches.

I checked these files with ninja check-llvm and all tests passed, but some fail here. Is there other checks I can perform before submitting a patch?

probably you compiled LLVM with a single backend. You need to compile LLVM with everything.

nemanjai added a comment.Mar 9 2023, 6:53 AM

You can also try a quick check of llvm-lit test/CodeGen/PowerPC to run all the tests in that directory. If that ends up running zero tests, you've definitely not built the PowerPC target.

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Diff 503563

llvm/test/CodeGen/PowerPC/2009-11-15-ProcImpDefsBug.ll

; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu
define void @gcov_exit() nounwind { define void @gcov_exit(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16) nounwind {
entry: entry:
br i1 undef, label %return, label %bb.nph341 br i1 %c0, label %return, label %bb.nph341
bb.nph341: ; preds = %entry bb.nph341: ; preds = %entry
br label %bb25 br label %bb25
bb25: ; preds = %read_fatal, %bb.nph341 bb25: ; preds = %read_fatal, %bb.nph341
br i1 undef, label %bb49.1, label %bb48 br i1 %c1, label %bb49.1, label %bb48
bb48: ; preds = %bb25 bb48: ; preds = %bb25
br label %bb49.1 br label %bb49.1
bb51: ; preds = %bb48.4, %bb49.3 bb51: ; preds = %bb48.4, %bb49.3
switch i32 undef, label %bb58 [ switch i32 undef, label %bb58 [
i32 0, label %rewrite i32 0, label %rewrite
i32 1734567009, label %bb59 i32 1734567009, label %bb59
] ]
bb58: ; preds = %bb51 bb58: ; preds = %bb51
br label %read_fatal br label %read_fatal
bb59: ; preds = %bb51 bb59: ; preds = %bb51
br i1 undef, label %bb60, label %bb3.i156 br i1 %c2, label %bb60, label %bb3.i156
bb3.i156: ; preds = %bb59 bb3.i156: ; preds = %bb59
br label %read_fatal br label %read_fatal
bb60: ; preds = %bb59 bb60: ; preds = %bb59
br i1 undef, label %bb78.preheader, label %rewrite br i1 %c3, label %bb78.preheader, label %rewrite
bb78.preheader: ; preds = %bb60 bb78.preheader: ; preds = %bb60
br i1 undef, label %bb62, label %bb80 br i1 %c4, label %bb62, label %bb80
bb62: ; preds = %bb78.preheader bb62: ; preds = %bb78.preheader
br i1 undef, label %bb64, label %read_mismatch br i1 %c5, label %bb64, label %read_mismatch
bb64: ; preds = %bb62 bb64: ; preds = %bb62
br i1 undef, label %bb65, label %read_mismatch br i1 %c6, label %bb65, label %read_mismatch
bb65: ; preds = %bb64 bb65: ; preds = %bb64
br i1 undef, label %bb75, label %read_mismatch br i1 %c7, label %bb75, label %read_mismatch
read_mismatch: ; preds = %bb98, %bb119.preheader, %bb72, %bb71, %bb65, %bb64, %bb62 read_mismatch: ; preds = %bb98, %bb119.preheader, %bb72, %bb71, %bb65, %bb64, %bb62
br label %read_fatal br label %read_fatal
bb71: ; preds = %bb75 bb71: ; preds = %bb75
br i1 undef, label %bb72, label %read_mismatch br i1 %c8, label %bb72, label %read_mismatch
bb72: ; preds = %bb71 bb72: ; preds = %bb71
br i1 undef, label %bb73, label %read_mismatch br i1 %c9, label %bb73, label %read_mismatch
bb73: ; preds = %bb72 bb73: ; preds = %bb72
unreachable unreachable
bb74: ; preds = %bb75 bb74: ; preds = %bb75
br label %bb75 br label %bb75
bb75: ; preds = %bb74, %bb65 bb75: ; preds = %bb74, %bb65
br i1 undef, label %bb74, label %bb71 br i1 %c10, label %bb74, label %bb71
bb80: ; preds = %bb78.preheader bb80: ; preds = %bb78.preheader
unreachable unreachable
read_fatal: ; preds = %read_mismatch, %bb3.i156, %bb58 read_fatal: ; preds = %read_mismatch, %bb3.i156, %bb58
br i1 undef, label %return, label %bb25 br i1 %c11, label %return, label %bb25
rewrite: ; preds = %bb60, %bb51 rewrite: ; preds = %bb60, %bb51
br i1 undef, label %bb94, label %bb119.preheader br i1 %c12, label %bb94, label %bb119.preheader
bb94: ; preds = %rewrite bb94: ; preds = %rewrite
unreachable unreachable
bb119.preheader: ; preds = %rewrite bb119.preheader: ; preds = %rewrite
br i1 undef, label %read_mismatch, label %bb98 br i1 %c13, label %read_mismatch, label %bb98
bb98: ; preds = %bb119.preheader bb98: ; preds = %bb119.preheader
br label %read_mismatch br label %read_mismatch
return: ; preds = %read_fatal, %entry return: ; preds = %read_fatal, %entry
ret void ret void
bb49.1: ; preds = %bb48, %bb25 bb49.1: ; preds = %bb48, %bb25
br i1 undef, label %bb49.2, label %bb48.2 br i1 %c14, label %bb49.2, label %bb48.2
bb49.2: ; preds = %bb48.2, %bb49.1 bb49.2: ; preds = %bb48.2, %bb49.1
br i1 undef, label %bb49.3, label %bb48.3 br i1 %c15, label %bb49.3, label %bb48.3
bb48.2: ; preds = %bb49.1 bb48.2: ; preds = %bb49.1
br label %bb49.2 br label %bb49.2
bb49.3: ; preds = %bb48.3, %bb49.2 bb49.3: ; preds = %bb48.3, %bb49.2
%c_ix.0.3 = phi i32 [ undef, %bb48.3 ], [ undef, %bb49.2 ] ; <i32> [#uses=1] %c_ix.0.3 = phi i32 [ undef, %bb48.3 ], [ undef, %bb49.2 ] ; <i32> [#uses=1]
br i1 undef, label %bb51, label %bb48.4 br i1 %c16, label %bb51, label %bb48.4
bb48.3: ; preds = %bb49.2 bb48.3: ; preds = %bb49.2
store ptr undef, ptr undef, align 4 store ptr undef, ptr undef, align 4
br label %bb49.3 br label %bb49.3
bb48.4: ; preds = %bb49.3 bb48.4: ; preds = %bb49.3
%0 = getelementptr inbounds [5 x ptr], ptr undef, i32 0, i32 %c_ix.0.3 ; <ptr> [#uses=0] %0 = getelementptr inbounds [5 x ptr], ptr undef, i32 0, i32 %c_ix.0.3 ; <ptr> [#uses=0]
br label %bb51 br label %bb51
} }

llvm/test/CodeGen/PowerPC/2009-11-25-ImpDefBug.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu.5 -mcpu=g5 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu.5 -mcpu=g5
; rdar://7422268 ; rdar://7422268
%struct..0EdgeT = type { i32, i32, float, float, i32, i32, i32, float, i32, i32 } %struct..0EdgeT = type { i32, i32, float, float, i32, i32, i32, float, i32, i32 }
define void @smooth_color_z_triangle(i32 %v0, i32 %v1, i32 %v2, i32 %pv) nounwind { define void @smooth_color_z_triangle(i32 %v0, i32 %v1, i32 %v2, i32 %pv, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6) nounwind {
entry: entry:
br i1 undef, label %return, label %bb14 br i1 %c0, label %return, label %bb14
bb14: ; preds = %entry bb14: ; preds = %entry
br i1 undef, label %bb15, label %return br i1 %c1, label %bb15, label %return
bb15: ; preds = %bb14 bb15: ; preds = %bb14
br i1 undef, label %bb16, label %bb17 br i1 %c2, label %bb16, label %bb17
bb16: ; preds = %bb15 bb16: ; preds = %bb15
br label %bb17 br label %bb17
bb17: ; preds = %bb16, %bb15 bb17: ; preds = %bb16, %bb15
%0 = fcmp olt float undef, 0.000000e+00 ; <i1> [#uses=2] %0 = fcmp olt float undef, 0.000000e+00 ; <i1> [#uses=2]
%eTop.eMaj = select i1 %0, ptr undef, ptr null ; <ptr> [#uses=1] %eTop.eMaj = select i1 %0, ptr undef, ptr null ; <ptr> [#uses=1]
br label %bb69 br label %bb69
bb24: ; preds = %bb69 bb24: ; preds = %bb69
br i1 undef, label %bb25, label %bb28 br i1 %c3, label %bb25, label %bb28
bb25: ; preds = %bb24 bb25: ; preds = %bb24
br label %bb33 br label %bb33
bb28: ; preds = %bb24 bb28: ; preds = %bb24
br i1 undef, label %return, label %bb32 br i1 %c4, label %return, label %bb32
bb32: ; preds = %bb28 bb32: ; preds = %bb28
br i1 %0, label %bb38, label %bb33 br i1 %0, label %bb38, label %bb33
bb33: ; preds = %bb32, %bb25 bb33: ; preds = %bb32, %bb25
br i1 undef, label %bb34, label %bb38 br i1 %c5, label %bb34, label %bb38
bb34: ; preds = %bb33 bb34: ; preds = %bb33
br label %bb38 br label %bb38
bb38: ; preds = %bb34, %bb33, %bb32 bb38: ; preds = %bb34, %bb33, %bb32
%eRight.08 = phi ptr [ %eTop.eMaj, %bb32 ], [ undef, %bb34 ], [ undef, %bb33 ] ; <ptr> [#uses=0] %eRight.08 = phi ptr [ %eTop.eMaj, %bb32 ], [ undef, %bb34 ], [ undef, %bb33 ] ; <ptr> [#uses=0]
%fdgOuter.0 = phi i32 [ %fdgOuter.1, %bb32 ], [ undef, %bb34 ], [ %fdgOuter.1, %bb33 ] ; <i32> [#uses=1] %fdgOuter.0 = phi i32 [ %fdgOuter.1, %bb32 ], [ undef, %bb34 ], [ %fdgOuter.1, %bb33 ] ; <i32> [#uses=1]
%fz.3 = phi i32 [ %fz.2, %bb32 ], [ 2147483647, %bb34 ], [ %fz.2, %bb33 ] ; <i32> [#uses=1] %fz.3 = phi i32 [ %fz.2, %bb32 ], [ 2147483647, %bb34 ], [ %fz.2, %bb33 ] ; <i32> [#uses=1]
%1 = add i32 undef, 1 ; <i32> [#uses=0] %1 = add i32 undef, 1 ; <i32> [#uses=0]
br label %bb69 br label %bb69
bb69: ; preds = %bb38, %bb17 bb69: ; preds = %bb38, %bb17
%fdgOuter.1 = phi i32 [ undef, %bb17 ], [ %fdgOuter.0, %bb38 ] ; <i32> [#uses=2] %fdgOuter.1 = phi i32 [ undef, %bb17 ], [ %fdgOuter.0, %bb38 ] ; <i32> [#uses=2]
%fz.2 = phi i32 [ undef, %bb17 ], [ %fz.3, %bb38 ] ; <i32> [#uses=2] %fz.2 = phi i32 [ undef, %bb17 ], [ %fz.3, %bb38 ] ; <i32> [#uses=2]
br i1 undef, label %bb24, label %return br i1 %c6, label %bb24, label %return
return: ; preds = %bb69, %bb28, %bb14, %entry return: ; preds = %bb69, %bb28, %bb14, %entry
ret void ret void
} }

llvm/test/CodeGen/PowerPC/2010-04-01-MachineCSEBug.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu
; rdar://7819990 ; rdar://7819990
%0 = type { i32 } %0 = type { i32 }
%1 = type { i64 } %1 = type { i64 }
%struct.Buffer = type { [1024 x i8], i64, i64, i64 } %struct.Buffer = type { [1024 x i8], i64, i64, i64 }
%struct.InStream = type { %struct.Buffer, %0, %1, ptr, ptr } %struct.InStream = type { %struct.Buffer, %0, %1, ptr, ptr }
%struct.InStreamMethods = type { ptr, ptr, ptr, ptr } %struct.InStreamMethods = type { ptr, ptr, ptr, ptr }
define i64 @t(ptr %is) nounwind optsize ssp { define i64 @t(ptr %is, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7) nounwind optsize ssp {
entry: entry:
br i1 undef, label %is_read_byte.exit, label %bb.i br i1 %c0, label %is_read_byte.exit, label %bb.i
bb.i: ; preds = %entry bb.i: ; preds = %entry
br label %is_read_byte.exit br label %is_read_byte.exit
is_read_byte.exit: ; preds = %bb.i, %entry is_read_byte.exit: ; preds = %bb.i, %entry
br i1 undef, label %is_read_byte.exit22, label %bb.i21 br i1 %c1, label %is_read_byte.exit22, label %bb.i21
bb.i21: ; preds = %is_read_byte.exit bb.i21: ; preds = %is_read_byte.exit
unreachable unreachable
is_read_byte.exit22: ; preds = %is_read_byte.exit is_read_byte.exit22: ; preds = %is_read_byte.exit
br i1 undef, label %is_read_byte.exit19, label %bb.i18 br i1 %c2, label %is_read_byte.exit19, label %bb.i18
bb.i18: ; preds = %is_read_byte.exit22 bb.i18: ; preds = %is_read_byte.exit22
br label %is_read_byte.exit19 br label %is_read_byte.exit19
is_read_byte.exit19: ; preds = %bb.i18, %is_read_byte.exit22 is_read_byte.exit19: ; preds = %bb.i18, %is_read_byte.exit22
br i1 undef, label %is_read_byte.exit16, label %bb.i15 br i1 %c3, label %is_read_byte.exit16, label %bb.i15
bb.i15: ; preds = %is_read_byte.exit19 bb.i15: ; preds = %is_read_byte.exit19
unreachable unreachable
is_read_byte.exit16: ; preds = %is_read_byte.exit19 is_read_byte.exit16: ; preds = %is_read_byte.exit19
%0 = shl i64 undef, 32 ; <i64> [#uses=1] %0 = shl i64 undef, 32 ; <i64> [#uses=1]
br i1 undef, label %is_read_byte.exit13, label %bb.i12 br i1 %c4, label %is_read_byte.exit13, label %bb.i12
bb.i12: ; preds = %is_read_byte.exit16 bb.i12: ; preds = %is_read_byte.exit16
unreachable unreachable
is_read_byte.exit13: ; preds = %is_read_byte.exit16 is_read_byte.exit13: ; preds = %is_read_byte.exit16
%1 = shl i64 undef, 24 ; <i64> [#uses=1] %1 = shl i64 undef, 24 ; <i64> [#uses=1]
br i1 undef, label %is_read_byte.exit10, label %bb.i9 br i1 %c5, label %is_read_byte.exit10, label %bb.i9
bb.i9: ; preds = %is_read_byte.exit13 bb.i9: ; preds = %is_read_byte.exit13
unreachable unreachable
is_read_byte.exit10: ; preds = %is_read_byte.exit13 is_read_byte.exit10: ; preds = %is_read_byte.exit13
%2 = shl i64 undef, 16 ; <i64> [#uses=1] %2 = shl i64 undef, 16 ; <i64> [#uses=1]
br i1 undef, label %is_read_byte.exit7, label %bb.i6 br i1 %c6, label %is_read_byte.exit7, label %bb.i6
bb.i6: ; preds = %is_read_byte.exit10 bb.i6: ; preds = %is_read_byte.exit10
br label %is_read_byte.exit7 br label %is_read_byte.exit7
is_read_byte.exit7: ; preds = %bb.i6, %is_read_byte.exit10 is_read_byte.exit7: ; preds = %bb.i6, %is_read_byte.exit10
%3 = shl i64 undef, 8 ; <i64> [#uses=1] %3 = shl i64 undef, 8 ; <i64> [#uses=1]
br i1 undef, label %is_read_byte.exit4, label %bb.i3 br i1 %c7, label %is_read_byte.exit4, label %bb.i3
bb.i3: ; preds = %is_read_byte.exit7 bb.i3: ; preds = %is_read_byte.exit7
unreachable unreachable
is_read_byte.exit4: ; preds = %is_read_byte.exit7 is_read_byte.exit4: ; preds = %is_read_byte.exit7
%4 = or i64 0, %0 ; <i64> [#uses=1] %4 = or i64 0, %0 ; <i64> [#uses=1]
%5 = or i64 %4, %1 ; <i64> [#uses=1] %5 = or i64 %4, %1 ; <i64> [#uses=1]
%6 = or i64 %5, %2 ; <i64> [#uses=1] %6 = or i64 %5, %2 ; <i64> [#uses=1]
%7 = or i64 %6, %3 ; <i64> [#uses=1] %7 = or i64 %6, %3 ; <i64> [#uses=1]
%8 = or i64 %7, 0 ; <i64> [#uses=1] %8 = or i64 %7, 0 ; <i64> [#uses=1]
ret i64 %8 ret i64 %8
} }

llvm/test/CodeGen/PowerPC/2016-01-07-BranchWeightCrash.ll

; RUN: llc <%s | FileCheck %s ; RUN: llc <%s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
%struct.buffer_t = type { i64, ptr, [4 x i32], [4 x i32], [4 x i32], i32, i8, i8, [2 x i8] } %struct.buffer_t = type { i64, ptr, [4 x i32], [4 x i32], [4 x i32], i32, i8, i8, [2 x i8] }
declare i32 @__f1(ptr, ptr noalias) declare i32 @__f1(ptr, ptr noalias)
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
define i32 @f1(ptr %__user_context, ptr noalias %f1.buffer) { define i32 @f1(ptr %__user_context, ptr noalias %f1.buffer, i1 %c0) {
entry: entry:
br i1 undef, label %"assert succeeded", label %"assert failed", !prof !1 br i1 %c0, label %"assert succeeded", label %"assert failed", !prof !1
"assert failed": ; preds = %entry "assert failed": ; preds = %entry
br label %destructor_block br label %destructor_block
"assert succeeded": ; preds = %entry "assert succeeded": ; preds = %entry
%__f1_result = call i32 @__f1(ptr %__user_context, ptr %f1.buffer) #5 %__f1_result = call i32 @__f1(ptr %__user_context, ptr %f1.buffer) #5
%0 = icmp eq i32 %__f1_result, 0 %0 = icmp eq i32 %__f1_result, 0
br i1 %0, label %"assert succeeded11", label %"assert failed10", !prof !1 br i1 %0, label %"assert succeeded11", label %"assert failed10", !prof !1
Show All 15 Lines

llvm/test/CodeGen/PowerPC/PR3488.ll

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
module asm "\09.section \22___kcrctab+free_reserved_area\22, \22a\22\09" module asm "\09.section \22___kcrctab+free_reserved_area\22, \22a\22\09"
module asm "\09.weak\09__crc_free_reserved_area\09" module asm "\09.weak\09__crc_free_reserved_area\09"
module asm "\09.long\09__crc_free_reserved_area\09" module asm "\09.long\09__crc_free_reserved_area\09"
module asm "\09.previous\09\09\09\09\09" module asm "\09.previous\09\09\09\09\09"
@nr_cpu_ids = external local_unnamed_addr global i32, align 4 @nr_cpu_ids = external local_unnamed_addr global i32, align 4
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @__alloc_pages_nodemask() #0 { define void @__alloc_pages_nodemask(i1 %c0) #0 {
entry: entry:
%0 = call i64 asm sideeffect "ld${1:U}${1:X} $0,$1", "=r,*m"(ptr elementtype(i64) undef) %0 = call i64 asm sideeffect "ld${1:U}${1:X} $0,$1", "=r,*m"(ptr elementtype(i64) undef)
br i1 undef, label %do.body.lr.ph.i.i.i, label %zone_page_state_snapshot.exit.i.i br i1 %c0, label %do.body.lr.ph.i.i.i, label %zone_page_state_snapshot.exit.i.i
; CHECK: ld 3, 0(3) ; CHECK: ld 3, 0(3)
do.body.lr.ph.i.i.i: ; preds = %entry do.body.lr.ph.i.i.i: ; preds = %entry
br label %do.body.i.i.i br label %do.body.i.i.i
do.body.i.i.i: ; preds = %do.body.i.i.i, %do.body.lr.ph.i.i.i do.body.i.i.i: ; preds = %do.body.i.i.i, %do.body.lr.ph.i.i.i
%x.022.i.i.i = phi i64 [ %0, %do.body.lr.ph.i.i.i ], [ %add7.i.i.i, %do.body.i.i.i ] %x.022.i.i.i = phi i64 [ %0, %do.body.lr.ph.i.i.i ], [ %add7.i.i.i, %do.body.i.i.i ]
%1 = load i8, ptr undef, align 1 %1 = load i8, ptr undef, align 1
Show All 11 Lines

llvm/test/CodeGen/PowerPC/aantidep-inline-asm-use.ll

; RUN: llc -O2 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -O2 -verify-machineinstrs < %s | FileCheck %s
; ModuleID = 'bugpoint-reduced-simplified.bc' ; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-grtev4-linux-gnu" target triple = "powerpc64le-grtev4-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_ZN10SubProcess19ScrubbedForkAndExecEiPiS0_PNS_7ResultsE() #0 align 2 { define void @_ZN10SubProcess19ScrubbedForkAndExecEiPiS0_PNS_7ResultsE(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18, i1 %c19, i1 %c20, i1 %c21, i1 %c22, i1 %c23, i1 %c24, i1 %c25, i1 %c26, i1 %c27, i1 %c28, i1 %c29, i1 %c30, i1 %c31, i1 %c32, i1 %c33, i1 %c34, i1 %c35, i1 %c36, i1 %c37, i1 %c38, i1 %c39, i1 %c40, i1 %c41, i1 %c42, i1 %c43, i1 %c44, i1 %c45, i1 %c46, i1 %c47) #0 align 2 {
; CHECK: lis 3, 1234 ; CHECK: lis 3, 1234
; CHECK-NOT: li 3 ; CHECK-NOT: li 3
; CHECK-NOT: ori 3 ; CHECK-NOT: ori 3
; CHECK-NOT: addi 3 ; CHECK-NOT: addi 3
; CHECK-NOT: addis 3 ; CHECK-NOT: addis 3
; CHECK-NOT: lis 3 ; CHECK-NOT: lis 3
; CHECK: sc ; CHECK: sc
br i1 undef, label %1, label %2 br i1 %c0, label %1, label %2
; <label>:1 ; preds = %0 ; <label>:1 ; preds = %0
br label %60 br label %60
; <label>:2 ; preds = %0 ; <label>:2 ; preds = %0
br i1 undef, label %3, label %4 br i1 %c1, label %3, label %4
; <label>:3 ; preds = %2 ; <label>:3 ; preds = %2
unreachable unreachable
; <label>:4 ; preds = %2 ; <label>:4 ; preds = %2
br i1 undef, label %.lr.ph111, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit br i1 %c2, label %.lr.ph111, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit
.lr.ph111: ; preds = %4 .lr.ph111: ; preds = %4
br label %5 br label %5
_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit: ; preds = %12, %4 _ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit: ; preds = %12, %4
br i1 undef, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader, label %13 br i1 %c3, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader, label %13
; <label>:5 ; preds = %12, %.lr.ph111 ; <label>:5 ; preds = %12, %.lr.ph111
br i1 undef, label %6, label %9 br i1 %c4, label %6, label %9
; <label>:6 ; preds = %5 ; <label>:6 ; preds = %5
br i1 undef, label %7, label %8 br i1 %c5, label %7, label %8
; <label>:7 ; preds = %6 ; <label>:7 ; preds = %6
unreachable unreachable
; <label>:8 ; preds = %6 ; <label>:8 ; preds = %6
br label %12 br label %12
; <label>:9 ; preds = %5 ; <label>:9 ; preds = %5
br i1 undef, label %10, label %11 br i1 %c6, label %10, label %11
; <label>:10 ; preds = %9 ; <label>:10 ; preds = %9
br label %12 br label %12
; <label>:11 ; preds = %9 ; <label>:11 ; preds = %9
br label %12 br label %12
; <label>:12 ; preds = %11, %10, %8 ; <label>:12 ; preds = %11, %10, %8
br i1 undef, label %5, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit br i1 %c7, label %5, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit
; <label>:13 ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit ; <label>:13 ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit
br i1 undef, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader, label %14 br i1 %c8, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader, label %14
; <label>:14 ; preds = %13 ; <label>:14 ; preds = %13
br label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader br label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader
_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader: ; preds = %14, %13, %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit _ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader: ; preds = %14, %13, %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit
br i1 undef, label %_ZN10SubProcess12SafeSyscalls5closeEi.exit.preheader, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge br i1 %c9, label %_ZN10SubProcess12SafeSyscalls5closeEi.exit.preheader, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge
_ZN10SubProcess12SafeSyscalls5closeEi.exit.preheader: ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19, %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader _ZN10SubProcess12SafeSyscalls5closeEi.exit.preheader: ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19, %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader
br label %_ZN10SubProcess12SafeSyscalls5closeEi.exit br label %_ZN10SubProcess12SafeSyscalls5closeEi.exit
_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge: ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19, %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader _ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge: ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19, %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader
br i1 undef, label %15, label %19 br i1 %c10, label %15, label %19
_ZN10SubProcess12SafeSyscalls5closeEi.exit: ; preds = %_ZN10SubProcess12SafeSyscalls5closeEi.exit, %_ZN10SubProcess12SafeSyscalls5closeEi.exit.preheader _ZN10SubProcess12SafeSyscalls5closeEi.exit: ; preds = %_ZN10SubProcess12SafeSyscalls5closeEi.exit, %_ZN10SubProcess12SafeSyscalls5closeEi.exit.preheader
br i1 undef, label %_ZN10SubProcess12SafeSyscalls5closeEi.exit, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19 br i1 %c11, label %_ZN10SubProcess12SafeSyscalls5closeEi.exit, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19
_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19: ; preds = %_ZN10SubProcess12SafeSyscalls5closeEi.exit _ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19: ; preds = %_ZN10SubProcess12SafeSyscalls5closeEi.exit
br i1 undef, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge, label %_ZN10SubProcess12SafeSyscalls5closeEi.exit.preheader br i1 %c12, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge, label %_ZN10SubProcess12SafeSyscalls5closeEi.exit.preheader
; <label>:15 ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge ; <label>:15 ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge
br label %16 br label %16
; <label>:16 ; preds = %17, %15 ; <label>:16 ; preds = %17, %15
br i1 undef, label %17, label %.critedge.preheader br i1 %c13, label %17, label %.critedge.preheader
; <label>:17 ; preds = %16 ; <label>:17 ; preds = %16
br i1 undef, label %16, label %.critedge.preheader br i1 %c14, label %16, label %.critedge.preheader
.critedge.preheader: ; preds = %17, %16 .critedge.preheader: ; preds = %17, %16
br label %.critedge br label %.critedge
.critedge: ; preds = %18, %.critedge.preheader .critedge: ; preds = %18, %.critedge.preheader
br i1 undef, label %18, label %.critedge8 br i1 %c15, label %18, label %.critedge8
; <label>:18 ; preds = %.critedge ; <label>:18 ; preds = %.critedge
br i1 undef, label %.critedge, label %.critedge8 br i1 %c16, label %.critedge, label %.critedge8
.critedge8: ; preds = %18, %.critedge .critedge8: ; preds = %18, %.critedge
br label %59 br label %59
; <label>:19 ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge ; <label>:19 ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge
br label %_ZN10SubProcess12SafeSyscalls5closeEi.exit22 br label %_ZN10SubProcess12SafeSyscalls5closeEi.exit22
_ZN10SubProcess12SafeSyscalls5closeEi.exit22: ; preds = %_ZN10SubProcess12SafeSyscalls5closeEi.exit22, %19 _ZN10SubProcess12SafeSyscalls5closeEi.exit22: ; preds = %_ZN10SubProcess12SafeSyscalls5closeEi.exit22, %19
br i1 undef, label %_ZN10SubProcess12SafeSyscalls5closeEi.exit22, label %20 br i1 %c17, label %_ZN10SubProcess12SafeSyscalls5closeEi.exit22, label %20
; <label>:20 ; preds = %_ZN10SubProcess12SafeSyscalls5closeEi.exit22 ; <label>:20 ; preds = %_ZN10SubProcess12SafeSyscalls5closeEi.exit22
%21 = alloca i8, i64 undef, align 1 %21 = alloca i8, i64 undef, align 1
br label %.thread.outer br label %.thread.outer
.thread.outer: ; preds = %._crit_edge, %20 .thread.outer: ; preds = %._crit_edge, %20
br label %.thread br label %.thread
.thread: ; preds = %45, %.thread.outer .thread: ; preds = %45, %.thread.outer
call void @llvm.memset.p0.i64(ptr align 8 undef, i8 0, i64 56, i1 false) call void @llvm.memset.p0.i64(ptr align 8 undef, i8 0, i64 56, i1 false)
store ptr %21, ptr undef, align 8 store ptr %21, ptr undef, align 8
store i32 1073741824, ptr undef, align 8 store i32 1073741824, ptr undef, align 8
%22 = call { i64, i64, i64, i64, i64, i64, i64 } asm sideeffect "sc\0A\09mfcr $0", "=&{r0},=&{r3},=&{r4},=&{r5},=&{r6},=&{r7},=&{r8},{r0},{r3},{r4},{r5},~{cr0},~{ctr},~{memory},~{r11},~{r12}"(i64 342, i64 80871424, i64 undef, i64 0) #2, !srcloc !1 %22 = call { i64, i64, i64, i64, i64, i64, i64 } asm sideeffect "sc\0A\09mfcr $0", "=&{r0},=&{r3},=&{r4},=&{r5},=&{r6},=&{r7},=&{r8},{r0},{r3},{r4},{r5},~{cr0},~{ctr},~{memory},~{r11},~{r12}"(i64 342, i64 80871424, i64 undef, i64 0) #2, !srcloc !1
br i1 undef, label %.lr.ph, label %.critedge15.preheader br i1 %c18, label %.lr.ph, label %.critedge15.preheader
.critedge15.preheader: ; preds = %_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge, %.thread .critedge15.preheader: ; preds = %_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge, %.thread
br i1 undef, label %.lr.ph93.preheader, label %.critedge15._crit_edge br i1 %c19, label %.lr.ph93.preheader, label %.critedge15._crit_edge
.lr.ph93.preheader: ; preds = %.critedge15.preheader .lr.ph93.preheader: ; preds = %.critedge15.preheader
br label %.lr.ph93 br label %.lr.ph93
.lr.ph: ; preds = %_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge, %.thread .lr.ph: ; preds = %_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge, %.thread
switch i32 undef, label %.critedge9 [ switch i32 undef, label %.critedge9 [
i32 11, label %_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge i32 11, label %_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge
i32 4, label %_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge i32 4, label %_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge
] ]
_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge: ; preds = %.lr.ph, %.lr.ph _ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge: ; preds = %.lr.ph, %.lr.ph
br i1 undef, label %.lr.ph, label %.critedge15.preheader br i1 %c20, label %.lr.ph, label %.critedge15.preheader
.critedge9: ; preds = %.lr.ph .critedge9: ; preds = %.lr.ph
unreachable unreachable
.critedge15._crit_edge: ; preds = %.critedge15, %.critedge15.preheader .critedge15._crit_edge: ; preds = %.critedge15, %.critedge15.preheader
br i1 undef, label %35, label %34 br i1 %c21, label %35, label %34
.lr.ph93: ; preds = %.critedge15, %.lr.ph93.preheader .lr.ph93: ; preds = %.critedge15, %.lr.ph93.preheader
switch i32 undef, label %33 [ switch i32 undef, label %33 [
i32 0, label %23 i32 0, label %23
i32 1, label %23 i32 1, label %23
i32 2, label %23 i32 2, label %23
i32 3, label %23 i32 3, label %23
i32 4, label %23 i32 4, label %23
i32 5, label %23 i32 5, label %23
i32 6, label %23 i32 6, label %23
i32 7, label %23 i32 7, label %23
i32 8, label %27 i32 8, label %27
i32 9, label %30 i32 9, label %30
] ]
; <label>:23 ; preds = %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93 ; <label>:23 ; preds = %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93
br i1 undef, label %24, label %.critedge15 br i1 %c22, label %24, label %.critedge15
; <label>:24 ; preds = %23 ; <label>:24 ; preds = %23
br i1 undef, label %.critedge15, label %25 br i1 %c23, label %.critedge15, label %25
; <label>:25 ; preds = %24 ; <label>:25 ; preds = %24
br i1 undef, label %.critedge15, label %26 br i1 %c24, label %.critedge15, label %26
; <label>:26 ; preds = %25 ; <label>:26 ; preds = %25
unreachable unreachable
; <label>:27 ; preds = %.lr.ph93 ; <label>:27 ; preds = %.lr.ph93
br i1 undef, label %.critedge15, label %28 br i1 %c25, label %.critedge15, label %28
; <label>:28 ; preds = %27 ; <label>:28 ; preds = %27
br i1 undef, label %29, label %.critedge15 br i1 %c26, label %29, label %.critedge15
; <label>:29 ; preds = %28 ; <label>:29 ; preds = %28
br label %.critedge15 br label %.critedge15
; <label>:30 ; preds = %.lr.ph93 ; <label>:30 ; preds = %.lr.ph93
br i1 undef, label %.critedge15, label %31 br i1 %c27, label %.critedge15, label %31
; <label>:31 ; preds = %30 ; <label>:31 ; preds = %30
br i1 undef, label %32, label %.critedge15 br i1 %c28, label %32, label %.critedge15
; <label>:32 ; preds = %31 ; <label>:32 ; preds = %31
br label %.critedge15 br label %.critedge15
; <label>:33 ; preds = %.lr.ph93 ; <label>:33 ; preds = %.lr.ph93
unreachable unreachable
.critedge15: ; preds = %32, %31, %30, %29, %28, %27, %25, %24, %23 .critedge15: ; preds = %32, %31, %30, %29, %28, %27, %25, %24, %23
br i1 undef, label %.lr.ph93, label %.critedge15._crit_edge br i1 %c29, label %.lr.ph93, label %.critedge15._crit_edge
; <label>:34 ; preds = %.critedge15._crit_edge ; <label>:34 ; preds = %.critedge15._crit_edge
unreachable unreachable
; <label>:35 ; preds = %.critedge15._crit_edge ; <label>:35 ; preds = %.critedge15._crit_edge
br i1 undef, label %45, label %36 br i1 %c30, label %45, label %36
; <label>:36 ; preds = %35 ; <label>:36 ; preds = %35
br i1 undef, label %37, label %38 br i1 %c31, label %37, label %38
; <label>:37 ; preds = %36 ; <label>:37 ; preds = %36
br i1 undef, label %.preheader, label %38 br i1 %c32, label %.preheader, label %38
.preheader: ; preds = %37 .preheader: ; preds = %37
br i1 undef, label %.lr.ph101, label %._crit_edge br i1 %c33, label %.lr.ph101, label %._crit_edge
.lr.ph101: ; preds = %.preheader .lr.ph101: ; preds = %.preheader
br label %39 br label %39
; <label>:38 ; preds = %37, %36 ; <label>:38 ; preds = %37, %36
unreachable unreachable
; <label>:39 ; preds = %43, %.lr.ph101 ; <label>:39 ; preds = %43, %.lr.ph101
br i1 undef, label %40, label %43 br i1 %c34, label %40, label %43
; <label>:40 ; preds = %39 ; <label>:40 ; preds = %39
br i1 undef, label %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit17, label %41 br i1 %c35, label %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit17, label %41
; <label>:41 ; preds = %40 ; <label>:41 ; preds = %40
unreachable unreachable
_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit17: ; preds = %40 _ZN10SubProcess12SafeSyscalls5fcntlEiil.exit17: ; preds = %40
br i1 undef, label %42, label %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit br i1 %c36, label %42, label %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit
; <label>:42 ; preds = %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit17 ; <label>:42 ; preds = %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit17
unreachable unreachable
_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit: ; preds = %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit17 _ZN10SubProcess12SafeSyscalls5fcntlEiil.exit: ; preds = %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit17
br i1 undef, label %.thread27, label %43 br i1 %c37, label %.thread27, label %43
; <label>:43 ; preds = %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit, %39 ; <label>:43 ; preds = %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit, %39
br i1 undef, label %39, label %._crit_edge br i1 %c38, label %39, label %._crit_edge
.thread27: ; preds = %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit .thread27: ; preds = %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit
br label %58 br label %58
._crit_edge: ; preds = %43, %.preheader ._crit_edge: ; preds = %43, %.preheader
br i1 undef, label %.thread.outer, label %44 br i1 %c39, label %.thread.outer, label %44
; <label>:44 ; preds = %._crit_edge ; <label>:44 ; preds = %._crit_edge
unreachable unreachable
; <label>:45 ; preds = %35 ; <label>:45 ; preds = %35
br i1 undef, label %46, label %.thread br i1 %c40, label %46, label %.thread
; <label>:46 ; preds = %45 ; <label>:46 ; preds = %45
br i1 undef, label %48, label %47 br i1 %c41, label %48, label %47
; <label>:47 ; preds = %46 ; <label>:47 ; preds = %46
unreachable unreachable
; <label>:48 ; preds = %46 ; <label>:48 ; preds = %46
br i1 undef, label %55, label %49 br i1 %c42, label %55, label %49
; <label>:49 ; preds = %48 ; <label>:49 ; preds = %48
br i1 undef, label %50, label %51 br i1 %c43, label %50, label %51
; <label>:50 ; preds = %49 ; <label>:50 ; preds = %49
br label %52 br label %52
; <label>:51 ; preds = %49 ; <label>:51 ; preds = %49
br label %52 br label %52
; <label>:52 ; preds = %51, %50 ; <label>:52 ; preds = %51, %50
br label %53 br label %53
; <label>:53 ; preds = %54, %52 ; <label>:53 ; preds = %54, %52
br i1 undef, label %54, label %.critedge13 br i1 %c44, label %54, label %.critedge13
; <label>:54 ; preds = %53 ; <label>:54 ; preds = %53
br i1 undef, label %53, label %.critedge13 br i1 %c45, label %53, label %.critedge13
.critedge13: ; preds = %54, %53 .critedge13: ; preds = %54, %53
br label %58 br label %58
; <label>:55 ; preds = %48 ; <label>:55 ; preds = %48
br label %56 br label %56
; <label>:56 ; preds = %57, %55 ; <label>:56 ; preds = %57, %55
br i1 undef, label %57, label %.critedge14 br i1 %c46, label %57, label %.critedge14
; <label>:57 ; preds = %56 ; <label>:57 ; preds = %56
br i1 undef, label %56, label %.critedge14 br i1 %c47, label %56, label %.critedge14
.critedge14: ; preds = %57, %56 .critedge14: ; preds = %57, %56
br label %58 br label %58
; <label>:58 ; preds = %.critedge14, %.critedge13, %.thread27 ; <label>:58 ; preds = %.critedge14, %.critedge13, %.thread27
br label %59 br label %59
; <label>:59 ; preds = %58, %.critedge8 ; <label>:59 ; preds = %58, %.critedge8
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llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 \ ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 \
; RUN: -verify-machineinstrs -O2 -mattr=vsx < %s | \ ; RUN: -verify-machineinstrs -O2 -mattr=vsx < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-AIX ; RUN: FileCheck %s --check-prefix=CHECK-AIX
; RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 \ ; RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
; RUN: -verify-machineinstrs -O2 -mattr=vsx < %s | \ ; RUN: -verify-machineinstrs -O2 -mattr=vsx < %s | \
; RUN: FileCheck %s ; RUN: FileCheck %s
define void @test_aix_splatimm(i32 %arg, i32 %arg1, i32 %arg2) { define void @test_aix_splatimm(i32 %arg, i32 %arg1, i32 %arg2, i1 %c0) {
; CHECK-AIX-LABEL: test_aix_splatimm: ; CHECK-AIX-LABEL: test_aix_splatimm:
; CHECK-AIX: # %bb.0: # %bb ; CHECK-AIX: # %bb.0: # %bb
; CHECK-AIX-NEXT: bclr 12, 20, 0 ; CHECK-AIX-NEXT: bclr 12, 20, 0
; CHECK-AIX-NEXT: # %bb.1: # %bb3 ; CHECK-AIX-NEXT: # %bb.1: # %bb3
; CHECK-AIX-NEXT: srwi 4, 4, 16 ; CHECK-AIX-NEXT: srwi 4, 4, 16
; CHECK-AIX-NEXT: srwi 5, 5, 16 ; CHECK-AIX-NEXT: srwi 5, 5, 16
; CHECK-AIX-NEXT: slwi 3, 3, 8 ; CHECK-AIX-NEXT: slwi 3, 3, 8
; CHECK-AIX-NEXT: mullw 4, 5, 4 ; CHECK-AIX-NEXT: mullw 4, 5, 4
Show All 30 Lines
; CHECK-NEXT: mullw 4, 4, 5 ; CHECK-NEXT: mullw 4, 4, 5
; CHECK-NEXT: vsplth 2, 2, 3 ; CHECK-NEXT: vsplth 2, 2, 3
; CHECK-NEXT: stxvd2x 34, 0, 3 ; CHECK-NEXT: stxvd2x 34, 0, 3
; CHECK-NEXT: neg 4, 4 ; CHECK-NEXT: neg 4, 4
; CHECK-NEXT: mtvsrd 35, 4 ; CHECK-NEXT: mtvsrd 35, 4
; CHECK-NEXT: vsplth 3, 3, 3 ; CHECK-NEXT: vsplth 3, 3, 3
; CHECK-NEXT: stxvd2x 35, 0, 3 ; CHECK-NEXT: stxvd2x 35, 0, 3
bb: bb:
br i1 undef, label %bb22, label %bb3 br i1 %c0, label %bb22, label %bb3
bb3: ; preds = %bb bb3: ; preds = %bb
%i = insertelement <8 x i16> undef, i16 0, i32 0 %i = insertelement <8 x i16> undef, i16 0, i32 0
%i4 = trunc i32 %arg to i16 %i4 = trunc i32 %arg to i16
%i5 = mul i16 %i4, -256 %i5 = mul i16 %i4, -256
%i6 = insertelement <8 x i16> %i, i16 %i5, i32 1 %i6 = insertelement <8 x i16> %i, i16 %i5, i32 1
%i7 = ashr i32 %arg1, 16 %i7 = ashr i32 %arg1, 16
%i8 = ashr i32 %arg2, 16 %i8 = ashr i32 %arg2, 16
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llvm/test/CodeGen/PowerPC/ashr-neg1.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @autogen_SD30723(i32) { define void @autogen_SD30723(i32, i1 %c0) {
BB: BB:
br label %CF80 br label %CF80
CF80: ; preds = %CF80, %BB CF80: ; preds = %CF80, %BB
%B = ashr i32 %0, -1 %B = ashr i32 %0, -1
br i1 undef, label %CF80, label %CF84 br i1 %c0, label %CF80, label %CF84
CF84: ; preds = %CF84, %CF80 CF84: ; preds = %CF84, %CF80
%Cmp62 = icmp sge i32 undef, %B %Cmp62 = icmp sge i32 undef, %B
br i1 %Cmp62, label %CF84, label %CF85 br i1 %Cmp62, label %CF84, label %CF85
CF85: ; preds = %CF85, %CF84 CF85: ; preds = %CF85, %CF84
br label %CF85 br label %CF85
} }

llvm/test/CodeGen/PowerPC/asym-regclass-copy.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; This tests that the GPRC/GPRC_NOR0 intersection subclass relationship with ; This tests that the GPRC/GPRC_NOR0 intersection subclass relationship with
; GPRC is handled correctly. When it was not, this test would assert. ; GPRC is handled correctly. When it was not, this test would assert.
@gen_random.last = external unnamed_addr global i64, align 8 @gen_random.last = external unnamed_addr global i64, align 8
@.str = external unnamed_addr constant [4 x i8], align 1 @.str = external unnamed_addr constant [4 x i8], align 1
declare double @gen_random(double) #0 declare double @gen_random(double) #0
declare void @benchmark_heapsort(i32 signext, ptr nocapture) #0 declare void @benchmark_heapsort(i32 signext, ptr nocapture) #0
define signext i32 @main(i32 signext %argc, ptr nocapture %argv) #0 { define signext i32 @main(i32 signext %argc, ptr nocapture %argv, i1 %c0, i1 %c1) #0 {
entry: entry:
br i1 undef, label %cond.true, label %cond.end br i1 %c0, label %cond.true, label %cond.end
cond.true: ; preds = %entry cond.true: ; preds = %entry
br label %cond.end br label %cond.end
cond.end: ; preds = %cond.true, %entry cond.end: ; preds = %cond.true, %entry
%cond = phi i32 [ 0, %cond.true ], [ 8000000, %entry ] %cond = phi i32 [ 0, %cond.true ], [ 8000000, %entry ]
%add = add i32 %cond, 1 %add = add i32 %cond, 1
%conv = sext i32 %add to i64 %conv = sext i32 %add to i64
%mul = shl nsw i64 %conv, 3 %mul = shl nsw i64 %conv, 3
%call1 = tail call noalias ptr @malloc(i64 %mul) #1 %call1 = tail call noalias ptr @malloc(i64 %mul) #1
br i1 undef, label %for.end, label %for.body.lr.ph br i1 %c1, label %for.end, label %for.body.lr.ph
for.body.lr.ph: ; preds = %cond.end for.body.lr.ph: ; preds = %cond.end
br label %for.body br label %for.body
for.body: ; preds = %for.body, %for.body.lr.ph for.body: ; preds = %for.body, %for.body.lr.ph
%indvars.iv = phi i64 [ 1, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ] %indvars.iv = phi i64 [ 1, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
%indvars.iv.next = add i64 %indvars.iv, 1 %indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
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llvm/test/CodeGen/PowerPC/bdzlr.ll

Show All 16 Lines
%union.TKey.5.680 = type { %struct.anon.0.4.679 } %union.TKey.5.680 = type { %struct.anon.0.4.679 }
%struct.anon.0.4.679 = type { %union.Value.16.691, i32, ptr } %struct.anon.0.4.679 = type { %union.Value.16.691, i32, ptr }
%union.TString.9.684 = type { %struct.anon.1.8.683 } %union.TString.9.684 = type { %struct.anon.1.8.683 }
%struct.anon.1.8.683 = type { ptr, i8, i8, i8, i32, i64 } %struct.anon.1.8.683 = type { ptr, i8, i8, i8, i32, i64 }
%struct.CallInfo.11.686 = type { ptr, ptr, ptr, ptr, i32, i32 } %struct.CallInfo.11.686 = type { ptr, ptr, ptr, ptr, i32, i32 }
%struct.lua_Debug.12.687 = type { i32, ptr, ptr, ptr, ptr, i32, i32, i32, i32, [60 x i8], i32 } %struct.lua_Debug.12.687 = type { i32, ptr, ptr, ptr, ptr, i32, i32, i32, i32, [60 x i8], i32 }
%struct.lua_longjmp.13.688 = type opaque %struct.lua_longjmp.13.688 = type opaque
define void @lua_xmove(i32 signext %n) #0 { define void @lua_xmove(i32 signext %n, i1 %c0, i1 %c1) #0 {
entry: entry:
br i1 undef, label %for.end, label %if.end br i1 %c0, label %for.end, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
br i1 undef, label %for.body.lr.ph, label %for.end br i1 %c1, label %for.body.lr.ph, label %for.end
for.body.lr.ph: ; preds = %if.end for.body.lr.ph: ; preds = %if.end
br label %for.body br label %for.body
for.body: ; preds = %for.body.for.body_crit_edge, %for.body.lr.ph for.body: ; preds = %for.body.for.body_crit_edge, %for.body.lr.ph
%0 = phi ptr [ undef, %for.body.lr.ph ], [ %.pre, %for.body.for.body_crit_edge ] %0 = phi ptr [ undef, %for.body.lr.ph ], [ %.pre, %for.body.for.body_crit_edge ]
%indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body.for.body_crit_edge ] %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body.for.body_crit_edge ]
%tt = getelementptr inbounds %struct.lua_TValue.17.692, ptr %0, i64 %indvars.iv, i32 1 %tt = getelementptr inbounds %struct.lua_TValue.17.692, ptr %0, i64 %indvars.iv, i32 1
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llvm/test/CodeGen/PowerPC/bv-pres-v8i1.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @autogen_SD70() { define void @autogen_SD70(i1 %c0, i1 %c1, i1 %c2, i1 %c3) {
BB: BB:
br label %CF78 br label %CF78
CF78: ; preds = %CF87, %CF78, %BB CF78: ; preds = %CF87, %CF78, %BB
br i1 undef, label %CF78, label %CF87 br i1 %c0, label %CF78, label %CF87
CF87: ; preds = %CF78 CF87: ; preds = %CF78
%Cmp19 = icmp sge <8 x i1> zeroinitializer, zeroinitializer %Cmp19 = icmp sge <8 x i1> zeroinitializer, zeroinitializer
%Cmp26 = icmp slt i32 -1, undef %Cmp26 = icmp slt i32 -1, undef
br i1 %Cmp26, label %CF78, label %CF79 br i1 %Cmp26, label %CF78, label %CF79
CF79: ; preds = %CF79, %CF87 CF79: ; preds = %CF79, %CF87
br i1 undef, label %CF79, label %CF82 br i1 %c1, label %CF79, label %CF82
CF82: ; preds = %CF82, %CF79 CF82: ; preds = %CF82, %CF79
br i1 undef, label %CF82, label %CF84 br i1 %c2, label %CF82, label %CF84
CF84: ; preds = %CF82 CF84: ; preds = %CF82
br label %CF br label %CF
CF: ; preds = %CF88, %CF, %CF84 CF: ; preds = %CF88, %CF, %CF84
br i1 undef, label %CF, label %CF85 br i1 %c3, label %CF, label %CF85
CF85: ; preds = %CF85, %CF CF85: ; preds = %CF85, %CF
%I52 = insertelement <8 x i1> %Cmp19, i1 %Cmp26, i32 6 %I52 = insertelement <8 x i1> %Cmp19, i1 %Cmp26, i32 6
%Cmp61 = icmp ult i32 477567, undef %Cmp61 = icmp ult i32 477567, undef
br i1 %Cmp61, label %CF85, label %CF88 br i1 %Cmp61, label %CF85, label %CF88
CF88: ; preds = %CF85 CF88: ; preds = %CF85
%E63 = extractelement <8 x i1> %I52, i32 5 %E63 = extractelement <8 x i1> %I52, i32 5
br i1 %E63, label %CF, label %CF80 br i1 %E63, label %CF, label %CF80
CF80: ; preds = %CF80, %CF88 CF80: ; preds = %CF80, %CF88
br label %CF80 br label %CF80
} }

llvm/test/CodeGen/PowerPC/bv-widen-undef.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @autogen_SD4357(i8) { define void @autogen_SD4357(i8, i1 %c0, i1 %c1) {
BB: BB:
br label %CF br label %CF
CF: ; preds = %CF, %BB CF: ; preds = %CF, %BB
br i1 undef, label %CF, label %CF77 br i1 %c0, label %CF, label %CF77
CF77: ; preds = %CF81, %CF77, %CF CF77: ; preds = %CF81, %CF77, %CF
%Shuff12 = shufflevector <2 x i8> <i8 -1, i8 -1>, <2 x i8> <i8 -1, i8 -1>, <2 x i32> <i32 0, i32 undef> %Shuff12 = shufflevector <2 x i8> <i8 -1, i8 -1>, <2 x i8> <i8 -1, i8 -1>, <2 x i32> <i32 0, i32 undef>
br i1 undef, label %CF77, label %CF80 br i1 %c1, label %CF77, label %CF80
CF80: ; preds = %CF80, %CF77 CF80: ; preds = %CF80, %CF77
%B21 = mul <2 x i8> %Shuff12, <i8 -1, i8 -1> %B21 = mul <2 x i8> %Shuff12, <i8 -1, i8 -1>
%Cmp24 = fcmp une ppc_fp128 0xM00000000000000000000000000000000, 0xM00000000000000000000000000000000 %Cmp24 = fcmp une ppc_fp128 0xM00000000000000000000000000000000, 0xM00000000000000000000000000000000
br i1 %Cmp24, label %CF80, label %CF81 br i1 %Cmp24, label %CF80, label %CF81
CF81: ; preds = %CF80 CF81: ; preds = %CF80
%I36 = insertelement <2 x i8> %B21, i8 %0, i32 0 %I36 = insertelement <2 x i8> %B21, i8 %0, i32 0
br label %CF77 br label %CF77
} }

llvm/test/CodeGen/PowerPC/cr-spills.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; This test case triggers several functions related to cr spilling, both in ; This test case triggers several functions related to cr spilling, both in
; frame lowering and to handle cr register pressure. When the register kill ; frame lowering and to handle cr register pressure. When the register kill
; flags were not being set correctly, this would cause the register scavenger to ; flags were not being set correctly, this would cause the register scavenger to
; assert. ; assert.
@SetupFastFullPelSearch.orig_pels = external unnamed_addr global [768 x i16], align 2 @SetupFastFullPelSearch.orig_pels = external unnamed_addr global [768 x i16], align 2
@weight_luma = external global i32 @weight_luma = external global i32
@offset_luma = external global i32 @offset_luma = external global i32
@wp_luma_round = external global i32, align 4 @wp_luma_round = external global i32, align 4
@luma_log_weight_denom = external global i32, align 4 @luma_log_weight_denom = external global i32, align 4
define void @SetupFastFullPelSearch() #0 { define void @SetupFastFullPelSearch(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14) #0 {
entry: entry:
%mul10 = mul nsw i32 undef, undef %mul10 = mul nsw i32 undef, undef
br i1 undef, label %land.end, label %land.lhs.true br i1 %c0, label %land.end, label %land.lhs.true
land.lhs.true: ; preds = %entry land.lhs.true: ; preds = %entry
switch i32 0, label %land.end [ switch i32 0, label %land.end [
i32 0, label %land.rhs i32 0, label %land.rhs
i32 3, label %land.rhs i32 3, label %land.rhs
] ]
land.rhs: ; preds = %land.lhs.true, %land.lhs.true land.rhs: ; preds = %land.lhs.true, %land.lhs.true
%tobool21 = icmp ne i32 undef, 0 %tobool21 = icmp ne i32 undef, 0
br label %land.end br label %land.end
land.end: ; preds = %land.rhs, %land.lhs.true, %entry land.end: ; preds = %land.rhs, %land.lhs.true, %entry
%0 = phi i1 [ %tobool21, %land.rhs ], [ false, %land.lhs.true ], [ false, %entry ] %0 = phi i1 [ %tobool21, %land.rhs ], [ false, %land.lhs.true ], [ false, %entry ]
%cond = load ptr, ptr undef, align 8 %cond = load ptr, ptr undef, align 8
br i1 undef, label %if.then95, label %for.body.lr.ph br i1 %c1, label %if.then95, label %for.body.lr.ph
if.then95: ; preds = %land.end if.then95: ; preds = %land.end
%cmp.i4.i1427 = icmp slt i32 undef, undef %cmp.i4.i1427 = icmp slt i32 undef, undef
br label %for.body.lr.ph br label %for.body.lr.ph
for.body.lr.ph: ; preds = %if.then95, %land.end for.body.lr.ph: ; preds = %if.then95, %land.end
br label %for.body br label %for.body
for.body: ; preds = %for.body, %for.body.lr.ph for.body: ; preds = %for.body, %for.body.lr.ph
br i1 undef, label %for.body, label %for.body252 br i1 %c2, label %for.body, label %for.body252
for.body252: ; preds = %for.inc997, %for.body for.body252: ; preds = %for.inc997, %for.body
%shl263 = add i32 undef, 80 %shl263 = add i32 undef, 80
br i1 %0, label %for.cond286.preheader, label %for.cond713.preheader br i1 %0, label %for.cond286.preheader, label %for.cond713.preheader
for.cond286.preheader: ; preds = %for.body252 for.cond286.preheader: ; preds = %for.body252
br label %for.cond290.preheader br label %for.cond290.preheader
▲ Show 20 Lines • Show All 272 Lines • ▼ Show 20 Linesfor.body293: ; preds = %for.body293, %for.cond290.preheader
%exitcond1692 = icmp eq i32 undef, 4 %exitcond1692 = icmp eq i32 undef, 4
br i1 %exitcond1692, label %for.end520, label %for.body293 br i1 %exitcond1692, label %for.end520, label %for.body293
for.end520: ; preds = %for.body293 for.end520: ; preds = %for.body293
store i32 %add346, ptr undef, align 4 store i32 %add346, ptr undef, align 4
store i32 %add402, ptr undef, align 4 store i32 %add402, ptr undef, align 4
store i32 %add458, ptr undef, align 4 store i32 %add458, ptr undef, align 4
store i32 %add514, ptr null, align 4 store i32 %add514, ptr null, align 4
br i1 undef, label %for.end543, label %for.cond290.preheader br i1 %c3, label %for.end543, label %for.cond290.preheader
for.end543: ; preds = %for.end520 for.end543: ; preds = %for.end520
br i1 undef, label %for.inc997, label %for.body549 br i1 %c4, label %for.inc997, label %for.body549
for.body549: ; preds = %for.inc701, %for.end543 for.body549: ; preds = %for.inc701, %for.end543
%call554 = call ptr null(ptr null, i32 signext undef, i32 signext %shl263) #1 %call554 = call ptr null(ptr null, i32 signext undef, i32 signext %shl263) #1
br label %for.cond559.preheader br label %for.cond559.preheader
for.cond559.preheader: ; preds = %for.cond559.preheader, %for.body549 for.cond559.preheader: ; preds = %for.cond559.preheader, %for.body549
br i1 undef, label %for.inc701, label %for.cond559.preheader br i1 %c5, label %for.inc701, label %for.cond559.preheader
for.inc701: ; preds = %for.cond559.preheader for.inc701: ; preds = %for.cond559.preheader
br i1 undef, label %for.inc997, label %for.body549 br i1 %c6, label %for.inc997, label %for.body549
for.cond713.preheader: ; preds = %for.end850, %for.body252 for.cond713.preheader: ; preds = %for.end850, %for.body252
br label %for.body716 br label %for.body716
for.body716: ; preds = %for.body716, %for.cond713.preheader for.body716: ; preds = %for.body716, %for.cond713.preheader
br i1 undef, label %for.end850, label %for.body716 br i1 %c7, label %for.end850, label %for.body716
for.end850: ; preds = %for.body716 for.end850: ; preds = %for.body716
br i1 undef, label %for.end873, label %for.cond713.preheader br i1 %c8, label %for.end873, label %for.cond713.preheader
for.end873: ; preds = %for.end850 for.end873: ; preds = %for.end850
br i1 undef, label %for.inc997, label %for.body879 br i1 %c9, label %for.inc997, label %for.body879
for.body879: ; preds = %for.inc992, %for.end873 for.body879: ; preds = %for.inc992, %for.end873
br label %for.cond889.preheader br label %for.cond889.preheader
for.cond889.preheader: ; preds = %for.end964, %for.body879 for.cond889.preheader: ; preds = %for.end964, %for.body879
br i1 undef, label %for.cond894.preheader.lr.ph, label %for.end964 br i1 %c10, label %for.cond894.preheader.lr.ph, label %for.end964
for.cond894.preheader.lr.ph: ; preds = %for.cond889.preheader for.cond894.preheader.lr.ph: ; preds = %for.cond889.preheader
br label %for.body898.lr.ph.us br label %for.body898.lr.ph.us
for.end957.us: ; preds = %for.body946.us for.end957.us: ; preds = %for.body946.us
br i1 undef, label %for.body898.lr.ph.us, label %for.end964 br i1 %c11, label %for.body898.lr.ph.us, label %for.end964
for.body946.us: ; preds = %for.body930.us, %for.body946.us for.body946.us: ; preds = %for.body930.us, %for.body946.us
br i1 false, label %for.body946.us, label %for.end957.us br i1 false, label %for.body946.us, label %for.end957.us
for.body930.us: ; preds = %for.body914.us, %for.body930.us for.body930.us: ; preds = %for.body914.us, %for.body930.us
br i1 undef, label %for.body930.us, label %for.body946.us br i1 %c12, label %for.body930.us, label %for.body946.us
for.body914.us: ; preds = %for.body898.us, %for.body914.us for.body914.us: ; preds = %for.body898.us, %for.body914.us
br i1 undef, label %for.body914.us, label %for.body930.us br i1 %c13, label %for.body914.us, label %for.body930.us
for.body898.us: ; preds = %for.body898.lr.ph.us, %for.body898.us for.body898.us: ; preds = %for.body898.lr.ph.us, %for.body898.us
br i1 undef, label %for.body898.us, label %for.body914.us br i1 %c14, label %for.body898.us, label %for.body914.us
for.body898.lr.ph.us: ; preds = %for.end957.us, %for.cond894.preheader.lr.ph for.body898.lr.ph.us: ; preds = %for.end957.us, %for.cond894.preheader.lr.ph
br label %for.body898.us br label %for.body898.us
for.end964: ; preds = %for.end957.us, %for.cond889.preheader for.end964: ; preds = %for.end957.us, %for.cond889.preheader
%inc990 = add nsw i32 undef, 1 %inc990 = add nsw i32 undef, 1
br i1 false, label %for.inc992, label %for.cond889.preheader br i1 false, label %for.inc992, label %for.cond889.preheader
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llvm/test/CodeGen/PowerPC/ctr-cleanup.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=a2 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mcpu=a2 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @main() #0 { define void @main(i1 %c0) #0 {
entry: entry:
br i1 undef, label %for.end, label %for.body br i1 %c0, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ] %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ]
%indvars.iv.next = add i64 %indvars.iv, 1 %indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 5 %exitcond = icmp eq i32 %lftr.wideiv, 5
br i1 %exitcond, label %for.end, label %for.body br i1 %exitcond, label %for.end, label %for.body
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llvm/test/CodeGen/PowerPC/ctrloop-large-ec.ll

; RUN: llc -mcpu=ppc32 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mcpu=ppc32 -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
target triple = "powerpc-unknown-linux-gnu" target triple = "powerpc-unknown-linux-gnu"
define void @fn1() { define void @fn1(i1 %c0) {
entry: entry:
br i1 undef, label %for.end, label %for.body br i1 %c0, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%inc3 = phi i64 [ %inc, %for.body ], [ undef, %entry ] %inc3 = phi i64 [ %inc, %for.body ], [ undef, %entry ]
%inc = add nsw i64 %inc3, 1 %inc = add nsw i64 %inc3, 1
%tobool = icmp eq i64 %inc, 0 %tobool = icmp eq i64 %inc, 0
br i1 %tobool, label %for.end, label %for.body br i1 %tobool, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry for.end: ; preds = %for.body, %entry
ret void ret void
} }
; On PPC32, CTR is also 32 bits, and so cannot hold a 64-bit count. ; On PPC32, CTR is also 32 bits, and so cannot hold a 64-bit count.
; CHECK: @fn1 ; CHECK: @fn1
; CHECK-NOT: mtctr ; CHECK-NOT: mtctr
; CHECK: blr ; CHECK: blr

llvm/test/CodeGen/PowerPC/ctrloop-reg.ll

Show All 38 Lines
declare i32 @zpop(ptr) declare i32 @zpop(ptr)
declare i32 @zsub(ptr) declare i32 @zsub(ptr)
declare void @interp_init(i32) nounwind declare void @interp_init(i32) nounwind
declare void @interp_fix_op(ptr nocapture) nounwind declare void @interp_fix_op(ptr nocapture) nounwind
define i32 @interpret(ptr %pref, i32 %user_errors) nounwind { define i32 @interpret(ptr %pref, i32 %user_errors, i1 %c0) nounwind {
entry: entry:
%erref = alloca %struct.ref_s.1.49.91.115.121.139.145.151.157.163.169.175.181.211, align 8 %erref = alloca %struct.ref_s.1.49.91.115.121.139.145.151.157.163.169.175.181.211, align 8
br i1 undef, label %retry.us, label %retry br i1 %c0, label %retry.us, label %retry
retry.us: ; preds = %if.end18, %retry, %retry, %retry, %retry, %entry retry.us: ; preds = %if.end18, %retry, %retry, %retry, %retry, %entry
ret i32 undef ret i32 undef
retry: ; preds = %if.end18, %entry retry: ; preds = %if.end18, %entry
%0 = phi ptr [ null, %entry ], [ %erref, %if.end18 ] %0 = phi ptr [ null, %entry ], [ %erref, %if.end18 ]
%call = call i32 @interp(ptr %0) %call = call i32 @interp(ptr %0)
switch i32 %call, label %if.end18 [ switch i32 %call, label %if.end18 [
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llvm/test/CodeGen/PowerPC/ctrloop-udivti3.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define hidden void @_mpd_shortdiv(i64 %n) #0 { define hidden void @_mpd_shortdiv(i64 %n, i1 %c0) #0 {
entry: entry:
br i1 undef, label %for.end, label %for.body.lr.ph br i1 %c0, label %for.end, label %for.body.lr.ph
for.body.lr.ph: ; preds = %entry for.body.lr.ph: ; preds = %entry
br label %for.body br label %for.body
for.body: ; preds = %for.body, %for.body.lr.ph for.body: ; preds = %for.body, %for.body.lr.ph
%i.018.in = phi i64 [ %n, %for.body.lr.ph ], [ %i.018, %for.body ] %i.018.in = phi i64 [ %n, %for.body.lr.ph ], [ %i.018, %for.body ]
%i.018 = add i64 %i.018.in, -1 %i.018 = add i64 %i.018.in, -1
%jj = sext i64 %i.018 to i128 %jj = sext i64 %i.018 to i128
Show All 16 Lines

llvm/test/CodeGen/PowerPC/early-ret2.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-CRB ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-CRB
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @_Z8example3iPiS_() #0 { define void @_Z8example3iPiS_(i1 %c0, i1 %c1) #0 {
entry: entry:
br i1 undef, label %while.end, label %while.body.lr.ph br i1 %c0, label %while.end, label %while.body.lr.ph
while.body.lr.ph: ; preds = %entry while.body.lr.ph: ; preds = %entry
br i1 undef, label %while.end, label %while.body br i1 %c1, label %while.end, label %while.body
while.body: ; preds = %while.body, %while.body.lr.ph while.body: ; preds = %while.body, %while.body.lr.ph
br i1 false, label %while.end, label %while.body, !llvm.loop.vectorize.already_vectorized !0 br i1 false, label %while.end, label %while.body, !llvm.loop.vectorize.already_vectorized !0
while.end: ; preds = %while.body, %while.body.lr.ph, %entry while.end: ; preds = %while.body, %while.body.lr.ph, %entry
ret void ret void
; CHECK: @_Z8example3iPiS_ ; CHECK: @_Z8example3iPiS_
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llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll

Show All 15 Lines
; updated: 416B %vreg18<def> = ISEL8 %vreg5, %vreg5, %vreg15<undef>; ; updated: 416B %vreg18<def> = ISEL8 %vreg5, %vreg5, %vreg15<undef>;
; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=true < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE ; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=true < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE
; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel ; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel
%"struct.pov::ot_block_struct" = type { %"struct.pov::ot_block_struct"*, [3 x double], [3 x double], float, float, float, float, float, float, float, float, float, [3 x float], float, float, [3 x double], i16 } %"struct.pov::ot_block_struct" = type { %"struct.pov::ot_block_struct"*, [3 x double], [3 x double], float, float, float, float, float, float, float, float, float, [3 x float], float, float, [3 x double], i16 }
%"struct.pov::ot_node_struct" = type { %"struct.pov::ot_id_struct", %"struct.pov::ot_block_struct"*, [8 x %"struct.pov::ot_node_struct"*] } %"struct.pov::ot_node_struct" = type { %"struct.pov::ot_id_struct", %"struct.pov::ot_block_struct"*, [8 x %"struct.pov::ot_node_struct"*] }
%"struct.pov::ot_id_struct" = type { i32, i32, i32, i32 } %"struct.pov::ot_id_struct" = type { i32, i32, i32, i32 }
define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE(%"struct.pov::ot_block_struct"* %new_block) { define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE(%"struct.pov::ot_block_struct"* %new_block, i1 %c0) {
; CHECK-GEN-ISEL-TRUE-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE: ; CHECK-GEN-ISEL-TRUE-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE:
; CHECK-GEN-ISEL-TRUE: # %bb.0: # %entry ; CHECK-GEN-ISEL-TRUE: # %bb.0: # %entry
; CHECK-GEN-ISEL-TRUE-NEXT: mflr r0 ; CHECK-GEN-ISEL-TRUE-NEXT: mflr r0
; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_def_cfa_offset 64 ; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_def_cfa_offset 64
; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset lr, 16 ; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset lr, 16
; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset r29, -24 ; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset r29, -24
; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset r30, -16 ; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset r30, -16
; CHECK-GEN-ISEL-TRUE-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-GEN-ISEL-TRUE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lineslor.rhs:
%Values = getelementptr inbounds %"struct.pov::ot_node_struct", %"struct.pov::ot_node_struct"* %this_node.0250, i64 0, i32 1 %Values = getelementptr inbounds %"struct.pov::ot_node_struct", %"struct.pov::ot_node_struct"* %this_node.0250, i64 0, i32 1
store %"struct.pov::ot_block_struct"* %new_block, %"struct.pov::ot_block_struct"** %Values, align 8 store %"struct.pov::ot_block_struct"* %new_block, %"struct.pov::ot_block_struct"** %Values, align 8
ret void ret void
while.body21: while.body21:
%call.i84 = tail call i8* @ZN3pov10pov_callocEmmPKciS1_pov() %call.i84 = tail call i8* @ZN3pov10pov_callocEmmPKciS1_pov()
store i8* %call.i84, i8** undef, align 8 store i8* %call.i84, i8** undef, align 8
%1 = bitcast i8* %call.i84 to %"struct.pov::ot_node_struct"* %1 = bitcast i8* %call.i84 to %"struct.pov::ot_node_struct"*
br i1 undef, label %cond.true18.i153, label %cond.false21.i156 br i1 %c0, label %cond.true18.i153, label %cond.false21.i156
cond.true18.i153: cond.true18.i153:
%shr2039.i152 = lshr i32 %temp_id.sroa.21.1, 1 %shr2039.i152 = lshr i32 %temp_id.sroa.21.1, 1
br label %while.cond11 br label %while.cond11
cond.false21.i156: cond.false21.i156:
%add23.i154 = add nsw i32 %temp_id.sroa.21.1, 1 %add23.i154 = add nsw i32 %temp_id.sroa.21.1, 1
%div24.i155 = sdiv i32 %add23.i154, 2 %div24.i155 = sdiv i32 %add23.i154, 2
br label %while.cond11 br label %while.cond11
} }
declare i8* @ZN3pov10pov_callocEmmPKciS1_pov() declare i8* @ZN3pov10pov_callocEmmPKciS1_pov()

llvm/test/CodeGen/PowerPC/ext-bool-trunc-repl.ll

; RUN: llc -verify-machineinstrs -O0 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -O0 < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
@c = external global i32, align 4 @c = external global i32, align 4
@d = external global [2 x i32], align 4 @d = external global [2 x i32], align 4
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @fn2() #0 { define void @fn2(i1 %c0, i1 %c1, i1 %c2, i1 %c3) #0 {
; CHECK-LABEL: @fn2 ; CHECK-LABEL: @fn2
br i1 undef, label %1, label %10 br i1 %c0, label %1, label %10
; <label>:1: ; preds = %0 ; <label>:1: ; preds = %0
br i1 undef, label %3, label %2 br i1 %c1, label %3, label %2
; <label>:2: ; preds = %2, %1 ; <label>:2: ; preds = %2, %1
br i1 undef, label %3, label %2 br i1 %c2, label %3, label %2
; <label>:3: ; preds = %2, %1 ; <label>:3: ; preds = %2, %1
br i1 undef, label %8, label %4 br i1 %c3, label %8, label %4
; <label>:4: ; preds = %4, %3 ; <label>:4: ; preds = %4, %3
%5 = phi i64 [ %6, %4 ], [ undef, %3 ] %5 = phi i64 [ %6, %4 ], [ undef, %3 ]
%6 = and i64 %5, and (i64 and (i64 and (i64 and (i64 and (i64 and (i64 and (i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)) %6 = and i64 %5, and (i64 and (i64 and (i64 and (i64 and (i64 and (i64 and (i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i16), i16 0), i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 lshr (i32 zext (i1 icmp eq (ptr getelementptr inbounds ([2 x i32], ptr @d, i64 0, i64 1), ptr @c) to i32), i32 6)) to i64))
%7 = icmp slt i32 undef, 6 %7 = icmp slt i32 undef, 6
br i1 %7, label %4, label %8 br i1 %7, label %4, label %8
; <label>:8: ; preds = %4, %3 ; <label>:8: ; preds = %4, %3
Show All 9 Lines

llvm/test/CodeGen/PowerPC/extra-toc-reg-deps.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
%"class.Foam::VectorSpace.10" = type { [3 x double] } %"class.Foam::VectorSpace.10" = type { [3 x double] }
%"class.Foam::Ostream.189" = type <{ %"class.Foam::IOstream.8", i16, [6 x i8] }> %"class.Foam::Ostream.189" = type <{ %"class.Foam::IOstream.8", i16, [6 x i8] }>
@_ZN4Foam4InfoE = external global %"class.Foam::messageStream.6", align 8 @_ZN4Foam4InfoE = external global %"class.Foam::messageStream.6", align 8
@.str27 = external unnamed_addr constant [24 x i8], align 1 @.str27 = external unnamed_addr constant [24 x i8], align 1
@.str28 = external unnamed_addr constant [7 x i8], align 1 @.str28 = external unnamed_addr constant [7 x i8], align 1
@_ZN4Foam4PoutE = external global %"class.Foam::prefixOSstream.27", align 8 @_ZN4Foam4PoutE = external global %"class.Foam::prefixOSstream.27", align 8
define void @_ZN4Foam13checkTopologyERKNS_8polyMeshEbb(i1 zeroext %allTopology) #0 personality ptr @__gxx_personality_v0 { define void @_ZN4Foam13checkTopologyERKNS_8polyMeshEbb(i1 zeroext %allTopology, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18, i1 %c19, i1 %c20, i1 %c21, i1 %c22) #0 personality ptr @__gxx_personality_v0 {
entry: entry:
br i1 undef, label %for.body, label %for.cond.cleanup br i1 %c0, label %for.body, label %for.cond.cleanup
; CHECK-LABEL: @_ZN4Foam13checkTopologyERKNS_8polyMeshEbb ; CHECK-LABEL: @_ZN4Foam13checkTopologyERKNS_8polyMeshEbb
; CHECK: addis [[REG1:[0-9]+]], 2, .LC0@toc@ha ; CHECK: addis [[REG1:[0-9]+]], 2, .LC0@toc@ha
; CHECK: std 2, 40(1) ; CHECK: std 2, 40(1)
; CHECK: ld {{[0-9]+}}, .LC0@toc@l([[REG1]]) ; CHECK: ld {{[0-9]+}}, .LC0@toc@l([[REG1]])
; CHECK: {{mr|ld}} 2, ; CHECK: {{mr|ld}} 2,
; CHECK: mtctr ; CHECK: mtctr
; CHECK: bctrl ; CHECK: bctrl
; CHECK: ld 2, 40(1) ; CHECK: ld 2, 40(1)
; CHECK: std 2, 40(1) ; CHECK: std 2, 40(1)
; CHECK: {{mr|ld}} 2, ; CHECK: {{mr|ld}} 2,
; CHECK: mtctr ; CHECK: mtctr
; CHECK: bctrl ; CHECK: bctrl
; CHECK: ld 2, 40(1) ; CHECK: ld 2, 40(1)
for.cond.cleanup: ; preds = %entry for.cond.cleanup: ; preds = %entry
br i1 undef, label %if.then.i, label %if.else.i br i1 %c1, label %if.then.i, label %if.else.i
if.then.i: ; preds = %for.cond.cleanup if.then.i: ; preds = %for.cond.cleanup
br i1 undef, label %if.then.i1435, label %if.else.i1436 br i1 %c2, label %if.then.i1435, label %if.else.i1436
if.else.i: ; preds = %for.cond.cleanup if.else.i: ; preds = %for.cond.cleanup
unreachable unreachable
if.then.i1435: ; preds = %if.then.i if.then.i1435: ; preds = %if.then.i
br label %_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit br label %_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit
if.else.i1436: ; preds = %if.then.i if.else.i1436: ; preds = %if.then.i
br label %_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit br label %_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit
_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit: ; preds = %if.else.i1436, %if.then.i1435 _ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit: ; preds = %if.else.i1436, %if.then.i1435
br i1 undef, label %for.body.i, label %_ZNK4Foam8ZoneMeshINS_8cellZoneENS_8polyMeshEE15checkDefinitionEb.exit br i1 %c3, label %for.body.i, label %_ZNK4Foam8ZoneMeshINS_8cellZoneENS_8polyMeshEE15checkDefinitionEb.exit
for.body: ; preds = %entry for.body: ; preds = %entry
unreachable unreachable
for.body.i: ; preds = %_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit for.body.i: ; preds = %_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit
unreachable unreachable
_ZNK4Foam8ZoneMeshINS_8cellZoneENS_8polyMeshEE15checkDefinitionEb.exit: ; preds = %_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit _ZNK4Foam8ZoneMeshINS_8cellZoneENS_8polyMeshEE15checkDefinitionEb.exit: ; preds = %_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit
br i1 undef, label %for.body.i1480, label %_ZNK4Foam8ZoneMeshINS_8faceZoneENS_8polyMeshEE15checkDefinitionEb.exit br i1 %c4, label %for.body.i1480, label %_ZNK4Foam8ZoneMeshINS_8faceZoneENS_8polyMeshEE15checkDefinitionEb.exit
for.body.i1480: ; preds = %_ZNK4Foam8ZoneMeshINS_8cellZoneENS_8polyMeshEE15checkDefinitionEb.exit for.body.i1480: ; preds = %_ZNK4Foam8ZoneMeshINS_8cellZoneENS_8polyMeshEE15checkDefinitionEb.exit
unreachable unreachable
_ZNK4Foam8ZoneMeshINS_8faceZoneENS_8polyMeshEE15checkDefinitionEb.exit: ; preds = %_ZNK4Foam8ZoneMeshINS_8cellZoneENS_8polyMeshEE15checkDefinitionEb.exit _ZNK4Foam8ZoneMeshINS_8faceZoneENS_8polyMeshEE15checkDefinitionEb.exit: ; preds = %_ZNK4Foam8ZoneMeshINS_8cellZoneENS_8polyMeshEE15checkDefinitionEb.exit
br i1 undef, label %for.body.i1504, label %_ZNK4Foam8ZoneMeshINS_9pointZoneENS_8polyMeshEE15checkDefinitionEb.exit br i1 %c5, label %for.body.i1504, label %_ZNK4Foam8ZoneMeshINS_9pointZoneENS_8polyMeshEE15checkDefinitionEb.exit
for.body.i1504: ; preds = %_ZNK4Foam8ZoneMeshINS_8faceZoneENS_8polyMeshEE15checkDefinitionEb.exit for.body.i1504: ; preds = %_ZNK4Foam8ZoneMeshINS_8faceZoneENS_8polyMeshEE15checkDefinitionEb.exit
unreachable unreachable
_ZNK4Foam8ZoneMeshINS_9pointZoneENS_8polyMeshEE15checkDefinitionEb.exit: ; preds = %_ZNK4Foam8ZoneMeshINS_8faceZoneENS_8polyMeshEE15checkDefinitionEb.exit _ZNK4Foam8ZoneMeshINS_9pointZoneENS_8polyMeshEE15checkDefinitionEb.exit: ; preds = %_ZNK4Foam8ZoneMeshINS_8faceZoneENS_8polyMeshEE15checkDefinitionEb.exit
invoke void @_ZN4Foam4word12stripInvalidEv() invoke void @_ZN4Foam4word12stripInvalidEv()
to label %_ZN4Foam4wordC2EPKcb.exit unwind label %lpad.i to label %_ZN4Foam4wordC2EPKcb.exit unwind label %lpad.i
lpad.i: ; preds = %_ZNK4Foam8ZoneMeshINS_9pointZoneENS_8polyMeshEE15checkDefinitionEb.exit lpad.i: ; preds = %_ZNK4Foam8ZoneMeshINS_9pointZoneENS_8polyMeshEE15checkDefinitionEb.exit
%0 = landingpad { ptr, i32 } %0 = landingpad { ptr, i32 }
cleanup cleanup
resume { ptr, i32 } %0 resume { ptr, i32 } %0
_ZN4Foam4wordC2EPKcb.exit: ; preds = %_ZNK4Foam8ZoneMeshINS_9pointZoneENS_8polyMeshEE15checkDefinitionEb.exit _ZN4Foam4wordC2EPKcb.exit: ; preds = %_ZNK4Foam8ZoneMeshINS_9pointZoneENS_8polyMeshEE15checkDefinitionEb.exit
invoke void @_ZN4Foam7cellSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE() invoke void @_ZN4Foam7cellSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE()
to label %invoke.cont59 unwind label %lpad to label %invoke.cont59 unwind label %lpad
invoke.cont59: ; preds = %_ZN4Foam4wordC2EPKcb.exit invoke.cont59: ; preds = %_ZN4Foam4wordC2EPKcb.exit
br i1 undef, label %_ZNSsD2Ev.exit, label %if.then.i.i, !prof !1 br i1 %c6, label %_ZNSsD2Ev.exit, label %if.then.i.i, !prof !1
if.then.i.i: ; preds = %invoke.cont59 if.then.i.i: ; preds = %invoke.cont59
br i1 true, label %if.then.i.i.i1508, label %if.else.i.i.i br i1 true, label %if.then.i.i.i1508, label %if.else.i.i.i
if.then.i.i.i1508: ; preds = %if.then.i.i if.then.i.i.i1508: ; preds = %if.then.i.i
br label %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i br label %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i
if.else.i.i.i: ; preds = %if.then.i.i if.else.i.i.i: ; preds = %if.then.i.i
br label %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i br label %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i
_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i: ; preds = %if.else.i.i.i, %if.then.i.i.i1508 _ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i: ; preds = %if.else.i.i.i, %if.then.i.i.i1508
br i1 undef, label %if.then4.i.i, label %_ZNSsD2Ev.exit br i1 %c7, label %if.then4.i.i, label %_ZNSsD2Ev.exit
if.then4.i.i: ; preds = %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i if.then4.i.i: ; preds = %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i
br label %_ZNSsD2Ev.exit br label %_ZNSsD2Ev.exit
_ZNSsD2Ev.exit: ; preds = %if.then4.i.i, %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i, %invoke.cont59 _ZNSsD2Ev.exit: ; preds = %if.then4.i.i, %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i, %invoke.cont59
br i1 undef, label %for.body70, label %for.cond.cleanup69 br i1 %c8, label %for.body70, label %for.cond.cleanup69
for.cond.cleanup69: ; preds = %_ZNSsD2Ev.exit for.cond.cleanup69: ; preds = %_ZNSsD2Ev.exit
br i1 undef, label %if.then121, label %if.else br i1 %c9, label %if.then121, label %if.else
lpad: ; preds = %_ZN4Foam4wordC2EPKcb.exit lpad: ; preds = %_ZN4Foam4wordC2EPKcb.exit
%1 = landingpad { ptr, i32 } %1 = landingpad { ptr, i32 }
cleanup cleanup
br i1 undef, label %_ZNSsD2Ev.exit1578, label %if.then.i.i1570, !prof !1 br i1 %c10, label %_ZNSsD2Ev.exit1578, label %if.then.i.i1570, !prof !1
if.then.i.i1570: ; preds = %lpad if.then.i.i1570: ; preds = %lpad
br i1 undef, label %if.then4.i.i1577, label %_ZNSsD2Ev.exit1578 br i1 %c11, label %if.then4.i.i1577, label %_ZNSsD2Ev.exit1578
if.then4.i.i1577: ; preds = %if.then.i.i1570 if.then4.i.i1577: ; preds = %if.then.i.i1570
unreachable unreachable
_ZNSsD2Ev.exit1578: ; preds = %if.then.i.i1570, %lpad _ZNSsD2Ev.exit1578: ; preds = %if.then.i.i1570, %lpad
unreachable unreachable
for.body70: ; preds = %_ZNSsD2Ev.exit for.body70: ; preds = %_ZNSsD2Ev.exit
Show All 38 Lines
if.end213: ; preds = %invoke.cont176 if.end213: ; preds = %invoke.cont176
invoke void @_ZN4Foam4word12stripInvalidEv() invoke void @_ZN4Foam4word12stripInvalidEv()
to label %_ZN4Foam4wordC2EPKcb.exit1777 unwind label %lpad.i1765 to label %_ZN4Foam4wordC2EPKcb.exit1777 unwind label %lpad.i1765
lpad.i1765: ; preds = %if.end213 lpad.i1765: ; preds = %if.end213
%5 = landingpad { ptr, i32 } %5 = landingpad { ptr, i32 }
cleanup cleanup
br i1 undef, label %eh.resume.i1776, label %if.then.i.i.i1767, !prof !1 br i1 %c12, label %eh.resume.i1776, label %if.then.i.i.i1767, !prof !1
if.then.i.i.i1767: ; preds = %lpad.i1765 if.then.i.i.i1767: ; preds = %lpad.i1765
unreachable unreachable
eh.resume.i1776: ; preds = %lpad.i1765 eh.resume.i1776: ; preds = %lpad.i1765
resume { ptr, i32 } %5 resume { ptr, i32 } %5
_ZN4Foam4wordC2EPKcb.exit1777: ; preds = %if.end213 _ZN4Foam4wordC2EPKcb.exit1777: ; preds = %if.end213
invoke void @_ZN4Foam7faceSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE() invoke void @_ZN4Foam7faceSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE()
to label %invoke.cont221 unwind label %lpad217 to label %invoke.cont221 unwind label %lpad217
invoke.cont221: ; preds = %_ZN4Foam4wordC2EPKcb.exit1777 invoke.cont221: ; preds = %_ZN4Foam4wordC2EPKcb.exit1777
br i1 undef, label %_ZNSsD2Ev.exit1792, label %if.then.i.i1784, !prof !1 br i1 %c13, label %_ZNSsD2Ev.exit1792, label %if.then.i.i1784, !prof !1
if.then.i.i1784: ; preds = %invoke.cont221 if.then.i.i1784: ; preds = %invoke.cont221
br i1 undef, label %if.then4.i.i1791, label %_ZNSsD2Ev.exit1792 br i1 %c14, label %if.then4.i.i1791, label %_ZNSsD2Ev.exit1792
if.then4.i.i1791: ; preds = %if.then.i.i1784 if.then4.i.i1791: ; preds = %if.then.i.i1784
br label %_ZNSsD2Ev.exit1792 br label %_ZNSsD2Ev.exit1792
_ZNSsD2Ev.exit1792: ; preds = %if.then4.i.i1791, %if.then.i.i1784, %invoke.cont221 _ZNSsD2Ev.exit1792: ; preds = %if.then4.i.i1791, %if.then.i.i1784, %invoke.cont221
%call232 = invoke zeroext i1 undef(ptr undef, i1 zeroext true, ptr undef) %call232 = invoke zeroext i1 undef(ptr undef, i1 zeroext true, ptr undef)
to label %invoke.cont231 unwind label %lpad230 to label %invoke.cont231 unwind label %lpad230
Show All 21 Lines %8 = landingpad { ptr, i32 }
cleanup cleanup
unreachable unreachable
_ZN4Foam4wordC2EPKcb.exit1862: ; preds = %invoke.cont243 _ZN4Foam4wordC2EPKcb.exit1862: ; preds = %invoke.cont243
invoke void @_ZN4Foam7faceSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE() invoke void @_ZN4Foam7faceSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE()
to label %invoke.cont280 unwind label %lpad276 to label %invoke.cont280 unwind label %lpad276
invoke.cont280: ; preds = %_ZN4Foam4wordC2EPKcb.exit1862 invoke.cont280: ; preds = %_ZN4Foam4wordC2EPKcb.exit1862
br i1 undef, label %_ZNSsD2Ev.exit1877, label %if.then.i.i1869, !prof !1 br i1 %c15, label %_ZNSsD2Ev.exit1877, label %if.then.i.i1869, !prof !1
if.then.i.i1869: ; preds = %invoke.cont280 if.then.i.i1869: ; preds = %invoke.cont280
unreachable unreachable
_ZNSsD2Ev.exit1877: ; preds = %invoke.cont280 _ZNSsD2Ev.exit1877: ; preds = %invoke.cont280
br i1 undef, label %if.then292, label %if.end328 br i1 %c16, label %if.then292, label %if.end328
if.then292: ; preds = %_ZNSsD2Ev.exit1877 if.then292: ; preds = %_ZNSsD2Ev.exit1877
unreachable unreachable
lpad276: ; preds = %_ZN4Foam4wordC2EPKcb.exit1862 lpad276: ; preds = %_ZN4Foam4wordC2EPKcb.exit1862
%9 = landingpad { ptr, i32 } %9 = landingpad { ptr, i32 }
cleanup cleanup
unreachable unreachable
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invoke.cont676: ; preds = %invoke.cont674 invoke.cont676: ; preds = %invoke.cont674
invoke void undef(ptr %call677) invoke void undef(ptr %call677)
to label %if.end878 unwind label %lpad663 to label %if.end878 unwind label %lpad663
lpad663: ; preds = %invoke.cont670, %if.end660, %invoke.cont668, %invoke.cont674, %invoke.cont676 lpad663: ; preds = %invoke.cont670, %if.end660, %invoke.cont668, %invoke.cont674, %invoke.cont676
%10 = landingpad { ptr, i32 } %10 = landingpad { ptr, i32 }
cleanup cleanup
br i1 undef, label %_ZN4Foam4ListIiED2Ev.exit.i3073, label %delete.notnull.i.i3071 br i1 %c17, label %_ZN4Foam4ListIiED2Ev.exit.i3073, label %delete.notnull.i.i3071
if.end878: ; preds = %invoke.cont676 if.end878: ; preds = %invoke.cont676
br i1 undef, label %_ZN4Foam11regionSplitD2Ev.exit, label %delete.notnull.i.i3056 br i1 %c18, label %_ZN4Foam11regionSplitD2Ev.exit, label %delete.notnull.i.i3056
delete.notnull.i.i3056: ; preds = %if.end878 delete.notnull.i.i3056: ; preds = %if.end878
unreachable unreachable
_ZN4Foam11regionSplitD2Ev.exit: ; preds = %if.end878 _ZN4Foam11regionSplitD2Ev.exit: ; preds = %if.end878
br i1 undef, label %if.then883, label %if.else888 br i1 %c19, label %if.then883, label %if.else888
if.then883: ; preds = %_ZN4Foam11regionSplitD2Ev.exit if.then883: ; preds = %_ZN4Foam11regionSplitD2Ev.exit
unreachable unreachable
delete.notnull.i.i3071: ; preds = %lpad663 delete.notnull.i.i3071: ; preds = %lpad663
unreachable unreachable
_ZN4Foam4ListIiED2Ev.exit.i3073: ; preds = %lpad663 _ZN4Foam4ListIiED2Ev.exit.i3073: ; preds = %lpad663
Show All 9 Lines %11 = landingpad { ptr, i32 }
cleanup cleanup
unreachable unreachable
_ZN4Foam4wordC2EPKcb.exit3098: ; preds = %if.else888 _ZN4Foam4wordC2EPKcb.exit3098: ; preds = %if.else888
invoke void @_ZN4Foam8pointSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE() invoke void @_ZN4Foam8pointSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE()
to label %invoke.cont902 unwind label %lpad898 to label %invoke.cont902 unwind label %lpad898
invoke.cont902: ; preds = %_ZN4Foam4wordC2EPKcb.exit3098 invoke.cont902: ; preds = %_ZN4Foam4wordC2EPKcb.exit3098
br i1 undef, label %_ZNSsD2Ev.exit3113, label %if.then.i.i3105, !prof !1 br i1 %c20, label %_ZNSsD2Ev.exit3113, label %if.then.i.i3105, !prof !1
if.then.i.i3105: ; preds = %invoke.cont902 if.then.i.i3105: ; preds = %invoke.cont902
br i1 undef, label %if.then4.i.i3112, label %_ZNSsD2Ev.exit3113 br i1 %c21, label %if.then4.i.i3112, label %_ZNSsD2Ev.exit3113
if.then4.i.i3112: ; preds = %if.then.i.i3105 if.then4.i.i3112: ; preds = %if.then.i.i3105
unreachable unreachable
_ZNSsD2Ev.exit3113: ; preds = %if.then.i.i3105, %invoke.cont902 _ZNSsD2Ev.exit3113: ; preds = %if.then.i.i3105, %invoke.cont902
%call.i31163117 = invoke zeroext i32 undef(ptr @_ZN4Foam4PoutE) %call.i31163117 = invoke zeroext i32 undef(ptr @_ZN4Foam4PoutE)
to label %call.i3116.noexc unwind label %lpad905.loopexit.split-lp to label %call.i3116.noexc unwind label %lpad905.loopexit.split-lp
call.i3116.noexc: ; preds = %_ZNSsD2Ev.exit3113 call.i3116.noexc: ; preds = %_ZNSsD2Ev.exit3113
%call5.i3118 = invoke zeroext i32 null(ptr @_ZN4Foam4PoutE, i32 zeroext undef) %call5.i3118 = invoke zeroext i32 null(ptr @_ZN4Foam4PoutE, i32 zeroext undef)
to label %invoke.cont906 unwind label %lpad905.loopexit.split-lp to label %invoke.cont906 unwind label %lpad905.loopexit.split-lp
invoke.cont906: ; preds = %call.i3116.noexc invoke.cont906: ; preds = %call.i3116.noexc
unreachable unreachable
lpad898: ; preds = %_ZN4Foam4wordC2EPKcb.exit3098 lpad898: ; preds = %_ZN4Foam4wordC2EPKcb.exit3098
%12 = landingpad { ptr, i32 } %12 = landingpad { ptr, i32 }
cleanup cleanup
br i1 undef, label %_ZNSsD2Ev.exit3204, label %if.then.i.i3196, !prof !1 br i1 %c22, label %_ZNSsD2Ev.exit3204, label %if.then.i.i3196, !prof !1
if.then.i.i3196: ; preds = %lpad898 if.then.i.i3196: ; preds = %lpad898
unreachable unreachable
_ZNSsD2Ev.exit3204: ; preds = %lpad898 _ZNSsD2Ev.exit3204: ; preds = %lpad898
unreachable unreachable
lpad905.loopexit.split-lp: ; preds = %call.i3116.noexc, %_ZNSsD2Ev.exit3113 lpad905.loopexit.split-lp: ; preds = %call.i3116.noexc, %_ZNSsD2Ev.exit3113
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llvm/test/CodeGen/PowerPC/fast-isel-icmp-split.ll

; RUN: llc -verify-machineinstrs -O0 -relocation-model=pic < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -O0 -relocation-model=pic < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux" target triple = "powerpc64le-unknown-linux"
%"class.std::__1::__tree_node.130.151" = type { %"class.std::__1::__tree_node_base.base.128.149", ptr } %"class.std::__1::__tree_node.130.151" = type { %"class.std::__1::__tree_node_base.base.128.149", ptr }
%"class.std::__1::__tree_node_base.base.128.149" = type <{ %"class.std::__1::__tree_end_node.127.148", ptr, ptr, i8 }> %"class.std::__1::__tree_node_base.base.128.149" = type <{ %"class.std::__1::__tree_end_node.127.148", ptr, ptr, i8 }>
%"class.std::__1::__tree_end_node.127.148" = type { ptr } %"class.std::__1::__tree_end_node.127.148" = type { ptr }
%"class.std::__1::__tree_node_base.126.147" = type <{ %"class.std::__1::__tree_end_node.127.148", ptr, ptr, i8, [7 x i8] }> %"class.std::__1::__tree_node_base.126.147" = type <{ %"class.std::__1::__tree_end_node.127.148", ptr, ptr, i8, [7 x i8] }>
%"class.boost::serialization::extended_type_info.129.150" = type { ptr, i32, ptr } %"class.boost::serialization::extended_type_info.129.150" = type { ptr, i32, ptr }
; Function Attrs: noinline ; Function Attrs: noinline
define void @_ZN5boost13serialization18extended_type_info4findEPKc() #0 align 2 personality ptr @__gxx_personality_v0 { define void @_ZN5boost13serialization18extended_type_info4findEPKc(i1 %c0) #0 align 2 personality ptr @__gxx_personality_v0 {
entry: entry:
br i1 undef, label %cond.true, label %cond.false br i1 %c0, label %cond.true, label %cond.false
; CHECK: @_ZN5boost13serialization18extended_type_info4findEPKc ; CHECK: @_ZN5boost13serialization18extended_type_info4findEPKc
cond.true: ; preds = %entry cond.true: ; preds = %entry
br label %cond.end br label %cond.end
cond.false: ; preds = %entry cond.false: ; preds = %entry
unreachable unreachable
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llvm/test/CodeGen/PowerPC/ifcvt-forked-bug-2016-08-08.ll

; ModuleID = 'bugpoint-reduced-instructions.bc' ; ModuleID = 'bugpoint-reduced-instructions.bc'
; RUN: llc -O2 -o - %s -verify-machineinstrs | FileCheck %s ; RUN: llc -O2 -o - %s -verify-machineinstrs | FileCheck %s
source_filename = "bugpoint-output-9ad75f8.bc" source_filename = "bugpoint-output-9ad75f8.bc"
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define hidden void @_ZN11__sanitizer25MaybeStartBackgroudThreadEv() local_unnamed_addr #0 { define hidden void @_ZN11__sanitizer25MaybeStartBackgroudThreadEv(i1 %c0, i1 %c1) local_unnamed_addr #0 {
entry: entry:
br i1 undef, label %land.lhs.true, label %if.end br i1 %c0, label %land.lhs.true, label %if.end
; CHECK: # %land.lhs.true ; CHECK: # %land.lhs.true
; Test updated due D63152 where any load/store prevents shrink-wrapping ; Test updated due D63152 where any load/store prevents shrink-wrapping
; CHECK-NEXT: bc ; CHECK-NEXT: bc
; CHECK-NEXT: # %if.end4 ; CHECK-NEXT: # %if.end4
land.lhs.true: ; preds = %entry land.lhs.true: ; preds = %entry
br i1 undef, label %return, label %if.end4 br i1 %c1, label %return, label %if.end4
if.end: ; preds = %entry if.end: ; preds = %entry
br i1 icmp ne (ptr @_ZN11__sanitizer19real_pthread_createEPvS0_PFS0_S0_ES0_, ptr null), label %if.end4, label %return br i1 icmp ne (ptr @_ZN11__sanitizer19real_pthread_createEPvS0_PFS0_S0_ES0_, ptr null), label %if.end4, label %return
if.end4: ; preds = %if.end, %land.lhs.true if.end4: ; preds = %if.end, %land.lhs.true
%call5 = tail call ptr @_ZN11__sanitizer21internal_start_threadEPFvPvES0_(ptr nonnull @_ZN11__sanitizer16BackgroundThreadEPv, ptr null) #7 %call5 = tail call ptr @_ZN11__sanitizer21internal_start_threadEPFvPvES0_(ptr nonnull @_ZN11__sanitizer16BackgroundThreadEPv, ptr null) #7
unreachable unreachable
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llvm/test/CodeGen/PowerPC/isel-rc-nox0.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@g_62 = external global [1 x [9 x i32]], align 4 @g_62 = external global [1 x [9 x i32]], align 4
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @main() #0 { define void @main(i1 %c0, i1 %c1, i1 %c2, i1 %c3) #0 {
entry: entry:
br i1 undef, label %cond.true, label %for.cond1.preheader.i br i1 %c0, label %cond.true, label %for.cond1.preheader.i
cond.true: ; preds = %entry cond.true: ; preds = %entry
br label %for.cond1.preheader.i br label %for.cond1.preheader.i
for.cond1.preheader.i: ; preds = %for.cond1.preheader.i, %cond.true, %entry for.cond1.preheader.i: ; preds = %for.cond1.preheader.i, %cond.true, %entry
br i1 undef, label %crc32_gentab.exit, label %for.cond1.preheader.i br i1 %c1, label %crc32_gentab.exit, label %for.cond1.preheader.i
crc32_gentab.exit: ; preds = %for.cond1.preheader.i crc32_gentab.exit: ; preds = %for.cond1.preheader.i
%tobool.i19.i.i = icmp eq i32 undef, 0 %tobool.i19.i.i = icmp eq i32 undef, 0
%retval.0.i.i.i = select i1 %tobool.i19.i.i, ptr getelementptr inbounds ([1 x [9 x i32]], ptr @g_62, i64 0, i64 0, i64 6), ptr getelementptr inbounds ([1 x [9 x i32]], ptr @g_62, i64 0, i64 0, i64 8) %retval.0.i.i.i = select i1 %tobool.i19.i.i, ptr getelementptr inbounds ([1 x [9 x i32]], ptr @g_62, i64 0, i64 0, i64 6), ptr getelementptr inbounds ([1 x [9 x i32]], ptr @g_62, i64 0, i64 0, i64 8)
br label %for.cond1.preheader.i2961.i br label %for.cond1.preheader.i2961.i
for.cond1.preheader.i2961.i: ; preds = %for.inc44.i2977.i, %crc32_gentab.exit for.cond1.preheader.i2961.i: ; preds = %for.inc44.i2977.i, %crc32_gentab.exit
call void @llvm.memset.p0.i64(ptr align 4 @g_62, i8 -1, i64 36, i1 false) #1 call void @llvm.memset.p0.i64(ptr align 4 @g_62, i8 -1, i64 36, i1 false) #1
%0 = load i32, ptr %retval.0.i.i.i, align 4 %0 = load i32, ptr %retval.0.i.i.i, align 4
%tobool.i2967.i = icmp eq i32 %0, 0 %tobool.i2967.i = icmp eq i32 %0, 0
br label %for.body21.i2968.i br label %for.body21.i2968.i
for.body21.i2968.i: ; preds = %safe_mod_func_int32_t_s_s.exit.i2974.i, %for.cond1.preheader.i2961.i for.body21.i2968.i: ; preds = %safe_mod_func_int32_t_s_s.exit.i2974.i, %for.cond1.preheader.i2961.i
br i1 %tobool.i2967.i, label %safe_mod_func_int32_t_s_s.exit.i2974.i, label %for.inc44.i2977.i br i1 %tobool.i2967.i, label %safe_mod_func_int32_t_s_s.exit.i2974.i, label %for.inc44.i2977.i
safe_mod_func_int32_t_s_s.exit.i2974.i: ; preds = %for.body21.i2968.i safe_mod_func_int32_t_s_s.exit.i2974.i: ; preds = %for.body21.i2968.i
br i1 undef, label %for.body21.i2968.i, label %for.inc44.i2977.i br i1 %c2, label %for.body21.i2968.i, label %for.inc44.i2977.i
for.inc44.i2977.i: ; preds = %safe_mod_func_int32_t_s_s.exit.i2974.i, %for.body21.i2968.i for.inc44.i2977.i: ; preds = %safe_mod_func_int32_t_s_s.exit.i2974.i, %for.body21.i2968.i
br i1 undef, label %func_80.exit2978.i, label %for.cond1.preheader.i2961.i br i1 %c3, label %func_80.exit2978.i, label %for.cond1.preheader.i2961.i
func_80.exit2978.i: ; preds = %for.inc44.i2977.i func_80.exit2978.i: ; preds = %for.inc44.i2977.i
unreachable unreachable
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) #1 declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) #1
attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind } attributes #1 = { nounwind }

llvm/test/CodeGen/PowerPC/lbzux.ll

target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; RUN: llc -verify-machineinstrs -disable-ppc-unaligned < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -disable-ppc-unaligned < %s | FileCheck %s
define fastcc void @allocateSpace(i1 %cond1, i1 %cond2, i32 %offset) nounwind { define fastcc void @allocateSpace(i1 %cond1, i1 %cond2, i32 %offset, i1 %c0, i1 %c1, i1 %c2) nounwind {
entry: entry:
%0 = load ptr, ptr undef, align 8 %0 = load ptr, ptr undef, align 8
br i1 undef, label %return, label %lor.lhs.false br i1 %c0, label %return, label %lor.lhs.false
lor.lhs.false: ; preds = %entry lor.lhs.false: ; preds = %entry
br i1 undef, label %if.end7, label %return br i1 %c1, label %if.end7, label %return
if.end7: ; preds = %lor.lhs.false if.end7: ; preds = %lor.lhs.false
br i1 undef, label %if.then15, label %if.end71 br i1 %c2, label %if.then15, label %if.end71
if.then15: ; preds = %if.end7 if.then15: ; preds = %if.end7
br label %while.cond br label %while.cond
while.cond: ; preds = %while.body, %if.then15 while.cond: ; preds = %while.body, %if.then15
%idxprom17 = sext i32 0 to i64 %idxprom17 = sext i32 0 to i64
%arrayidx18 = getelementptr inbounds i8, ptr %0, i64 %idxprom17 %arrayidx18 = getelementptr inbounds i8, ptr %0, i64 %idxprom17
br i1 %cond1, label %if.end71, label %while.body br i1 %cond1, label %if.end71, label %while.body
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llvm/test/CodeGen/PowerPC/licm-remat.ll

Show All 11 Lines
@_ZN6snappy8internalL10char_tableE = internal unnamed_addr constant [5 x i16] [i16 1, i16 2052, i16 4097, i16 8193, i16 2], align 2 @_ZN6snappy8internalL10char_tableE = internal unnamed_addr constant [5 x i16] [i16 1, i16 2052, i16 4097, i16 8193, i16 2], align 2
@_ZN6snappy8internalL8wordmaskE = internal unnamed_addr constant [5 x i32] [i32 0, i32 255, i32 65535, i32 16777215, i32 -1], align 4 @_ZN6snappy8internalL8wordmaskE = internal unnamed_addr constant [5 x i32] [i32 0, i32 255, i32 65535, i32 16777215, i32 -1], align 4
; Function Attrs: argmemonly nounwind ; Function Attrs: argmemonly nounwind
declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) #2 declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) #2
; Function Attrs: argmemonly nounwind ; Function Attrs: argmemonly nounwind
declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1) #2 declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1) #2
define linkonce_odr void @ZN6snappyDecompressor_(ptr %this, ptr %writer) { define linkonce_odr void @ZN6snappyDecompressor_(ptr %this, ptr %writer, i1 %c0, i1 %c1, i1 %c2) {
; CHECK-LABEL: ZN6snappyDecompressor_: ; CHECK-LABEL: ZN6snappyDecompressor_:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK: addis 3, 2, _ZN6snappy8internalL8wordmaskE@toc@ha ; CHECK: addis 3, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
; CHECK-DAG: addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l ; CHECK-DAG: addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l
; CHECK-DAG: addis 5, 2, _ZN6snappy8internalL10char_tableE@toc@ha ; CHECK-DAG: addis 5, 2, _ZN6snappy8internalL10char_tableE@toc@ha
; CHECK-DAG: addi 24, 5, _ZN6snappy8internalL10char_tableE@toc@l ; CHECK-DAG: addi 24, 5, _ZN6snappy8internalL10char_tableE@toc@l
; CHECK: .LBB0_2: # %for.cond ; CHECK: .LBB0_2: # %for.cond
; CHECK-NOT: addis {{[0-9]+}}, 2, _ZN6snappy8internalL8wordmaskE@toc@ha ; CHECK-NOT: addis {{[0-9]+}}, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
; CHECK-NOT: addis {{[0-9]+}}, 2, _ZN6snappy8internalL10char_tableE@toc@ha ; CHECK-NOT: addis {{[0-9]+}}, 2, _ZN6snappy8internalL10char_tableE@toc@ha
; CHECK: bctrl ; CHECK: bctrl
entry: entry:
%ip_limit_ = getelementptr inbounds %"class.snappy::SnappyDecompressor", ptr %this, i64 0, i32 2 %ip_limit_ = getelementptr inbounds %"class.snappy::SnappyDecompressor", ptr %this, i64 0, i32 2
%curr_iov_index_.i = getelementptr inbounds %"class.snappy::SnappyIOVecWriter", ptr %writer, i64 0, i32 2 %curr_iov_index_.i = getelementptr inbounds %"class.snappy::SnappyIOVecWriter", ptr %writer, i64 0, i32 2
%curr_iov_written_.i = getelementptr inbounds %"class.snappy::SnappyIOVecWriter", ptr %writer, i64 0, i32 3 %curr_iov_written_.i = getelementptr inbounds %"class.snappy::SnappyIOVecWriter", ptr %writer, i64 0, i32 3
br label %for.cond br label %for.cond
for.cond: ; preds = %if.end82, %if.then56, %if.end49, %entry for.cond: ; preds = %if.end82, %if.then56, %if.end49, %entry
%ip.0 = phi ptr [ null, %entry ], [ %add.ptr50, %if.end49 ], [ null, %if.then56 ], [ undef, %if.end82 ] %ip.0 = phi ptr [ null, %entry ], [ %add.ptr50, %if.end49 ], [ null, %if.then56 ], [ undef, %if.end82 ]
%incdec.ptr = getelementptr inbounds i8, ptr %ip.0, i64 1 %incdec.ptr = getelementptr inbounds i8, ptr %ip.0, i64 1
%0 = load i8, ptr %ip.0, align 1 %0 = load i8, ptr %ip.0, align 1
%conv = zext i8 %0 to i32 %conv = zext i8 %0 to i32
br i1 undef, label %if.then7, label %if.else br i1 %c0, label %if.then7, label %if.else
if.then7: ; preds = %for.cond if.then7: ; preds = %for.cond
%1 = lshr i32 %conv, 2 %1 = lshr i32 %conv, 2
%add = add nuw nsw i32 %1, 1 %add = add nuw nsw i32 %1, 1
%conv9 = zext i32 %add to i64 %conv9 = zext i32 %add to i64
%2 = load i64, ptr %ip_limit_, align 8 %2 = load i64, ptr %ip_limit_, align 8
%sub.ptr.sub13 = sub i64 %2, 0 %sub.ptr.sub13 = sub i64 %2, 0
%3 = load i64, ptr undef, align 8 %3 = load i64, ptr undef, align 8
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while.cond.preheader.i: ; preds = %while.body.preheader while.cond.preheader.i: ; preds = %while.body.preheader
%call39 = call ptr undef(ptr undef, ptr nonnull undef) %call39 = call ptr undef(ptr undef, ptr nonnull undef)
unreachable unreachable
while.end: ; preds = %if.end25 while.end: ; preds = %if.end25
br label %while.cond.preheader.i176 br label %while.cond.preheader.i176
while.cond.preheader.i176: ; preds = %while.end while.cond.preheader.i176: ; preds = %while.end
br i1 undef, label %if.end49, label %while.body.lr.ph.i182 br i1 %c1, label %if.end49, label %while.body.lr.ph.i182
while.body.lr.ph.i182: ; preds = %while.cond.preheader.i176 while.body.lr.ph.i182: ; preds = %while.cond.preheader.i176
%.pre.i181 = load i64, ptr %curr_iov_written_.i, align 8 %.pre.i181 = load i64, ptr %curr_iov_written_.i, align 8
%10 = load ptr, ptr undef, align 8 %10 = load ptr, ptr undef, align 8
%11 = load i64, ptr %curr_iov_index_.i, align 8 %11 = load i64, ptr %curr_iov_index_.i, align 8
%iov_len.i185 = getelementptr inbounds %"struct.snappy::iovec", ptr %10, i64 %11, i32 1 %iov_len.i185 = getelementptr inbounds %"struct.snappy::iovec", ptr %10, i64 %11, i32 1
%12 = load i64, ptr %iov_len.i185, align 8 %12 = load i64, ptr %iov_len.i185, align 8
br label %cond.end.i190 br label %cond.end.i190
cond.end.i190: ; preds = %while.body.lr.ph.i182 cond.end.i190: ; preds = %while.body.lr.ph.i182
br i1 undef, label %if.end18.i207, label %if.then10.i193 br i1 %c2, label %if.end18.i207, label %if.then10.i193
if.then10.i193: ; preds = %cond.end.i190 if.then10.i193: ; preds = %cond.end.i190
%add12.i191 = add i64 %11, 1 %add12.i191 = add i64 %11, 1
%iov_len22.phi.trans.insert.i194 = getelementptr inbounds %"struct.snappy::iovec", ptr %10, i64 %add12.i191, i32 1 %iov_len22.phi.trans.insert.i194 = getelementptr inbounds %"struct.snappy::iovec", ptr %10, i64 %add12.i191, i32 1
%.pre48.i195 = load i64, ptr %iov_len22.phi.trans.insert.i194, align 8 %.pre48.i195 = load i64, ptr %iov_len22.phi.trans.insert.i194, align 8
br label %if.end18.i207 br label %if.end18.i207
if.end18.i207: ; preds = %if.then10.i193, %cond.end.i190 if.end18.i207: ; preds = %if.then10.i193, %cond.end.i190
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llvm/test/CodeGen/PowerPC/merge-st-chain-op.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@_ZNSs4_Rep20_S_empty_rep_storageE = external global [0 x i64], align 8 @_ZNSs4_Rep20_S_empty_rep_storageE = external global [0 x i64], align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_ZN5clang7tooling15RefactoringTool10runAndSaveEPNS0_21FrontendActionFactoryE() #0 align 2 { define void @_ZN5clang7tooling15RefactoringTool10runAndSaveEPNS0_21FrontendActionFactoryE(i1 %c0) #0 align 2 {
entry: entry:
br i1 undef, label %_ZN4llvm18IntrusiveRefCntPtrIN5clang13DiagnosticIDsEEC2EPS2_.exit, label %return br i1 %c0, label %_ZN4llvm18IntrusiveRefCntPtrIN5clang13DiagnosticIDsEEC2EPS2_.exit, label %return
; CHECK: @_ZN5clang7tooling15RefactoringTool10runAndSaveEPNS0_21FrontendActionFactoryE ; CHECK: @_ZN5clang7tooling15RefactoringTool10runAndSaveEPNS0_21FrontendActionFactoryE
_ZN4llvm18IntrusiveRefCntPtrIN5clang13DiagnosticIDsEEC2EPS2_.exit: ; preds = %entry _ZN4llvm18IntrusiveRefCntPtrIN5clang13DiagnosticIDsEEC2EPS2_.exit: ; preds = %entry
%call2 = call noalias ptr @_Znwm() #3 %call2 = call noalias ptr @_Znwm() #3
store <2 x ptr> <ptr getelementptr inbounds ([0 x i64], ptr @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3), ptr getelementptr inbounds ([0 x i64], ptr @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3)>, ptr undef, align 8 store <2 x ptr> <ptr getelementptr inbounds ([0 x i64], ptr @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3), ptr getelementptr inbounds ([0 x i64], ptr @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3)>, ptr undef, align 8
%IgnoreWarnings.i = getelementptr inbounds i8, ptr %call2, i64 4 %IgnoreWarnings.i = getelementptr inbounds i8, ptr %call2, i64 4
call void @llvm.memset.p0.i64(ptr align 8 null, i8 0, i64 48, i1 false) #4 call void @llvm.memset.p0.i64(ptr align 8 null, i8 0, i64 48, i1 false) #4
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llvm/test/CodeGen/PowerPC/misched.ll

; RUN: llc < %s -enable-misched -verify-machineinstrs ; RUN: llc < %s -enable-misched -verify-machineinstrs
; PR14302 ; PR14302
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
@b = external global [16000 x double], align 32 @b = external global [16000 x double], align 32
define void @pr14302() nounwind { define void @pr14302(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5) nounwind {
entry: entry:
tail call void @putchar() nounwind tail call void @putchar() nounwind
br label %for.body br label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
br i1 undef, label %for.body, label %for.body24.i br i1 %c0, label %for.body, label %for.body24.i
for.body24.i: ; preds = %for.body24.i, %for.body for.body24.i: ; preds = %for.body24.i, %for.body
store double 1.000000e+00, ptr undef, align 8 store double 1.000000e+00, ptr undef, align 8
br i1 undef, label %for.body24.i58, label %for.body24.i br i1 %c1, label %for.body24.i58, label %for.body24.i
for.body24.i58: ; preds = %for.body24.i58, %for.body24.i for.body24.i58: ; preds = %for.body24.i58, %for.body24.i
%arrayidx26.i55.1 = getelementptr inbounds [16000 x double], ptr @b, i64 0, i64 undef %arrayidx26.i55.1 = getelementptr inbounds [16000 x double], ptr @b, i64 0, i64 undef
store double 1.000000e+00, ptr %arrayidx26.i55.1, align 8 store double 1.000000e+00, ptr %arrayidx26.i55.1, align 8
br i1 undef, label %for.body24.i64, label %for.body24.i58 br i1 %c2, label %for.body24.i64, label %for.body24.i58
for.body24.i64: ; preds = %for.body24.i64, %for.body24.i58 for.body24.i64: ; preds = %for.body24.i64, %for.body24.i58
%exitcond.2489 = icmp eq i32 0, 16000 %exitcond.2489 = icmp eq i32 0, 16000
br i1 %exitcond.2489, label %for.body24.i70, label %for.body24.i64 br i1 %exitcond.2489, label %for.body24.i70, label %for.body24.i64
for.body24.i70: ; preds = %for.body24.i70, %for.body24.i64 for.body24.i70: ; preds = %for.body24.i70, %for.body24.i64
br i1 undef, label %for.body24.i76, label %for.body24.i70 br i1 %c3, label %for.body24.i76, label %for.body24.i70
for.body24.i76: ; preds = %for.body24.i76, %for.body24.i70 for.body24.i76: ; preds = %for.body24.i76, %for.body24.i70
br i1 undef, label %set1d.exit77, label %for.body24.i76 br i1 %c4, label %set1d.exit77, label %for.body24.i76
set1d.exit77: ; preds = %for.body24.i76 set1d.exit77: ; preds = %for.body24.i76
br label %for.body29 br label %for.body29
for.body29: ; preds = %for.body29, %set1d.exit77 for.body29: ; preds = %for.body29, %set1d.exit77
br i1 undef, label %for.end35, label %for.body29 br i1 %c5, label %for.end35, label %for.body29
for.end35: ; preds = %for.body29 for.end35: ; preds = %for.body29
ret void ret void
} }
declare void @putchar() declare void @putchar()

llvm/test/CodeGen/PowerPC/mma-phi-accs.ll

Show First 20 Lines • Show All 198 Lines • ▼ Show 20 Linesfor.body:
%13 = load <16 x i8>, ptr %arrayidx3, align 16 %13 = load <16 x i8>, ptr %arrayidx3, align 16
%14 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %Acc.015, <256 x i1> %2, <16 x i8> %13) %14 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %Acc.015, <256 x i1> %2, <16 x i8> %13)
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
} }
; This test uses an unprimed accumulator PHI node with two operands: an ; This test uses an unprimed accumulator PHI node with two operands: an
; implicitely defined unprimed accumulator and the unprimed result of the call
; to xvf64gerpp. The compiler should replace this PHI node by a primed ; to xvf64gerpp. The compiler should replace this PHI node by a primed
; accumulator PHI node. ; accumulator PHI node.
define void @testImplicitDef(ptr %ptr) { define void @testImplicitDef(ptr %ptr, i1 %c0) {
; CHECK-LABEL: testImplicitDef: ; CHECK-LABEL: testImplicitDef:
; CHECK: # %bb.0: # %label1 ; CHECK: # %bb.0: # %label1
; CHECK-NEXT: # implicit-def: $acc0 ; CHECK-NEXT: # implicit-def: $acc0
; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB2_2 ; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB2_2
; CHECK-NEXT: # %bb.1: # %label2 ; CHECK-NEXT: # %bb.1: # %label2
; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0 ; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0
; CHECK-NEXT: .LBB2_2: # %label3 ; CHECK-NEXT: .LBB2_2: # %label3
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 0(r3) ; CHECK-NEXT: stxv vs0, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: testImplicitDef: ; CHECK-BE-LABEL: testImplicitDef:
; CHECK-BE: # %bb.0: # %label1 ; CHECK-BE: # %bb.0: # %label1
; CHECK-BE-NEXT: # implicit-def: $acc0 ; CHECK-BE-NEXT: # implicit-def: $acc0
; CHECK-BE-NEXT: bc 12, 4*cr5+lt, .LBB2_2 ; CHECK-BE-NEXT: bc 12, 4*cr5+lt, .LBB2_2
; CHECK-BE-NEXT: # %bb.1: # %label2 ; CHECK-BE-NEXT: # %bb.1: # %label2
; CHECK-BE-NEXT: xvf64gerpp acc0, vsp34, vs0 ; CHECK-BE-NEXT: xvf64gerpp acc0, vsp34, vs0
; CHECK-BE-NEXT: .LBB2_2: # %label3 ; CHECK-BE-NEXT: .LBB2_2: # %label3
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs3, 0(r3) ; CHECK-BE-NEXT: stxv vs3, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
label1: label1:
br i1 undef, label %label3, label %label2 br i1 %c0, label %label3, label %label2
label2: label2:
%0 = call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> undef, <256 x i1> undef, <16 x i8> undef) %0 = call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> undef, <256 x i1> undef, <16 x i8> undef)
br label %label3 br label %label3
label3: label3:
%1 = phi <512 x i1> [ undef, %label1 ], [ %0, %label2 ] %1 = phi <512 x i1> [ undef, %label1 ], [ %0, %label2 ]
%2 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %1) %2 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %1)
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llvm/test/CodeGen/PowerPC/negctr.ll

; RUN: llc < %s -mcpu=a2 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mcpu=a2 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mcpu=a2 -disable-lsr -verify-machineinstrs | FileCheck -check-prefix=NOLSR %s ; RUN: llc < %s -mcpu=a2 -disable-lsr -verify-machineinstrs | FileCheck -check-prefix=NOLSR %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @main() #0 { define void @main(i1 %c0) #0 {
entry: entry:
br i1 undef, label %for.end, label %for.body br i1 %c0, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ] %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ]
%indvars.iv.next = add i64 %indvars.iv, 1 %indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 0 %exitcond = icmp eq i32 %lftr.wideiv, 0
br i1 %exitcond, label %for.end, label %for.body br i1 %exitcond, label %for.end, label %for.body
; CHECK: @main ; CHECK: @main
; CHECK: li [[REG:[0-9]+]], -1 ; CHECK: li [[REG:[0-9]+]], -1
; CHECK: rldic [[REG2:[0-9]+]], [[REG]], 0, 32 ; CHECK: rldic [[REG2:[0-9]+]], [[REG]], 0, 32
; CHECK: mtctr [[REG2]] ; CHECK: mtctr [[REG2]]
; CHECK: bdnz ; CHECK: bdnz
for.end: ; preds = %for.body, %entry for.end: ; preds = %for.body, %entry
ret void ret void
} }
define void @main1() #0 { define void @main1(i1 %c0) #0 {
entry: entry:
br i1 undef, label %for.end, label %for.body br i1 %c0, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ] %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ]
%indvars.iv.next = add i64 %indvars.iv, 1 %indvars.iv.next = add i64 %indvars.iv, 1
%exitcond = icmp eq i64 %indvars.iv.next, 0 %exitcond = icmp eq i64 %indvars.iv.next, 0
br i1 %exitcond, label %for.end, label %for.body br i1 %exitcond, label %for.end, label %for.body
; CHECK: @main1 ; CHECK: @main1
; CHECK: li [[REG:[0-9]+]], -1 ; CHECK: li [[REG:[0-9]+]], -1
; CHECK: mtctr [[REG]] ; CHECK: mtctr [[REG]]
; CHECK: bdnz ; CHECK: bdnz
for.end: ; preds = %for.body, %entry for.end: ; preds = %for.body, %entry
ret void ret void
} }
define void @main2() #0 { define void @main2(i1 %c0) #0 {
entry: entry:
br i1 undef, label %for.end, label %for.body br i1 %c0, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ] %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ]
%indvars.iv.next = add i64 %indvars.iv, 1 %indvars.iv.next = add i64 %indvars.iv, 1
%exitcond = icmp eq i64 %indvars.iv.next, -100000 %exitcond = icmp eq i64 %indvars.iv.next, -100000
br i1 %exitcond, label %for.end, label %for.body br i1 %exitcond, label %for.end, label %for.body
; CHECK: @main2 ; CHECK: @main2
; CHECK: lis [[REG:[0-9]+]], -2 ; CHECK: lis [[REG:[0-9]+]], -2
; CHECK: ori [[REG2:[0-9]+]], [[REG]], 31071 ; CHECK: ori [[REG2:[0-9]+]], [[REG]], 31071
; CHECK: mtctr [[REG2]] ; CHECK: mtctr [[REG2]]
; CHECK: bdnz ; CHECK: bdnz
for.end: ; preds = %for.body, %entry for.end: ; preds = %for.body, %entry
ret void ret void
} }
define void @main3() #0 { define void @main3(i1 %c0) #0 {
entry: entry:
br i1 undef, label %for.end, label %for.body br i1 %c0, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 127984, %entry ] %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 127984, %entry ]
%indvars.iv.next = add i64 %indvars.iv, -16 %indvars.iv.next = add i64 %indvars.iv, -16
%exitcond = icmp eq i64 %indvars.iv.next, -16 %exitcond = icmp eq i64 %indvars.iv.next, -16
br i1 %exitcond, label %for.end, label %for.body br i1 %exitcond, label %for.end, label %for.body
; NOLSR: @main3 ; NOLSR: @main3
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llvm/test/CodeGen/PowerPC/no-dup-of-bdnz.ll

; RUN: opt -passes='early-cse<memssa>,loop-mssa(loop-rotate,licm,loop-rotate)' -earlycse-debug-hash -S %s -o - | FileCheck %s ; RUN: opt -passes='early-cse<memssa>,loop-mssa(loop-rotate,licm,loop-rotate)' -earlycse-debug-hash -S %s -o - | FileCheck %s
; ModuleID = 'bugpoint-reduced-simplified.bc' ; ModuleID = 'bugpoint-reduced-simplified.bc'
source_filename = "bugpoint-output-8903f29.bc" source_filename = "bugpoint-output-8903f29.bc"
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
define void @test(i64 %arg.ssa, i64 %arg.nb) local_unnamed_addr { define void @test(i64 %arg.ssa, i64 %arg.nb, i1 %c0, i1 %c1) local_unnamed_addr {
; Ensure that loop rotation doesn't duplicate the call to ; Ensure that loop rotation doesn't duplicate the call to
; llvm.loop.decrement ; llvm.loop.decrement
; CHECK-LABEL: test ; CHECK-LABEL: test
; CHECK: call i1 @llvm.loop.decrement ; CHECK: call i1 @llvm.loop.decrement
; CHECK-NOT: call i1 @llvm.loop.decrement ; CHECK-NOT: call i1 @llvm.loop.decrement
; CHECK: declare i1 @llvm.loop.decrement ; CHECK: declare i1 @llvm.loop.decrement
entry: entry:
switch i32 undef, label %BB_8 [ switch i32 undef, label %BB_8 [
Show All 20 Lines
BB_4: ; preds = %BB_3 BB_4: ; preds = %BB_3
%.810.us = add nuw nsw i64 %bcount.1.us, 1 %.810.us = add nuw nsw i64 %bcount.1.us, 1
br label %BB_1 br label %BB_1
BB_5: ; preds = %BB_7, %BB_5 BB_5: ; preds = %BB_7, %BB_5
%lsr.iv20.i116 = phi i64 [ %2, %BB_7 ], [ %lsr.iv.next21.i126, %BB_5 ] %lsr.iv20.i116 = phi i64 [ %2, %BB_7 ], [ %lsr.iv.next21.i126, %BB_5 ]
%lsr.iv.next21.i126 = add i64 %lsr.iv20.i116, 1 %lsr.iv.next21.i126 = add i64 %lsr.iv20.i116, 1
br i1 undef, label %BB_5, label %BB_6 br i1 %c0, label %BB_5, label %BB_6
BB_6: ; preds = %BB_5 BB_6: ; preds = %BB_5
ret void ret void
BB_7: ; preds = %BB_3 BB_7: ; preds = %BB_3
br label %BB_5 br label %BB_5
BB_8: ; preds = %entry BB_8: ; preds = %entry
ret void ret void
BB_9: ; preds = %entry, %entry BB_9: ; preds = %entry, %entry
br label %BB_10 br label %BB_10
BB_10: ; preds = %BB_9 BB_10: ; preds = %BB_9
br label %BB_11 br label %BB_11
BB_11: ; preds = %BB_11, %BB_10 BB_11: ; preds = %BB_11, %BB_10
br i1 undef, label %BB_11, label %BB_12 br i1 %c1, label %BB_11, label %BB_12
BB_12: ; preds = %BB_11 BB_12: ; preds = %BB_11
call void @llvm.set.loop.iterations.i64(i64 %arg.nb) call void @llvm.set.loop.iterations.i64(i64 %arg.nb)
br label %BB_1 br label %BB_1
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
declare void @llvm.set.loop.iterations.i64(i64) #0 declare void @llvm.set.loop.iterations.i64(i64) #0
; Function Attrs: nounwind ; Function Attrs: nounwind
declare i1 @llvm.loop.decrement.i32(i32) #0 declare i1 @llvm.loop.decrement.i32(i32) #0
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/optimize-andiso.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
define float @floatundisf(i64 %a) { define float @floatundisf(i64 %a, i1 %c0) {
; CHECK-LABEL: floatundisf: ; CHECK-LABEL: floatundisf:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor f1, f1, f1 ; CHECK-NEXT: xxlxor f1, f1, f1
; CHECK-NEXT: bclr 12, 4*cr5+lt, 0 ; CHECK-NEXT: bclr 12, 4*cr5+lt, 0
; CHECK-NEXT: # %bb.1: # %sw.epilog ; CHECK-NEXT: # %bb.1: # %sw.epilog
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: li r5, 2 ; CHECK-NEXT: li r5, 2
; CHECK-NEXT: andis. r4, r3, 1024 ; CHECK-NEXT: andis. r4, r3, 1024
; CHECK-NEXT: li r4, 3 ; CHECK-NEXT: li r4, 3
; CHECK-NEXT: iseleq r4, r5, r4 ; CHECK-NEXT: iseleq r4, r5, r4
; CHECK-NEXT: srd r3, r3, r4 ; CHECK-NEXT: srd r3, r3, r4
; CHECK-NEXT: clrlwi r3, r3, 9 ; CHECK-NEXT: clrlwi r3, r3, 9
; CHECK-NEXT: mtfprd f0, r3 ; CHECK-NEXT: mtfprd f0, r3
; CHECK-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-NEXT: xscvspdpn f1, vs0 ; CHECK-NEXT: xscvspdpn f1, vs0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
br i1 undef, label %return, label %sw.epilog br i1 %c0, label %return, label %sw.epilog
sw.epilog: ; preds = %entry sw.epilog: ; preds = %entry
%or14 = or i64 0, %a %or14 = or i64 0, %a
%inc = add i64 %or14, 1 %inc = add i64 %or14, 1
%and16 = and i64 %inc, 67108864 %and16 = and i64 %inc, 67108864
%tobool = icmp eq i64 %and16, 0 %tobool = icmp eq i64 %and16, 0
%tmp.select.v = select i1 %tobool, i64 2, i64 3 %tmp.select.v = select i1 %tobool, i64 2, i64 3
%tmp.select = lshr i64 %inc, %tmp.select.v %tmp.select = lshr i64 %inc, %tmp.select.v
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llvm/test/CodeGen/PowerPC/p10-spill-crun.ll

Show All 27 Lines
declare i8 @call_1(ptr) local_unnamed_addr declare i8 @call_1(ptr) local_unnamed_addr
declare i32 @call_2(ptr, ptr) local_unnamed_addr declare i32 @call_2(ptr, ptr) local_unnamed_addr
declare i32 @call_3(ptr, ptr) local_unnamed_addr declare i32 @call_3(ptr, ptr) local_unnamed_addr
declare ptr @call_4(ptr, i32, i32, i32, i32, i32, i16, i16, ptr, ptr, i32, float, float, float, float, ptr) local_unnamed_addr declare ptr @call_4(ptr, i32, i32, i32, i32, i32, i16, i16, ptr, ptr, i32, float, float, float, float, ptr) local_unnamed_addr
declare i32 @call_5(ptr) local_unnamed_addr declare i32 @call_5(ptr) local_unnamed_addr
declare i8 @call_6(ptr, i32) local_unnamed_addr declare i8 @call_6(ptr, i32) local_unnamed_addr
define dso_local void @P10_Spill_CR_UN(ptr %arg, ptr %arg1, i32 %arg2) local_unnamed_addr { define dso_local void @P10_Spill_CR_UN(ptr %arg, ptr %arg1, i32 %arg2, i1 %c0) local_unnamed_addr {
; CHECK-LABEL: P10_Spill_CR_UN: ; CHECK-LABEL: P10_Spill_CR_UN:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: mfcr r12 ; CHECK-NEXT: mfcr r12
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stw r12, 8(r1) ; CHECK-NEXT: stw r12, 8(r1)
; CHECK-NEXT: stdu r1, -224(r1) ; CHECK-NEXT: stdu r1, -224(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 224 ; CHECK-NEXT: .cfi_def_cfa_offset 224
▲ Show 20 Lines • Show All 298 Lines • ▼ Show 20 Linesbb:
%tmp3 = tail call zeroext i8 @call_1(ptr %arg1) %tmp3 = tail call zeroext i8 @call_1(ptr %arg1)
%tmp4 = icmp ne i8 %tmp3, 0 %tmp4 = icmp ne i8 %tmp3, 0
%tmp5 = tail call signext i32 @call_2(ptr %arg, ptr %arg1) %tmp5 = tail call signext i32 @call_2(ptr %arg, ptr %arg1)
%tmp6 = and i32 %arg2, 16 %tmp6 = and i32 %arg2, 16
%tmp7 = icmp ne i32 %tmp6, 0 %tmp7 = icmp ne i32 %tmp6, 0
br label %bb8 br label %bb8
bb8: ; preds = %bb bb8: ; preds = %bb
br i1 undef, label %bb9, label %bb11 br i1 %c0, label %bb9, label %bb11
bb9: ; preds = %bb8 bb9: ; preds = %bb8
%tmp10 = call signext i32 @call_3(ptr %arg, ptr %arg1) %tmp10 = call signext i32 @call_3(ptr %arg, ptr %arg1)
br label %bb12 br label %bb12
bb11: ; preds = %bb8 bb11: ; preds = %bb8
br label %bb12 br label %bb12
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llvm/test/CodeGen/PowerPC/post-ra-ec.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.inode.0.12.120 = type { ptr } %struct.inode.0.12.120 = type { ptr }
%struct.kstat2.1.13.121 = type { i32 } %struct.kstat2.1.13.121 = type { i32 }
%struct.task_struct.4.16.124 = type { ptr, %struct.atomic_t.2.14.122, ptr } %struct.task_struct.4.16.124 = type { ptr, %struct.atomic_t.2.14.122, ptr }
%struct.atomic_t.2.14.122 = type { i32 } %struct.atomic_t.2.14.122 = type { i32 }
%struct.signal_struct.3.15.123 = type { i64 } %struct.signal_struct.3.15.123 = type { i64 }
%struct.pid.5.17.125 = type { ptr } %struct.pid.5.17.125 = type { ptr }
; Function Attrs: nounwind ; Function Attrs: nounwind
define signext i32 @proc_task_getattr(ptr nocapture readonly %inode, ptr nocapture %stat) #0 { define signext i32 @proc_task_getattr(ptr nocapture readonly %inode, ptr nocapture %stat, i1 %c0) #0 {
entry: entry:
%call1.i = tail call ptr @get_pid_task(ptr undef, i32 zeroext 0) #0 %call1.i = tail call ptr @get_pid_task(ptr undef, i32 zeroext 0) #0
br i1 undef, label %if.end, label %if.then br i1 %c0, label %if.end, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%0 = load i64, ptr undef, align 8 %0 = load i64, ptr undef, align 8
%conv.i = trunc i64 %0 to i32 %conv.i = trunc i64 %0 to i32
%1 = load i32, ptr null, align 4 %1 = load i32, ptr null, align 4
%add = add i32 %1, %conv.i %add = add i32 %1, %conv.i
store i32 %add, ptr null, align 4 store i32 %add, ptr null, align 4
%counter.i.i = getelementptr inbounds %struct.task_struct.4.16.124, ptr %call1.i, i64 0, i32 1, i32 0 %counter.i.i = getelementptr inbounds %struct.task_struct.4.16.124, ptr %call1.i, i64 0, i32 1, i32 0
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llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

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; immediate (post) dominator for the (restore) save blocks. When either the Save ; immediate (post) dominator for the (restore) save blocks. When either the Save
; or Restore block is located in an infinite loop the only immediate (post) ; or Restore block is located in an infinite loop the only immediate (post)
; dominator is itself. In this case, we cannot perform shrink wrapping, but we ; dominator is itself. In this case, we cannot perform shrink wrapping, but we
; should return gracefully and continue compilation. ; should return gracefully and continue compilation.
; The only condition for this test is the compilation finishes correctly. ; The only condition for this test is the compilation finishes correctly.
; ;
; CHECK-LABEL: {{.*}}infiniteloop ; CHECK-LABEL: {{.*}}infiniteloop
; CHECK: blr ; CHECK: blr
define void @infiniteloop() { define void @infiniteloop(i1 %c0) {
entry: entry:
br i1 undef, label %if.then, label %if.end br i1 %c0, label %if.then, label %if.end
if.then: if.then:
%ptr = alloca i32, i32 4 %ptr = alloca i32, i32 4
br label %for.body br label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ] %sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
%call = tail call i32 @something() %call = tail call i32 @something()
%add = add nsw i32 %call, %sum.03 %add = add nsw i32 %call, %sum.03
store i32 %add, ptr %ptr store i32 %add, ptr %ptr
br label %for.body br label %for.body
if.end: if.end:
ret void ret void
} }
; Another infinite loop test this time with a body bigger than just one block. ; Another infinite loop test this time with a body bigger than just one block.
; CHECK-LABEL: {{.*}}infiniteloop2 ; CHECK-LABEL: {{.*}}infiniteloop2
; CHECK: blr ; CHECK: blr
define void @infiniteloop2() { define void @infiniteloop2(i1 %c0, i1 %c1) {
entry: entry:
br i1 undef, label %if.then, label %if.end br i1 %c0, label %if.then, label %if.end
if.then: if.then:
%ptr = alloca i32, i32 4 %ptr = alloca i32, i32 4
br label %for.body br label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%sum.03 = phi i32 [ 0, %if.then ], [ %add, %body1 ], [ 1, %body2] %sum.03 = phi i32 [ 0, %if.then ], [ %add, %body1 ], [ 1, %body2]
%call = tail call i32 asm "mftb $0, 268", "=r,~{r14}"() %call = tail call i32 asm "mftb $0, 268", "=r,~{r14}"()
%add = add nsw i32 %call, %sum.03 %add = add nsw i32 %call, %sum.03
store i32 %add, ptr %ptr store i32 %add, ptr %ptr
br i1 undef, label %body1, label %body2 br i1 %c1, label %body1, label %body2
body1: body1:
tail call void asm sideeffect "nop", "~{r14}"() tail call void asm sideeffect "nop", "~{r14}"()
br label %for.body br label %for.body
body2: body2:
tail call void asm sideeffect "nop", "~{r14}"() tail call void asm sideeffect "nop", "~{r14}"()
br label %for.body br label %for.body
if.end: if.end:
ret void ret void
} }
; Another infinite loop test this time with two nested infinite loop. ; Another infinite loop test this time with two nested infinite loop.
; CHECK-LABEL: {{.*}}infiniteloop3 ; CHECK-LABEL: {{.*}}infiniteloop3
; CHECK: bclr ; CHECK: bclr
define void @infiniteloop3() { define void @infiniteloop3(i1 %c0, i1 %c1) {
entry: entry:
br i1 undef, label %loop2a, label %body br i1 %c0, label %loop2a, label %body
body: ; preds = %entry body: ; preds = %entry
br i1 undef, label %loop2a, label %end br i1 %c1, label %loop2a, label %end
loop1: ; preds = %loop2a, %loop2b loop1: ; preds = %loop2a, %loop2b
%var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ] %var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ]
%next.phi = phi ptr [ %next.load, %loop2b ], [ %next.var, %loop2a ] %next.phi = phi ptr [ %next.load, %loop2b ], [ %next.var, %loop2a ]
%0 = icmp eq ptr %var, null %0 = icmp eq ptr %var, null
%next.load = load ptr, ptr undef %next.load = load ptr, ptr undef
br i1 %0, label %loop2a, label %loop2b br i1 %0, label %loop2a, label %loop2b
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llvm/test/CodeGen/PowerPC/ppc-vaarg-agg.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
target triple = "powerpc-montavista-linux-gnuspe" target triple = "powerpc-montavista-linux-gnuspe"
%struct.__va_list_tag.0.9.18.23.32.41.48.55.62.67.72.77.82.87.90.93.96.101.105 = type { i8, i8, i16, ptr, ptr } %struct.__va_list_tag.0.9.18.23.32.41.48.55.62.67.72.77.82.87.90.93.96.101.105 = type { i8, i8, i16, ptr, ptr }
define fastcc void @test1(ptr %args) { define fastcc void @test1(ptr %args, i1 %c0) {
entry: entry:
br i1 undef, label %repeat, label %maxlen_reached br i1 %c0, label %repeat, label %maxlen_reached
repeat: ; preds = %entry repeat: ; preds = %entry
switch i32 undef, label %sw.bb323 [ switch i32 undef, label %sw.bb323 [
i32 77, label %sw.bb72 i32 77, label %sw.bb72
i32 111, label %sw.bb309 i32 111, label %sw.bb309
i32 80, label %sw.bb313 i32 80, label %sw.bb313
i32 117, label %sw.bb326 i32 117, label %sw.bb326
i32 88, label %sw.bb321 i32 88, label %sw.bb321
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llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \ ; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ ; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -ppc-track-subreg-liveness < %s | FileCheck %s --check-prefix=TRACKLIVE ; RUN: -ppc-track-subreg-liveness < %s | FileCheck %s --check-prefix=TRACKLIVE
%0 = type <{ double }> %0 = type <{ double }>
%1 = type <{ double }> %1 = type <{ double }>
define void @acc_regalloc(ptr %arg, ptr %arg1, ptr %arg2) local_unnamed_addr { define void @acc_regalloc(ptr %arg, ptr %arg1, ptr %arg2, i1 %c0) local_unnamed_addr {
; CHECK-LABEL: acc_regalloc: ; CHECK-LABEL: acc_regalloc:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: lwz r3, 0(r3) ; CHECK-NEXT: lwz r3, 0(r3)
; CHECK-NEXT: lxv v4, 0(0) ; CHECK-NEXT: lxv v4, 0(0)
; CHECK-NEXT: xxlxor v0, v0, v0 ; CHECK-NEXT: xxlxor v0, v0, v0
; CHECK-NEXT: xxlxor v1, v1, v1 ; CHECK-NEXT: xxlxor v1, v1, v1
; CHECK-NEXT: xxlxor v2, v2, v2 ; CHECK-NEXT: xxlxor v2, v2, v2
; CHECK-NEXT: li r6, 1 ; CHECK-NEXT: li r6, 1
▲ Show 20 Lines • Show All 259 Lines • ▼ Show 20 Linesbb82: ; preds = %bb82, %bb9
%i87 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i86, <256 x i1> undef, <16 x i8> undef) %i87 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i86, <256 x i1> undef, <16 x i8> undef)
%i88 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i85, <256 x i1> undef, <16 x i8> undef) %i88 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i85, <256 x i1> undef, <16 x i8> undef)
%i89 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i84, <256 x i1> undef, <16 x i8> undef) %i89 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i84, <256 x i1> undef, <16 x i8> undef)
%i90 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i83, <256 x i1> undef, <16 x i8> undef) %i90 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i83, <256 x i1> undef, <16 x i8> undef)
%i91 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i87, <256 x i1> undef, <16 x i8> undef) %i91 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i87, <256 x i1> undef, <16 x i8> undef)
%i92 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i88, <256 x i1> undef, <16 x i8> undef) %i92 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i88, <256 x i1> undef, <16 x i8> undef)
%i93 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i89, <256 x i1> undef, <16 x i8> undef) %i93 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i89, <256 x i1> undef, <16 x i8> undef)
%i94 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i90, <256 x i1> undef, <16 x i8> undef) %i94 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i90, <256 x i1> undef, <16 x i8> undef)
br i1 undef, label %bb95, label %bb82 br i1 %c0, label %bb95, label %bb82
bb95: ; preds = %bb82 bb95: ; preds = %bb82
%i96 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i91) %i96 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i91)
%i97 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i96, 2 %i97 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i96, 2
%i98 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i92) %i98 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i92)
%i99 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i98, 3 %i99 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i98, 3
%i100 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i93) %i100 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i93)
%i101 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i100, 2 %i101 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i100, 2
Show All 18 Lines

llvm/test/CodeGen/PowerPC/ppc64-xxsplti32dx-pattern-check.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
; CHECK-NOT: Impossible reg-to-reg copy ; CHECK-NOT: Impossible reg-to-reg copy
; CHECK-LABEL: test_xxsplti32dx ; CHECK-LABEL: test_xxsplti32dx
; CHECK: xxsplti32dx ; CHECK: xxsplti32dx
;; Test reduced from larger application where bug was initially detected. ;; Test reduced from larger application where bug was initially detected.
;; This test checks that the correct register class is used for xxsplti32dx. ;; This test checks that the correct register class is used for xxsplti32dx.
declare dso_local void @callee() local_unnamed_addr declare dso_local void @callee() local_unnamed_addr
define dso_local void @test_xxsplti32dx() local_unnamed_addr { define dso_local void @test_xxsplti32dx(i1 %c0) local_unnamed_addr {
entry: entry:
%i1 = load double, ptr undef, align 8 %i1 = load double, ptr undef, align 8
br label %for.body124 br label %for.body124
for.body124: for.body124:
%E0 = phi double [ 0.000000e+00, %entry ], [ %E1, %for.end1072 ] %E0 = phi double [ 0.000000e+00, %entry ], [ %E1, %for.end1072 ]
br i1 undef, label %for.body919.preheader, label %for.end1072 br i1 %c0, label %for.body919.preheader, label %for.end1072
for.body919.preheader: for.body919.preheader:
%i4 = load double, ptr null, align 8 %i4 = load double, ptr null, align 8
%i5 = load double, ptr null, align 8 %i5 = load double, ptr null, align 8
%i15 = insertelement <2 x double> poison, double %i5, i32 0 %i15 = insertelement <2 x double> poison, double %i5, i32 0
%i23 = insertelement <2 x double> undef, double %i4, i32 1 %i23 = insertelement <2 x double> undef, double %i4, i32 1
%i24 = insertelement <2 x double> %i15, double 0x3FC5555555555555, i32 1 %i24 = insertelement <2 x double> %i15, double 0x3FC5555555555555, i32 1
%i25 = fmul fast <2 x double> %i23, %i24 %i25 = fmul fast <2 x double> %i23, %i24
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llvm/test/CodeGen/PowerPC/pr16556.ll

; RUN: llc -verify-machineinstrs < %s ; RUN: llc -verify-machineinstrs < %s
; This test formerly failed due to no handling for a ppc_fp128 undef. ; This test formerly failed due to no handling for a ppc_fp128 undef.
target datalayout = "E-p:32:32:32-S0-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:64:128-v64:64:64-v128:128:128-a0:0:64-n32" target datalayout = "E-p:32:32:32-S0-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:64:128-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "powerpc-unknown-linux-gnu" target triple = "powerpc-unknown-linux-gnu"
%core.time.TickDuration.37.125 = type { i64 } %core.time.TickDuration.37.125 = type { i64 }
define weak_odr fastcc i64 @_D4core4time12TickDuration30__T2toVAyaa7_7365636f6e6473TlZ2toMxFNaNbNfZl(ptr %.this_arg) { define weak_odr fastcc i64 @_D4core4time12TickDuration30__T2toVAyaa7_7365636f6e6473TlZ2toMxFNaNbNfZl(ptr %.this_arg, i1 %c0) {
entry: entry:
br i1 undef, label %noassert, label %assert br i1 %c0, label %noassert, label %assert
assert: ; preds = %entry assert: ; preds = %entry
unreachable unreachable
noassert: ; preds = %entry noassert: ; preds = %entry
%tmp9 = fptosi ppc_fp128 undef to i64 %tmp9 = fptosi ppc_fp128 undef to i64
ret i64 %tmp9 ret i64 %tmp9
} }

llvm/test/CodeGen/PowerPC/pr17168.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 < %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 < %s
; This test formerly failed due to a DBG_VALUE being placed prior to a PHI ; This test formerly failed due to a DBG_VALUE being placed prior to a PHI
; when fast-isel is partially successful before punting to DAG-isel. ; when fast-isel is partially successful before punting to DAG-isel.
source_filename = "test/CodeGen/PowerPC/pr17168.ll" source_filename = "test/CodeGen/PowerPC/pr17168.ll"
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@grid_points = external global [3 x i32], align 4, !dbg !0 @grid_points = external global [3 x i32], align 4, !dbg !0
; Function Attrs: nounwind ; Function Attrs: nounwind
define fastcc void @compute_rhs() #0 !dbg !263 { define fastcc void @compute_rhs(i1 %c0, i1 %c1, i1 %c2) #0 !dbg !263 {
entry: entry:
br i1 undef, label %for.cond871.preheader.for.inc960_crit_edge, label %for.end1042, !dbg !281 br i1 %c0, label %for.cond871.preheader.for.inc960_crit_edge, label %for.end1042, !dbg !281
for.cond871.preheader.for.inc960_crit_edge: ; preds = %for.cond871.preheader.for.inc960_crit_edge, %entry for.cond871.preheader.for.inc960_crit_edge: ; preds = %for.cond871.preheader.for.inc960_crit_edge, %entry
br i1 false, label %for.cond871.preheader.for.inc960_crit_edge, label %for.cond964.preheader, !dbg !281 br i1 false, label %for.cond871.preheader.for.inc960_crit_edge, label %for.cond964.preheader, !dbg !281
for.cond964.preheader: ; preds = %for.cond871.preheader.for.inc960_crit_edge for.cond964.preheader: ; preds = %for.cond871.preheader.for.inc960_crit_edge
br i1 undef, label %for.cond968.preheader, label %for.end1042, !dbg !283 br i1 %c1, label %for.cond968.preheader, label %for.end1042, !dbg !283
for.cond968.preheader: ; preds = %for.cond968.preheader, %for.cond964.preheader for.cond968.preheader: ; preds = %for.cond968.preheader, %for.cond964.preheader
br i1 false, label %for.cond968.preheader, label %for.end1042, !dbg !283 br i1 false, label %for.cond968.preheader, label %for.end1042, !dbg !283
for.end1042: ; preds = %for.cond968.preheader, %for.cond964.preheader, %entry for.end1042: ; preds = %for.cond968.preheader, %for.cond964.preheader, %entry
%0 = phi i32 [ undef, %for.cond964.preheader ], [ undef, %for.cond968.preheader ], [ undef, %entry ] %0 = phi i32 [ undef, %for.cond964.preheader ], [ undef, %for.cond968.preheader ], [ undef, %entry ]
%1 = load i32, ptr @grid_points, align 4, !dbg !285, !tbaa !286 %1 = load i32, ptr @grid_points, align 4, !dbg !285, !tbaa !286
tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !268, metadata !290), !dbg !291 tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !268, metadata !290), !dbg !291
%sub10454270 = add nsw i32 %0, -1, !dbg !291 %sub10454270 = add nsw i32 %0, -1, !dbg !291
%cmp10464271 = icmp sgt i32 %sub10454270, 1, !dbg !291 %cmp10464271 = icmp sgt i32 %sub10454270, 1, !dbg !291
%sub11134263 = add nsw i32 %1, -1, !dbg !293 %sub11134263 = add nsw i32 %1, -1, !dbg !293
%cmp11144264 = icmp sgt i32 %sub11134263, 1, !dbg !293 %cmp11144264 = icmp sgt i32 %sub11134263, 1, !dbg !293
br i1 %cmp11144264, label %for.cond1116.preheader, label %for.cond1816.preheader.for.inc1898_crit_edge, !dbg !293 br i1 %cmp11144264, label %for.cond1116.preheader, label %for.cond1816.preheader.for.inc1898_crit_edge, !dbg !293
for.cond1116.preheader: ; preds = %for.inc1658, %for.end1042 for.cond1116.preheader: ; preds = %for.inc1658, %for.end1042
br i1 %cmp10464271, label %for.body1123, label %for.inc1658, !dbg !295 br i1 %cmp10464271, label %for.body1123, label %for.inc1658, !dbg !295
for.body1123: ; preds = %for.body1123, %for.cond1116.preheader for.body1123: ; preds = %for.body1123, %for.cond1116.preheader
br label %for.body1123, !dbg !298 br label %for.body1123, !dbg !298
for.inc1658: ; preds = %for.cond1116.preheader for.inc1658: ; preds = %for.cond1116.preheader
br i1 undef, label %for.cond1116.preheader, label %for.cond1816.preheader.for.inc1898_crit_edge, !dbg !293 br i1 %c2, label %for.cond1116.preheader, label %for.cond1816.preheader.for.inc1898_crit_edge, !dbg !293
for.cond1816.preheader.for.inc1898_crit_edge: ; preds = %for.cond1816.preheader.for.inc1898_crit_edge, %for.inc1658, %for.end1042 for.cond1816.preheader.for.inc1898_crit_edge: ; preds = %for.cond1816.preheader.for.inc1898_crit_edge, %for.inc1658, %for.end1042
br label %for.cond1816.preheader.for.inc1898_crit_edge, !dbg !301 br label %for.cond1816.preheader.for.inc1898_crit_edge, !dbg !301
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
▲ Show 20 Lines • Show All 314 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/pr18663-2.ll

Show All 40 Lines
declare void @_ZN4Foam7IOerrorclEPKcS2_iRKNS_8IOstreamE() #0 declare void @_ZN4Foam7IOerrorclEPKcS2_iRKNS_8IOstreamE() #0
declare void @_ZN4Foam7IOerror4exitEi() #0 declare void @_ZN4Foam7IOerror4exitEi() #0
; Function Attrs: inlinehint ; Function Attrs: inlinehint
declare void @_ZN4Foam8fileName12stripInvalidEv() #2 align 2 declare void @_ZN4Foam8fileName12stripInvalidEv() #2 align 2
define void @_ZN4Foam3CSVINS_6VectorIdEEE4readEv() #0 align 2 personality ptr @__gxx_personality_v0 { define void @_ZN4Foam3CSVINS_6VectorIdEEE4readEv(i1 %c0, i1 %c1, i1 %c2) #0 align 2 personality ptr @__gxx_personality_v0 {
entry: entry:
invoke void @_ZN4Foam6string6expandEb() invoke void @_ZN4Foam6string6expandEb()
to label %invoke.cont unwind label %lpad to label %invoke.cont unwind label %lpad
invoke.cont: ; preds = %entry invoke.cont: ; preds = %entry
br i1 undef, label %if.then.i.i.i.i176, label %_ZN4Foam6stringC2ERKS0_.exit.i br i1 %c0, label %if.then.i.i.i.i176, label %_ZN4Foam6stringC2ERKS0_.exit.i
if.then.i.i.i.i176: ; preds = %invoke.cont if.then.i.i.i.i176: ; preds = %invoke.cont
invoke void @_ZNKSt3__121__basic_string_commonILb1EE20__throw_length_errorEv() invoke void @_ZNKSt3__121__basic_string_commonILb1EE20__throw_length_errorEv()
to label %.noexc unwind label %lpad to label %.noexc unwind label %lpad
.noexc: ; preds = %if.then.i.i.i.i176 .noexc: ; preds = %if.then.i.i.i.i176
unreachable unreachable
_ZN4Foam6stringC2ERKS0_.exit.i: ; preds = %invoke.cont _ZN4Foam6stringC2ERKS0_.exit.i: ; preds = %invoke.cont
invoke void @_ZN4Foam8fileName12stripInvalidEv() invoke void @_ZN4Foam8fileName12stripInvalidEv()
to label %invoke.cont2 unwind label %lpad.i to label %invoke.cont2 unwind label %lpad.i
lpad.i: ; preds = %_ZN4Foam6stringC2ERKS0_.exit.i lpad.i: ; preds = %_ZN4Foam6stringC2ERKS0_.exit.i
%0 = landingpad { ptr, i32 } %0 = landingpad { ptr, i32 }
cleanup cleanup
br label %ehcleanup142 br label %ehcleanup142
invoke.cont2: ; preds = %_ZN4Foam6stringC2ERKS0_.exit.i invoke.cont2: ; preds = %_ZN4Foam6stringC2ERKS0_.exit.i
invoke void @_ZN4Foam8IFstreamC1ERKNS_8fileNameENS_8IOstream12streamFormatENS4_13versionNumberE() invoke void @_ZN4Foam8IFstreamC1ERKNS_8fileNameENS_8IOstream12streamFormatENS4_13versionNumberE()
to label %invoke.cont4 unwind label %lpad3 to label %invoke.cont4 unwind label %lpad3
invoke.cont4: ; preds = %invoke.cont2 invoke.cont4: ; preds = %invoke.cont2
br i1 undef, label %for.body, label %if.then br i1 %c1, label %for.body, label %if.then
if.then: ; preds = %invoke.cont4 if.then: ; preds = %invoke.cont4
invoke void @_ZN4Foam7IOerrorclEPKcS2_iRKNS_8IOstreamE() invoke void @_ZN4Foam7IOerrorclEPKcS2_iRKNS_8IOstreamE()
to label %invoke.cont8 unwind label %lpad5 to label %invoke.cont8 unwind label %lpad5
invoke.cont8: ; preds = %if.then invoke.cont8: ; preds = %if.then
invoke void @_ZN4FoamlsERNS_7OstreamEPKc() invoke void @_ZN4FoamlsERNS_7OstreamEPKc()
to label %memptr.end.i unwind label %lpad5 to label %memptr.end.i unwind label %lpad5
Show All 13 Lineslpad3: ; preds = %invoke.cont2
br label %ehcleanup142 br label %ehcleanup142
lpad5: ; preds = %memptr.end.i, %invoke.cont8, %if.then lpad5: ; preds = %memptr.end.i, %invoke.cont8, %if.then
%3 = landingpad { ptr, i32 } %3 = landingpad { ptr, i32 }
cleanup cleanup
br label %ehcleanup142 br label %ehcleanup142
if.end: ; preds = %memptr.end.i if.end: ; preds = %memptr.end.i
br i1 undef, label %for.body, label %vector.body br i1 %c2, label %for.body, label %vector.body
for.body: ; preds = %if.end, %invoke.cont4 for.body: ; preds = %if.end, %invoke.cont4
invoke void @_ZNKSt3__18ios_base6getlocEv() invoke void @_ZNKSt3__18ios_base6getlocEv()
to label %.noexc205 unwind label %lpad19 to label %.noexc205 unwind label %lpad19
.noexc205: ; preds = %for.body .noexc205: ; preds = %for.body
invoke void @_ZNKSt3__16locale9use_facetERNS0_2idE() invoke void @_ZNKSt3__16locale9use_facetERNS0_2idE()
to label %invoke.cont.i.i.i unwind label %lpad.i.i.i to label %invoke.cont.i.i.i unwind label %lpad.i.i.i
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llvm/test/CodeGen/PowerPC/pr24546.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s
; Verify that we no longer crash in VSX swap removal when debug values ; Verify that we no longer crash in VSX swap removal when debug values
; are in the code stream. ; are in the code stream.
@php_intpow10.powers = external unnamed_addr constant [23 x double], align 8, !dbg !24 @php_intpow10.powers = external unnamed_addr constant [23 x double], align 8, !dbg !24
; Function Attrs: nounwind ; Function Attrs: nounwind
define double @_php_math_round(double %value, i32 signext %places, i32 signext %mode) #0 !dbg !6 { define double @_php_math_round(double %value, i32 signext %places, i32 signext %mode, i1 %c0, i1 %c1) #0 !dbg !6 {
entry: entry:
br i1 undef, label %if.then, label %if.else, !dbg !32 br i1 %c0, label %if.then, label %if.else, !dbg !32
if.then: ; preds = %entry if.then: ; preds = %entry
%conv = sitofp i32 undef to double, !dbg !34 %conv = sitofp i32 undef to double, !dbg !34
br i1 undef, label %if.then.i, label %if.end.i, !dbg !36 br i1 %c1, label %if.then.i, label %if.end.i, !dbg !36
if.then.i: ; preds = %if.then if.then.i: ; preds = %if.then
%call.i = tail call double @pow(double 1.000000e+01, double undef) #3, !dbg !39 %call.i = tail call double @pow(double 1.000000e+01, double undef) #3, !dbg !39
br label %php_intpow10.exit, !dbg !41 br label %php_intpow10.exit, !dbg !41
if.end.i: ; preds = %if.then if.end.i: ; preds = %if.then
%0 = load double, ptr undef, align 8, !dbg !42, !tbaa !43 %0 = load double, ptr undef, align 8, !dbg !42, !tbaa !43
br label %php_intpow10.exit, !dbg !47 br label %php_intpow10.exit, !dbg !47
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llvm/test/CodeGen/PowerPC/pr24636.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
@c = external global i32, align 4 @c = external global i32, align 4
@b = external global [1 x i32], align 4 @b = external global [1 x i32], align 4
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @fn2() #0 align 4 { define void @fn2(i1 %c0, i1 %c1, i1 %c2, i1 %c3) #0 align 4 {
br i1 undef, label %.lr.ph, label %4 br i1 %c0, label %.lr.ph, label %4
; We used to crash because a bad DAGCombine was creating i32-typed SETCC nodes, ; We used to crash because a bad DAGCombine was creating i32-typed SETCC nodes,
; even when crbits are enabled. ; even when crbits are enabled.
; CHECK-LABEL: @fn2 ; CHECK-LABEL: @fn2
; CHECK: blr ; CHECK: blr
.lr.ph: ; preds = %0 .lr.ph: ; preds = %0
br i1 undef, label %.lr.ph.split, label %.preheader br i1 %c1, label %.lr.ph.split, label %.preheader
.preheader: ; preds = %.preheader, %.lr.ph .preheader: ; preds = %.preheader, %.lr.ph
br i1 undef, label %.lr.ph.split, label %.preheader br i1 %c2, label %.lr.ph.split, label %.preheader
.lr.ph.split: ; preds = %.preheader, %.lr.ph .lr.ph.split: ; preds = %.preheader, %.lr.ph
br i1 undef, label %._crit_edge, label %.lr.ph.split.split br i1 %c3, label %._crit_edge, label %.lr.ph.split.split
.lr.ph.split.split: ; preds = %.lr.ph.split.split, %.lr.ph.split .lr.ph.split.split: ; preds = %.lr.ph.split.split, %.lr.ph.split
%1 = phi i32 [ %2, %.lr.ph.split.split ], [ undef, %.lr.ph.split ] %1 = phi i32 [ %2, %.lr.ph.split.split ], [ undef, %.lr.ph.split ]
%2 = and i32 %1, and (i32 and (i32 and (i32 and (i32 and (i32 and (i32 and (i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)) %2 = and i32 %1, and (i32 and (i32 and (i32 and (i32 and (i32 and (i32 and (i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq (ptr @c, ptr @b), i1 true, i1 false) to i32))
%3 = icmp slt i32 undef, 4 %3 = icmp slt i32 undef, 4
br i1 %3, label %.lr.ph.split.split, label %._crit_edge br i1 %3, label %.lr.ph.split.split, label %._crit_edge
._crit_edge: ; preds = %.lr.ph.split.split, %.lr.ph.split ._crit_edge: ; preds = %.lr.ph.split.split, %.lr.ph.split
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llvm/test/CodeGen/PowerPC/pr25157-peephole.ll

; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck \
; RUN: %s --check-prefix=CHECK-P9 ; RUN: %s --check-prefix=CHECK-P9
; Verify peephole simplification of splats and swaps. Bugpoint-reduced ; Verify peephole simplification of splats and swaps. Bugpoint-reduced
; test from Eric Schweitz. ; test from Eric Schweitz.
%struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625 = type <{ [28 x i8] }> %struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625 = type <{ [28 x i8] }>
%struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626 = type <{ [64 x i8] }> %struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626 = type <{ [64 x i8] }>
@.BSS38 = external global %struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625, align 32 @.BSS38 = external global %struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625, align 32
@_main1_2_ = external global %struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626, section ".comm", align 16 @_main1_2_ = external global %struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626, section ".comm", align 16
define void @aercalc_() { define void @aercalc_(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6) {
L.entry: L.entry:
br i1 undef, label %L.LB38_2426, label %L.LB38_2911 br i1 %c0, label %L.LB38_2426, label %L.LB38_2911
L.LB38_2911: L.LB38_2911:
br i1 undef, label %L.LB38_2140, label %L.LB38_2640 br i1 %c1, label %L.LB38_2140, label %L.LB38_2640
L.LB38_2640: L.LB38_2640:
unreachable unreachable
L.LB38_2426: L.LB38_2426:
br i1 undef, label %L.LB38_2438, label %L.LB38_2920 br i1 %c2, label %L.LB38_2438, label %L.LB38_2920
L.LB38_2920: L.LB38_2920:
br i1 undef, label %L.LB38_2438, label %L.LB38_2921 br i1 %c3, label %L.LB38_2438, label %L.LB38_2921
L.LB38_2921: L.LB38_2921:
br label %L.LB38_2140 br label %L.LB38_2140
L.LB38_2140: L.LB38_2140:
ret void ret void
L.LB38_2438: L.LB38_2438:
br i1 undef, label %L.LB38_2451, label %L.LB38_2935 br i1 %c4, label %L.LB38_2451, label %L.LB38_2935
L.LB38_2935: L.LB38_2935:
br i1 undef, label %L.LB38_2451, label %L.LB38_2936 br i1 %c5, label %L.LB38_2451, label %L.LB38_2936
L.LB38_2936: L.LB38_2936:
unreachable unreachable
L.LB38_2451: L.LB38_2451:
br i1 undef, label %L.LB38_2452, label %L.LB38_2937 br i1 %c6, label %L.LB38_2452, label %L.LB38_2937
L.LB38_2937: L.LB38_2937:
unreachable unreachable
L.LB38_2452: L.LB38_2452:
%0 = load float, ptr getelementptr inbounds (%struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625, ptr @.BSS38, i64 0, i32 0, i64 16), align 16 %0 = load float, ptr getelementptr inbounds (%struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625, ptr @.BSS38, i64 0, i32 0, i64 16), align 16
%1 = fpext float %0 to double %1 = fpext float %0 to double
%2 = insertelement <2 x double> undef, double %1, i32 1 %2 = insertelement <2 x double> undef, double %1, i32 1
Show All 14 Lines

llvm/test/CodeGen/PowerPC/pr25157.ll

; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck \
; RUN: --check-prefix=CHECK-P9 %s ; RUN: --check-prefix=CHECK-P9 %s
; Verify correct generation of an lxsspx rather than an invalid optimization ; Verify correct generation of an lxsspx rather than an invalid optimization
; to lxvdsx. Bugpoint-reduced test from Eric Schweitz. ; to lxvdsx. Bugpoint-reduced test from Eric Schweitz.
%struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625 = type <{ [28 x i8] }> %struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625 = type <{ [28 x i8] }>
%struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626 = type <{ [64 x i8] }> %struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626 = type <{ [64 x i8] }>
@.BSS38 = external global %struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625, align 32 @.BSS38 = external global %struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625, align 32
@_main1_2_ = external global %struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626, section ".comm", align 16 @_main1_2_ = external global %struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626, section ".comm", align 16
define void @aercalc_() { define void @aercalc_(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6) {
L.entry: L.entry:
br i1 undef, label %L.LB38_2426, label %L.LB38_2911 br i1 %c0, label %L.LB38_2426, label %L.LB38_2911
L.LB38_2911: L.LB38_2911:
br i1 undef, label %L.LB38_2140, label %L.LB38_2640 br i1 %c1, label %L.LB38_2140, label %L.LB38_2640
L.LB38_2640: L.LB38_2640:
unreachable unreachable
L.LB38_2426: L.LB38_2426:
br i1 undef, label %L.LB38_2438, label %L.LB38_2920 br i1 %c2, label %L.LB38_2438, label %L.LB38_2920
L.LB38_2920: L.LB38_2920:
br i1 undef, label %L.LB38_2438, label %L.LB38_2921 br i1 %c3, label %L.LB38_2438, label %L.LB38_2921
L.LB38_2921: L.LB38_2921:
br label %L.LB38_2140 br label %L.LB38_2140
L.LB38_2140: L.LB38_2140:
ret void ret void
L.LB38_2438: L.LB38_2438:
br i1 undef, label %L.LB38_2451, label %L.LB38_2935 br i1 %c4, label %L.LB38_2451, label %L.LB38_2935
L.LB38_2935: L.LB38_2935:
br i1 undef, label %L.LB38_2451, label %L.LB38_2936 br i1 %c5, label %L.LB38_2451, label %L.LB38_2936
L.LB38_2936: L.LB38_2936:
unreachable unreachable
L.LB38_2451: L.LB38_2451:
br i1 undef, label %L.LB38_2452, label %L.LB38_2937 br i1 %c6, label %L.LB38_2452, label %L.LB38_2937
L.LB38_2937: L.LB38_2937:
unreachable unreachable
L.LB38_2452: L.LB38_2452:
%0 = load float, ptr getelementptr inbounds (%struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625, ptr @.BSS38, i64 0, i32 0, i64 16), align 16 %0 = load float, ptr getelementptr inbounds (%struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625, ptr @.BSS38, i64 0, i32 0, i64 16), align 16
%1 = fpext float %0 to double %1 = fpext float %0 to double
%2 = insertelement <2 x double> undef, double %1, i32 1 %2 = insertelement <2 x double> undef, double %1, i32 1
store <2 x double> %2, ptr getelementptr inbounds (%struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626, ptr @_main1_2_, i64 0, i32 0, i64 32), align 16 store <2 x double> %2, ptr getelementptr inbounds (%struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626, ptr @_main1_2_, i64 0, i32 0, i64 32), align 16
unreachable unreachable
} }
; CHECK-LABEL: @aercalc_ ; CHECK-LABEL: @aercalc_
; CHECK: lfs ; CHECK: lfs
; CHECK-P9-LABEL: @aercalc_ ; CHECK-P9-LABEL: @aercalc_
; CHECK-P9: lfs ; CHECK-P9: lfs

llvm/test/CodeGen/PowerPC/pr43527.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; We don't want to produce a CTR loop due to the call to lrint in the body. ; We don't want to produce a CTR loop due to the call to lrint in the body.
define dso_local void @test(i64 %arg, i64 %arg1) { define dso_local void @test(i64 %arg, i64 %arg1, i1 %c0, i1 %c1) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_5 ; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_5
; CHECK-NEXT: # %bb.1: # %bb3 ; CHECK-NEXT: # %bb.1: # %bb3
; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_6 ; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_6
; CHECK-NEXT: # %bb.2: # %bb4 ; CHECK-NEXT: # %bb.2: # %bb4
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
Show All 21 Lines
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: .LBB0_5: # %bb2 ; CHECK-NEXT: .LBB0_5: # %bb2
; CHECK-NEXT: .LBB0_6: # %bb14 ; CHECK-NEXT: .LBB0_6: # %bb14
bb: bb:
br i1 undef, label %bb3, label %bb2 br i1 %c0, label %bb3, label %bb2
bb2: ; preds = %bb bb2: ; preds = %bb
unreachable unreachable
bb3: ; preds = %bb bb3: ; preds = %bb
%tmp = sub i64 %arg1, %arg %tmp = sub i64 %arg1, %arg
br i1 undef, label %bb4, label %bb14 br i1 %c1, label %bb4, label %bb14
bb4: ; preds = %bb3 bb4: ; preds = %bb3
br label %bb5 br label %bb5
bb5: ; preds = %bb5, %bb4 bb5: ; preds = %bb5, %bb4
%tmp6 = phi i64 [ %tmp12, %bb5 ], [ 0, %bb4 ] %tmp6 = phi i64 [ %tmp12, %bb5 ], [ 0, %bb4 ]
%tmp7 = getelementptr inbounds float, ptr null, i64 %tmp6 %tmp7 = getelementptr inbounds float, ptr null, i64 %tmp6
%tmp8 = load float, ptr %tmp7, align 4 %tmp8 = load float, ptr %tmp7, align 4
Show All 16 Lines

llvm/test/CodeGen/PowerPC/pr45709.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: -mcpu=pwr6 -ppc-asm-full-reg-names -mattr=-vsx \ ; RUN: -mcpu=pwr6 -ppc-asm-full-reg-names -mattr=-vsx \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
; There is code in the SDAG to expand FMAX/FMIN with fast flags to SELECT_CC. ; There is code in the SDAG to expand FMAX/FMIN with fast flags to SELECT_CC.
; On PPC, we had SELECT_CC legalized using Promote for all vector types ; On PPC, we had SELECT_CC legalized using Promote for all vector types
; (including the type that they are all promoted to - which caused an infinite ; (including the type that they are all promoted to - which caused an infinite
; loop in legalization). This test just ensures that we terminate on such input. ; loop in legalization). This test just ensures that we terminate on such input.
define dso_local void @_ZN1a1bEv(<4 x float> %in) local_unnamed_addr #0 align 2 { define dso_local void @_ZN1a1bEv(<4 x float> %in, i1 %c0, i1 %c1) local_unnamed_addr #0 align 2 {
; CHECK-LABEL: _ZN1a1bEv: ; CHECK-LABEL: _ZN1a1bEv:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_6 ; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_6
; CHECK-NEXT: b .LBB0_1 ; CHECK-NEXT: b .LBB0_1
; CHECK-NEXT: .LBB0_1: # %.preheader ; CHECK-NEXT: .LBB0_1: # %.preheader
; CHECK-NEXT: b .LBB0_2 ; CHECK-NEXT: b .LBB0_2
; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: b .LBB0_3 ; CHECK-NEXT: b .LBB0_3
Show All 19 Lines
; CHECK-NEXT: stw r3, -64(r1) ; CHECK-NEXT: stw r3, -64(r1)
; CHECK-NEXT: addi r3, r1, -64 ; CHECK-NEXT: addi r3, r1, -64
; CHECK-NEXT: lvx v2, 0, r3 ; CHECK-NEXT: lvx v2, 0, r3
; CHECK-NEXT: addi r3, r1, -16 ; CHECK-NEXT: addi r3, r1, -16
; CHECK-NEXT: stvx v2, 0, r3 ; CHECK-NEXT: stvx v2, 0, r3
; CHECK-NEXT: lfs f0, -16(r1) ; CHECK-NEXT: lfs f0, -16(r1)
; CHECK-NEXT: .LBB0_6: ; CHECK-NEXT: .LBB0_6:
; CHECK-NEXT: blr ; CHECK-NEXT: blr
br i1 undef, label %7, label %1 br i1 %c0, label %7, label %1
1: ; preds = %1, %0 1: ; preds = %1, %0
br i1 undef, label %2, label %1 br i1 %c1, label %2, label %1
2: ; preds = %1 2: ; preds = %1
%3 = shufflevector <4 x float> %in, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> %3 = shufflevector <4 x float> %in, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
%4 = call fast <4 x float> @llvm.maxnum.v4f32(<4 x float> %3, <4 x float> zeroinitializer) %4 = call fast <4 x float> @llvm.maxnum.v4f32(<4 x float> %3, <4 x float> zeroinitializer)
%5 = call fast <4 x float> @llvm.maxnum.v4f32(<4 x float> %4, <4 x float> undef) %5 = call fast <4 x float> @llvm.maxnum.v4f32(<4 x float> %4, <4 x float> undef)
%6 = extractelement <4 x float> %5, i32 0 %6 = extractelement <4 x float> %5, i32 0
br label %7 br label %7
Show All 9 Lines

llvm/test/CodeGen/PowerPC/pr46923.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s
@bar = external constant i64, align 8 @bar = external constant i64, align 8
define i1 @foo() { define i1 @foo(i1 %c0) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
br label %next br label %next
next: next:
br i1 undef, label %true, label %false br i1 %c0, label %true, label %false
true: true:
br label %end br label %end
false: false:
br label %end br label %end
end: end:
%a = phi i1 [ icmp ugt (i64 0, i64 ptrtoint (ptr @bar to i64)), %true ], %a = phi i1 [ icmp ugt (i64 0, i64 ptrtoint (ptr @bar to i64)), %true ],
[ icmp ugt (i64 0, i64 2), %false ] [ icmp ugt (i64 0, i64 2), %false ]
ret i1 %a ret i1 %a
} }

llvm/test/CodeGen/PowerPC/pr48519.ll

Show First 20 Lines • Show All 137 Lines • ▼ Show 20 Linesbb3: ; preds = %bb1
%i7 = fcmp uno float %i6, 0.000000e+00 %i7 = fcmp uno float %i6, 0.000000e+00
%i8 = or i1 %i7, false %i8 = or i1 %i7, false
br i1 %i8, label %bb1, label %bb9 br i1 %i8, label %bb1, label %bb9
bb9: ; preds = %bb3, %bb1 bb9: ; preds = %bb3, %bb1
ret void ret void
} }
define void @func_48786() #0 { define void @func_48786(i1 %c0) #0 {
; CHECK-LABEL: func_48786: ; CHECK-LABEL: func_48786:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: mfocrf r12, 32 ; CHECK-NEXT: mfocrf r12, 32
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: stw r12, 8(r1) ; CHECK-NEXT: stw r12, 8(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1) ; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: std r30, 32(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, 32(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: .LBB2_5: # %bb15 ; CHECK-P9-NEXT: .LBB2_5: # %bb15
bb: bb:
%i = load i64, ptr addrspace(11) undef, align 8 %i = load i64, ptr addrspace(11) undef, align 8
%i1 = load i64, ptr addrspace(11) undef, align 8 %i1 = load i64, ptr addrspace(11) undef, align 8
br label %bb2 br label %bb2
bb2: ; preds = %bb12, %bb bb2: ; preds = %bb12, %bb
%i3 = phi i64 [ undef, %bb ], [ %i13, %bb12 ] %i3 = phi i64 [ undef, %bb ], [ %i13, %bb12 ]
br i1 undef, label %bb10, label %bb4 br i1 %c0, label %bb10, label %bb4
bb4: ; preds = %bb2 bb4: ; preds = %bb2
switch i32 undef, label %bb9 [ switch i32 undef, label %bb9 [
i32 1426063360, label %bb5 i32 1426063360, label %bb5
i32 1275068416, label %bb5 i32 1275068416, label %bb5
] ]
bb5: ; preds = %bb4, %bb4 bb5: ; preds = %bb4, %bb4
▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/pr49509.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
target datalayout = "E-m:e-p:32:32-i64:64-n32" target datalayout = "E-m:e-p:32:32-i64:64-n32"
define void @test() { define void @test(i1 %c0, i1 %c1) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: bc 12, 20, .LBB0_2 ; CHECK-NEXT: bc 12, 20, .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb2 ; CHECK-NEXT: # %bb.1: # %bb2
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: stw 3, 0(3) ; CHECK-NEXT: stw 3, 0(3)
; CHECK-NEXT: lis 3, 256 ; CHECK-NEXT: lis 3, 256
; CHECK-NEXT: stw 3, 0(3) ; CHECK-NEXT: stw 3, 0(3)
Show All 32 Lines
; CHECK-NEXT: ori 3, 6, 0 ; CHECK-NEXT: ori 3, 6, 0
; CHECK-NEXT: b .LBB0_10 ; CHECK-NEXT: b .LBB0_10
; CHECK-NEXT: .LBB0_9: # %bb66 ; CHECK-NEXT: .LBB0_9: # %bb66
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: .LBB0_10: # %bb66 ; CHECK-NEXT: .LBB0_10: # %bb66
; CHECK-NEXT: stw 3, 0(3) ; CHECK-NEXT: stw 3, 0(3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
bb: bb:
br i1 undef, label %bb2, label %bb1 br i1 %c0, label %bb2, label %bb1
bb2: ; preds = %bb bb2: ; preds = %bb
%i = select i1 undef, i64 0, i64 72057594037927936 %i = select i1 undef, i64 0, i64 72057594037927936
store i64 %i, ptr undef, align 8 store i64 %i, ptr undef, align 8
ret void ret void
bb1: ; preds = %bb bb1: ; preds = %bb
%i50 = load i8, ptr undef, align 8 %i50 = load i8, ptr undef, align 8
%i52 = load i128, ptr null, align 8 %i52 = load i128, ptr null, align 8
%i62 = icmp eq i8 %i50, 0 %i62 = icmp eq i8 %i50, 0
br i1 undef, label %bb66, label %bb64 br i1 %c1, label %bb66, label %bb64
bb64: ; preds = %bb63 bb64: ; preds = %bb63
ret void ret void
bb66: ; preds = %bb63 bb66: ; preds = %bb63
%i67 = lshr i128 -1, 0 %i67 = lshr i128 -1, 0
%i68 = xor i128 %i52, -1 %i68 = xor i128 %i52, -1
%i69 = add i128 0, %i68 %i69 = add i128 0, %i68
%i70 = and i128 %i67, %i69 %i70 = and i128 %i67, %i69
%i71 = icmp eq i128 %i70, 0 %i71 = icmp eq i128 %i70, 0
%i74 = select i1 %i62, i64 0, i64 72057594037927936 %i74 = select i1 %i62, i64 0, i64 72057594037927936
%i75 = select i1 %i71, i64 144115188075855872, i64 %i74 %i75 = select i1 %i71, i64 144115188075855872, i64 %i74
store i64 %i75, ptr undef, align 8 store i64 %i75, ptr undef, align 8
ret void ret void
} }

llvm/test/CodeGen/PowerPC/preinc-ld-sel-crash.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux" target triple = "powerpc64le-unknown-linux"
%t1 = type { ptr, ptr } %t1 = type { ptr, ptr }
%t2 = type <{ ptr, i32, [4 x i8] }> %t2 = type <{ ptr, i32, [4 x i8] }>
%t3 = type { ptr } %t3 = type { ptr }
@_ZN4Foam10SLListBase13endConstIter_E = external global %t1 @_ZN4Foam10SLListBase13endConstIter_E = external global %t1
define void @_ZN4FoamrsIbEERNS_7IstreamES2_RNS_4ListIT_EE() #0 { define void @_ZN4FoamrsIbEERNS_7IstreamES2_RNS_4ListIT_EE(i1 %c0, i1 %c1, i1 %c2) #0 {
entry: entry:
switch i32 undef, label %if.else82 [ switch i32 undef, label %if.else82 [
i32 9, label %if.then i32 9, label %if.then
i32 6, label %invoke.cont10 i32 6, label %invoke.cont10
i32 1, label %invoke.cont61 i32 1, label %invoke.cont61
] ]
if.then: ; preds = %entry if.then: ; preds = %entry
unreachable unreachable
invoke.cont10: ; preds = %entry invoke.cont10: ; preds = %entry
unreachable unreachable
invoke.cont61: ; preds = %entry invoke.cont61: ; preds = %entry
br i1 undef, label %if.end75, label %if.then64 br i1 %c0, label %if.end75, label %if.then64
if.then64: ; preds = %invoke.cont61 if.then64: ; preds = %invoke.cont61
unreachable unreachable
if.end75: ; preds = %invoke.cont61 if.end75: ; preds = %invoke.cont61
br i1 undef, label %if.then17.i, label %if.then.i181 br i1 %c1, label %if.then17.i, label %if.then.i181
if.then.i181: ; preds = %if.end75 if.then.i181: ; preds = %if.end75
unreachable unreachable
if.then17.i: ; preds = %if.end75 if.then17.i: ; preds = %if.end75
%tobool.i.i.i = icmp eq i32 undef, 0 %tobool.i.i.i = icmp eq i32 undef, 0
%0 = load ptr, ptr undef, align 8 %0 = load ptr, ptr undef, align 8
%agg.tmp.sroa.3.0.copyload33.in.i = select i1 %tobool.i.i.i, ptr getelementptr inbounds (%t1, ptr @_ZN4Foam10SLListBase13endConstIter_E, i64 0, i32 1), ptr %0 %agg.tmp.sroa.3.0.copyload33.in.i = select i1 %tobool.i.i.i, ptr getelementptr inbounds (%t1, ptr @_ZN4Foam10SLListBase13endConstIter_E, i64 0, i32 1), ptr %0
%agg.tmp.sroa.3.0.copyload33.i = load i64, ptr %agg.tmp.sroa.3.0.copyload33.in.i, align 8 %agg.tmp.sroa.3.0.copyload33.i = load i64, ptr %agg.tmp.sroa.3.0.copyload33.in.i, align 8
%1 = inttoptr i64 %agg.tmp.sroa.3.0.copyload33.i to ptr %1 = inttoptr i64 %agg.tmp.sroa.3.0.copyload33.i to ptr
%2 = load ptr, ptr getelementptr inbounds (%t1, ptr @_ZN4Foam10SLListBase13endConstIter_E, i64 0, i32 1), align 8 %2 = load ptr, ptr getelementptr inbounds (%t1, ptr @_ZN4Foam10SLListBase13endConstIter_E, i64 0, i32 1), align 8
%cmp.i37.i = icmp eq ptr %1, %2 %cmp.i37.i = icmp eq ptr %1, %2
br i1 %cmp.i37.i, label %invoke.cont79, label %for.body.lr.ph.i br i1 %cmp.i37.i, label %invoke.cont79, label %for.body.lr.ph.i
; CHECK-LABEL: @_ZN4FoamrsIbEERNS_7IstreamES2_RNS_4ListIT_EE ; CHECK-LABEL: @_ZN4FoamrsIbEERNS_7IstreamES2_RNS_4ListIT_EE
for.body.lr.ph.i: ; preds = %if.then17.i for.body.lr.ph.i: ; preds = %if.then17.i
br label %for.body.i br label %for.body.i
for.body.i: ; preds = %for.body.i, %for.body.lr.ph.i for.body.i: ; preds = %for.body.i, %for.body.lr.ph.i
br i1 undef, label %invoke.cont79, label %for.body.i br i1 %c2, label %invoke.cont79, label %for.body.i
invoke.cont79: ; preds = %for.body.i, %if.then17.i invoke.cont79: ; preds = %for.body.i, %if.then17.i
unreachable unreachable
if.else82: ; preds = %entry if.else82: ; preds = %entry
ret void ret void
} }
attributes #0 = { "target-cpu"="a2q" } attributes #0 = { "target-cpu"="a2q" }

llvm/test/CodeGen/PowerPC/preincprep-nontrans-crash.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "e-p:64:64-i64:64-n32:64" target datalayout = "e-p:64:64-i64:64-n32:64"
target triple = "powerpc64le-linux" target triple = "powerpc64le-linux"
%struct.BSS1.0.9.28.39.43.46.47.54.56.57.64.65.69.71.144 = type <{ [220 x i8] }> %struct.BSS1.0.9.28.39.43.46.47.54.56.57.64.65.69.71.144 = type <{ [220 x i8] }>
@.BSS1 = external unnamed_addr global %struct.BSS1.0.9.28.39.43.46.47.54.56.57.64.65.69.71.144, align 32 @.BSS1 = external unnamed_addr global %struct.BSS1.0.9.28.39.43.46.47.54.56.57.64.65.69.71.144, align 32
; Function Attrs: noinline nounwind ; Function Attrs: noinline nounwind
define void @ety2_() #0 { define void @ety2_(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) #0 {
; This test case used to crash because the preinc prep pass would assume that ; This test case used to crash because the preinc prep pass would assume that
; if X-Y could be simplified to a constant, than so could Y-X. While not ; if X-Y could be simplified to a constant, than so could Y-X. While not
; desirable, we cannot actually make this guarantee. ; desirable, we cannot actually make this guarantee.
; CHECK-LABEL: @ety2_ ; CHECK-LABEL: @ety2_
L.entry: L.entry:
%0 = load i32, i32* undef, align 4 %0 = load i32, i32* undef, align 4
%1 = sext i32 %0 to i64 %1 = sext i32 %0 to i64
%2 = shl nsw i64 %1, 3 %2 = shl nsw i64 %1, 3
%3 = add nsw i64 %2, 8 %3 = add nsw i64 %2, 8
br label %L.LB1_425 br label %L.LB1_425
L.LB1_425: ; preds = %L.LB1_427, %L.entry L.LB1_425: ; preds = %L.LB1_427, %L.entry
%4 = phi i64 [ %21, %L.LB1_427 ], [ undef, %L.entry ] %4 = phi i64 [ %21, %L.LB1_427 ], [ undef, %L.entry ]
br i1 undef, label %L.LB1_427, label %L.LB1_816 br i1 %c0, label %L.LB1_427, label %L.LB1_816
L.LB1_816: ; preds = %L.LB1_425 L.LB1_816: ; preds = %L.LB1_425
switch i32 undef, label %L.LB1_432 [ switch i32 undef, label %L.LB1_432 [
i32 30, label %L.LB1_805 i32 30, label %L.LB1_805
i32 10, label %L.LB1_451 i32 10, label %L.LB1_451
i32 20, label %L.LB1_451 i32 20, label %L.LB1_451
] ]
L.LB1_451: ; preds = %L.LB1_816, %L.LB1_816 L.LB1_451: ; preds = %L.LB1_816, %L.LB1_816
unreachable unreachable
L.LB1_432: ; preds = %L.LB1_816 L.LB1_432: ; preds = %L.LB1_816
%.in.31 = lshr i64 %4, 32 %.in.31 = lshr i64 %4, 32
%5 = trunc i64 %.in.31 to i32 %5 = trunc i64 %.in.31 to i32
br i1 undef, label %L.LB1_769, label %L.LB1_455 br i1 %c1, label %L.LB1_769, label %L.LB1_455
L.LB1_455: ; preds = %L.LB1_432 L.LB1_455: ; preds = %L.LB1_432
unreachable unreachable
L.LB1_769: ; preds = %L.LB1_432 L.LB1_769: ; preds = %L.LB1_432
%6 = sext i32 %5 to i64 %6 = sext i32 %5 to i64
%7 = add nsw i64 %6, 2 %7 = add nsw i64 %6, 2
%8 = add nsw i64 %6, -1 %8 = add nsw i64 %6, -1
%9 = mul i64 %8, %1 %9 = mul i64 %8, %1
%10 = add i64 %9, %7 %10 = add i64 %9, %7
%11 = shl i64 %10, 3 %11 = shl i64 %10, 3
%12 = getelementptr i8, i8* undef, i64 %11 %12 = getelementptr i8, i8* undef, i64 %11
%13 = mul nsw i64 %6, %1 %13 = mul nsw i64 %6, %1
%14 = add i64 %7, %13 %14 = add i64 %7, %13
%15 = shl i64 %14, 3 %15 = shl i64 %14, 3
%16 = getelementptr i8, i8* undef, i64 %15 %16 = getelementptr i8, i8* undef, i64 %15
br i1 undef, label %L.LB1_662, label %L.LB1_662.prol br i1 %c2, label %L.LB1_662, label %L.LB1_662.prol
L.LB1_662.prol: ; preds = %L.LB1_662.prol, %L.LB1_769 L.LB1_662.prol: ; preds = %L.LB1_662.prol, %L.LB1_769
%indvars.iv.next20.prol = add nuw nsw i64 undef, 1 %indvars.iv.next20.prol = add nuw nsw i64 undef, 1
br i1 undef, label %L.LB1_662, label %L.LB1_662.prol br i1 %c3, label %L.LB1_662, label %L.LB1_662.prol
L.LB1_662: ; preds = %L.LB1_437.2, %L.LB1_662.prol, %L.LB1_769 L.LB1_662: ; preds = %L.LB1_437.2, %L.LB1_662.prol, %L.LB1_769
%indvars.iv19 = phi i64 [ %indvars.iv.next20.3, %L.LB1_437.2 ], [ 0, %L.LB1_769 ], [ %indvars.iv.next20.prol, %L.LB1_662.prol ] %indvars.iv19 = phi i64 [ %indvars.iv.next20.3, %L.LB1_437.2 ], [ 0, %L.LB1_769 ], [ %indvars.iv.next20.prol, %L.LB1_662.prol ]
%indvars.iv.next20 = add nuw nsw i64 %indvars.iv19, 1 %indvars.iv.next20 = add nuw nsw i64 %indvars.iv19, 1
%17 = mul i64 %indvars.iv.next20, %3 %17 = mul i64 %indvars.iv.next20, %3
%18 = getelementptr i8, i8* %16, i64 %17 %18 = getelementptr i8, i8* %16, i64 %17
%19 = bitcast i8* %18 to double* %19 = bitcast i8* %18 to double*
store double 0.000000e+00, double* %19, align 8 store double 0.000000e+00, double* %19, align 8
%indvars.iv.next20.1 = add nsw i64 %indvars.iv19, 2 %indvars.iv.next20.1 = add nsw i64 %indvars.iv19, 2
%20 = mul i64 %indvars.iv.next20.1, %3 %20 = mul i64 %indvars.iv.next20.1, %3
br i1 undef, label %L.LB1_437.2, label %L.LB1_824.2 br i1 %c4, label %L.LB1_437.2, label %L.LB1_824.2
L.LB1_427: ; preds = %L.LB1_425 L.LB1_427: ; preds = %L.LB1_425
%21 = load i64, i64* bitcast (i8* getelementptr inbounds (%struct.BSS1.0.9.28.39.43.46.47.54.56.57.64.65.69.71.144, %struct.BSS1.0.9.28.39.43.46.47.54.56.57.64.65.69.71.144* @.BSS1, i64 0, i32 0, i64 8) to i64*), align 8 %21 = load i64, i64* bitcast (i8* getelementptr inbounds (%struct.BSS1.0.9.28.39.43.46.47.54.56.57.64.65.69.71.144, %struct.BSS1.0.9.28.39.43.46.47.54.56.57.64.65.69.71.144* @.BSS1, i64 0, i32 0, i64 8) to i64*), align 8
br label %L.LB1_425 br label %L.LB1_425
L.LB1_805: ; preds = %L.LB1_816 L.LB1_805: ; preds = %L.LB1_816
ret void ret void
Show All 13 Lines

llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O3 < %s | FileCheck %s \ ; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O3 < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-P9 ; RUN: --check-prefix=CHECK-P9
%class.A = type <{ %"class.D", %"class.D", i32, i32, i32, %"class.B", %"class.C", %"class.C", %"class.C", %"class.C", %"class.D", [2 x i8], %"class.E", %"class.F", %"class.G", %"class.G", %"class.H", i32, [4 x i8] }> %class.A = type <{ %"class.D", %"class.D", i32, i32, i32, %"class.B", %"class.C", %"class.C", %"class.C", %"class.C", %"class.D", [2 x i8], %"class.E", %"class.F", %"class.G", %"class.G", %"class.H", i32, [4 x i8] }>
%"class.B" = type { [441 x i32] } %"class.B" = type { [441 x i32] }
%"class.C" = type { [442 x i16] } %"class.C" = type { [442 x i16] }
%"class.D" = type { [441 x i16] } %"class.D" = type { [441 x i16] }
%"class.E" = type { [4 x i32] } %"class.E" = type { [4 x i32] }
%"class.F" = type { [8 x i32] } %"class.F" = type { [8 x i32] }
%"class.G" = type { [2 x i32] } %"class.G" = type { [2 x i32] }
%"class.H" = type { %"struct.A" } %"class.H" = type { %"struct.A" }
%"struct.A" = type { %"struct.B" } %"struct.A" = type { %"struct.B" }
%"struct.B" = type { ptr, ptr, ptr } %"struct.B" = type { ptr, ptr, ptr }
define dso_local i1 @t(ptr %this, i32 %color, i32 %vertex) local_unnamed_addr { define dso_local i1 @t(ptr %this, i32 %color, i32 %vertex, i1 %c0, i1 %c1) local_unnamed_addr {
; CHECK-P9-LABEL: t: ; CHECK-P9-LABEL: t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: li r5, 1 ; CHECK-P9-NEXT: li r5, 1
; CHECK-P9-NEXT: bc 12, 4*cr5+lt, .LBB0_4 ; CHECK-P9-NEXT: bc 12, 4*cr5+lt, .LBB0_4
; CHECK-P9-NEXT: # %bb.1: # %land.lhs.true ; CHECK-P9-NEXT: # %bb.1: # %land.lhs.true
; CHECK-P9-NEXT: bc 12, 4*cr5+lt, .LBB0_5 ; CHECK-P9-NEXT: bc 12, 4*cr5+lt, .LBB0_5
; CHECK-P9-NEXT: .LBB0_2: # %for.inc ; CHECK-P9-NEXT: .LBB0_2: # %for.inc
; CHECK-P9-NEXT: lhz r3, 5308(r3) ; CHECK-P9-NEXT: lhz r3, 5308(r3)
; CHECK-P9-NEXT: cmplwi r3, 2 ; CHECK-P9-NEXT: cmplwi r3, 2
; CHECK-P9-NEXT: bge- cr0, .LBB0_6 ; CHECK-P9-NEXT: bge- cr0, .LBB0_6
; CHECK-P9-NEXT: # %bb.3: # %land.lhs.true.1 ; CHECK-P9-NEXT: # %bb.3: # %land.lhs.true.1
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; CHECK-P9-NEXT: .LBB0_4: # %lor.lhs.false ; CHECK-P9-NEXT: .LBB0_4: # %lor.lhs.false
; CHECK-P9-NEXT: cmplwi r4, 0 ; CHECK-P9-NEXT: cmplwi r4, 0
; CHECK-P9-NEXT: bne cr0, .LBB0_2 ; CHECK-P9-NEXT: bne cr0, .LBB0_2
; CHECK-P9-NEXT: .LBB0_5: # %cleanup16 ; CHECK-P9-NEXT: .LBB0_5: # %cleanup16
; CHECK-P9-NEXT: mr r3, r5 ; CHECK-P9-NEXT: mr r3, r5
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; CHECK-P9-NEXT: .LBB0_6: # %lor.lhs.false.1 ; CHECK-P9-NEXT: .LBB0_6: # %lor.lhs.false.1
entry: entry:
br i1 undef, label %land.lhs.true, label %lor.lhs.false br i1 %c0, label %land.lhs.true, label %lor.lhs.false
land.lhs.true: ; preds = %entry land.lhs.true: ; preds = %entry
br i1 undef, label %cleanup16, label %for.inc br i1 %c1, label %cleanup16, label %for.inc
lor.lhs.false: ; preds = %entry lor.lhs.false: ; preds = %entry
%cmp11 = icmp ne i16 0, 2 %cmp11 = icmp ne i16 0, 2
%cmp13 = icmp eq i32 0, %color %cmp13 = icmp eq i32 0, %color
%or.cond = and i1 %cmp13, %cmp11 %or.cond = and i1 %cmp13, %cmp11
br i1 %or.cond, label %cleanup16, label %for.inc br i1 %or.cond, label %cleanup16, label %for.inc
for.inc: ; preds = %lor.lhs.false, %land.lhs.true for.inc: ; preds = %lor.lhs.false, %land.lhs.true
Show All 22 Lines

llvm/test/CodeGen/PowerPC/remap-crash.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @autogen_SD13() { define void @autogen_SD13(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7) {
BB: BB:
br label %CF78 br label %CF78
CF78: ; preds = %CF87, %CF86, %CF78, %BB CF78: ; preds = %CF87, %CF86, %CF78, %BB
%Cmp = icmp ule <16 x i64> zeroinitializer, zeroinitializer %Cmp = icmp ule <16 x i64> zeroinitializer, zeroinitializer
br i1 undef, label %CF78, label %CF86 br i1 %c0, label %CF78, label %CF86
CF86: ; preds = %CF78 CF86: ; preds = %CF78
br i1 undef, label %CF78, label %CF84 br i1 %c1, label %CF78, label %CF84
CF84: ; preds = %CF84, %CF86 CF84: ; preds = %CF84, %CF86
br i1 undef, label %CF84, label %CF87 br i1 %c2, label %CF84, label %CF87
CF87: ; preds = %CF84 CF87: ; preds = %CF84
br i1 undef, label %CF78, label %CF82 br i1 %c3, label %CF78, label %CF82
CF82: ; preds = %CF82, %CF87 CF82: ; preds = %CF82, %CF87
br i1 undef, label %CF82, label %CF83 br i1 %c4, label %CF82, label %CF83
CF83: ; preds = %CF82 CF83: ; preds = %CF82
br label %CF br label %CF
CF: ; preds = %CF80, %CF81, %CF, %CF83 CF: ; preds = %CF80, %CF81, %CF, %CF83
br i1 undef, label %CF, label %CF81 br i1 %c5, label %CF, label %CF81
CF81: ; preds = %CF CF81: ; preds = %CF
%Se = sext <16 x i1> %Cmp to <16 x i16> %Se = sext <16 x i1> %Cmp to <16 x i16>
br i1 undef, label %CF, label %CF80 br i1 %c6, label %CF, label %CF80
CF80: ; preds = %CF81 CF80: ; preds = %CF81
br i1 undef, label %CF, label %CF76 br i1 %c7, label %CF, label %CF76
CF76: ; preds = %CF76, %CF80 CF76: ; preds = %CF76, %CF80
%Sl58 = select i1 undef, <16 x i16> %Se, <16 x i16> %Se %Sl58 = select i1 undef, <16 x i16> %Se, <16 x i16> %Se
br label %CF76 br label %CF76
} }
define void @autogen_SD1067() { define void @autogen_SD1067(i1 %c0) {
BB: BB:
%FC = sitofp <4 x i32> zeroinitializer to <4 x ppc_fp128> %FC = sitofp <4 x i32> zeroinitializer to <4 x ppc_fp128>
br label %CF77 br label %CF77
CF77: ; preds = %CF77, %BB CF77: ; preds = %CF77, %BB
%brmerge = or i1 false, undef %brmerge = or i1 false, %c0
br i1 %brmerge, label %CF77, label %CF85 br i1 %brmerge, label %CF77, label %CF85
CF85: ; preds = %CF77 CF85: ; preds = %CF77
%Shuff19 = shufflevector <4 x ppc_fp128> %FC, <4 x ppc_fp128> %FC, <4 x i32> <i32 7, i32 1, i32 3, i32 5> %Shuff19 = shufflevector <4 x ppc_fp128> %FC, <4 x ppc_fp128> %FC, <4 x i32> <i32 7, i32 1, i32 3, i32 5>
br label %CF75 br label %CF75
CF75: ; preds = %CF75, %CF85 CF75: ; preds = %CF75, %CF85
br label %CF75 br label %CF75
} }

llvm/test/CodeGen/PowerPC/rlwimi-and.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-crbits -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-crbits -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
define void @test() align 2 { define void @test(i1 %c0, i1 %c1, i1 %c2) align 2 {
entry: entry:
br i1 undef, label %codeRepl1, label %codeRepl31 br i1 %c0, label %codeRepl1, label %codeRepl31
codeRepl1: ; preds = %entry codeRepl1: ; preds = %entry
br i1 undef, label %codeRepl4, label %codeRepl29 br i1 %c1, label %codeRepl4, label %codeRepl29
codeRepl4: ; preds = %codeRepl1 codeRepl4: ; preds = %codeRepl1
br i1 undef, label %codeRepl12, label %codeRepl17 br i1 %c2, label %codeRepl12, label %codeRepl17
codeRepl12: ; preds = %codeRepl4 codeRepl12: ; preds = %codeRepl4
unreachable unreachable
codeRepl17: ; preds = %codeRepl4 codeRepl17: ; preds = %codeRepl4
%0 = load i8, ptr undef, align 2 %0 = load i8, ptr undef, align 2
%1 = and i8 %0, 1 %1 = and i8 %0, 1
%not.tobool.i.i.i = icmp eq i8 %1, 0 %not.tobool.i.i.i = icmp eq i8 %1, 0
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llvm/test/CodeGen/PowerPC/rs-undef-use.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @autogen_SD156869(ptr, ptr) { define void @autogen_SD156869(ptr, ptr, i1 %c0, i1 %c1, i1 %c2) {
BB: BB:
%A3 = alloca <2 x i1> %A3 = alloca <2 x i1>
%A2 = alloca <8 x i32> %A2 = alloca <8 x i32>
br label %CF br label %CF
CF: ; preds = %CF85, %CF, %BB CF: ; preds = %CF85, %CF, %BB
br i1 undef, label %CF, label %CF82.critedge br i1 %c0, label %CF, label %CF82.critedge
CF82.critedge: ; preds = %CF CF82.critedge: ; preds = %CF
store i8 -59, ptr %0 store i8 -59, ptr %0
br label %CF82 br label %CF82
CF82: ; preds = %CF82, %CF82.critedge CF82: ; preds = %CF82, %CF82.critedge
%L17 = load i8, ptr %0 %L17 = load i8, ptr %0
%E18 = extractelement <2 x i64> undef, i32 0 %E18 = extractelement <2 x i64> undef, i32 0
br i1 undef, label %CF82, label %CF84.critedge br i1 %c1, label %CF82, label %CF84.critedge
CF84.critedge: ; preds = %CF82 CF84.critedge: ; preds = %CF82
store i64 455385, ptr %A3 store i64 455385, ptr %A3
br label %CF84 br label %CF84
CF84: ; preds = %CF84, %CF84.critedge CF84: ; preds = %CF84, %CF84.critedge
%L40 = load i64, ptr %A3 %L40 = load i64, ptr %A3
store i64 -1, ptr %A3 store i64 -1, ptr %A3
%Sl46 = select i1 undef, i1 undef, i1 false %Sl46 = select i1 undef, i1 undef, i1 false
br i1 %Sl46, label %CF84, label %CF85 br i1 %Sl46, label %CF84, label %CF85
CF85: ; preds = %CF84 CF85: ; preds = %CF84
%L47 = load i64, ptr %A3 %L47 = load i64, ptr %A3
store i64 %E18, ptr %A3 store i64 %E18, ptr %A3
store ppc_fp128 0xM4D436562A0416DE00000000000000000, ptr %A2 store ppc_fp128 0xM4D436562A0416DE00000000000000000, ptr %A2
%Cmp61 = icmp slt i64 %L47, %L40 %Cmp61 = icmp slt i64 %L47, %L40
br i1 %Cmp61, label %CF, label %CF77 br i1 %Cmp61, label %CF, label %CF77
CF77: ; preds = %CF77, %CF85 CF77: ; preds = %CF77, %CF85
br i1 undef, label %CF77, label %CF81 br i1 %c2, label %CF77, label %CF81
CF81: ; preds = %CF77 CF81: ; preds = %CF77
store i8 %L17, ptr %1 store i8 %L17, ptr %1
ret void ret void
} }

llvm/test/CodeGen/PowerPC/sdag-ppcf128.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mattr=-crbits < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mattr=-crbits < %s | FileCheck %s
; ;
; PR14751: Unsupported type in SelectionDAG::getConstantFP() ; PR14751: Unsupported type in SelectionDAG::getConstantFP()
define fastcc void @_D3std4math4sqrtFNaNbNfcZc() { define fastcc void @_D3std4math4sqrtFNaNbNfcZc(i1 %c0) {
entry: entry:
br i1 undef, label %if, label %else br i1 %c0, label %if, label %else
; CHECK: cmplwi 3, 0 ; CHECK: cmplwi 3, 0
if: ; preds = %entry if: ; preds = %entry
store { ppc_fp128, ppc_fp128 } zeroinitializer, ptr undef store { ppc_fp128, ppc_fp128 } zeroinitializer, ptr undef
ret void ret void
else: ; preds = %entry else: ; preds = %entry
unreachable unreachable
} }

llvm/test/CodeGen/PowerPC/set0-v8i16.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @autogen_SD367951() { define void @autogen_SD367951(i1 %c0) {
BB: BB:
%Shuff = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 26, i32 28, i32 30, i32 undef, i32 2, i32 4, i32 undef, i32 undef, i32 10, i32 undef, i32 14, i32 16, i32 undef, i32 20, i32 undef, i32 24> %Shuff = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 26, i32 28, i32 30, i32 undef, i32 2, i32 4, i32 undef, i32 undef, i32 10, i32 undef, i32 14, i32 16, i32 undef, i32 20, i32 undef, i32 24>
%Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> %Shuff, <16 x i32> <i32 20, i32 undef, i32 24, i32 26, i32 28, i32 undef, i32 0, i32 undef, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18> %Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> %Shuff, <16 x i32> <i32 20, i32 undef, i32 24, i32 26, i32 28, i32 undef, i32 0, i32 undef, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18>
%Cmp11 = icmp ugt <16 x i16> %Shuff7, zeroinitializer %Cmp11 = icmp ugt <16 x i16> %Shuff7, zeroinitializer
%E27 = extractelement <16 x i1> %Cmp11, i32 5 %E27 = extractelement <16 x i1> %Cmp11, i32 5
br label %CF76 br label %CF76
CF76: ; preds = %CF80, %CF76, %BB CF76: ; preds = %CF80, %CF76, %BB
br i1 undef, label %CF76, label %CF80 br i1 %c0, label %CF76, label %CF80
CF80: ; preds = %CF76 CF80: ; preds = %CF76
%Sl37 = select i1 %E27, <16 x i16> undef, <16 x i16> %Shuff %Sl37 = select i1 %E27, <16 x i16> undef, <16 x i16> %Shuff
br label %CF76 br label %CF76
} }

llvm/test/CodeGen/PowerPC/sink-side-effect.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le -mcpu=pwr9 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64le -mcpu=pwr9 -verify-machineinstrs < %s | FileCheck %s
define double @zot(ptr %arg, ptr %arg1, ptr %arg2) { define double @zot(ptr %arg, ptr %arg1, ptr %arg2, i1 %c0) {
; CHECK-LABEL: zot: ; CHECK-LABEL: zot:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: bc 12, 20, .LBB0_2 ; CHECK-NEXT: bc 12, 20, .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb3 ; CHECK-NEXT: # %bb.1: # %bb3
; CHECK-NEXT: lhz 5, 0(5) ; CHECK-NEXT: lhz 5, 0(5)
; CHECK-NEXT: rlwinm. 5, 5, 28, 30, 31 ; CHECK-NEXT: rlwinm. 5, 5, 28, 30, 31
; CHECK-NEXT: .LBB0_2: # %bb10 ; CHECK-NEXT: .LBB0_2: # %bb10
; CHECK-NEXT: lfs 0, 0(4) ; CHECK-NEXT: lfs 0, 0(4)
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; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: cmpw 4, 3 ; CHECK-NEXT: cmpw 4, 3
; CHECK-NEXT: bge 0, .LBB0_3 ; CHECK-NEXT: bge 0, .LBB0_3
; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: xsmuldp 1, 1, 0 ; CHECK-NEXT: xsmuldp 1, 1, 0
; CHECK-NEXT: b .LBB0_3 ; CHECK-NEXT: b .LBB0_3
bb: bb:
%tmp = load i32, ptr %arg, align 8 %tmp = load i32, ptr %arg, align 8
br i1 undef, label %bb9, label %bb3 br i1 %c0, label %bb9, label %bb3
bb3: bb3:
%tmp4 = load i16, ptr %arg2, align 4 %tmp4 = load i16, ptr %arg2, align 4
%tmp5 = lshr i16 %tmp4, 4 %tmp5 = lshr i16 %tmp4, 4
%tmp6 = and i16 %tmp5, 3 %tmp6 = and i16 %tmp5, 3
%tmp7 = zext i16 %tmp6 to i32 %tmp7 = zext i16 %tmp6 to i32
%tmp8 = icmp eq i16 %tmp6, 0 %tmp8 = icmp eq i16 %tmp6, 0
br i1 %tmp8, label %bb9, label %bb10 br i1 %tmp8, label %bb9, label %bb10
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llvm/test/CodeGen/PowerPC/sj-ctr-loop.ll

; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.__jmp_buf_tag.1.15.17.21.25.49.53.55 = type { [64 x i64], i32, %struct.__sigset_t.0.14.16.20.24.48.52.54, [8 x i8] } %struct.__jmp_buf_tag.1.15.17.21.25.49.53.55 = type { [64 x i64], i32, %struct.__sigset_t.0.14.16.20.24.48.52.54, [8 x i8] }
%struct.__sigset_t.0.14.16.20.24.48.52.54 = type { [16 x i64] } %struct.__sigset_t.0.14.16.20.24.48.52.54 = type { [16 x i64] }
@env_sigill = external global [1 x %struct.__jmp_buf_tag.1.15.17.21.25.49.53.55], align 16 @env_sigill = external global [1 x %struct.__jmp_buf_tag.1.15.17.21.25.49.53.55], align 16
; CHECK-LABEL: @main ; CHECK-LABEL: @main
; CHECK-NOT: mtctr ; CHECK-NOT: mtctr
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @main() #0 { define void @main(i1 %c0, i1 %c1) #0 {
entry: entry:
br i1 undef, label %return, label %if.end br i1 %c0, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
br i1 undef, label %for.body.lr.ph, label %for.end.thread br i1 %c1, label %for.body.lr.ph, label %for.end.thread
for.end.thread: ; preds = %if.end for.end.thread: ; preds = %if.end
br label %return br label %return
for.body.lr.ph: ; preds = %if.end for.body.lr.ph: ; preds = %if.end
br label %for.body br label %for.body
for.cond: ; preds = %for.body for.cond: ; preds = %for.body
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llvm/test/CodeGen/PowerPC/sms-iterator.ll

; REQUIRES: asserts ; REQUIRES: asserts
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
; RUN: -mcpu=pwr9 --ppc-enable-pipeliner -debug-only=pipeliner 2>&1 \ ; RUN: -mcpu=pwr9 --ppc-enable-pipeliner -debug-only=pipeliner 2>&1 \
; RUN: >/dev/null | FileCheck %s ; RUN: >/dev/null | FileCheck %s
%0 = type { i32, [16 x double] } %0 = type { i32, [16 x double] }
; CHECK: MII = 3 MAX_II = 13 (rec=3, res=2) ; CHECK: MII = 3 MAX_II = 13 (rec=3, res=2)
define dso_local fastcc double @_ZN3povL9polysolveEiPdS0_() unnamed_addr #0 { define dso_local fastcc double @_ZN3povL9polysolveEiPdS0_(i1 %c0, i1 %c1) unnamed_addr #0 {
br label %1 br label %1
1: ; preds = %1, %0 1: ; preds = %1, %0
br i1 undef, label %2, label %1 br i1 %c0, label %2, label %1
2: ; preds = %1 2: ; preds = %1
br i1 undef, label %14, label %3 br i1 %c1, label %14, label %3
3: ; preds = %3, %2 3: ; preds = %3, %2
%4 = phi i64 [ %7, %3 ], [ undef, %2 ] %4 = phi i64 [ %7, %3 ], [ undef, %2 ]
%5 = phi double [ %11, %3 ], [ undef, %2 ] %5 = phi double [ %11, %3 ], [ undef, %2 ]
%6 = phi i64 [ %12, %3 ], [ undef, %2 ] %6 = phi i64 [ %12, %3 ], [ undef, %2 ]
%7 = add nsw i64 %4, -1 %7 = add nsw i64 %4, -1
%8 = fmul fast double %5, 1.000000e+07 %8 = fmul fast double %5, 1.000000e+07
%9 = getelementptr inbounds %0, ptr null, i64 1, i32 1, i64 %7 %9 = getelementptr inbounds %0, ptr null, i64 1, i32 1, i64 %7
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llvm/test/CodeGen/PowerPC/spill-nor0.ll

; RUN: llc -verify-machineinstrs < %s -O0 -mcpu=ppc64 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -O0 -mcpu=ppc64 | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_ZN4llvm3sys17RunningOnValgrindEv() #0 { define void @_ZN4llvm3sys17RunningOnValgrindEv(i1 %c0, i1 %c1) #0 {
entry: entry:
br i1 undef, label %if.then, label %if.end br i1 %c0, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
ret void ret void
if.end: ; preds = %entry if.end: ; preds = %entry
%0 = call i64 asm sideeffect "mr 3,$1\0A\09mr 4,$2\0A\09rotldi 0,0,3 ; rotldi 0,0,13\0A\09rotldi 0,0,61 ; rotldi 0,0,51\0A\09or 1,1,1\0A\09mr $0,3", "=b,b,b,~{cc},~{memory},~{r3},~{r4}"(i32 0, ptr undef) #0 %0 = call i64 asm sideeffect "mr 3,$1\0A\09mr 4,$2\0A\09rotldi 0,0,3 ; rotldi 0,0,13\0A\09rotldi 0,0,61 ; rotldi 0,0,51\0A\09or 1,1,1\0A\09mr $0,3", "=b,b,b,~{cc},~{memory},~{r3},~{r4}"(i32 0, ptr undef) #0
br i1 undef, label %end0, label %end1 ; need successor blocks to force spill br i1 %c1, label %end0, label %end1 ; need successor blocks to force spill
end0: end0:
unreachable unreachable
end1: end1:
unreachable unreachable
; CHECK-LABEL: @_ZN4llvm3sys17RunningOnValgrindEv ; CHECK-LABEL: @_ZN4llvm3sys17RunningOnValgrindEv
; CHECK: stw ; CHECK: stw
; CHECK: lwz ; CHECK: lwz
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/spill_p9_setb.ll

; NOTE: This test case aims to test the sequence of spilling the CR[0-7]LT bits ; NOTE: This test case aims to test the sequence of spilling the CR[0-7]LT bits
; NOTE: on POWER9 using the setb instruction. ; NOTE: on POWER9 using the setb instruction.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s \ ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s \
; RUN: | FileCheck %s --check-prefix=CHECK-P9 ; RUN: | FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s \ ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s \
; RUN: | FileCheck %s --check-prefix=CHECK-P9 ; RUN: | FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s \ ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s \
; RUN: | FileCheck %s --check-prefix=CHECK-P8 ; RUN: | FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s \ ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s \
; RUN: | FileCheck %s --check-prefix=CHECK-P8 ; RUN: | FileCheck %s --check-prefix=CHECK-P8
define void @p9_setb_spill() { define void @p9_setb_spill(i1 %c0) {
; CHECK-P9-LABEL: p9_setb_spill: ; CHECK-P9-LABEL: p9_setb_spill:
; CHECK-P9: # %bb.1: # %if.then ; CHECK-P9: # %bb.1: # %if.then
; CHECK-P9-DAG: crnot 4*cr[[CREG:.*]]+lt, eq ; CHECK-P9-DAG: crnot 4*cr[[CREG:.*]]+lt, eq
; CHECK-P9-DAG: setb [[REG1:.*]], cr[[CREG]] ; CHECK-P9-DAG: setb [[REG1:.*]], cr[[CREG]]
; CHECK-P9-DAG: stw [[REG1]] ; CHECK-P9-DAG: stw [[REG1]]
; CHECK-P9: blr ; CHECK-P9: blr
; CHECK-P9: .LBB0_4: # %if.then1 ; CHECK-P9: .LBB0_4: # %if.then1
; ;
; CHECK-P8-LABEL: p9_setb_spill: ; CHECK-P8-LABEL: p9_setb_spill:
; CHECK-P8: # %bb.1: # %if.then ; CHECK-P8: # %bb.1: # %if.then
; CHECK-P8-DAG: crnot 4*cr[[CREG2:.*]]+lt, eq ; CHECK-P8-DAG: crnot 4*cr[[CREG2:.*]]+lt, eq
; CHECK-P8-DAG: mfocrf [[REG2:.*]], ; CHECK-P8-DAG: mfocrf [[REG2:.*]],
; CHECK-P8-DAG: rlwinm [[REG2]], [[REG2]] ; CHECK-P8-DAG: rlwinm [[REG2]], [[REG2]]
; CHECK-P8-DAG: stw [[REG2]] ; CHECK-P8-DAG: stw [[REG2]]
; CHECK-P8: blr ; CHECK-P8: blr
; CHECK-P8: .LBB0_4: # %if.then1 ; CHECK-P8: .LBB0_4: # %if.then1
entry: entry:
br i1 undef, label %if.end, label %if.then br i1 %c0, label %if.end, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%call = tail call signext i32 @fn_call() %call = tail call signext i32 @fn_call()
%cmp1 = icmp ne i32 %call, 0 %cmp1 = icmp ne i32 %call, 0
br label %if.end br label %if.end
if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
%off0 = phi i1 [ %cmp1, %if.then ], [ false, %entry ] %off0 = phi i1 [ %cmp1, %if.then ], [ false, %entry ]
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llvm/test/CodeGen/PowerPC/split-index-tc.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%"class.llvm::MachineOperand" = type { i8, [3 x i8], i64, ptr, i64 } %"class.llvm::MachineOperand" = type { i8, [3 x i8], i64, ptr, i64 }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj() #0 align 2 { define void @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8) #0 align 2 {
; If we were able to split out the indexing, the load with update should be ; If we were able to split out the indexing, the load with update should be
; removed (resulting in a nearly-empty output). ; removed (resulting in a nearly-empty output).
; CHECK-LABEL: @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj ; CHECK-LABEL: @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj
; CHECK-NOT: lhzu ; CHECK-NOT: lhzu
entry: entry:
%0 = load ptr, ptr undef, align 8 %0 = load ptr, ptr undef, align 8
br i1 undef, label %_ZNK4llvm14MachineOperand6getRegEv.exit, label %cond.false.i123 br i1 %c0, label %_ZNK4llvm14MachineOperand6getRegEv.exit, label %cond.false.i123
cond.false.i123: ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit cond.false.i123: ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit
unreachable unreachable
_ZNK4llvm14MachineOperand6getRegEv.exit: ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit _ZNK4llvm14MachineOperand6getRegEv.exit: ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit
%IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand", ptr %0, i64 undef, i32 1 %IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand", ptr %0, i64 undef, i32 1
%bf.load.i = load i24, ptr %IsDef.i, align 1 %bf.load.i = load i24, ptr %IsDef.i, align 1
%1 = and i24 %bf.load.i, 128 %1 = and i24 %bf.load.i, 128
br i1 undef, label %for.cond.cleanup, label %for.body.lr.ph br i1 %c1, label %for.cond.cleanup, label %for.body.lr.ph
for.body.lr.ph: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit for.body.lr.ph: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit
%2 = zext i24 %1 to i32 %2 = zext i24 %1 to i32
br i1 undef, label %cond.false.i134, label %_ZNK4llvm18MCRegAliasIteratordeEv.exit br i1 %c2, label %cond.false.i134, label %_ZNK4llvm18MCRegAliasIteratordeEv.exit
for.cond.cleanup: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit for.cond.cleanup: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit
br i1 undef, label %_ZNK4llvm14MachineOperand5isDefEv.exit, label %cond.false.i129 br i1 %c3, label %_ZNK4llvm14MachineOperand5isDefEv.exit, label %cond.false.i129
cond.false.i129: ; preds = %for.cond.cleanup cond.false.i129: ; preds = %for.cond.cleanup
unreachable unreachable
_ZNK4llvm14MachineOperand5isDefEv.exit: ; preds = %for.cond.cleanup _ZNK4llvm14MachineOperand5isDefEv.exit: ; preds = %for.cond.cleanup
br i1 undef, label %_ZNK4llvm14MachineOperand6getRegEv.exit247, label %cond.false.i244 br i1 %c4, label %_ZNK4llvm14MachineOperand6getRegEv.exit247, label %cond.false.i244
cond.false.i134: ; preds = %for.body.lr.ph cond.false.i134: ; preds = %for.body.lr.ph
unreachable unreachable
_ZNK4llvm18MCRegAliasIteratordeEv.exit: ; preds = %for.body.lr.ph _ZNK4llvm18MCRegAliasIteratordeEv.exit: ; preds = %for.body.lr.ph
unreachable unreachable
cond.false.i244: ; preds = %_ZNK4llvm14MachineOperand5isDefEv.exit cond.false.i244: ; preds = %_ZNK4llvm14MachineOperand5isDefEv.exit
unreachable unreachable
_ZNK4llvm14MachineOperand6getRegEv.exit247: ; preds = %_ZNK4llvm14MachineOperand5isDefEv.exit _ZNK4llvm14MachineOperand6getRegEv.exit247: ; preds = %_ZNK4llvm14MachineOperand5isDefEv.exit
br i1 undef, label %if.then53, label %if.end55 br i1 %c5, label %if.then53, label %if.end55
if.then53: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit247 if.then53: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit247
unreachable unreachable
if.end55: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit247 if.end55: ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit247
br i1 undef, label %_ZNK4llvm14MachineOperand6isDeadEv.exit262, label %cond.false.i257 br i1 %c6, label %_ZNK4llvm14MachineOperand6isDeadEv.exit262, label %cond.false.i257
cond.false.i257: ; preds = %if.end55 cond.false.i257: ; preds = %if.end55
unreachable unreachable
_ZNK4llvm14MachineOperand6isDeadEv.exit262: ; preds = %if.end55 _ZNK4llvm14MachineOperand6isDeadEv.exit262: ; preds = %if.end55
%bf.load.i259 = load i24, ptr %IsDef.i, align 1 %bf.load.i259 = load i24, ptr %IsDef.i, align 1
br i1 undef, label %if.then57, label %if.else59 br i1 %c7, label %if.then57, label %if.else59
if.then57: ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262 if.then57: ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262
unreachable unreachable
if.else59: ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262 if.else59: ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262
br i1 undef, label %if.end89, label %if.then62 br i1 %c8, label %if.end89, label %if.then62
if.then62: ; preds = %if.else59 if.then62: ; preds = %if.else59
unreachable unreachable
if.end89: ; preds = %if.else59 if.end89: ; preds = %if.else59
unreachable unreachable
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/std-unal-fi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @autogen_SD4932(i8) { define void @autogen_SD4932(i8, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6) {
BB: BB:
%A4 = alloca i8 %A4 = alloca i8
%A = alloca <1 x ppc_fp128> %A = alloca <1 x ppc_fp128>
%Shuff = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 undef, i32 29, i32 31, i32 1, i32 3, i32 5> %Shuff = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 undef, i32 29, i32 31, i32 1, i32 3, i32 5>
br label %CF br label %CF
CF: ; preds = %CF80, %CF, %BB CF: ; preds = %CF80, %CF, %BB
%L5 = load i64, ptr undef %L5 = load i64, ptr undef
store i8 %0, ptr %A4 store i8 %0, ptr %A4
%Shuff7 = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> %Shuff, <16 x i32> <i32 28, i32 30, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 undef, i32 20, i32 22, i32 24, i32 26> %Shuff7 = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> %Shuff, <16 x i32> <i32 28, i32 30, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 undef, i32 20, i32 22, i32 24, i32 26>
br i1 undef, label %CF, label %CF77 br i1 %c0, label %CF, label %CF77
CF77: ; preds = %CF81, %CF83, %CF77, %CF CF77: ; preds = %CF81, %CF83, %CF77, %CF
br i1 undef, label %CF77, label %CF82 br i1 %c1, label %CF77, label %CF82
CF82: ; preds = %CF82, %CF77 CF82: ; preds = %CF82, %CF77
%L19 = load i64, ptr undef %L19 = load i64, ptr undef
store <1 x ppc_fp128> zeroinitializer, ptr %A store <1 x ppc_fp128> zeroinitializer, ptr %A
store i8 -65, ptr %A4 store i8 -65, ptr %A4
br i1 undef, label %CF82, label %CF83 br i1 %c2, label %CF82, label %CF83
CF83: ; preds = %CF82 CF83: ; preds = %CF82
%L34 = load i64, ptr undef %L34 = load i64, ptr undef
br i1 undef, label %CF77, label %CF81 br i1 %c3, label %CF77, label %CF81
CF81: ; preds = %CF83 CF81: ; preds = %CF83
%Shuff43 = shufflevector <16 x i32> %Shuff7, <16 x i32> undef, <16 x i32> <i32 15, i32 17, i32 19, i32 21, i32 23, i32 undef, i32 undef, i32 29, i32 31, i32 undef, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13> %Shuff43 = shufflevector <16 x i32> %Shuff7, <16 x i32> undef, <16 x i32> <i32 15, i32 17, i32 19, i32 21, i32 23, i32 undef, i32 undef, i32 29, i32 31, i32 undef, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13>
store ppc_fp128 0xM00000000000000000000000000000000, ptr %A4 store ppc_fp128 0xM00000000000000000000000000000000, ptr %A4
br i1 undef, label %CF77, label %CF78 br i1 %c4, label %CF77, label %CF78
CF78: ; preds = %CF78, %CF81 CF78: ; preds = %CF78, %CF81
br i1 undef, label %CF78, label %CF79 br i1 %c5, label %CF78, label %CF79
CF79: ; preds = %CF79, %CF78 CF79: ; preds = %CF79, %CF78
br i1 undef, label %CF79, label %CF80 br i1 %c6, label %CF79, label %CF80
CF80: ; preds = %CF79 CF80: ; preds = %CF79
store i64 %L19, ptr undef store i64 %L19, ptr undef
%Cmp75 = icmp uge i32 206779, undef %Cmp75 = icmp uge i32 206779, undef
br i1 %Cmp75, label %CF, label %CF76 br i1 %Cmp75, label %CF, label %CF76
CF76: ; preds = %CF80 CF76: ; preds = %CF80
store i64 %L5, ptr undef store i64 %L5, ptr undef
store i64 %L34, ptr undef store i64 %L34, ptr undef
ret void ret void
} }
define void @autogen_SD88042(ptr, ptr, i8) { define void @autogen_SD88042(ptr, ptr, i8, i1 %c0, i1 %c1) {
BB: BB:
%A4 = alloca <2 x i1> %A4 = alloca <2 x i1>
%A = alloca <16 x float> %A = alloca <16 x float>
%L = load i8, ptr %0 %L = load i8, ptr %0
%Sl = select i1 false, ptr %A, ptr %A %Sl = select i1 false, ptr %A, ptr %A
%Sl27 = select i1 false, i8 undef, i8 %L %Sl27 = select i1 false, i8 undef, i8 %L
br label %CF br label %CF
CF: ; preds = %CF78, %CF, %BB CF: ; preds = %CF78, %CF, %BB
br i1 undef, label %CF, label %CF77 br i1 %c0, label %CF, label %CF77
CF77: ; preds = %CF80, %CF77, %CF CF77: ; preds = %CF80, %CF77, %CF
store <16 x float> zeroinitializer, ptr %Sl store <16 x float> zeroinitializer, ptr %Sl
%L58 = load i32, ptr %1 %L58 = load i32, ptr %1
store i8 0, ptr %0 store i8 0, ptr %0
br i1 undef, label %CF77, label %CF80 br i1 %c1, label %CF77, label %CF80
CF80: ; preds = %CF77 CF80: ; preds = %CF77
store i64 0, ptr %A4 store i64 0, ptr %A4
%E67 = extractelement <8 x i1> zeroinitializer, i32 1 %E67 = extractelement <8 x i1> zeroinitializer, i32 1
br i1 %E67, label %CF77, label %CF78 br i1 %E67, label %CF77, label %CF78
CF78: ; preds = %CF80 CF78: ; preds = %CF80
%Cmp73 = icmp eq i32 189865, %L58 %Cmp73 = icmp eq i32 189865, %L58
br i1 %Cmp73, label %CF, label %CF76 br i1 %Cmp73, label %CF, label %CF76
CF76: ; preds = %CF78 CF76: ; preds = %CF78
store i8 %2, ptr %0 store i8 %2, ptr %0
store i8 %Sl27, ptr %0 store i8 %Sl27, ptr %0
ret void ret void
} }
define void @autogen_SD37497(ptr, ptr, ptr) { define void @autogen_SD37497(ptr, ptr, ptr, i1 %c0) {
BB: BB:
%A1 = alloca i1 %A1 = alloca i1
%I8 = insertelement <1 x i32> <i32 -1>, i32 454855, i32 0 %I8 = insertelement <1 x i32> <i32 -1>, i32 454855, i32 0
%Cmp = icmp ult <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, undef %Cmp = icmp ult <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, undef
%L10 = load i64, ptr %2 %L10 = load i64, ptr %2
%E11 = extractelement <4 x i1> %Cmp, i32 2 %E11 = extractelement <4 x i1> %Cmp, i32 2
br label %CF72 br label %CF72
CF72: ; preds = %CF74, %CF72, %BB CF72: ; preds = %CF74, %CF72, %BB
store double 0xB47BB29A53790718, ptr undef store double 0xB47BB29A53790718, ptr undef
%E18 = extractelement <1 x i32> <i32 -1>, i32 0 %E18 = extractelement <1 x i32> <i32 -1>, i32 0
%FC22 = sitofp <1 x i32> %I8 to <1 x float> %FC22 = sitofp <1 x i32> %I8 to <1 x float>
br i1 undef, label %CF72, label %CF74 br i1 %c0, label %CF72, label %CF74
CF74: ; preds = %CF72 CF74: ; preds = %CF72
store i8 0, ptr %0 store i8 0, ptr %0
%L31 = load i64, ptr %A1 %L31 = load i64, ptr %A1
store i64 477323, ptr %A1 store i64 477323, ptr %A1
%Sl37 = select i1 false, ptr undef, ptr %1 %Sl37 = select i1 false, ptr undef, ptr %1
%Cmp38 = icmp ugt i1 undef, undef %Cmp38 = icmp ugt i1 undef, undef
br i1 %Cmp38, label %CF72, label %CF73 br i1 %Cmp38, label %CF72, label %CF73
Show All 9 Lines

llvm/test/CodeGen/PowerPC/stwu-sched.ll

; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-ctrloops < %s -verify-machineinstrs \ ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-ctrloops < %s -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefix=CHECK-ITIN ; RUN: | FileCheck %s --check-prefix=CHECK-ITIN
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-ctrloops < %s -verify-machineinstrs \ ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-ctrloops < %s -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefix=CHECK-ITIN ; RUN: | FileCheck %s --check-prefix=CHECK-ITIN
%0 = type { i32, i32 } %0 = type { i32, i32 }
; Function Attrs: norecurse nounwind writeonly ; Function Attrs: norecurse nounwind writeonly
define void @initCombList(ptr nocapture, i32 signext) local_unnamed_addr #0 { define void @initCombList(ptr nocapture, i32 signext, i1 %c0, i1 %c1) local_unnamed_addr #0 {
; CHECK-LABEL: initCombList: ; CHECK-LABEL: initCombList:
; CHECK: addi 4, 4, -8 ; CHECK: addi 4, 4, -8
; CHECK: stwu [[REG:[0-9]+]], 64(3) ; CHECK: stwu [[REG:[0-9]+]], 64(3)
; CHECK-ITIN-LABEL: initCombList: ; CHECK-ITIN-LABEL: initCombList:
; CHECK-ITIN: stwu [[REG:[0-9]+]], 64(3) ; CHECK-ITIN: stwu [[REG:[0-9]+]], 64(3)
; CHECK-ITIN-NEXT: addi [[REG2:[0-9]+]], [[REG2]], 8 ; CHECK-ITIN-NEXT: addi [[REG2:[0-9]+]], [[REG2]], 8
%3 = zext i32 %1 to i64 %3 = zext i32 %1 to i64
br i1 undef, label %6, label %4 br i1 %c0, label %6, label %4
; <label>:4: ; preds = %2 ; <label>:4: ; preds = %2
store i32 0, ptr undef, align 4, !tbaa !1 store i32 0, ptr undef, align 4, !tbaa !1
%5 = add nuw nsw i64 0, 1 %5 = add nuw nsw i64 0, 1
br label %6 br label %6
; <label>:6: ; preds = %4, %2 ; <label>:6: ; preds = %4, %2
%7 = phi i64 [ 0, %2 ], [ %5, %4 ] %7 = phi i64 [ 0, %2 ], [ %5, %4 ]
br i1 undef, label %23, label %8 br i1 %c1, label %23, label %8
; <label>:8: ; preds = %8, %6 ; <label>:8: ; preds = %8, %6
%9 = phi i64 [ %21, %8 ], [ %7, %6 ] %9 = phi i64 [ %21, %8 ], [ %7, %6 ]
%10 = getelementptr inbounds %0, ptr %0, i64 %9, i32 1 %10 = getelementptr inbounds %0, ptr %0, i64 %9, i32 1
store i32 0, ptr %10, align 4, !tbaa !1 store i32 0, ptr %10, align 4, !tbaa !1
%11 = add nuw nsw i64 %9, 1 %11 = add nuw nsw i64 %9, 1
%12 = getelementptr inbounds %0, ptr %0, i64 %11, i32 1 %12 = getelementptr inbounds %0, ptr %0, i64 %11, i32 1
store i32 0, ptr %12, align 4, !tbaa !1 store i32 0, ptr %12, align 4, !tbaa !1
Show All 32 Lines

llvm/test/CodeGen/PowerPC/stwux.ll

target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
@multvec_i = external unnamed_addr global [100 x i32], align 4 @multvec_i = external unnamed_addr global [100 x i32], align 4
define fastcc void @subs_STMultiExceptIntern(i32 %input) nounwind { define fastcc void @subs_STMultiExceptIntern(i32 %input, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind {
entry: entry:
br i1 undef, label %while.body.lr.ph, label %return br i1 %c0, label %while.body.lr.ph, label %return
while.body.lr.ph: ; preds = %entry while.body.lr.ph: ; preds = %entry
br label %while.body br label %while.body
while.body: ; preds = %if.end12, %while.body.lr.ph while.body: ; preds = %if.end12, %while.body.lr.ph
%i.0240 = phi i32 [ -1, %while.body.lr.ph ], [ %i.1, %if.end12 ] %i.0240 = phi i32 [ -1, %while.body.lr.ph ], [ %i.1, %if.end12 ]
br i1 undef, label %if.end12, label %if.then br i1 %c1, label %if.end12, label %if.then
if.then: ; preds = %while.body if.then: ; preds = %while.body
%0 = add i32 %input, 1 %0 = add i32 %input, 1
br label %if.end12 br label %if.end12
if.end12: ; preds = %if.then, %while.body if.end12: ; preds = %if.then, %while.body
%i.1 = phi i32 [ %i.0240, %while.body ], [ %0, %if.then ] %i.1 = phi i32 [ %i.0240, %while.body ], [ %0, %if.then ]
br i1 undef, label %while.body, label %while.end br i1 %c2, label %while.body, label %while.end
while.end: ; preds = %if.end12 while.end: ; preds = %if.end12
br i1 undef, label %return, label %if.end15 br i1 %c3, label %return, label %if.end15
if.end15: ; preds = %while.end if.end15: ; preds = %while.end
%idxprom.i.i230 = sext i32 %i.1 to i64 %idxprom.i.i230 = sext i32 %i.1 to i64
%arrayidx18 = getelementptr inbounds [100 x i32], ptr @multvec_i, i64 0, i64 %idxprom.i.i230 %arrayidx18 = getelementptr inbounds [100 x i32], ptr @multvec_i, i64 0, i64 %idxprom.i.i230
store i32 0, ptr %arrayidx18, align 4 store i32 0, ptr %arrayidx18, align 4
br i1 undef, label %while.body21, label %while.end90 br i1 %c4, label %while.body21, label %while.end90
while.body21: ; preds = %if.end15 while.body21: ; preds = %if.end15
unreachable unreachable
while.end90: ; preds = %if.end15 while.end90: ; preds = %if.end15
store i32 0, ptr %arrayidx18, align 4 store i32 0, ptr %arrayidx18, align 4
br label %return br label %return
return: ; preds = %while.end90, %while.end, %entry return: ; preds = %while.end90, %while.end, %entry
ret void ret void
; CHECK: @subs_STMultiExceptIntern ; CHECK: @subs_STMultiExceptIntern
; CHECK: stwux ; CHECK: stwux
} }

llvm/test/CodeGen/PowerPC/sub-bv-types.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @autogen_SD10521() { define void @autogen_SD10521(i1 %c0) {
BB: BB:
%Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 undef, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 undef, i32 22, i32 undef, i32 26, i32 undef, i32 30> %Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 undef, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 undef, i32 22, i32 undef, i32 26, i32 undef, i32 30>
br label %CF br label %CF
CF: ; preds = %CF78, %CF, %BB CF: ; preds = %CF78, %CF, %BB
%I27 = insertelement <16 x i16> %Shuff7, i16 1360, i32 8 %I27 = insertelement <16 x i16> %Shuff7, i16 1360, i32 8
%B28 = sub <16 x i16> %I27, %Shuff7 %B28 = sub <16 x i16> %I27, %Shuff7
br i1 undef, label %CF, label %CF78 br i1 %c0, label %CF, label %CF78
CF78: ; preds = %CF CF78: ; preds = %CF
%B42 = xor <16 x i16> %B28, %Shuff7 %B42 = xor <16 x i16> %B28, %Shuff7
br label %CF br label %CF
} }

llvm/test/CodeGen/PowerPC/subreg-postra.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @jbd2_journal_commit_transaction(ptr %journal, i64 %inp1, i32 %inp2, define void @jbd2_journal_commit_transaction(ptr %journal, i64 %inp1, i32 %inp2,
ptr %inp3, ptr %inp4, ptr %inp3, ptr %inp4,
ptr %inp5, i1 %inp6, ptr %inp5, i1 %inp6,
i1 %inp7, i1 %inp8) #0 { i1 %inp7, i1 %inp8) #0 {
entry: entry:
br i1 undef, label %do.body, label %if.then5 br i1 %c0, label %do.body, label %if.then5
if.then5: ; preds = %entry if.then5: ; preds = %entry
unreachable unreachable
do.body: ; preds = %entry do.body: ; preds = %entry
br i1 undef, label %do.body.i, label %trace_jbd2_start_commit.exit br i1 %c1, label %do.body.i, label %trace_jbd2_start_commit.exit
do.body.i: ; preds = %do.body do.body.i: ; preds = %do.body
unreachable unreachable
trace_jbd2_start_commit.exit: ; preds = %do.body trace_jbd2_start_commit.exit: ; preds = %do.body
br i1 undef, label %do.body.i1116, label %trace_jbd2_commit_locking.exit br i1 %c2, label %do.body.i1116, label %trace_jbd2_commit_locking.exit
do.body.i1116: ; preds = %trace_jbd2_start_commit.exit do.body.i1116: ; preds = %trace_jbd2_start_commit.exit
br i1 undef, label %if.end.i1123, label %do.body5.i1122 br i1 %c3, label %if.end.i1123, label %do.body5.i1122
do.body5.i1122: ; preds = %do.body.i1116 do.body5.i1122: ; preds = %do.body.i1116
unreachable unreachable
if.end.i1123: ; preds = %do.body.i1116 if.end.i1123: ; preds = %do.body.i1116
br label %trace_jbd2_commit_locking.exit br label %trace_jbd2_commit_locking.exit
trace_jbd2_commit_locking.exit: ; preds = %if.end.i1123, %trace_jbd2_start_commit.exit trace_jbd2_commit_locking.exit: ; preds = %if.end.i1123, %trace_jbd2_start_commit.exit
br i1 undef, label %spin_unlock.exit1146, label %if.then.i.i.i.i1144 br i1 %c4, label %spin_unlock.exit1146, label %if.then.i.i.i.i1144
if.then.i.i.i.i1144: ; preds = %trace_jbd2_commit_locking.exit if.then.i.i.i.i1144: ; preds = %trace_jbd2_commit_locking.exit
unreachable unreachable
spin_unlock.exit1146: ; preds = %trace_jbd2_commit_locking.exit spin_unlock.exit1146: ; preds = %trace_jbd2_commit_locking.exit
br i1 undef, label %spin_unlock.exit1154, label %if.then.i.i.i.i1152 br i1 %c5, label %spin_unlock.exit1154, label %if.then.i.i.i.i1152
if.then.i.i.i.i1152: ; preds = %spin_unlock.exit1146 if.then.i.i.i.i1152: ; preds = %spin_unlock.exit1146
br label %spin_unlock.exit1154 br label %spin_unlock.exit1154
spin_unlock.exit1154: ; preds = %if.then.i.i.i.i1152, %spin_unlock.exit1146 spin_unlock.exit1154: ; preds = %if.then.i.i.i.i1152, %spin_unlock.exit1146
br i1 undef, label %do.body.i1159, label %trace_jbd2_commit_flushing.exit br i1 %c6, label %do.body.i1159, label %trace_jbd2_commit_flushing.exit
do.body.i1159: ; preds = %spin_unlock.exit1154 do.body.i1159: ; preds = %spin_unlock.exit1154
unreachable unreachable
trace_jbd2_commit_flushing.exit: ; preds = %spin_unlock.exit1154 trace_jbd2_commit_flushing.exit: ; preds = %spin_unlock.exit1154
br i1 undef, label %for.end.i, label %for.body.lr.ph.i br i1 %c7, label %for.end.i, label %for.body.lr.ph.i
for.body.lr.ph.i: ; preds = %trace_jbd2_commit_flushing.exit for.body.lr.ph.i: ; preds = %trace_jbd2_commit_flushing.exit
br i1 undef, label %spin_unlock.exit.i, label %if.then.i.i.i.i.i br i1 %c8, label %spin_unlock.exit.i, label %if.then.i.i.i.i.i
if.then.i.i.i.i.i: ; preds = %for.body.lr.ph.i if.then.i.i.i.i.i: ; preds = %for.body.lr.ph.i
unreachable unreachable
spin_unlock.exit.i: ; preds = %for.body.lr.ph.i spin_unlock.exit.i: ; preds = %for.body.lr.ph.i
unreachable unreachable
for.end.i: ; preds = %trace_jbd2_commit_flushing.exit for.end.i: ; preds = %trace_jbd2_commit_flushing.exit
br i1 undef, label %journal_submit_data_buffers.exit, label %if.then.i.i.i.i31.i br i1 %c9, label %journal_submit_data_buffers.exit, label %if.then.i.i.i.i31.i
if.then.i.i.i.i31.i: ; preds = %for.end.i if.then.i.i.i.i31.i: ; preds = %for.end.i
unreachable unreachable
journal_submit_data_buffers.exit: ; preds = %for.end.i journal_submit_data_buffers.exit: ; preds = %for.end.i
br i1 undef, label %if.end103, label %if.then102 br i1 %c10, label %if.end103, label %if.then102
if.then102: ; preds = %journal_submit_data_buffers.exit if.then102: ; preds = %journal_submit_data_buffers.exit
unreachable unreachable
if.end103: ; preds = %journal_submit_data_buffers.exit if.end103: ; preds = %journal_submit_data_buffers.exit
br i1 undef, label %do.body.i1182, label %trace_jbd2_commit_logging.exit br i1 %c11, label %do.body.i1182, label %trace_jbd2_commit_logging.exit
do.body.i1182: ; preds = %if.end103 do.body.i1182: ; preds = %if.end103
unreachable unreachable
trace_jbd2_commit_logging.exit: ; preds = %if.end103 trace_jbd2_commit_logging.exit: ; preds = %if.end103
br i1 undef, label %for.end.i1287, label %for.body.i1277 br i1 %c12, label %for.end.i1287, label %for.body.i1277
for.body.i1277: ; preds = %trace_jbd2_commit_logging.exit for.body.i1277: ; preds = %trace_jbd2_commit_logging.exit
unreachable unreachable
for.end.i1287: ; preds = %trace_jbd2_commit_logging.exit for.end.i1287: ; preds = %trace_jbd2_commit_logging.exit
br i1 undef, label %journal_finish_inode_data_buffers.exit, label %if.then.i.i.i.i84.i br i1 %c13, label %journal_finish_inode_data_buffers.exit, label %if.then.i.i.i.i84.i
if.then.i.i.i.i84.i: ; preds = %for.end.i1287 if.then.i.i.i.i84.i: ; preds = %for.end.i1287
unreachable unreachable
journal_finish_inode_data_buffers.exit: ; preds = %for.end.i1287 journal_finish_inode_data_buffers.exit: ; preds = %for.end.i1287
br i1 undef, label %if.end256, label %if.then249 br i1 %c14, label %if.end256, label %if.then249
if.then249: ; preds = %journal_finish_inode_data_buffers.exit if.then249: ; preds = %journal_finish_inode_data_buffers.exit
unreachable unreachable
if.end256: ; preds = %journal_finish_inode_data_buffers.exit if.end256: ; preds = %journal_finish_inode_data_buffers.exit
br i1 undef, label %do.body277, label %if.then260 br i1 %c15, label %do.body277, label %if.then260
if.then260: ; preds = %if.end256 if.then260: ; preds = %if.end256
br label %do.body277 br label %do.body277
do.body277: ; preds = %if.then260, %if.end256 do.body277: ; preds = %if.then260, %if.end256
br label %while.body318 br label %while.body318
while.body318: ; preds = %wait_on_buffer.exit, %do.body277 while.body318: ; preds = %wait_on_buffer.exit, %do.body277
▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/test-and-cmp-folding.ll

; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 \ ; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
declare void @free() declare void @free()
define dso_local fastcc void @test2() { define dso_local fastcc void @test2(i1 %c0, i1 %c1) {
; CHECK-LABEL: test2 ; CHECK-LABEL: test2
entry: entry:
switch i16 undef, label %sw.default [ switch i16 undef, label %sw.default [
i16 10, label %sw.bb52 i16 10, label %sw.bb52
i16 134, label %sw.bb54 i16 134, label %sw.bb54
] ]
sw.default: ; preds = %entry sw.default: ; preds = %entry
unreachable unreachable
sw.bb52: ; preds = %entry, %entry, %entry, %entry, %entry, %entry sw.bb52: ; preds = %entry, %entry, %entry, %entry, %entry, %entry
br i1 undef, label %if.then14.i, label %sw.epilog.i642 br i1 %c0, label %if.then14.i, label %sw.epilog.i642
if.then14.i: ; preds = %sw.bb52 if.then14.i: ; preds = %sw.bb52
%call39.i = call i64 @test() #3 %call39.i = call i64 @test() #3
%and.i126.i = and i64 %call39.i, 1 %and.i126.i = and i64 %call39.i, 1
br i1 undef, label %dummy.exit.i, label %if.then.i.i.i636 br i1 %c1, label %dummy.exit.i, label %if.then.i.i.i636
if.then.i.i.i636: ; preds = %if.then14.i if.then.i.i.i636: ; preds = %if.then14.i
%0 = load ptr, ptr undef, align 8 %0 = load ptr, ptr undef, align 8
call void @free() #3 call void @free() #3
br label %dummy.exit.i br label %dummy.exit.i
dummy.exit.i: ; preds = %if.then.i.i.i636, %if.then14.i dummy.exit.i: ; preds = %if.then.i.i.i636, %if.then14.i
; CHECK: # %dummy.exit.i ; CHECK: # %dummy.exit.i
Show All 22 Lines

llvm/test/CodeGen/PowerPC/vsel-prom.ll

; RUN: llc -mcpu=pwr7 < %s -verify-machineinstrs | FileCheck %s ; RUN: llc -mcpu=pwr7 < %s -verify-machineinstrs | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @Compute_Lateral() #0 { define void @Compute_Lateral(i1 %c0) #0 {
entry: entry:
br i1 undef, label %if.then, label %if.end br i1 %c0, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
unreachable unreachable
if.end: ; preds = %entry if.end: ; preds = %entry
%0 = select i1 undef, <2 x double> undef, <2 x double> zeroinitializer %0 = select i1 undef, <2 x double> undef, <2 x double> zeroinitializer
%1 = extractelement <2 x double> %0, i32 1 %1 = extractelement <2 x double> %0, i32 1
store double %1, ptr undef, align 8 store double %1, ptr undef, align 8
ret void ret void
; CHECK-LABEL: @Compute_Lateral ; CHECK-LABEL: @Compute_Lateral
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/vsx-fma-mutate-trivial-copy.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @LSH_recall_init(float %d_min, float %W) #0 { define void @LSH_recall_init(float %d_min, float %W, i1 %c0) #0 {
entry: entry:
br i1 undef, label %for.body.lr.ph, label %for.end br i1 %c0, label %for.body.lr.ph, label %for.end
; CHECK-LABEL: @LSH_recall_init ; CHECK-LABEL: @LSH_recall_init
; CHECK: xsmaddadp ; CHECK: xsmaddadp
for.body.lr.ph: ; preds = %entry for.body.lr.ph: ; preds = %entry
%conv3 = fpext float %W to double %conv3 = fpext float %W to double
br label %for.body br label %for.body
Show All 22 Lines

llvm/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll

; RUN: llc < %s -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @acosh_float8(<4 x i32> %v1, <4 x i32> %v2, <4 x float> %x) #0 { define void @acosh_float8(<4 x i32> %v1, <4 x i32> %v2, <4 x float> %x, i1 %c0) #0 {
entry: entry:
br i1 undef, label %if.then, label %if.end br i1 %c0, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
%0 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %x, <4 x float> <float 0x3FE62E4200000000, float 0x3FE62E4200000000, float 0x3FE62E4200000000, float 0x3FE62E4200000000>, <4 x float> %x) #0 %0 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %x, <4 x float> <float 0x3FE62E4200000000, float 0x3FE62E4200000000, float 0x3FE62E4200000000, float 0x3FE62E4200000000>, <4 x float> %x) #0
%astype.i.i.74.i = bitcast <4 x float> %0 to <4 x i32> %astype.i.i.74.i = bitcast <4 x float> %0 to <4 x i32>
%and.i.i.76.i = and <4 x i32> %astype.i.i.74.i, %v1 %and.i.i.76.i = and <4 x i32> %astype.i.i.74.i, %v1
%or.i.i.79.i = or <4 x i32> %and.i.i.76.i, %v2 %or.i.i.79.i = or <4 x i32> %and.i.i.76.i, %v2
%astype5.i.i.80.i = bitcast <4 x i32> %or.i.i.79.i to <4 x float> %astype5.i.i.80.i = bitcast <4 x i32> %or.i.i.79.i to <4 x float>
%1 = shufflevector <4 x float> %astype5.i.i.80.i, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %1 = shufflevector <4 x float> %astype5.i.i.80.i, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
Show All 17 Lines

llvm/test/CodeGen/PowerPC/vsx-infl-copy2.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc(i32* nocapture readonly %first) #0 { define void @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc(i32* nocapture readonly %first, i1 %c0, i1 %c1) #0 {
entry: entry:
br i1 false, label %loop2_start, label %if.end5 br i1 false, label %loop2_start, label %if.end5
; CHECK-LABEL: @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc ; CHECK-LABEL: @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc
loop2_start: ; preds = %loop2_start, %entry loop2_start: ; preds = %loop2_start, %entry
br i1 undef, label %loop2_start, label %if.then.i31 br i1 %c0, label %loop2_start, label %if.then.i31
if.end5: ; preds = %entry if.end5: ; preds = %entry
br i1 undef, label %loop_start.preheader, label %if.then.i31 br i1 %c1, label %loop_start.preheader, label %if.then.i31
loop_start.preheader: ; preds = %if.end5 loop_start.preheader: ; preds = %if.end5
br i1 false, label %middle.block, label %vector.body br i1 false, label %middle.block, label %vector.body
vector.body: ; preds = %vector.body, %loop_start.preheader vector.body: ; preds = %vector.body, %loop_start.preheader
%vec.phi61 = phi <4 x i32> [ %34, %vector.body ], [ zeroinitializer, %loop_start.preheader ] %vec.phi61 = phi <4 x i32> [ %34, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
%vec.phi62 = phi <4 x i32> [ %35, %vector.body ], [ zeroinitializer, %loop_start.preheader ] %vec.phi62 = phi <4 x i32> [ %35, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
%vec.phi63 = phi <4 x i32> [ %36, %vector.body ], [ zeroinitializer, %loop_start.preheader ] %vec.phi63 = phi <4 x i32> [ %36, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
▲ Show 20 Lines • Show All 90 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vsx-self-copy.ll

; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s -verify-machineinstrs | FileCheck %s ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s -verify-machineinstrs | FileCheck %s ; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s -verify-machineinstrs | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define double @takFP(double %x, double %y, double %z) #0 { define double @takFP(double %x, double %y, double %z, i1 %c0) #0 {
entry: entry:
br i1 undef, label %if.then, label %return br i1 %c0, label %if.then, label %return
if.then: ; preds = %if.then, %entry if.then: ; preds = %if.then, %entry
%x.tr16 = phi double [ %call, %if.then ], [ %x, %entry ] %x.tr16 = phi double [ %call, %if.then ], [ %x, %entry ]
%call = tail call double @takFP(double undef, double undef, double undef) %call = tail call double @takFP(double undef, double undef, double undef)
%call4 = tail call double @takFP(double undef, double %x.tr16, double undef) %call4 = tail call double @takFP(double undef, double %x.tr16, double undef)
%cmp = fcmp olt double undef, %call %cmp = fcmp olt double undef, %call
br i1 %cmp, label %if.then, label %return br i1 %cmp, label %if.then, label %return
Show All 12 Lines

llvm/test/CodeGen/PowerPC/vsx-spill-norwstore.ll

; RUN: llc -mcpu=pwr7 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mcpu=pwr7 -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@.str1 = external unnamed_addr constant [5 x i8], align 1 @.str1 = external unnamed_addr constant [5 x i8], align 1
@.str10 = external unnamed_addr constant [9 x i8], align 1 @.str10 = external unnamed_addr constant [9 x i8], align 1
@.v2f64 = external unnamed_addr constant <2 x double>, align 16 @.v2f64 = external unnamed_addr constant <2 x double>, align 16
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @main() #0 { define void @main(i1 %c0) #0 {
; CHECK-LABEL: @main ; CHECK-LABEL: @main
; Make sure that the stxvd2x passes -verify-machineinstrs ; Make sure that the stxvd2x passes -verify-machineinstrs
; CHECK: stxvd2x ; CHECK: stxvd2x
entry: entry:
%val = load <2 x double>, ptr @.v2f64, align 16 %val = load <2 x double>, ptr @.v2f64, align 16
%0 = tail call <8 x i16> @llvm.ppc.altivec.vupkhsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1>) #0 %0 = tail call <8 x i16> @llvm.ppc.altivec.vupkhsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1>) #0
%1 = tail call <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1>) #0 %1 = tail call <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1>) #0
br i1 false, label %if.then.i68.i, label %check.exit69.i br i1 false, label %if.then.i68.i, label %check.exit69.i
if.then.i68.i: ; preds = %entry if.then.i68.i: ; preds = %entry
unreachable unreachable
check.exit69.i: ; preds = %entry check.exit69.i: ; preds = %entry
br i1 undef, label %if.then.i63.i, label %check.exit64.i br i1 %c0, label %if.then.i63.i, label %check.exit64.i
if.then.i63.i: ; preds = %check.exit69.i if.then.i63.i: ; preds = %check.exit69.i
tail call void (ptr, ...) @printf(ptr @.str10, ptr @.str1, <2 x double> %val) #0 tail call void (ptr, ...) @printf(ptr @.str10, ptr @.str1, <2 x double> %val) #0
br label %check.exit64.i br label %check.exit64.i
check.exit64.i: ; preds = %if.then.i63.i, %check.exit69.i check.exit64.i: ; preds = %if.then.i63.i, %check.exit69.i
%2 = tail call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> %0, <8 x i16> <i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 0, i16 -1, i16 0>) #0 %2 = tail call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> %0, <8 x i16> <i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 0, i16 -1, i16 0>) #0
%tobool.i55.i = icmp eq i32 %2, 0 %tobool.i55.i = icmp eq i32 %2, 0
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llvm/test/CodeGen/PowerPC/xray-ret-is-terminator.ll

; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
define void @ILLBeBack() #0 { define void @ILLBeBack(i1 %c0, i1 %c1) #0 {
; CHECK-LABEL: @ILLBeBack ; CHECK-LABEL: @ILLBeBack
; CHECK: bne {{[0-9]+}}, [[LABEL:\.[a-zA-Z0-9_]+]] ; CHECK: bne {{[0-9]+}}, [[LABEL:\.[a-zA-Z0-9_]+]]
; CHECK: [[LABEL]]: ; CHECK: [[LABEL]]:
; CHECK: bl __xray_FunctionExit ; CHECK: bl __xray_FunctionExit
bb: bb:
br i1 undef, label %bb1, label %bb8 br i1 %c0, label %bb1, label %bb8
bb1: bb1:
%tmp = tail call i64 asm sideeffect "", "=&r,=*m,b,r,*m,~{cc}"(ptr elementtype(i64) nonnull undef, ptr nonnull undef, i64 1, ptr elementtype(i64) nonnull undef) %tmp = tail call i64 asm sideeffect "", "=&r,=*m,b,r,*m,~{cc}"(ptr elementtype(i64) nonnull undef, ptr nonnull undef, i64 1, ptr elementtype(i64) nonnull undef)
%tmp2 = icmp eq i64 %tmp, 0 %tmp2 = icmp eq i64 %tmp, 0
br i1 %tmp2, label %bb3, label %bb8 br i1 %tmp2, label %bb3, label %bb8
bb3: bb3:
%tmp4 = tail call i64 asm sideeffect "", "=&r,=*m,b,r,r,*m,~{cc}"(ptr elementtype(i64) undef, ptr undef, i64 0, i64 undef, ptr elementtype(i64) undef) %tmp4 = tail call i64 asm sideeffect "", "=&r,=*m,b,r,r,*m,~{cc}"(ptr elementtype(i64) undef, ptr undef, i64 0, i64 undef, ptr elementtype(i64) undef)
%tmp5 = icmp eq i64 0, %tmp4 %tmp5 = icmp eq i64 0, %tmp4
br i1 %tmp5, label %bb6, label %bb3 br i1 %tmp5, label %bb6, label %bb3
bb6: bb6:
br i1 undef, label %bb7, label %bb8 br i1 %c1, label %bb7, label %bb8
bb7: bb7:
tail call void () undef() tail call void () undef()
ret void ret void
bb8: bb8:
ret void ret void
} }
attributes #0 = { "function-instrument"="xray-always" } attributes #0 = { "function-instrument"="xray-always" }

llvm/test/CodeGen/PowerPC/xvcmpeqdp-v2f64.ll

; RUN: llc < %s -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @__fmax_double3_3D_exec(<3 x double> %input1, <3 x i64> %input2, define void @__fmax_double3_3D_exec(<3 x double> %input1, <3 x i64> %input2,
<3 x i1> %input3, <3 x i64> %input4, <3 x i1> %input3, <3 x i64> %input4,
<3 x i64> %input5, ptr %input6) #0 { <3 x i64> %input5, ptr %input6) #0 {
entry: entry:
br i1 undef, label %if.then.i, label %fmax_double3.exit br i1 %c0, label %if.then.i, label %fmax_double3.exit
if.then.i: ; preds = %entry if.then.i: ; preds = %entry
%cmp24.i.i = fcmp ord <3 x double> %input1, zeroinitializer %cmp24.i.i = fcmp ord <3 x double> %input1, zeroinitializer
%sext25.i.i = sext <3 x i1> %cmp24.i.i to <3 x i64> %sext25.i.i = sext <3 x i1> %cmp24.i.i to <3 x i64>
%neg.i.i = xor <3 x i64> %sext25.i.i, <i64 -1, i64 -1, i64 -1> %neg.i.i = xor <3 x i64> %sext25.i.i, <i64 -1, i64 -1, i64 -1>
%or.i.i = or <3 x i64> %input2, %neg.i.i %or.i.i = or <3 x i64> %input2, %neg.i.i
%neg.i.i.i = select <3 x i1> %input3, <3 x i64> zeroinitializer, <3 x i64> %sext25.i.i %neg.i.i.i = select <3 x i1> %input3, <3 x i64> zeroinitializer, <3 x i64> %sext25.i.i
%and.i.i.i = and <3 x i64> %input4, %neg.i.i.i %and.i.i.i = and <3 x i64> %input4, %neg.i.i.i
%and26.i.i.i = and <3 x i64> %input5, %or.i.i %and26.i.i.i = and <3 x i64> %input5, %or.i.i
%or.i.i.i = or <3 x i64> %and.i.i.i, %and26.i.i.i %or.i.i.i = or <3 x i64> %and.i.i.i, %and26.i.i.i
%astype32.i.i.i = bitcast <3 x i64> %or.i.i.i to <3 x double> %astype32.i.i.i = bitcast <3 x i64> %or.i.i.i to <3 x double>
%extractVec33.i.i.i = shufflevector <3 x double> %astype32.i.i.i, <3 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> %extractVec33.i.i.i = shufflevector <3 x double> %astype32.i.i.i, <3 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
store <4 x double> %extractVec33.i.i.i, ptr %input6, align 32 store <4 x double> %extractVec33.i.i.i, ptr %input6, align 32
br label %fmax_double3.exit br label %fmax_double3.exit
; CHECK-LABEL: @__fmax_double3_3D_exec ; CHECK-LABEL: @__fmax_double3_3D_exec
; CHECK: xvcmpeqdp ; CHECK: xvcmpeqdp
fmax_double3.exit: ; preds = %if.then.i, %entry fmax_double3.exit: ; preds = %if.then.i, %entry
br i1 undef, label %if.then, label %do.end br i1 %c1, label %if.then, label %do.end
if.then: ; preds = %fmax_double3.exit if.then: ; preds = %fmax_double3.exit
unreachable unreachable
do.end: ; preds = %fmax_double3.exit do.end: ; preds = %fmax_double3.exit
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/zero-not-run.ll

; RUN: llc -verify-machineinstrs -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s ; RUN: llc -verify-machineinstrs -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define internal ptr @func_65(ptr %p_66) #0 { define internal ptr @func_65(ptr %p_66, i1 %c0) #0 {
entry: entry:
br i1 undef, label %for.body, label %for.end731 br i1 %c0, label %for.body, label %for.end731
for.body: ; preds = %entry for.body: ; preds = %entry
%0 = load i32, ptr undef, align 4 %0 = load i32, ptr undef, align 4
%or31 = or i32 %0, 319143828 %or31 = or i32 %0, 319143828
store i32 %or31, ptr undef, align 4 store i32 %or31, ptr undef, align 4
%cmp32 = icmp eq i32 319143828, %or31 %cmp32 = icmp eq i32 319143828, %or31
%conv33 = zext i1 %cmp32 to i32 %conv33 = zext i1 %cmp32 to i32
%conv34 = sext i32 %conv33 to i64 %conv34 = sext i32 %conv33 to i64
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