[test] Remove occurences of br undef in CodeGen/AArch64 tests

[kritgpt]

Summary

This patch removes br undef as suggested by https://discourse.llvm.org/t/please-dont-use-br-undef-in-tests-aka-please-avoid-test-cases-with-ub/63115. Script used: https://gist.github.com/kritgpt/69bfc7ef78e1784716c693d531a58adf.

[fhahn]

Not sure if replace_undef_X is an ideal name. Might be better to use something short like cX or condX

[kritgpt]

In D145333#4170852, @fhahn wrote:

Not sure if replace_undef_X is an ideal name. Might be better to use something short like cX or condX

I went for this name to avoid clashes with any existing arguments. Wasn't sure if cX or condX are already used in any of the tests.

[Groverkss]

llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll

1005

This is why you are getting failed tests. % is not a valid variable name character for FileCheck.

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll

 
 declare ptr @wibble(ptr returned, ptr)
 
 declare void @baz(i32, ptr)
 
 
 ; Check that with 2 jump tables, the phi node doesn't lose the edge from the
 ; second one.
-define void @jt_2_tables_phi_edge_from_second() {
+define void @jt_2_tables_phi_edge_from_second(i1 %replace_undef_0) {
   ; CHECK-LABEL: name: jt_2_tables_phi_edge_from_second
   ; CHECK: bb.1.entry:
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 123
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 263
   ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 265
   ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 270
   ; CHECK-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 279

 sw.bb9.i:                                         ; preds = %sw.bb14.i48
   br label %land.rhs.lr.ph
 
 sw.bb12.i:                                        ; preds = %sw.bb14.i48
   br label %land.rhs.lr.ph
 
 land.rhs.lr.ph:                                   ; preds = %sw.bb12.i, %sw.bb9.i, %sw.bb8.i, %sw.bb7.i, %sw.bb6.i, %sw.bb4.i, %sw.bb1.i, %sw.bb14.i48
   %retval.0.i.ph = phi i32 [ 0, %sw.bb14.i48 ], [ 1, %sw.bb1.i ], [ 4, %sw.bb4.i ], [ 6, %sw.bb6.i ], [ 7, %sw.bb7.i ], [ 8, %sw.bb8.i ], [ 9, %sw.bb9.i ], [ 12, %sw.bb12.i ]
-  br i1 undef, label %while.body, label %while.end
+  br i1 %replace_undef_0, label %while.body, label %while.end
 
 while.body:                                       ; preds = %land.rhs.lr.ph
   call void @jt_2_tables_phi_edge_from_second()
   unreachable
 
 while.end:                                        ; preds = %land.rhs.lr.ph, %sw.bb14.i48
   %op.0.lcssa = phi i32 [ 15, %sw.bb14.i48 ], [ %retval.0.i.ph, %land.rhs.lr.ph ]
   ret void

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll

 ; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-fuchsia"
 
 declare void @llvm.dbg.value(metadata, metadata, metadata) #0
 ; Check that we don't crash when we have a metadata use of %i not being dominated by the def.
 ; CHECK-LABEL: @foo
 ; CHECK: DBG_VALUE %1:_(p0), $noreg, !370, !DIExpression(DW_OP_LLVM_fragment, 0, 64)
-define hidden void @foo() unnamed_addr #1 !dbg !230 {
-  br i1 undef, label %bb4, label %bb5
+define hidden void @foo(i1 %replace_undef_0) unnamed_addr #1 !dbg !230 {
+  br i1 %replace_undef_0, label %bb4, label %bb5
 
 bb4:                                              ; preds = %bb3
   %i = extractvalue { ptr, i64 } undef, 0
   ret void
 
 bb5:                                              ; preds = %bb3
   call void @llvm.dbg.value(metadata ptr %i, metadata !370, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64)), !dbg !372
   ret void

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll

 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
 ;
 ; Make sure that we don't duplicate successors/predecessors when translating
 ; indirectbr instructions with duplicate block labels.
 
-define void @foo() {
+define void @foo(i1 %replace_undef_0) {
   ; CHECK-LABEL: name: foo
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK:   successors: %bb.2(0x2aaaaaaa), %bb.4(0x2aaaaaaa), %bb.3(0x2aaaaaaa)
   ; CHECK:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
   ; CHECK:   G_BRINDIRECT [[DEF]](p0)
   ; CHECK: bb.2 (%ir-block.1):
   ; CHECK:   successors:
   ; CHECK: bb.3 (%ir-block.2):
   ; CHECK:   successors:
   ; CHECK: bb.4 (%ir-block.3):
   ; CHECK:   RET_ReallyLR
-  indirectbr ptr undef, [label %1, label %3, label %2, label %3, label %3]
+  indirectbr ptr %replace_undef_0, [label %1, label %3, label %2, label %3, label %3]
 1:
   unreachable
 2:
   unreachable
 3:
   ret void
 }

llvm/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll

 ; RUN: llc -O3 -mcpu=cortex-a53 -mtriple=aarch64--linux-gnu %s -o - | FileCheck %s
 ; PR20188: don't crash when merging sexts.
 
 ; CHECK: foo:
-define void @foo() unnamed_addr align 2 {
+define void @foo(i1 %replace_undef_0, i1 %replace_undef_1, i1 %replace_undef_2) unnamed_addr align 2 {
 entry:
   br label %invoke.cont145
 
 invoke.cont145:
   %or.cond = and i1 undef, false
   br i1 %or.cond, label %if.then274, label %invoke.cont145
 
 if.then274:
   %0 = load i32, ptr null, align 4
-  br i1 undef, label %invoke.cont291, label %if.else313
+  br i1 %replace_undef_0, label %invoke.cont291, label %if.else313
 
 invoke.cont291:
   %idxprom.i.i.i605 = sext i32 %0 to i64
   %arrayidx.i.i.i607 = getelementptr inbounds double, ptr undef, i64 %idxprom.i.i.i605
   %idxprom.i.i.i596 = sext i32 %0 to i64
   %arrayidx.i.i.i598 = getelementptr inbounds double, ptr undef, i64 %idxprom.i.i.i596
   br label %if.end356
 
 if.else313:
   %cmp314 = fcmp olt double undef, 0.000000e+00
   br i1 %cmp314, label %invoke.cont317, label %invoke.cont353
 
 invoke.cont317:
-  br i1 undef, label %invoke.cont326, label %invoke.cont334
+  br i1 %replace_undef_1, label %invoke.cont326, label %invoke.cont334
 
 invoke.cont326:
   %idxprom.i.i.i587 = sext i32 %0 to i64
   %arrayidx.i.i.i589 = getelementptr inbounds double, ptr undef, i64 %idxprom.i.i.i587
   %sub329 = fsub fast double undef, undef
   br label %invoke.cont334
 
 invoke.cont334:
   %lo.1 = phi double [ %sub329, %invoke.cont326 ], [ undef, %invoke.cont317 ]
-  br i1 undef, label %invoke.cont342, label %if.end356
+  br i1 %replace_undef_2, label %invoke.cont342, label %if.end356
 
 invoke.cont342:
   %idxprom.i.i.i578 = sext i32 %0 to i64
   %arrayidx.i.i.i580 = getelementptr inbounds double, ptr undef, i64 %idxprom.i.i.i578
   br label %if.end356
 
 invoke.cont353:
   %idxprom.i.i.i572 = sext i32 %0 to i64
   %arrayidx.i.i.i574 = getelementptr inbounds double, ptr undef, i64 %idxprom.i.i.i572
   br label %if.end356
 
 if.end356:
   %lo.2 = phi double [ 0.000000e+00, %invoke.cont291 ], [ %lo.1, %invoke.cont342 ], [ undef, %invoke.cont353 ], [ %lo.1, %invoke.cont334 ]
   call void null(i32 %0, double %lo.2)
   unreachable
 }

llvm/test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll

 ; RUN: llc < %s -mtriple=arm64-apple-darwin
 
 ; Can't copy or spill / restore CPSR.
 ; rdar://9105206
 
-define fastcc void @t() ssp align 2 {
+define fastcc void @t(i1 %replace_undef_0, i1 %replace_undef_1, i1 %replace_undef_2, i1 %replace_undef_3, i1 %replace_undef_4) ssp align 2 {
 entry:
-  br i1 undef, label %bb3.i, label %bb2.i
+  br i1 %replace_undef_0, label %bb3.i, label %bb2.i
 
 bb2.i:                                            ; preds = %entry
   br label %bb3.i
 
 bb3.i:                                            ; preds = %bb2.i, %entry
-  br i1 undef, label %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71, label %bb.i69
+  br i1 %replace_undef_1, label %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71, label %bb.i69
 
 bb.i69:                                           ; preds = %bb3.i
   br label %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71
 
 _ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71: ; preds = %bb.i69, %bb3.i
   %0 = select i1 undef, float 0.000000e+00, float undef
   %1 = fdiv float %0, undef
   %2 = fcmp ult float %1, 0xBF847AE140000000
   %storemerge9 = select i1 %2, float %1, float 0.000000e+00
   store float %storemerge9, ptr undef, align 4
-  br i1 undef, label %bb42, label %bb47
+  br i1 %replace_undef_2, label %bb42, label %bb47
 
 bb42:                                             ; preds = %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71
-  br i1 undef, label %bb46, label %bb53
+  br i1 %replace_undef_3, label %bb46, label %bb53
 
 bb46:                                             ; preds = %bb42
   br label %bb48
 
 bb47:                                             ; preds = %_ZN12gjkepa2_impl3EPA6appendERNS0_5sListEPNS0_5sFaceE.exit71
   br label %bb48
 
 bb48:                                             ; preds = %bb47, %bb46
-  br i1 undef, label %bb1.i14, label %bb.i13
+  br i1 %replace_undef_4, label %bb1.i14, label %bb.i13
 
 bb.i13:                                           ; preds = %bb48
   br label %bb1.i14
 
 bb1.i14:                                          ; preds = %bb.i13, %bb48
   br label %bb53
 
 bb53:                                             ; preds = %bb1.i14, %bb42
   ret void
 }

llvm/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll

 ; RUN: llc < %s -mtriple=arm64-apple-darwin
 
 ; rdar://9146594
 
 source_filename = "test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll"
 
 ; Function Attrs: nounwind ssp
-define void @drt_vsprintf() #0 {
+define void @drt_vsprintf(i1 %replace_undef_0) #0 {
 entry:
   %do_tab_convert = alloca i32, align 4
-  br i1 undef, label %if.then24, label %if.else295, !dbg !11
+  br i1 %replace_undef_0, label %if.then24, label %if.else295, !dbg !11
 
 if.then24:                                        ; preds = %entry
   unreachable
 
 if.else295:                                       ; preds = %entry
   call void @llvm.dbg.declare(metadata ptr %do_tab_convert, metadata !14, metadata !16), !dbg !17
   store i32 0, ptr %do_tab_convert, align 4, !dbg !18
   unreachable

llvm/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll

 ; RUN: llc < %s -mtriple=arm64-apple-iOS5.0
 
 ; CPSR is not allocatable so fast allocatable wouldn't mark them killed.
 ; rdar://9313272
 
-define hidden void @t() nounwind {
+define hidden void @t(i1 %replace_undef_0) nounwind {
 entry:
   %cmp = icmp eq ptr null, undef
   %frombool = zext i1 %cmp to i8
   store i8 %frombool, ptr undef, align 1
   %tmp4 = load i8, ptr undef, align 1
   %tobool = trunc i8 %tmp4 to i1
   br i1 %tobool, label %land.lhs.true, label %if.end
 
 land.lhs.true:                                    ; preds = %entry
   unreachable
 
 if.end:                                           ; preds = %entry
-  br i1 undef, label %land.lhs.true14, label %if.end33
+  br i1 %replace_undef_0, label %land.lhs.true14, label %if.end33
 
 land.lhs.true14:                                  ; preds = %if.end
   unreachable
 
 if.end33:                                         ; preds = %if.end
   unreachable
 }

llvm/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll

 ; RUN: llc < %s -mtriple=arm64-eabi
 
 ; The target lowering for integer comparisons was replacing some DAG nodes
 ; during operation legalization, which resulted in dangling pointers,
 ; cycles in DAGs, and eventually crashes.  This is the testcase for
 ; one of those crashes. (rdar://10653656)
 
-define void @test(i1 zeroext %IsArrow) nounwind ssp align 2 {
+define void @test(i1 zeroext %IsArrow, i1 %replace_undef_0, i1 %replace_undef_1, i1 %replace_undef_2, i1 %replace_undef_3) nounwind ssp align 2 {
 entry:
-  br i1 undef, label %return, label %lor.lhs.false
+  br i1 %replace_undef_0, label %return, label %lor.lhs.false
 
 lor.lhs.false:
-  br i1 undef, label %return, label %if.end
+  br i1 %replace_undef_1, label %return, label %if.end
 
 if.end:
   %tmp.i = load i64, ptr undef, align 8
   %and.i.i.i = and i64 %tmp.i, -16
   br i1 %IsArrow, label %if.else_crit_edge, label %if.end32
 
 if.else_crit_edge:
-  br i1 undef, label %if.end32, label %return
+  br i1 %replace_undef_2, label %if.end32, label %return
 
 if.end32:
   %0 = icmp ult i32 undef, 3
   %1 = zext i64 %tmp.i to i320
   %.pn.v = select i1 %0, i320 128, i320 64
   %.pn = shl i320 %1, %.pn.v
   %ins346392 = or i320 %.pn, 0
   store i320 %ins346392, ptr undef, align 8
-  br i1 undef, label %sw.bb.i.i, label %exit
+  br i1 %replace_undef_3, label %sw.bb.i.i, label %exit
 
 sw.bb.i.i:
   unreachable
 
 exit:
   unreachable
 
 return:
   ret void
 }

llvm/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll

 declare i64 @strlen(ptr nocapture) nounwind readonly optsize
 
 declare ptr @__strcpy_chk(ptr, ptr, i64) nounwind optsize
 
 declare ptr @__strcat_chk(ptr, ptr, i64) nounwind optsize
 
 declare noalias ptr @xstrdup(ptr) optsize
 
-define ptr @dyld_fix_path(ptr %path) nounwind optsize ssp {
+define ptr @dyld_fix_path(ptr %path, i1 %replace_undef_0, i1 %replace_undef_1, i1 %replace_undef_2, i1 %replace_undef_3) nounwind optsize ssp {
 entry:
-  br i1 undef, label %if.end56, label %for.cond
+  br i1 %replace_undef_0, label %if.end56, label %for.cond
 
 for.cond:                                         ; preds = %entry
-  br i1 undef, label %for.cond10, label %for.body
+  br i1 %replace_undef_1, label %for.cond10, label %for.body
 
 for.body:                                         ; preds = %for.cond
   unreachable
 
 for.cond10:                                       ; preds = %for.cond
-  br i1 undef, label %if.end56, label %for.body14
+  br i1 %replace_undef_2, label %if.end56, label %for.body14
 
 for.body14:                                       ; preds = %for.cond10
   %call22 = tail call i64 @strlen(ptr undef) nounwind optsize
   %sext = shl i64 %call22, 32
   %conv30 = ashr exact i64 %sext, 32
   %add29 = sub i64 0, %conv30
   %sub = add i64 %add29, 0
   %add31 = shl i64 %sub, 32
   %sext59 = add i64 %add31, 4294967296
   %conv33 = ashr exact i64 %sext59, 32
   %call34 = tail call noalias ptr @xmalloc(i64 %conv33) nounwind optsize
-  br i1 undef, label %cond.false45, label %cond.true43
+  br i1 %replace_undef_3, label %cond.false45, label %cond.true43
 
 cond.true43:                                      ; preds = %for.body14
   unreachable
 
 cond.false45:                                     ; preds = %for.body14
   %add.ptr = getelementptr inbounds i8, ptr %path, i64 %conv30
   unreachable
 
 if.end56:                                         ; preds = %for.cond10, %entry
   ret ptr null
 }
 
 declare i32 @strncmp(ptr nocapture, ptr nocapture, i64) nounwind readonly optsize
 
 declare ptr @strcpy(ptr, ptr nocapture) nounwind

llvm/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll

 ; RUN: llc < %s -mtriple=arm64-eabi
 ; Make sure we are not crashing on this test.
 
-define void @autogen_SD13158() {
+define void @autogen_SD13158(i1 %replace_undef_0, i1 %replace_undef_1) {
 entry:
   %B26 = frem float 0.000000e+00, undef
-  br i1 undef, label %CF, label %CF77
+  br i1 %replace_undef_0, label %CF, label %CF77
 
 CF:                                               ; preds = %CF, %CF76
   store float %B26, ptr undef
-  br i1 undef, label %CF, label %CF77
+  br i1 %replace_undef_1, label %CF, label %CF77
 
 CF77:                                             ; preds = %CF
   ret void
 }

llvm/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll

 ; RUN: llc < %s -mtriple=arm64-eabi
 
 ; Make sure we are not crashing on this test.
 
-define void @autogen_SD12881() {
+define void @autogen_SD12881(i1 %replace_undef_0) {
 BB:
   %B17 = ashr <4 x i32> zeroinitializer, zeroinitializer
   br label %CF
 
 CF:                                               ; preds = %CF83, %CF, %BB
-  br i1 undef, label %CF, label %CF83
+  br i1 %replace_undef_0, label %CF, label %CF83
 
 CF83:                                             ; preds = %CF
   %FC70 = sitofp <4 x i32> %B17 to <4 x double>
   br label %CF
 }
 
 
-define void @autogen_SD12881_2() {
+define void @autogen_SD12881_2(i1 %replace_undef_0) {
 BB:
   %B17 = ashr <4 x i32> zeroinitializer, zeroinitializer
   br label %CF
 
 CF:                                               ; preds = %CF83, %CF, %BB
-  br i1 undef, label %CF, label %CF83
+  br i1 %replace_undef_0, label %CF, label %CF83
 
 CF83:                                             ; preds = %CF
   %FC70 = uitofp <4 x i32> %B17 to <4 x double>
   br label %CF
 }
 
 define void @_Z12my_example2bv() nounwind noinline ssp {
 entry:
   %0 = fptosi <2 x double> undef to <2 x i32>
   store <2 x i32> %0, ptr undef, align 8
   ret void
 }

llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll

; OPT-NEXT:    ret i16 [[CONV19]]
   %conv19 = trunc i32 %or18 to i16
 
   ret i16 %conv19
 }
 
 ; The following test excercises the case where we have a BFI
 ; instruction with the same input in both operands. We need to
 ; track the useful bits through both operands.
-define void @sameOperandBFI(i64 %src, i64 %src2, ptr %ptr) {
+define void @sameOperandBFI(i64 %src, i64 %src2, ptr %ptr, i1 %replace_undef_0) {
 ; LLC-LABEL: sameOperandBFI:
 ; LLC:       // %bb.0: // %entry
 ; LLC-NEXT:    cbnz wzr, .LBB30_2
 ; LLC-NEXT:  // %bb.1: // %if.else
 ; LLC-NEXT:    lsr x8, x0, #47
 ; LLC-NEXT:    and w9, w1, #0x3
 ; LLC-NEXT:    bfi w9, w8, #2, #2
 ; LLC-NEXT:    orr w8, w9, w9, lsl #4
 ; LLC-NEXT:    strh w8, [x2]
 ; LLC-NEXT:  .LBB30_2: // %end
 ; LLC-NEXT:    ret
 ; OPT-LABEL: @sameOperandBFI(
 ; OPT-NEXT:  entry:
 ; OPT-NEXT:    [[SHR47:%.*]] = lshr i64 [[SRC:%.*]], 47
 ; OPT-NEXT:    [[SRC2_TRUNC:%.*]] = trunc i64 [[SRC2:%.*]] to i32
-; OPT-NEXT:    br i1 undef, label [[END:%.*]], label [[IF_ELSE:%.*]]
+; OPT-NEXT:    br i1 [[%replace_undef_0:%.*]], label [[END:%.*]], label [[IF_ELSE:%.*]]
 ; OPT:       if.else:
 ; OPT-NEXT:    [[AND3:%.*]] = and i32 [[SRC2_TRUNC]], 3
 ; OPT-NEXT:    [[SHL2:%.*]] = shl nuw nsw i64 [[SHR47]], 2
 ; OPT-NEXT:    [[SHL2_TRUNC:%.*]] = trunc i64 [[SHL2]] to i32
 ; OPT-NEXT:    [[AND12:%.*]] = and i32 [[SHL2_TRUNC]], 12
 ; OPT-NEXT:    [[BFISOURCE:%.*]] = or i32 [[AND3]], [[AND12]]
 ; OPT-NEXT:    [[BFIRHS:%.*]] = shl nuw nsw i32 [[BFISOURCE]], 4
 ; OPT-NEXT:    [[BFI:%.*]] = or i32 [[BFIRHS]], [[BFISOURCE]]
 ; OPT-NEXT:    [[BFITRUNC:%.*]] = trunc i32 [[BFI]] to i16
 ; OPT-NEXT:    store i16 [[BFITRUNC]], ptr [[PTR:%.*]], align 4
 ; OPT-NEXT:    br label [[END]]
 ; OPT:       end:
 ; OPT-NEXT:    ret void
 entry:
   %shr47 = lshr i64 %src, 47
   %src2.trunc = trunc i64 %src2 to i32
-  br i1 undef, label %end, label %if.else
+  br i1 %replace_undef_0, label %end, label %if.else
 
 if.else:
   %and3 = and i32 %src2.trunc, 3
   %shl2 = shl nuw nsw i64 %shr47, 2
   %shl2.trunc = trunc i64 %shl2 to i32
   %and12 = and i32 %shl2.trunc, 12
   %BFISource = or i32 %and3, %and12         ; ...00000ABCD
   %BFIRHS = shl nuw nsw i32 %BFISource, 4   ; ...0ABCD0000
   %BFI = or i32 %BFIRHS, %BFISource         ; ...0ABCDABCD
   %BFItrunc = trunc i32 %BFI to i16
   store i16 %BFItrunc, ptr %ptr, align 4
   br label %end
 
 end:
   ret void
 }

llvm/test/CodeGen/AArch64/arm64-call-tailcalls.ll

 
 define float @t5(float %a) nounwind readonly ssp {
 ; CHECK-LABEL: t5:
 ; CHECK: b  _sinf
   %tmp = tail call float @sinf(float %a) nounwind readonly
   ret float %tmp
 }
 
-define void @t7() nounwind {
+define void @t7(i1 %replace_undef_0) nounwind {
 ; CHECK-LABEL: t7:
 ; CHECK: b  _foo
 ; CHECK: b  _bar
 
-  br i1 undef, label %bb, label %bb1.lr.ph
+  br i1 %replace_undef_0, label %bb, label %bb1.lr.ph
 
 bb1.lr.ph:                                        ; preds = %entry
   tail call void @bar() nounwind
   ret void
 
 bb:                                               ; preds = %entry
   tail call void @foo() nounwind
   ret void

llvm/test/CodeGen/AArch64/arm64-collect-loh.ll

define void @uninterestingSub(i8* nocapture %row) #0 {
   %add.i.402 = add <16 x i8> zeroinitializer, %vext157
   store <16 x i8> %add.i.402, <16 x i8>* %tmp4, align 16
   ret void
 }
 
 @.str.89 = external unnamed_addr constant [12 x i8], align 1
 @.str.90 = external unnamed_addr constant [5 x i8], align 1
 ; CHECK-LABEL: test_r274582
-define void @test_r274582(double %x) {
+define void @test_r274582(double %x, i1 %replace_undef_0) {
 entry:
-  br i1 undef, label %if.then.i, label %if.end.i
+  br i1 %replace_undef_0, label %if.then.i, label %if.end.i
 if.then.i:
   ret void
 if.end.i:
 ; CHECK: .loh AdrpLdrGot
 ; CHECK: .loh AdrpLdrGot
 ; CHECK: .loh AdrpAdrp
 ; CHECK: .loh AdrpLdr
   %mul = fmul double %x, 1.000000e-06
   %add = fadd double %mul, %mul
   %sub = fsub double %add, %add
   call void (i8*, ...) @callee(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.89, i64 0, i64 0), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str.90, i64 0, i64 0), double %sub)
   unreachable
 }
 declare void @callee(i8* nocapture readonly, ...) 
 
 attributes #0 = { "target-cpu"="cyclone" }

llvm/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll

 ; RUN: llc -mtriple="arm64-apple-ios" < %s | FileCheck %s
 ;
 ; Check that the dead register definition pass is considering implicit defs.
 ; When rematerializing through truncates, the coalescer may produce instructions
 ; with dead defs, but live implicit-defs of subregs:
 ; E.g. dead %x1 = MOVi64imm 2, implicit-def %w1; %x1:GPR64, %w1:GPR32
 ; These instructions are live, and their definitions should not be rewritten.
 ;
 ; <rdar://problem/16492408>
 
-define void @testcase() {
+define void @testcase(i1 %replace_undef_0) {
 ; CHECK: testcase:
 ; CHECK-NOT: orr xzr, xzr, #0x2
 
 bb1:
   %tmp1 = tail call float @ceilf(float 2.000000e+00)
   %tmp2 = fptoui float %tmp1 to i64
-  br i1 undef, label %bb2, label %bb3
+  br i1 %replace_undef_0, label %bb2, label %bb3
 
 bb2:
   tail call void @foo()
   br label %bb3
 
 bb3:
   %tmp3 = trunc i64 %tmp2 to i32
   tail call void @bar(i32 %tmp3)
   ret void
 }
 
 declare void @foo()
 declare void @bar(i32)
 declare float @ceilf(float) nounwind readnone

llvm/test/CodeGen/AArch64/arm64-early-ifcvt.ll

 
 done:
   %cond = phi i64 [ %x, %ne_bb ], [ %y, %entry ]
   ret i64 %cond
 }
 
 ; This function from 175.vpr folds an ADDWri into a CSINC.
 ; Remember to clear the kill flag on the ADDWri.
-define i32 @get_ytrack_to_xtracks() nounwind ssp {
+define i32 @get_ytrack_to_xtracks(i1 %replace_undef_0, i1 %replace_undef_1) nounwind ssp {
 entry:
   br label %for.body
 
 for.body:
   %x0 = load i32, ptr undef, align 4
-  br i1 undef, label %if.then.i146, label %is_sbox.exit155
+  br i1 %replace_undef_0, label %if.then.i146, label %is_sbox.exit155
 
 if.then.i146:
   %add8.i143 = add nsw i32 0, %x0
   %rem.i144 = srem i32 %add8.i143, %x0
   %add9.i145 = add i32 %rem.i144, 1
   br label %is_sbox.exit155
 
 is_sbox.exit155:                                  ; preds = %if.then.i146, %for.body
   %seg_offset.0.i151 = phi i32 [ %add9.i145, %if.then.i146 ], [ undef, %for.body ]
   %idxprom15.i152 = sext i32 %seg_offset.0.i151 to i64
   %arrayidx18.i154 = getelementptr inbounds i32, ptr null, i64 %idxprom15.i152
   %x1 = load i32, ptr %arrayidx18.i154, align 4
-  br i1 undef, label %for.body51, label %for.body
+  br i1 %replace_undef_1, label %for.body51, label %for.body
 
 for.body51:                                       ; preds = %is_sbox.exit155
   call fastcc void @get_switch_type(i32 %x1, i32 undef, i16 signext undef, i16 signext undef, ptr undef)
   unreachable
 }
 declare fastcc void @get_switch_type(i32, i32, i16 signext, i16 signext, ptr nocapture) nounwind ssp

llvm/test/CodeGen/AArch64/arm64-fast-isel.ll

entry:
   %sub.ptr.div = sdiv exact i64 %arg, 8
   %tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8)
   %tmp1 = extractvalue { i64, i1 } %tmp, 0
   ret i64 %tmp1
 }
 
 declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
 
-define void @logicalReg() {
+define void @logicalReg(i1 %replace_undef_0) {
 ; Make sure we generate a logical reg = reg, reg instruction without any
 ; machine verifier errors.
 ; CHECK-LABEL: logicalReg:
 ; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}}
 ; CHECK: ret
 entry:
-  br i1 undef, label %cond.end, label %cond.false
+  br i1 %replace_undef_0, label %cond.end, label %cond.false
 
 cond.false:
   %cond = select i1 undef, i1 true, i1 false
   br label %cond.end
 
 cond.end:
   %cond13 = phi i1 [ %cond, %cond.false ], [ true, %entry ]
   ret void
 }
 

llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll

 ; Make sure that we handle infinite loops properly When checking that the Save
 ; and Restore blocks are control flow equivalent, the loop searches for the
 ; immediate (post) dominator for the (restore) save blocks. When either the Save
 ; or Restore block is located in an infinite loop the only immediate (post)
 ; dominator is itself. In this case, we cannot perform shrink wrapping, but we
 ; should return gracefully and continue compilation.
 ; The only condition for this test is the compilation finishes correctly.
 ;
-define void @infiniteloop() {
+define void @infiniteloop(i1 %replace_undef_0) {
 ; ENABLE-LABEL: infiniteloop:
 ; ENABLE:       ; %bb.0: ; %entry
 ; ENABLE-NEXT:    stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
 ; ENABLE-NEXT:    .cfi_def_cfa_offset 32
 ; ENABLE-NEXT:    stp x29, x30, [sp, #16] ; 16-byte Folded Spill
 ; ENABLE-NEXT:    add x29, sp, #16
 ; ENABLE-NEXT:    .cfi_def_cfa w29, 16
 ; ENABLE-NEXT:    .cfi_offset w30, -8

 ; DISABLE-NEXT:    str w20, [x19]
 ; DISABLE-NEXT:    b LBB10_2
 ; DISABLE-NEXT:  LBB10_3: ; %if.end
 ; DISABLE-NEXT:    sub sp, x29, #16
 ; DISABLE-NEXT:    ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
 ; DISABLE-NEXT:    ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
 ; DISABLE-NEXT:    ret
 entry:
-  br i1 undef, label %if.then, label %if.end
+  br i1 %replace_undef_0, label %if.then, label %if.end
 
 if.then:
   %ptr = alloca i32, i32 4
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
   %sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
   %call = tail call i32 @something()
   %add = add nsw i32 %call, %sum.03
   store i32 %add, ptr %ptr
   br label %for.body
 
 if.end:
   ret void
 }
 
 ; Another infinite loop test this time with a body bigger than just one block.
-define void @infiniteloop2() {
+define void @infiniteloop2(i1 %replace_undef_0, i1 %replace_undef_1) {
 ; ENABLE-LABEL: infiniteloop2:
 ; ENABLE:       ; %bb.0: ; %entry
 ; ENABLE-NEXT:    stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
 ; ENABLE-NEXT:    .cfi_def_cfa_offset 32
 ; ENABLE-NEXT:    stp x29, x30, [sp, #16] ; 16-byte Folded Spill
 ; ENABLE-NEXT:    add x29, sp, #16
 ; ENABLE-NEXT:    .cfi_def_cfa w29, 16
 ; ENABLE-NEXT:    .cfi_offset w30, -8

 ; DISABLE-NEXT:    ; InlineAsm End
 ; DISABLE-NEXT:    b LBB11_2
 ; DISABLE-NEXT:  LBB11_3: ; %if.end
 ; DISABLE-NEXT:    sub sp, x29, #16
 ; DISABLE-NEXT:    ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
 ; DISABLE-NEXT:    ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
 ; DISABLE-NEXT:    ret
 entry:
-  br i1 undef, label %if.then, label %if.end
+  br i1 %replace_undef_0, label %if.then, label %if.end
 
 if.then:
   %ptr = alloca i32, i32 4
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
   %sum.03 = phi i32 [ 0, %if.then ], [ %add, %body1 ], [ 1, %body2]
   %call = tail call i32 asm "mov $0, #0", "=r,~{x19}"()
   %add = add nsw i32 %call, %sum.03
   store i32 %add, ptr %ptr
-  br i1 undef, label %body1, label %body2
+  br i1 %replace_undef_1, label %body1, label %body2
 
 body1:
   tail call void asm sideeffect "nop", "~{x19}"()
   br label %for.body
 
 body2:
   tail call void asm sideeffect "nop", "~{x19}"()
   br label %for.body
 
 if.end:
   ret void
 }
 
 ; Another infinite loop test this time with two nested infinite loop.
-define void @infiniteloop3() {
+define void @infiniteloop3(i1 %replace_undef_0, i1 %replace_undef_1) {
 ; ENABLE-LABEL: infiniteloop3:
 ; ENABLE:       ; %bb.0: ; %entry
 ; ENABLE-NEXT:    cbnz wzr, LBB12_5
 ; ENABLE-NEXT:  ; %bb.1: ; %loop2a.preheader
 ; ENABLE-NEXT:    mov x8, xzr
 ; ENABLE-NEXT:    mov x9, xzr
 ; ENABLE-NEXT:    mov x11, xzr
 ; ENABLE-NEXT:    b LBB12_3

 ; DISABLE-NEXT:    cbnz x8, LBB12_2
 ; DISABLE-NEXT:  ; %bb.4: ; in Loop: Header=BB12_3 Depth=1
 ; DISABLE-NEXT:    mov x8, x10
 ; DISABLE-NEXT:    mov x11, x10
 ; DISABLE-NEXT:    b LBB12_3
 ; DISABLE-NEXT:  LBB12_5: ; %end
 ; DISABLE-NEXT:    ret
 entry:
-  br i1 undef, label %loop2a, label %body
+  br i1 %replace_undef_0, label %loop2a, label %body
 
 body:                                             ; preds = %entry
-  br i1 undef, label %loop2a, label %end
+  br i1 %replace_undef_1, label %loop2a, label %end
 
 loop1:                                            ; preds = %loop2a, %loop2b
   %var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ]
   %next.phi = phi ptr [ %next.load, %loop2b ], [ %next.var, %loop2a ]
   %0 = icmp eq ptr %var, null
   %next.load = load ptr, ptr undef
   br i1 %0, label %loop2a, label %loop2b
 

llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll

 ; RUN: llc  -mtriple=aarch64-linux-gnu -enable-misched=false < %s | FileCheck %s
 
 ;target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 ;target triple = "aarch64--linux-gnu"
 
 
 ; CHECK-LABEL: test
 ; CHECK: str     x30, [sp, #-16]!
 ; CHECK: adrp    x8, q   
 ; CHECK: ldr     x8, [x8, :lo12:q]
 ; CHECK: stp     xzr, xzr, [x8] 
 ; CHECK: bl f
 
 @q = external dso_local unnamed_addr global ptr, align 8
 
 ; Function Attrs: nounwind
-define void @test() local_unnamed_addr #0 {
+define void @test(i1 %replace_undef_0) local_unnamed_addr #0 {
 entry:
   br label %for.body453.i
 
 for.body453.i:                                    ; preds = %for.body453.i, %entry
-  br i1 undef, label %for.body453.i, label %for.end705.i
+  br i1 %replace_undef_0, label %for.body453.i, label %for.end705.i
 
 for.end705.i:                                     ; preds = %for.body453.i
   %0 = load ptr, ptr @q, align 8
   store <2 x i16> zeroinitializer, ptr %0, align 2
   %1 = getelementptr i16, ptr %0, i64 2
   store <2 x i16> zeroinitializer, ptr %1, align 2
   %2 = getelementptr i16, ptr %0, i64 4
   store <2 x i16> zeroinitializer, ptr %2, align 2

llvm/test/CodeGen/AArch64/br-to-eh-lpad.ll

 ; RUN: llc < %s -mtriple=aarch64-apple-ios -verify-machineinstrs
 
 ; This function tests that the machine verifier accepts an unconditional
 ; branch from an invoke basic block, to its EH landing pad basic block.
 ; The test is brittle and isn't ideally reduced, because in most cases the
 ; branch would be removed (for instance, turned into a fallthrough), and in
 ; that case, the machine verifier, which relies on analyzing branches for this
 ; kind of verification, is unable to check anything, so accepts the CFG.
 
-define void @test_branch_to_landingpad() personality ptr @__objc_personality_v0 {
+define void @test_branch_to_landingpad(i1 %replace_undef_0, i1 %replace_undef_1) personality ptr @__objc_personality_v0 {
 entry:
-  br i1 undef, label %if.end50.thread, label %if.then6
+  br i1 %replace_undef_0, label %if.end50.thread, label %if.then6
 
 lpad:
   %0 = landingpad { ptr, i32 }
           catch ptr @"OBJC_EHTYPE_$_NSString"
           catch ptr @OBJC_EHTYPE_id
           catch ptr null
-  br i1 undef, label %invoke.cont33, label %catch.fallthrough
+  br i1 %replace_undef_1, label %invoke.cont33, label %catch.fallthrough
 
 catch.fallthrough:
   %matches31 = icmp eq i32 undef, 0
   br i1 %matches31, label %invoke.cont41, label %finally.catchall
 
 if.then6:
   invoke void @objc_exception_throw()
           to label %invoke.cont7 unwind label %lpad

llvm/test/CodeGen/AArch64/br-undef-cond.ll

 ; RUN: llc < %s -verify-machineinstrs
 
 ; Make sure we don't end up with a CBNZ of an undef v-/phys-reg.
 
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "arm64-apple-ios"
 
 declare void @bar(ptr)
 
-define void @foo(ptr %m, i32 %off0) {
+define void @foo(ptr %m, i32 %off0, i1 %replace_undef_0, i1 %replace_undef_1) {
 .thread1653:
-  br i1 undef, label %0, label %.thread1880
+  br i1 %replace_undef_0, label %0, label %.thread1880
 
   %1 = icmp eq i32 undef, 0
   %.not = xor i1 %1, true
-  %brmerge = or i1 %.not, undef
+  %brmerge = or i1 %.not, %replace_undef_1
   br i1 %brmerge, label %.thread1880, label %.thread1705
 
 .thread1705:
   ret void
 
 .thread1880:
   %m1652.ph = phi ptr [ %m, %0 ], [ null, %.thread1653 ]
   call void @bar(ptr %m1652.ph)
   ret void
 }

llvm/test/CodeGen/AArch64/gep-nullptr.ll

 ; RUN: llc -O3 -aarch64-enable-gep-opt=true   < %s |FileCheck %s
 target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128"
 target triple = "aarch64--linux-gnu"
 
 %structA = type { i8, i8, i8, i8, i8, i8, [4 x i8], i8, i8, [2 x i32], [2 x %unionMV], [4 x [2 x %unionMV]], [4 x [2 x %unionMV]], [4 x i8], ptr, ptr, i32, ptr }
 %unionMV = type { i32 }
 
 ; Function Attrs: nounwind
-define void @test(ptr %mi_block) {
+define void @test(ptr %mi_block, i1 %replace_undef_0) {
 entry:
-  br i1 undef, label %for.body13.us, label %if.else
+  br i1 %replace_undef_0, label %for.body13.us, label %if.else
 
 ; Just make sure we don't get a compiler ICE due to dereferncing a nullptr.
 ; CHECK-LABEL: test
 for.body13.us:                                    ; preds = %entry
   %indvars.iv.next40 = or i64 0, 1
   %packed4.i.us.1 = getelementptr inbounds %structA, ptr %mi_block, i64 0, i32 11, i64 0, i64 %indvars.iv.next40, i32 0
   unreachable
 
 if.else:                                          ; preds = %entry
   ret void
 }
 

llvm/test/CodeGen/AArch64/inline-asm-blockaddress.ll

 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
 ; CHECK-LABEL: foo:
 ; CHECK: TEST .Ltmp0
-define void @foo() {
+define void @foo(i1 %replace_undef_0) {
 entry:
   br label %bar
 bar:
   call void asm sideeffect "#TEST $0", "i,~{dirflag},~{fpsr},~{flags}"(ptr blockaddress(@foo, %bar))
   ret void
 indirectgoto:
-  indirectbr ptr undef, [label %bar]
+  indirectbr ptr %replace_undef_0, [label %bar]
 }

llvm/test/CodeGen/AArch64/madd-combiner.ll

 ; CHECK-NEXT:    msub w0, w0, w1, w8
 ; CHECK-NEXT:    ret
   %1 = mul i32 %a, %b
   %2 = sub i32 4, %1
   ret i32 %2
 }
 
 ; bugpoint reduced test case. This only tests that we pass the MI verifier.
-define void @mul_add_imm2() {
+define void @mul_add_imm2(i1 %replace_undef_0) {
 ; CHECK-ISEL-LABEL: mul_add_imm2:
 ; CHECK-ISEL:       ; %bb.0: ; %entry
 ; CHECK-ISEL-NEXT:    mov w8, #1
 ; CHECK-ISEL-NEXT:  LBB2_1: ; %for.body8
 ; CHECK-ISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-ISEL-NEXT:    cbnz w8, LBB2_1
 ; CHECK-ISEL-NEXT:  ; %bb.2: ; %for.end20
 ; CHECK-ISEL-NEXT:    ret

 ; CHECK-FAST-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-FAST-NEXT:    cmp x8, x9
 ; CHECK-FAST-NEXT:    b.lt LBB2_1
 ; CHECK-FAST-NEXT:  ; %bb.2: ; %for.end20
 ; CHECK-FAST-NEXT:    ret
 entry:
   br label %for.body
 for.body:
-  br i1 undef, label %for.body, label %for.body8
+  br i1 %replace_undef_0, label %for.body, label %for.body8
 for.body8:
   %0 = mul i64 undef, -3
   %mul1971 = add i64 %0, -3
   %cmp7 = icmp slt i64 %mul1971, 1390451930000
   br i1 %cmp7, label %for.body8, label %for.end20
 for.end20:
   ret void
 }

llvm/test/CodeGen/AArch64/optimize-cond-branch.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -o - %s | FileCheck %s
 target triple = "arm64--"
 
 ; AArch64InstrInfo::optimizeCondBranch() optimizes the
 ; "x = and y, 256; cmp x, 0; br" from an "and; cbnz" to a tbnz instruction.
 ; It forgot to clear the a flag resulting in a MachineVerifier complaint.
 ;
 ; Writing a stable/simple test is tricky since most tbz instructions are already
 ; formed in SelectionDAG, optimizeCondBranch() only triggers if the and
 ; instruction is in a different block than the conditional jump.
 
-define void @func() uwtable {
+define void @func(i1 %replace_undef_0) uwtable {
 ; CHECK-LABEL: func:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    cbnz w8, .LBB0_3
 ; CHECK-NEXT:  // %bb.1: // %b1
 ; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    .cfi_offset w30, -16

 ; CHECK-NEXT:    .cfi_restore w30
 ; CHECK-NEXT:    cbnz w0, .LBB0_3
 ; CHECK-NEXT:  .LBB0_5: // %common.ret
 ; CHECK-NEXT:    ret
   %c0 = icmp sgt i64 0, 0
   br i1 %c0, label %b1, label %b6
 
 b1:
-  br i1 undef, label %b3, label %b2
+  br i1 %replace_undef_0, label %b3, label %b2
 
 b2:
   %v0 = tail call i32 @extfunc()
   br label %b5
 
 b3:
   %v1 = load i32, ptr undef, align 4
   %v2 = and i32 %v1, 256

llvm/test/CodeGen/AArch64/shrink-wrap.ll

 @g19 = external unnamed_addr constant [144 x i32], align 4
 @g20 = external unnamed_addr global [144 x [144 x i8]], align 1
 @g21 = external unnamed_addr global i32, align 4
 
 declare fastcc i32 @foo()
 
 declare fastcc i32 @bar()
 
-define internal fastcc i32 @func(i32 %alpha, i32 %beta) {
+define internal fastcc i32 @func(i32 %alpha, i32 %beta, i1 %replace_undef_0) {
 entry:
   %v1 = alloca [2 x [11 x i32]], align 4
   %v2 = alloca [11 x i32], align 16
   %v3 = alloca [11 x i32], align 16
   switch i32 undef, label %if.end.9 [
     i32 4, label %if.then.6
     i32 3, label %if.then.2
   ]
if.end.9:
   %idxprom69 = sext i32 %tmp4 to i64
   br label %for.body
 
 for.body:
   %v6 = phi i32 [ 0, %if.end.9 ], [ %v7, %for.inc ]
   %a.0983 = phi i32 [ 1, %if.end.9 ], [ %a.1, %for.inc ]
   %arrayidx = getelementptr inbounds [62 x i32], ptr @g17, i64 0, i64 undef
   %tmp5 = load i32, ptr %arrayidx, align 4
-  br i1 undef, label %for.inc, label %if.else.51
+  br i1 %replace_undef_0, label %for.inc, label %if.else.51
 
 if.else.51:
   %idxprom53 = sext i32 %tmp5 to i64
   %arrayidx54 = getelementptr inbounds [144 x i32], ptr @g3, i64 0, i64 %idxprom53
   %tmp6 = load i32, ptr %arrayidx54, align 4
   switch i32 %tmp6, label %for.inc [
     i32 1, label %block.bb
     i32 10, label %block.bb.159

llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll

 ; RUN: llc -mtriple=arm64--- -stop-after=finalize-isel -o - %s | FileCheck %s
 
 ; Check that we ignore the zeroext attribute on the return type of the tail
 ; call, since the return value is unused. This happens during CodeGenPrepare in
 ; dupRetToEnableTailCallOpts, which calls attributesPermitTailCall to check if
 ; the attributes of the caller and the callee match.
 
 declare zeroext i1 @zcallee()
-define void @zcaller() {
+define void @zcaller(i1 %replace_undef_0) {
 ; CHECK-LABEL: name: zcaller
 entry:
-  br i1 undef, label %calllabel, label %retlabel
+  br i1 %replace_undef_0, label %calllabel, label %retlabel
 calllabel:
 ; CHECK: bb.1.calllabel:
 ; CHECK-NOT: BL @zcallee
 ; CHECK-NEXT: TCRETURNdi @zcallee
   %unused_result = tail call zeroext i1 @zcallee()
   br label %retlabel
 retlabel:
   ret void
 }
 
 declare signext i1 @scallee()
-define void @scaller() {
+define void @scaller(i1 %replace_undef_0) {
 ; CHECK-LABEL: name: scaller
 entry:
-  br i1 undef, label %calllabel, label %retlabel
+  br i1 %replace_undef_0, label %calllabel, label %retlabel
 calllabel:
 ; CHECK: bb.1.calllabel:
 ; CHECK-NOT: BL @scallee
 ; CHECK-NEXT: TCRETURNdi @scallee
   %unused_result = tail call signext i1 @scallee()
   br label %retlabel
 retlabel:
   ret void
 }

llvm/test/CodeGen/AArch64/tailcall-ssp-split-debug.ll

 ; RUN: llc -mtriple=arm64-apple-ios %s -o - | FileCheck %s
 
-define swifttailcc void @foo(ptr %call) ssp {
+define swifttailcc void @foo(ptr %call, i1 %replace_undef_0) ssp {
 ; CHECK-LABEL: foo:
   %var = alloca [28 x i8], align 16
-  br i1 undef, label %if.then, label %if.end
+  br i1 %replace_undef_0, label %if.then, label %if.end
 
 if.then:
   ret void
 
 if.end:
   ; CHECK: mov x[[NULL:[0-9]+]], xzr
   ; CHECK: ldr [[FPTR:x[0-9]+]], [x[[NULL]]]
   ; CHECK: br [[FPTR]]