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Differential D144360

[WebAssembly] Add more combine pattern for vector shift
ClosedPublic

Authored by junparser on Feb 19 2023, 10:07 PM.

Details

Reviewers
tlively
aheejin
dschuff
Commits
rGe9d7f96a11ba: [WebAssembly] Add more combine pattern for vector shift
Summary

After change with D144169, the codegen generates redundant instructions
like and and wrap. This fixes it.

Diff Detail

Event Timeline

junparser created this revision.Feb 19 2023, 10:07 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 19 2023, 10:07 PM
Herald added subscribers: pmatos, asb, ecnelises and 4 others. · View Herald Transcript
junparser requested review of this revision.Feb 19 2023, 10:07 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 19 2023, 10:07 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B214671: Diff 498722.Feb 19 2023, 10:59 PM
tlively accepted this revision.Feb 21 2023, 7:57 AM

Great, thank you!

This revision is now accepted and ready to land.Feb 21 2023, 7:57 AM
This revision was landed with ongoing or failed builds.Feb 21 2023, 5:59 PM
Closed by commit rGe9d7f96a11ba: [WebAssembly] Add more combine pattern for vector shift (authored by junparser). · Explain Why
This revision was automatically updated to reflect the committed changes.
junparser added a commit: rGe9d7f96a11ba: [WebAssembly] Add more combine pattern for vector shift.

Revision Contents

PathSize
llvm/
lib/
Target/
WebAssembly/
6 lines
test/
CodeGen/
WebAssembly/
49 lines

Diff 499336

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

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def : Pat<(wasm_shl (v4i32 V128:$lhs), (and I32:$rhs, 31)), def : Pat<(wasm_shl (v4i32 V128:$lhs), (and I32:$rhs, 31)),
(SHL_I32x4 V128:$lhs, I32:$rhs)>; (SHL_I32x4 V128:$lhs, I32:$rhs)>;
def : Pat<(wasm_shr_s (v4i32 V128:$lhs), (and I32:$rhs, 31)), def : Pat<(wasm_shr_s (v4i32 V128:$lhs), (and I32:$rhs, 31)),
(SHR_S_I32x4 V128:$lhs, I32:$rhs)>; (SHR_S_I32x4 V128:$lhs, I32:$rhs)>;
def : Pat<(wasm_shr_u (v4i32 V128:$lhs), (and I32:$rhs, 31)), def : Pat<(wasm_shr_u (v4i32 V128:$lhs), (and I32:$rhs, 31)),
(SHR_U_I32x4 V128:$lhs, I32:$rhs)>; (SHR_U_I32x4 V128:$lhs, I32:$rhs)>;
def : Pat<(wasm_shl (v2i64 V128:$lhs), (and I32:$rhs, 63)),
(SHL_I64x2 V128:$lhs, I32:$rhs)>;
def : Pat<(wasm_shr_s (v2i64 V128:$lhs), (and I32:$rhs, 63)),
(SHR_S_I64x2 V128:$lhs, I32:$rhs)>;
def : Pat<(wasm_shr_u (v2i64 V128:$lhs), (and I32:$rhs, 63)),
(SHR_U_I64x2 V128:$lhs, I32:$rhs)>;
def : Pat<(wasm_shl (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))), def : Pat<(wasm_shl (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))),
(SHL_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>; (SHL_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>;
def : Pat<(wasm_shr_s (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))), def : Pat<(wasm_shr_s (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))),
(SHR_S_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>; (SHR_S_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>;
def : Pat<(wasm_shr_u (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))), def : Pat<(wasm_shr_u (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))),
(SHR_U_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>; (SHR_U_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 494 Lines • Show Last 20 Lines

llvm/test/CodeGen/WebAssembly/masked-shifts.ll

Show First 20 Lines • Show All 496 Lines • ▼ Show 20 Lines
; CHECK-NEXT: i64x2.shr_u ; CHECK-NEXT: i64x2.shr_u
; CHECK-NEXT: # fallthrough-return ; CHECK-NEXT: # fallthrough-return
%t = insertelement <2 x i64> undef, i64 %x, i32 0 %t = insertelement <2 x i64> undef, i64 %x, i32 0
%s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%m = and <2 x i64> %s, <i64 63, i64 63> %m = and <2 x i64> %s, <i64 63, i64 63>
%a = lshr <2 x i64> %v, %m %a = lshr <2 x i64> %v, %m
ret <2 x i64> %a ret <2 x i64> %a
} }
define <2 x i64> @shl_v2i64_i32(<2 x i64> %v, i32 %x) {
; CHECK-LABEL: shl_v2i64_i32:
; CHECK: .functype shl_v2i64_i32 (v128, i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
; CHECK-NEXT: i64x2.shl
; CHECK-NEXT: # fallthrough-return
%z = and i32 %x, 63
%m = zext i32 %z to i64
%t = insertelement <2 x i64> undef, i64 %m, i32 0
%s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%a = shl <2 x i64> %v, %s
ret <2 x i64> %a
}
define <2 x i64> @ashr_v2i64_i32(<2 x i64> %v, i32 %x) {
; CHECK-LABEL: ashr_v2i64_i32:
; CHECK: .functype ashr_v2i64_i32 (v128, i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
; CHECK-NEXT: i64x2.shr_s
; CHECK-NEXT: # fallthrough-return
%z = and i32 %x, 63
%m = zext i32 %z to i64
%t = insertelement <2 x i64> undef, i64 %m, i32 0
%s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%a = ashr <2 x i64> %v, %s
ret <2 x i64> %a
}
define <2 x i64> @lshr_v2i64_i32(<2 x i64> %v, i32 %x) {
; CHECK-LABEL: lshr_v2i64_i32:
; CHECK: .functype lshr_v2i64_i32 (v128, i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
; CHECK-NEXT: i64x2.shr_u
; CHECK-NEXT: # fallthrough-return
%z = and i32 %x, 63
%m = zext i32 %z to i64
%t = insertelement <2 x i64> undef, i64 %m, i32 0
%s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%a = lshr <2 x i64> %v, %s
ret <2 x i64> %a
}