[BOLT][NFC] Return struct from evaluateX86MemoryOperand

[Amir]

Summary

Simplify MCPlusBuilder::evaluateX86MemoryOperand: make it return a struct
with memory operand analysis struct X86MemOperand.

[rafauler]

Thanks!

bolt/include/bolt/Core/MCPlusBuilder.h

public:
 
   /// Return true if a pair of instructions represented by \p Insts
   /// could be fused into a single uop.
   virtual bool isMacroOpFusionPair(ArrayRef<MCInst> Insts) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
+  struct X86MemOperand {
+    unsigned BaseRegNum;
+    int64_t ScaleImm;
+    unsigned IndexRegNum;
+    int64_t DispImm;
+    unsigned SegRegNum;
+    const MCExpr *DispExpr = nullptr;
+  };
+
   /// Given an instruction with (compound) memory operand, evaluate and return
   /// the corresponding values. Note that the operand could be in any position,
   /// but there is an assumption there's only one compound memory operand.
   /// Return true upon success, return false if the instruction does not have
   /// a memory operand.
   ///
   /// Since a Displacement field could be either an immediate or an expression,
   /// the function sets either \p DispImm or \p DispExpr value.
-  virtual bool
-  evaluateX86MemoryOperand(const MCInst &Inst, unsigned *BaseRegNum,
-                           int64_t *ScaleImm, unsigned *IndexRegNum,
-                           int64_t *DispImm, unsigned *SegmentRegNum,
-                           const MCExpr **DispExpr = nullptr) const {
+  virtual std::optional<X86MemOperand>
+  evaluateX86MemoryOperand(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
-    return false;
+    return std::nullopt;
   }
 
   /// Given an instruction with memory addressing attempt to statically compute
   /// the address being accessed. Return true on success, and the address in
   /// \p Target.
   ///
   /// For RIP-relative addressing the caller is required to pass instruction
   /// \p Address and \p Size.

bolt/include/bolt/Passes/RetpolineInsertion.h

 public:
   IndirectBranchInfo(MCInst &Inst, MCPlusBuilder &MIB);
   bool isMem() const { return IsMem; }
   bool isReg() const { return !IsMem; }
   bool isCall() const { return IsCall; }
   bool isJump() const { return !IsCall; }
   bool isTailCall() const { return IsTailCall; }
 
-  struct MemOpInfo {
-    unsigned BaseRegNum;
-    int64_t ScaleValue;
-    unsigned IndexRegNum;
-    int64_t DispValue;
-    unsigned SegRegNum;
-    const MCExpr *DispExpr{nullptr};
-  };
+  using MemOpInfo = MCPlusBuilder::X86MemOperand;
 
   union {
     // Register branch information
     MCPhysReg BranchReg;
 
     // Memory branch information
     MemOpInfo Memory;
   };

bolt/lib/Passes/RetpolineInsertion.cpp

if (R11Available) {
       BB2.addInstruction(StoreToStack);
     } else {
       MCInst PushR11;
       MIB.createPushRegister(PushR11, MIB.getX86R11(), 8);
       BB2.addInstruction(PushR11);
 
       MCInst LoadCalleeAddrs;
       const IndirectBranchInfo::MemOpInfo &MemRef = BrInfo.Memory;
-      MIB.createLoad(LoadCalleeAddrs, MemRef.BaseRegNum, MemRef.ScaleValue,
-                     MemRef.IndexRegNum, MemRef.DispValue, MemRef.DispExpr,
+      MIB.createLoad(LoadCalleeAddrs, MemRef.BaseRegNum, MemRef.ScaleImm,
+                     MemRef.IndexRegNum, MemRef.DispImm, MemRef.DispExpr,
                      MemRef.SegRegNum, MIB.getX86R11(), 8);
 
       BB2.addInstruction(LoadCalleeAddrs);
 
       MCInst StoreToStack;
       MIB.createSaveToStack(StoreToStack, MIB.getStackPointer(), 8,
                             MIB.getX86R11(), 8);
       BB2.addInstruction(StoreToStack);
if (MemRef.DispExpr) {
     MemRef.DispExpr->print(Ostream, BC.AsmInfo.get());
     Ostream.flush();
   }
 
   Tag += MemRef.BaseRegNum != BC.MIB->getNoRegister()
              ? "r" + to_string(MemRef.BaseRegNum)
              : "";
 
-  Tag +=
-      MemRef.DispExpr ? "+" + DispExprStr : "+" + to_string(MemRef.DispValue);
+  Tag += MemRef.DispExpr ? "+" + DispExprStr : "+" + to_string(MemRef.DispImm);
 
   Tag += MemRef.IndexRegNum != BC.MIB->getNoRegister()
-             ? "+" + to_string(MemRef.ScaleValue) + "*" +
+             ? "+" + to_string(MemRef.ScaleImm) + "*" +
                    to_string(MemRef.IndexRegNum)
              : "";
 
   Tag += MemRef.SegRegNum != BC.MIB->getNoRegister()
              ? "_seg_" + to_string(MemRef.SegRegNum)
              : "";
 
   return Tag;
void createBranchReplacement(BinaryContext &BC,
                              bool R11Available,
                              InstructionListType &Replacement,
                              const MCSymbol *RetpolineSymbol) {
   auto &MIB = *BC.MIB;
   // Load the branch address in r11 if available
   if (BrInfo.isMem() && R11Available) {
     const IndirectBranchInfo::MemOpInfo &MemRef = BrInfo.Memory;
     MCInst LoadCalleeAddrs;
-    MIB.createLoad(LoadCalleeAddrs, MemRef.BaseRegNum, MemRef.ScaleValue,
-                   MemRef.IndexRegNum, MemRef.DispValue, MemRef.DispExpr,
+    MIB.createLoad(LoadCalleeAddrs, MemRef.BaseRegNum, MemRef.ScaleImm,
+                   MemRef.IndexRegNum, MemRef.DispImm, MemRef.DispExpr,
                    MemRef.SegRegNum, MIB.getX86R11(), 8);
     Replacement.push_back(LoadCalleeAddrs);
   }
 
   // Call the retpoline
   MCInst RetpolineCall;
   MIB.createDirectCall(RetpolineCall, RetpolineSymbol, BC.Ctx.get(),
                        BrInfo.isJump() || BrInfo.isTailCall());
 
   Replacement.push_back(RetpolineCall);
 }
 
 IndirectBranchInfo::IndirectBranchInfo(MCInst &Inst, MCPlusBuilder &MIB) {
   IsCall = MIB.isCall(Inst);
   IsTailCall = MIB.isTailCall(Inst);
 
   if (MIB.isBranchOnMem(Inst)) {
     IsMem = true;
-    if (!MIB.evaluateX86MemoryOperand(Inst, &Memory.BaseRegNum,
-                                      &Memory.ScaleValue,
-                                      &Memory.IndexRegNum, &Memory.DispValue,
-                                      &Memory.SegRegNum, &Memory.DispExpr))
+    std::optional<MCPlusBuilder::X86MemOperand> MO =
+        MIB.evaluateX86MemoryOperand(Inst);
+    if (!MO)
       llvm_unreachable("not expected");
+    Memory = MO.value();
   } else if (MIB.isBranchOnReg(Inst)) {
     assert(MCPlus::getNumPrimeOperands(Inst) == 1 && "expect 1 operand");
     BranchReg = Inst.getOperand(0).getReg();
   } else {
     llvm_unreachable("unexpected instruction");
   }
 }
 
for (BinaryBasicBlock &BB : Function) {
         }
 
         // If the instruction addressing pattern uses rsp and the retpoline
         // loads the callee address then displacement needs to be updated
         if (BrInfo.isMem() && !R11Available) {
           IndirectBranchInfo::MemOpInfo &MemRef = BrInfo.Memory;
           int Addend = (BrInfo.isJump() || BrInfo.isTailCall()) ? 8 : 16;
           if (MemRef.BaseRegNum == MIB.getStackPointer())
-            MemRef.DispValue += Addend;
+            MemRef.DispImm += Addend;
           if (MemRef.IndexRegNum == MIB.getStackPointer())
-            MemRef.DispValue += Addend * MemRef.ScaleValue;
+            MemRef.DispImm += Addend * MemRef.ScaleImm;
         }
 
         TargetRetpoline = getOrCreateRetpoline(BC, BrInfo, R11Available);
 
         createBranchReplacement(BC, BrInfo, R11Available, Replacement,
                                 TargetRetpoline->getSymbol());
 
         It = BB.replaceInstruction(It, Replacement.begin(), Replacement.end());

bolt/lib/Target/X86/X86MCPlusBuilder.cpp

bool isMacroOpFusionPair(ArrayRef<MCInst> Insts) const override {
     X86::CondCode CC = static_cast<X86::CondCode>(getCondCode(SecondInst));
     X86::SecondMacroFusionInstKind BranchKind =
         X86::classifySecondCondCodeInMacroFusion(CC);
     if (BranchKind == X86::SecondMacroFusionInstKind::Invalid)
       return false;
     return X86::isMacroFused(CmpKind, BranchKind);
   }
 
-  bool
-  evaluateX86MemoryOperand(const MCInst &Inst, unsigned *BaseRegNum,
-                           int64_t *ScaleImm, unsigned *IndexRegNum,
-                           int64_t *DispImm, unsigned *SegmentRegNum,
-                           const MCExpr **DispExpr = nullptr) const override {
-    assert(BaseRegNum && ScaleImm && IndexRegNum && SegmentRegNum &&
-           "one of the input pointers is null");
+  std::optional<X86MemOperand>
+  evaluateX86MemoryOperand(const MCInst &Inst) const override {
     int MemOpNo = getMemoryOperandNo(Inst);
     if (MemOpNo < 0)
-      return false;
+      return std::nullopt;
     unsigned MemOpOffset = static_cast<unsigned>(MemOpNo);
 
     if (MemOpOffset + X86::AddrSegmentReg >= MCPlus::getNumPrimeOperands(Inst))
-      return false;
+      return std::nullopt;
 
     const MCOperand &Base = Inst.getOperand(MemOpOffset + X86::AddrBaseReg);
     const MCOperand &Scale = Inst.getOperand(MemOpOffset + X86::AddrScaleAmt);
     const MCOperand &Index = Inst.getOperand(MemOpOffset + X86::AddrIndexReg);
     const MCOperand &Disp = Inst.getOperand(MemOpOffset + X86::AddrDisp);
     const MCOperand &Segment =
         Inst.getOperand(MemOpOffset + X86::AddrSegmentReg);
 
     // Make sure it is a well-formed memory operand.
     if (!Base.isReg() || !Scale.isImm() || !Index.isReg() ||
         (!Disp.isImm() && !Disp.isExpr()) || !Segment.isReg())
-      return false;
+      return std::nullopt;
 
-    *BaseRegNum = Base.getReg();
-    *ScaleImm = Scale.getImm();
-    *IndexRegNum = Index.getReg();
-    if (Disp.isImm()) {
-      assert(DispImm && "DispImm needs to be set");
-      *DispImm = Disp.getImm();
-      if (DispExpr)
-        *DispExpr = nullptr;
-    } else {
-      assert(DispExpr && "DispExpr needs to be set");
-      *DispExpr = Disp.getExpr();
-      if (DispImm)
-        *DispImm = 0;
-    }
-    *SegmentRegNum = Segment.getReg();
-    return true;
+    X86MemOperand MO;
+    MO.BaseRegNum = Base.getReg();
+    MO.ScaleImm = Scale.getImm();
+    MO.IndexRegNum = Index.getReg();
+    MO.DispImm = Disp.isImm() ? Disp.getImm() : 0;
+    MO.DispExpr = Disp.isExpr() ? Disp.getExpr() : nullptr;
+    MO.SegRegNum = Segment.getReg();
+    return MO;
   }
 
   bool evaluateMemOperandTarget(const MCInst &Inst, uint64_t &Target,
                                 uint64_t Address,
                                 uint64_t Size) const override {
-    unsigned      BaseRegNum;
-    int64_t       ScaleValue;
-    unsigned      IndexRegNum;
-    int64_t       DispValue;
-    unsigned      SegRegNum;
-    const MCExpr *DispExpr = nullptr;
-    if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, &IndexRegNum,
-                                  &DispValue, &SegRegNum, &DispExpr))
+    std::optional<X86MemOperand> MO = evaluateX86MemoryOperand(Inst);
+    if (!MO)
       return false;
 
     // Make sure it's a well-formed addressing we can statically evaluate.
-    if ((BaseRegNum != X86::RIP && BaseRegNum != X86::NoRegister) ||
-        IndexRegNum != X86::NoRegister || SegRegNum != X86::NoRegister ||
-        DispExpr)
+    if ((MO->BaseRegNum != X86::RIP && MO->BaseRegNum != X86::NoRegister) ||
+        MO->IndexRegNum != X86::NoRegister ||
+        MO->SegRegNum != X86::NoRegister || MO->DispExpr)
       return false;
 
-    Target = DispValue;
-    if (BaseRegNum == X86::RIP) {
+    Target = MO->DispImm;
+    if (MO->BaseRegNum == X86::RIP) {
       assert(Size != 0 && "instruction size required in order to statically "
                           "evaluate RIP-relative address");
       Target += Address + Size;
     }
     return true;
   }
 
   MCInst::iterator getMemOperandDisp(MCInst &Inst) const override {
bool isStackAccess(const MCInst &Inst, bool &IsLoad, bool &IsStore,
     case X86::MOV16mr: I = {2, false, true, true, true};  break;
     case X86::MOV32mr: I = {4, false, true, true, true};  break;
     case X86::MOV64mr: I = {8, false, true, true, true};  break;
     case X86::MOV8mi: I = {1, false, true, false, true}; break;
     case X86::MOV16mi: I = {2, false, true, false, true}; break;
     case X86::MOV32mi: I = {4, false, true, false, true}; break;
     } // end switch (Inst.getOpcode())
 
-    unsigned BaseRegNum;
-    int64_t ScaleValue;
-    unsigned IndexRegNum;
-    int64_t DispValue;
-    unsigned SegRegNum;
-    const MCExpr *DispExpr;
-    if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, &IndexRegNum,
-                                  &DispValue, &SegRegNum, &DispExpr)) {
+    std::optional<X86MemOperand> MO = evaluateX86MemoryOperand(Inst);
+    if (!MO) {
       LLVM_DEBUG(dbgs() << "Evaluate failed on ");
       LLVM_DEBUG(Inst.dump());
       return false;
     }
 
     // Make sure it's a stack access
-    if (BaseRegNum != X86::RBP && BaseRegNum != X86::RSP)
+    if (MO->BaseRegNum != X86::RBP && MO->BaseRegNum != X86::RSP)
       return false;
 
     IsLoad = I.IsLoad;
     IsStore = I.IsStore;
     IsStoreFromReg = I.StoreFromReg;
     Size = I.DataSize;
     IsSimple = I.Simple;
-    StackPtrReg = BaseRegNum;
-    StackOffset = DispValue;
-    IsIndexed = IndexRegNum != X86::NoRegister || SegRegNum != X86::NoRegister;
+    StackPtrReg = MO->BaseRegNum;
+    StackOffset = MO->DispImm;
+    IsIndexed =
+        MO->IndexRegNum != X86::NoRegister || MO->SegRegNum != X86::NoRegister;
 
     if (!I.Simple)
       return true;
 
     // Retrieve related register in simple MOV from/to stack operations.
     unsigned MemOpOffset = static_cast<unsigned>(MemOpNo);
     if (I.IsLoad) {
       MCOperand RegOpnd = Inst.getOperand(0);
void changeToPushOrPop(MCInst &Inst) const override {
     case X86::MOV64rm: I = {8, true, false}; break;
     case X86::MOV16mr: I = {2, false, true};  break;
     case X86::MOV32mr: I = {4, false, true};  break;
     case X86::MOV64mr: I = {8, false, true};  break;
     case X86::MOV16mi: I = {2, false, false}; break;
     case X86::MOV32mi: I = {4, false, false}; break;
     } // end switch (Inst.getOpcode())
 
-    unsigned BaseRegNum;
-    int64_t ScaleValue;
-    unsigned IndexRegNum;
-    int64_t DispValue;
-    unsigned SegRegNum;
-    const MCExpr *DispExpr;
-    if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, &IndexRegNum,
-                                  &DispValue, &SegRegNum, &DispExpr)) {
+    std::optional<X86MemOperand> MO = evaluateX86MemoryOperand(Inst);
+    if (!MO) {
       llvm_unreachable("Evaluate failed");
       return;
     }
     // Make sure it's a stack access
-    if (BaseRegNum != X86::RBP && BaseRegNum != X86::RSP) {
+    if (MO->BaseRegNum != X86::RBP && MO->BaseRegNum != X86::RSP) {
       llvm_unreachable("Not a stack access");
       return;
     }
 
     unsigned MemOpOffset = getMemoryOperandNo(Inst);
     unsigned NewOpcode = 0;
     if (I.IsLoad) {
       switch (I.DataSize) {
case X86::ADD64i32:
         return false;
       if (ErrorOr<int64_t> InputVal = getOperandVal(X86::RAX))
         Output = *InputVal + Inst.getOperand(0).getImm();
       else
         return false;
       break;
 
     case X86::LEA64r: {
-      unsigned BaseRegNum;
-      int64_t ScaleValue;
-      unsigned IndexRegNum;
-      int64_t DispValue;
-      unsigned SegRegNum;
-      const MCExpr *DispExpr = nullptr;
-      if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue,
-                                    &IndexRegNum, &DispValue, &SegRegNum,
-                                    &DispExpr))
+      std::optional<X86MemOperand> MO = evaluateX86MemoryOperand(Inst);
+      if (!MO)
         return false;
 
-      if (BaseRegNum == X86::NoRegister || IndexRegNum != X86::NoRegister ||
-          SegRegNum != X86::NoRegister || DispExpr)
+      if (MO->BaseRegNum == X86::NoRegister ||
+          MO->IndexRegNum != X86::NoRegister ||
+          MO->SegRegNum != X86::NoRegister || MO->DispExpr)
         return false;
 
-      if (ErrorOr<int64_t> InputVal = getOperandVal(BaseRegNum))
-        Output = *InputVal + DispValue;
+      if (ErrorOr<int64_t> InputVal = getOperandVal(MO->BaseRegNum))
+        Output = *InputVal + MO->DispImm;
       else
         return false;
 
       break;
     }
     }
     return true;
   }
while (++II != IE) {
         if (MovDestReg != R2)
           std::swap(R1, R2);
         if (MovDestReg != R2) {
           LLVM_DEBUG(dbgs() << "MOV instruction expected to set %r2\n");
           break;
         }
 
         // Verify operands for MOV.
-        unsigned  BaseRegNum;
-        int64_t   ScaleValue;
-        unsigned  IndexRegNum;
-        int64_t   DispValue;
-        unsigned  SegRegNum;
-        if (!evaluateX86MemoryOperand(Instr, &BaseRegNum, &ScaleValue,
-                                      &IndexRegNum, &DispValue, &SegRegNum))
-          break;
-        if (BaseRegNum != R1 || ScaleValue != 4 ||
-            IndexRegNum == X86::NoRegister || DispValue != 0 ||
-            SegRegNum != X86::NoRegister)
+        std::optional<X86MemOperand> MO = evaluateX86MemoryOperand(Instr);
+        if (!MO)
+          break;
+        if (MO->BaseRegNum != R1 || MO->ScaleImm != 4 ||
+            MO->IndexRegNum == X86::NoRegister || MO->DispImm != 0 ||
+            MO->SegRegNum != X86::NoRegister)
           break;
         MovInstr = &Instr;
       } else {
         if (!InstrDesc.hasDefOfPhysReg(Instr, R1, *RegInfo))
           continue;
         if (!isLEA64r(Instr)) {
           LLVM_DEBUG(dbgs() << "LEA instruction expected\n");
           break;
         }
         if (Instr.getOperand(0).getReg() != R1) {
           LLVM_DEBUG(dbgs() << "LEA instruction expected to set %r1\n");
           break;
         }
 
         // Verify operands for LEA.
-        unsigned      BaseRegNum;
-        int64_t       ScaleValue;
-        unsigned      IndexRegNum;
-        const MCExpr *DispExpr = nullptr;
-        int64_t       DispValue;
-        unsigned      SegRegNum;
-        if (!evaluateX86MemoryOperand(Instr, &BaseRegNum, &ScaleValue,
-                                      &IndexRegNum, &DispValue, &SegRegNum,
-                                      &DispExpr))
-          break;
-        if (BaseRegNum != RegInfo->getProgramCounter() ||
-            IndexRegNum != X86::NoRegister || SegRegNum != X86::NoRegister ||
-            DispExpr == nullptr)
+        std::optional<X86MemOperand> MO = evaluateX86MemoryOperand(Instr);
+        if (!MO)
+          break;
+        if (MO->BaseRegNum != RegInfo->getProgramCounter() ||
+            MO->IndexRegNum != X86::NoRegister ||
+            MO->SegRegNum != X86::NoRegister || MO->DispExpr == nullptr)
           break;
         MemLocInstr = &Instr;
         break;
       }
     }
 
     if (!MemLocInstr)
       return std::make_pair(IndirectBranchType::UNKNOWN, nullptr);
if (MCPlus::getNumPrimeOperands(Instruction) == 1) {
       }
     } else {
       MemLocInstr = &Instruction;
     }
 
     const MCRegister RIPRegister = RegInfo->getProgramCounter();
 
     // Analyze the memory location.
-    unsigned BaseRegNum, IndexRegNum, SegRegNum;
-    int64_t ScaleValue, DispValue;
-    const MCExpr *DispExpr;
-
-    if (!evaluateX86MemoryOperand(*MemLocInstr, &BaseRegNum, &ScaleValue,
-                                  &IndexRegNum, &DispValue, &SegRegNum,
-                                  &DispExpr))
+    std::optional<X86MemOperand> MO = evaluateX86MemoryOperand(*MemLocInstr);
+    if (!MO)
       return IndirectBranchType::UNKNOWN;
 
-    BaseRegNumOut = BaseRegNum;
-    IndexRegNumOut = IndexRegNum;
-    DispValueOut = DispValue;
-    DispExprOut = DispExpr;
+    BaseRegNumOut = MO->BaseRegNum;
+    IndexRegNumOut = MO->IndexRegNum;
+    DispValueOut = MO->DispImm;
+    DispExprOut = MO->DispExpr;
 
-    if ((BaseRegNum != X86::NoRegister && BaseRegNum != RIPRegister) ||
-        SegRegNum != X86::NoRegister)
+    if ((MO->BaseRegNum != X86::NoRegister && MO->BaseRegNum != RIPRegister) ||
+        MO->SegRegNum != X86::NoRegister)
       return IndirectBranchType::UNKNOWN;
 
     if (MemLocInstr == &Instruction &&
-        (!ScaleValue || IndexRegNum == X86::NoRegister)) {
+        (!MO->ScaleImm || MO->IndexRegNum == X86::NoRegister)) {
       MemLocInstrOut = MemLocInstr;
       return IndirectBranchType::POSSIBLE_FIXED_BRANCH;
     }
 
     if (Type == IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE &&
-        (ScaleValue != 1 || BaseRegNum != RIPRegister))
+        (MO->ScaleImm != 1 || MO->BaseRegNum != RIPRegister))
       return IndirectBranchType::UNKNOWN;
 
     if (Type != IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE &&
-        ScaleValue != PtrSize)
+        MO->ScaleImm != PtrSize)
       return IndirectBranchType::UNKNOWN;
 
     MemLocInstrOut = MemLocInstr;
 
     return Type;
   }
 
   /// Analyze a callsite to see if it could be a virtual method call.  This only
bool analyzeVirtualMethodCall(InstructionIterator ForwardBegin,
     MethodOffset = 0;
 
     std::reverse_iterator<InstructionIterator> Itr(ForwardEnd);
     std::reverse_iterator<InstructionIterator> End(ForwardBegin);
 
     MCInst &CallInst = *Itr++;
     assert(isIndirectBranch(CallInst) || isCall(CallInst));
 
-    unsigned BaseReg, IndexReg, SegmentReg;
-    int64_t Scale, Disp;
-    const MCExpr *DispExpr;
-
     // The call can just be jmp offset(reg)
-    if (evaluateX86MemoryOperand(CallInst, &BaseReg, &Scale, &IndexReg, &Disp,
-                                 &SegmentReg, &DispExpr)) {
-      if (!DispExpr && BaseReg != X86::RIP && BaseReg != X86::RBP &&
-          BaseReg != X86::NoRegister) {
-        MethodRegNum = BaseReg;
-        if (Scale == 1 && IndexReg == X86::NoRegister &&
-            SegmentReg == X86::NoRegister) {
+    if (std::optional<X86MemOperand> MO = evaluateX86MemoryOperand(CallInst)) {
+      if (!MO->DispExpr && MO->BaseRegNum != X86::RIP &&
+          MO->BaseRegNum != X86::RBP && MO->BaseRegNum != X86::NoRegister) {
+        MethodRegNum = MO->BaseRegNum;
+        if (MO->ScaleImm == 1 && MO->IndexRegNum == X86::NoRegister &&
+            MO->SegRegNum == X86::NoRegister) {
           VtableRegNum = MethodRegNum;
-          MethodOffset = Disp;
+          MethodOffset = MO->DispImm;
           MethodFetchInsns.push_back(&CallInst);
           return true;
         }
       }
       return false;
     }
     if (CallInst.getOperand(0).isReg())
       MethodRegNum = CallInst.getOperand(0).getReg();
     else
       return false;
 
     if (MethodRegNum == X86::RIP || MethodRegNum == X86::RBP) {
       VtableRegNum = X86::NoRegister;
       MethodRegNum = X86::NoRegister;
       return false;
     }
 
     // find load from vtable, this may or may not include the method offset
     while (Itr != End) {
       MCInst &CurInst = *Itr++;
       const MCInstrDesc &Desc = Info->get(CurInst.getOpcode());
       if (Desc.hasDefOfPhysReg(CurInst, MethodRegNum, *RegInfo)) {
-        if (isLoad(CurInst) &&
-            evaluateX86MemoryOperand(CurInst, &BaseReg, &Scale, &IndexReg,
-                                     &Disp, &SegmentReg, &DispExpr)) {
-          if (!DispExpr && Scale == 1 && BaseReg != X86::RIP &&
-              BaseReg != X86::RBP && BaseReg != X86::NoRegister &&
-              IndexReg == X86::NoRegister && SegmentReg == X86::NoRegister &&
-              BaseReg != X86::RIP) {
-            VtableRegNum = BaseReg;
-            MethodOffset = Disp;
+        if (!isLoad(CurInst))
+          return false;
+        if (std::optional<X86MemOperand> MO =
+                evaluateX86MemoryOperand(CurInst)) {
+          if (!MO->DispExpr && MO->ScaleImm == 1 &&
+              MO->BaseRegNum != X86::RIP && MO->BaseRegNum != X86::RBP &&
+              MO->BaseRegNum != X86::NoRegister &&
+              MO->IndexRegNum == X86::NoRegister &&
+              MO->SegRegNum == X86::NoRegister && MO->BaseRegNum != X86::RIP) {
+            VtableRegNum = MO->BaseRegNum;
+            MethodOffset = MO->DispImm;
             MethodFetchInsns.push_back(&CurInst);
             if (MethodOffset != 0)
               return true;
             break;
           }
         }
         return false;
       }