[PowerPC] Fix the implicit casting for the emulated intrinsics

[maryammo]

Summary

This patch is to fix some implicit castings for emulated intrinsics
so that there are no lax-vector-conversions errors and warnings.

[nemanjai]

LGTM as long as the naming nit is addressed.

clang/lib/Headers/ppc_wrappers/emmintrin.h

58

The name __v2f seems strange since __vector float is a vector of 4 float values. Should this be __v4f?

[amyk]

clang/lib/Headers/ppc_wrappers/emmintrin.h

58

nit: Could we also put this to where we put the double?

clang/lib/Headers/ppc_wrappers/smmintrin.h

310

Potentially silly question, but is it intentionally for that mask for be signed?

[maryammo]

clang/lib/Headers/ppc_wrappers/smmintrin.h

310

In altivec header, vec_unpackh 's parameter is either signed char or bool char, so we need explicit casting since __charmask is unsigned char.

[maryammo]

Address review comments

clang/lib/Headers/ppc_wrappers/emmintrin.h

 
 #include <altivec.h>
 
 /* We need definitions from the SSE header files.  */
 #include <xmmintrin.h>
 
 /* SSE2 */
 typedef __vector double __v2df;
+typedef __vector float __v4f;
 typedef __vector long long __v2di;
 typedef __vector unsigned long long __v2du;
 typedef __vector int __v4si;
 typedef __vector unsigned int __v4su;
 typedef __vector short __v8hi;
 typedef __vector unsigned short __v8hu;
 typedef __vector signed char __v16qi;
 typedef __vector unsigned char __v16qu;
 
 /* The Intel API is flexible enough that we must allow aliasing with other
    vector types, and their scalar components.  */
 typedef long long __m128i __attribute__((__vector_size__(16), __may_alias__));
 typedef double __m128d __attribute__((__vector_size__(16), __may_alias__));
 
 /* Unaligned version of the same types.  */
 typedef long long __m128i_u
     __attribute__((__vector_size__(16), __may_alias__, __aligned__(1)));

 }
 
 #ifdef _ARCH_PWR8
 extern __inline __m128d
     __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     _mm_cvtpi32_pd(__m64 __A) {
   __v4si __temp;
   __v2di __tmp2;
-  __v2df __result;
+  __v4f __result;
 
   __temp = (__v4si)vec_splats(__A);
   __tmp2 = (__v2di)vec_unpackl(__temp);
   __result = vec_ctf((__vector signed long long)__tmp2, 0);
   return (__m128d)__result;
 }
 #endif
 

clang/lib/Headers/ppc_wrappers/smmintrin.h

extern __inline int
     _mm_extract_ps(__m128 __X, const int __N) {
   return ((__v4si)__X)[__N & 3];
 }
 
 #ifdef _ARCH_PWR8
 extern __inline __m128i
     __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     _mm_blend_epi16(__m128i __A, __m128i __B, const int __imm8) {
-  __v16qi __charmask = vec_splats((signed char)__imm8);
+  __v16qu __charmask = vec_splats((unsigned char)__imm8);
   __charmask = vec_gb(__charmask);
-  __v8hu __shortmask = (__v8hu)vec_unpackh(__charmask);
+  __v8hu __shortmask = (__v8hu)vec_unpackh((__v16qi)__charmask);
 #ifdef __BIG_ENDIAN__
   __shortmask = vec_reve(__shortmask);
 #endif
   return (__m128i)vec_sel((__v8hu)__A, (__v8hu)__B, __shortmask);
 }
 #endif
 
 extern __inline __m128i

clang/test/CodeGen/PowerPC/ppc-smmintrin.c

test_blend() {
   _mm_blend_pd(md1, md2, 0);
   _mm_blendv_pd(md1, md2, md1);
 }
 
 // CHECK-LABEL: @test_blend
 
 // CHECK-LABEL: define available_externally <2 x i64> @_mm_blend_epi16(<2 x i64> noundef %{{[0-9a-zA-Z_.]+}}, <2 x i64> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
 // CHECK: %[[TRUNC:[0-9a-zA-Z_.]+]] = trunc i32 %{{[0-9a-zA-Z_.]+}} to i8
-// CHECK: call <16 x i8> @vec_splats(signed char)(i8 noundef signext %[[TRUNC]])
+// CHECK: call <16 x i8> @vec_splats(unsigned char)(i8 noundef zeroext %[[TRUNC]])
 // CHECK: call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %{{[0-9a-zA-Z_.]+}})
 // CHECK: %[[PACK:[0-9a-zA-Z_.]+]] = call <8 x i16> @vec_unpackh(signed char vector[16])
 // CHECK: store <8 x i16> %[[PACK]], ptr %{{[0-9a-zA-Z_.]+}}, align 16
 // BE: %[[REVE:[0-9a-zA-Z_.]+]] = call <8 x i16> @vec_reve(unsigned short vector[8])
 // BE: store <8 x i16> %[[REVE]], ptr %{{[0-9a-zA-Z_.]+}}, align 16
 // CHECK: call <8 x i16> @vec_sel(unsigned short vector[8], unsigned short vector[8], unsigned short vector[8])
 
 // P10-LABEL: define available_externally <2 x i64> @_mm_blendv_epi8(<2 x i64> noundef %{{[0-9a-zA-Z_.]+}}, <2 x i64> noundef %{{[0-9a-zA-Z_.]+}}, <2 x i64> noundef %{{[0-9a-zA-Z_.]+}})

 // CHECK: zext i16 %{{[0-9a-zA-Z_.]+}} to i32
 // CHECK: extractelement <8 x i16> %{{[0-9a-zA-Z_.]+}}, i64 %{{[0-9a-zA-Z_.]+}}
 // CHECK: add i64 %{{[0-9a-zA-Z_.]+}}, 1
 
 void __attribute__((noinline))
 test_round() {
   _mm_round_ps(mn1, 0);
   _mm_round_ss(mn1, mn2, 0);
-  _mm_round_pd(mn1, 0);
-  _mm_round_sd(mn1, mn2, 0);
+  _mm_round_pd(md1, 0);
+  _mm_round_sd(md1, md2, 0);
 }
 
 // CHECK-LABEL: @test_round
 
 // CHECK-LABEL: define available_externally <4 x float> @_mm_round_ps(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
 // CHECK: call signext i32 @__builtin_mffs()
 // CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}})
 // CHECK: %{{[0-9a-zA-Z_.]+}} = call <4 x float> asm "", "=^wa,0"