[PowerPC] Add Binary Coded Decimal Assist Instructions

[stefanp]

Summary

This patch adds three instructions for Binary Coded Decimal (BCD).
They are: cdtbcd, cbcdtd, addg6s.

[amyk]

LGTM.

[stefanp]

Rebased to top of trunk.

llvm/lib/Target/PowerPC/P10InstrResources.td

 def : InstRW<[P10W_F2_4C, P10W_DISP_ANY],
       (instrs
     TRAP, TW
 )>;
 
 // 4 Cycles ALU2 operations, 1 input operands
 def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read],
       (instrs
+    CBCDTD, CBCDTD8,
+    CDTBCD, CDTBCD8,
     CNTLZD,
     CNTLZD_rec,
     CNTLZW, CNTLZW8,
     CNTLZW8_rec, CNTLZW_rec,
     CNTTZD,
     CNTTZD_rec,
     CNTTZW, CNTTZW8,
     CNTTZW8_rec, CNTTZW_rec,
def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read, P10FX_Read],
     ADDIC_rec,
     ADD4O_rec, ADD8O_rec,
     SUBFE8_rec, SUBFE_rec,
     SUBFE8O_rec, SUBFEO_rec,
     SUBF8O_rec, SUBFO_rec
 )>;
 
 // 2-way crack instructions
+// 3 Cycles ALU operations, and 4 Cycles ALU2 operations, 2 input operands
+def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_F2_4C, P10W_DISP_ANY],
+      (instrs
+    ADDG6S, ADDG6S8
+)>;
+
+// 2-way crack instructions
 // 3 Cycles ALU operations, and 3 Cycles ALU operations, 0 input operands
 def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY],
       (instrs
     HRFID,
     MFFSCE,
     RFID,
     STOP
 )>;

llvm/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[],
   RFDI,
   RFMCI,
   SC,
   DCBA,
   DCBI,
   DCCCI,
   ICCCI,
   ADDEX,
-  ADDEX8
+  ADDEX8,
+  CDTBCD, CDTBCD8,
+  CBCDTD, CBCDTD8,
+  ADDG6S, ADDG6S8
 )> { let Unsupported = 1; }

llvm/lib/Target/PowerPC/PPCBack2BackFusion.def

FUSION_OP_SET(ADD4,
     ANDC8,
     ANDC8_rec,
     ANDC_rec,
     ANDI8_rec,
     ANDIS8_rec,
     ANDIS_rec,
     ANDI_rec,
     AND_rec,
+    CBCDTD,
+    CBCDTD8,
+    CDTBCD,
+    CDTBCD8,
     CMPB,
     CMPB8,
     CNTLZD,
     CNTLZD_rec,
     CNTLZW,
     CNTLZW8,
     CNTLZW8_rec,
     CNTLZW_rec,
FUSION_OP_SET(ADD4,
     ANDC8,
     ANDC8_rec,
     ANDC_rec,
     ANDI8_rec,
     ANDIS8_rec,
     ANDIS_rec,
     ANDI_rec,
     AND_rec,
+    CBCDTD,
+    CBCDTD8,
+    CDTBCD,
+    CDTBCD8,
     CMPB,
     CMPB8,
     CMPD,
     CMPDI,
     CMPEQB,
     CMPLD,
     CMPLDI,
     CMPLW,

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 
 // popcntw also does a population count on the high 32 bits (storing the
 // results in the high 32-bits of the output). We'll ignore that here (which is
 // safe because we never separately use the high part of the 64-bit registers).
 def POPCNTW : XForm_11<31, 378, (outs gprc:$RA), (ins gprc:$RST),
                        "popcntw $RA, $RST", IIC_IntGeneral,
                        [(set i32:$RA, (ctpop i32:$RST))]>;
 
-let isCodeGenOnly = 1 in
+let isCodeGenOnly = 1 in {
 def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$RA), (ins g8rc:$RST),
                         "popcntb $RA, $RST", IIC_IntGeneral,
                         [(set i64:$RA, (int_ppc_popcntb i64:$RST))]>;
 
+def CDTBCD8 : XForm_11<31, 282, (outs g8rc:$RA), (ins g8rc:$RST),
+                       "cdtbcd $RA, $RST", IIC_IntGeneral, []>;
+def CBCDTD8 : XForm_11<31, 314, (outs g8rc:$RA), (ins g8rc:$RST),
+                       "cbcdtd $RA, $RST", IIC_IntGeneral, []>;
+
+def ADDG6S8 : XOForm_1<31, 74, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
+                       "addg6s $RT, $RA, $RB", IIC_IntGeneral, []>;
+}
+
 defm DIVD  : XOForm_1rcr<31, 489, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
                           "divd", "$RT, $RA, $RB", IIC_IntDivD,
                           [(set i64:$RT, (sdiv i64:$RA, i64:$RB))]>, isPPC64;
 defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
                           "divdu", "$RT, $RA, $RB", IIC_IntDivD,
                           [(set i64:$RT, (udiv i64:$RA, i64:$RB))]>, isPPC64;
 defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
                          "divde", "$RT, $RA, $RB", IIC_IntDivD,

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def TDI : DForm_base<2, (outs), (ins u5imm:$RST, g8rc:$RA, s16imm:$D, variable_ops),
                      "tdi $RST, $RA, $D", IIC_IntTrapD, []>;
 def TD : XForm_1<31, 68, (outs), (ins u5imm:$RST, g8rc:$RA, g8rc:$RB, variable_ops),
                  "td $RST, $RA, $RB", IIC_IntTrapD, []>;
 
 def POPCNTB : XForm_11<31, 122, (outs gprc:$RA), (ins gprc:$RST),
                        "popcntb $RA, $RST", IIC_IntGeneral,
                        [(set i32:$RA, (int_ppc_popcntb i32:$RST))]>;
 
+def CDTBCD : XForm_11<31, 282, (outs gprc:$RA), (ins gprc:$RST),
+                      "cdtbcd $RA, $RST", IIC_IntGeneral, []>;
+def CBCDTD : XForm_11<31, 314, (outs gprc:$RA), (ins gprc:$RST),
+                      "cbcdtd $RA, $RST", IIC_IntGeneral, []>;
+
+def ADDG6S : XOForm_1<31, 74, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+                      "addg6s $RT, $RA, $RB", IIC_IntGeneral, []>;
+
 //===----------------------------------------------------------------------===//
 // PPC32 Load Instructions.
 //
 
 // Unindexed (r+i) Loads.
 let PPC970_Unit = 2 in {
 def LBZ : DForm_1<34, (outs gprc:$RST), (ins (memri $D, $RA):$addr),
                   "lbz $RST, $addr", IIC_LdStLoad,

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt

 0x7c 0x62 0x26 0x35
 
 # CHECK: extswsli 2, 3, 4                
 0x7c 0x62 0x26 0xf4
 
 # CHECK: extswsli. 2, 3, 4               
 0x7c 0x62 0x26 0xf5
 
+# CHECK: cdtbcd 2, 7
+0x7c 0xe2 0x02 0x34
+
+# CHECK: cbcdtd 2, 7
+0x7c 0xe2 0x02 0x74
+
+# CHECK: addg6s 2, 3, 4
+0x7c 0x43 0x20 0x94
+
 # CHECK: mtspr 600, 2                    
 0x7c 0x58 0x93 0xa6
 
 # CHECK: mfspr 2, 600                    
 0x7c 0x58 0x92 0xa6
 
 # CHECK: mtudscr 2
 0x7c 0x43 0x03 0xa6

llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt

 0x75 0x26 0x62 0x7c
 
 # CHECK: srad 2, 3, 4
 0x34 0x26 0x62 0x7c
 
 # CHECK: srad. 2, 3, 4
 0x35 0x26 0x62 0x7c
 
+# CHECK: cdtbcd 2, 7
+0x34 0x02 0xe2 0x7c
+
+# CHECK: cbcdtd 2, 7
+0x74 0x02 0xe2 0x7c
+
+# CHECK: addg6s 2, 3, 4
+0x94 0x20 0x43 0x7c
+
 # CHECK: mtspr 600, 2
 0xa6 0x93 0x58 0x7c
 
 # CHECK: mfspr 2, 600
 0xa6 0x92 0x58 0x7c
 
 # CHECK: mtcrf 123, 2
 0x20 0xb1 0x47 0x7c

llvm/test/MC/PowerPC/ppc64-encoding.s

 # CHECK-BE: extswsli 2, 3, 4                # encoding: [0x7c,0x62,0x26,0xf4]
 # CHECK-LE: extswsli 2, 3, 4                # encoding: [0xf4,0x26,0x62,0x7c]
             extswsli 2, 3, 4
 # CHECK-BE: extswsli. 2, 3, 4               # encoding: [0x7c,0x62,0x26,0xf5]
 # CHECK-LE: extswsli. 2, 3, 4               # encoding: [0xf5,0x26,0x62,0x7c]
             extswsli. 2, 3, 4
 
 
-# FIXME: BCD assist instructions
+# BCD assist instructions
+
+# CHECK-BE: cdtbcd 2, 7                     # encoding: [0x7c,0xe2,0x02,0x34]
+# CHECK-LE: cdtbcd 2, 7                     # encoding: [0x34,0x02,0xe2,0x7c]
+            cdtbcd 2, 7
+# CHECK-BE: cbcdtd 2, 7                     # encoding: [0x7c,0xe2,0x02,0x74]
+# CHECK-LE: cbcdtd 2, 7                     # encoding: [0x74,0x02,0xe2,0x7c]
+            cbcdtd 2, 7
+# CHECK-BE: addg6s 2, 3, 4                  # encoding: [0x7c,0x43,0x20,0x94]
+# CHECK-LE: addg6s 2, 3, 4                  # encoding: [0x94,0x20,0x43,0x7c]
+            addg6s 2, 3, 4
 
 # Move to/from system register instructions
 
 # CHECK-BE: mtspr 600, 2                    # encoding: [0x7c,0x58,0x93,0xa6]
 # CHECK-LE: mtspr 600, 2                    # encoding: [0xa6,0x93,0x58,0x7c]
             mtspr 600, 2
 # CHECK-BE: mfspr 2, 600                    # encoding: [0x7c,0x58,0x92,0xa6]
 # CHECK-LE: mfspr 2, 600                    # encoding: [0xa6,0x92,0x58,0x7c]