[GISel][PowerPC][WIP] Support G_ATOMICRMW_*

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

private:
 
   std::optional<bool> selectI64ImmDirect(MachineInstr &I,
                                          MachineBasicBlock &MBB,
                                          MachineRegisterInfo &MRI, Register Reg,
                                          uint64_t Imm) const;
   bool selectI64Imm(MachineInstr &I, MachineBasicBlock &MBB,
                     MachineRegisterInfo &MRI) const;
 
+  ComplexRendererFns SelectForceXForm(MachineOperand &Root) const;
+
   const PPCTargetMachine &TM;
   const PPCSubtarget &STI;
   const PPCInstrInfo &TII;
   const PPCRegisterInfo &TRI;
   const PPCRegisterBankInfo &RBI;
 
 #define GET_GLOBALISEL_PREDICATES_DECL
 #include "PPCGenGlobalISel.inc"
bool PPCInstructionSelector::select(MachineInstr &I) {
   case TargetOpcode::G_CONSTANT:
     return selectI64Imm(I, MBB, MRI);
   case TargetOpcode::G_CONSTANT_POOL:
     return selectConstantPool(I, MBB, MRI);
   }
   return false;
 }
 
+InstructionSelector::ComplexRendererFns
+PPCInstructionSelector::SelectForceXForm(MachineOperand &Root) const {
+  if (!Root.isReg())
+    return std::nullopt;
+  Register Reg = Root.getReg();
+  if (!Reg)
+    return std::nullopt;
+  return {{[=](MachineInstrBuilder &MIB) {
+             TM.isPPC64() ? MIB.addUse(PPC::ZERO8) : MIB.addUse(PPC::ZERO);
+           },
+           [=](MachineInstrBuilder &MIB) { MIB.addUse(Reg); }}};
+}
+
 namespace llvm {
 InstructionSelector *
 createPPCInstructionSelector(const PPCTargetMachine &TM,
                              const PPCSubtarget &Subtarget,
                              const PPCRegisterBankInfo &RBI) {
   return new PPCInstructionSelector(TM, Subtarget, RBI);
 }
 } // end namespace llvm

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

 
 #include "PPCLegalizerInfo.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "ppc-legalinfo"
 
 using namespace llvm;
 using namespace LegalizeActions;
+using namespace LegalityPredicates;
 
 PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
   using namespace TargetOpcode;
   const LLT P0 = LLT::pointer(0, 64);
   const LLT S1 = LLT::scalar(1);
   const LLT S8 = LLT::scalar(8);
   const LLT S16 = LLT::scalar(16);
   const LLT S32 = LLT::scalar(32);
PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
   getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
       .legalForCartesianProduct({S32, S64}, {S64});
 
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
       .legalForTypesWithMemDesc({{S64, P0, S64, 8}, {S32, P0, S32, 4}});
 
   getActionDefinitionsBuilder(G_FCONSTANT).lowerFor({S32, S64});
   getActionDefinitionsBuilder(G_CONSTANT_POOL).legalFor({P0});
+  getActionDefinitionsBuilder(
+      {G_ATOMICRMW_XCHG, G_ATOMICRMW_ADD, G_ATOMICRMW_SUB})
+      .clampScalar(0, S8, S64)
+      .legalIf(all(typeInSet(0, {S8, S16, S32, S64}), typeIs(1, P0)));
 
   getLegacyLegalizerInfo().computeTables();
 }

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h

 namespace llvm {
 class TargetRegisterInfo;
 
 class PPCGenRegisterBankInfo : public RegisterBankInfo {
 protected:
   enum PartialMappingIdx {
     PMI_None = -1,
     PMI_GPR32 = 1,
-    PMI_GPR64 = 2,
-    PMI_FPR32 = 3,
-    PMI_FPR64 = 4,
-    PMI_CR = 5,
+    PMI_GPR64,
+    PMI_FPR32,
+    PMI_FPR64,
+    PMI_CR,
     PMI_Min = PMI_GPR32,
+    PMI_FirstGPR = PMI_GPR32,
+    PMI_LastGPR = PMI_GPR64,
   };
 
   static RegisterBankInfo::PartialMapping PartMappings[];
   static RegisterBankInfo::ValueMapping ValMappings[];
   static PartialMappingIdx BankIDToCopyMapIdx[];
 
   /// Get the pointer to the ValueMapping representing the RegisterBank
   /// at \p RBIdx.

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

if (onlyDefinesFP(*DefMI, MRI, TRI))
           {getValueMapping(Size == 64 ? PMI_FPR64 : PMI_FPR32),
            getValueMapping(PMI_GPR64)});
     else
       OperandsMapping = getOperandsMapping(
           {getValueMapping(Size == 64 ? PMI_GPR64 : PMI_GPR32),
            getValueMapping(PMI_GPR64)});
     break;
   }
-  case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
-    // FIXME: We have to check every operand in this MI and compute value
-    // mapping accordingly.
+  default: {
     SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
+    for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
+      const MachineOperand &MO = MI.getOperand(Idx);
+      if (!MO.isReg())
+        continue;
+      Register Reg = MO.getReg();
+      if (!Reg)
+        continue;
+      LLT Ty = MRI.getType(Reg);
+      if (!Ty.isValid())
+        continue;
+      unsigned Size = Ty.getSizeInBits();
+      const ValueMapping *VM = nullptr;
+      if (Size == 32)
+        VM = getValueMapping(PMI_GPR32);
+      else if (Size == 64)
+        VM = getValueMapping(PMI_GPR64);
+      if (!VM || !VM->isValid())
+        return getInvalidInstructionMapping();
+      OpdsMapping[Idx] = VM;
+    }
     OperandsMapping = getOperandsMapping(OpdsMapping);
     break;
   }
-  default:
-    return getInvalidInstructionMapping();
   }
 
   return getInstructionMapping(MappingID, Cost, OperandsMapping, NumOperands);
 }
 
 /// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
 /// having only floating-point operands.
 /// FIXME: this is copied from target AArch64. Needs some code refactor here to

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 def DForm  : ComplexPattern<iPTR, 2, "SelectDForm",    [], [SDNPWantParent]>;
 def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm",   [], [SDNPWantParent]>;
 def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm",   [], [SDNPWantParent]>;
 def XForm  : ComplexPattern<iPTR, 2, "SelectXForm",    [], [SDNPWantParent]>;
 def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm", [], [SDNPWantParent]>;
 def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm", [], [SDNPWantParent]>;
 def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm",   [], [SDNPWantParent]>;
 
+// Mapping complex patterns to GlobalISel equivalence.
+def GI_ForceXForm : GIComplexOperandMatcher<s64, "SelectForceXForm">,
+                    GIComplexPatternEquiv<ForceXForm>;
+
 //===----------------------------------------------------------------------===//
 // PowerPC Instruction Predicate Definitions.
 def In32BitMode  : Predicate<"!Subtarget->isPPC64()">;
 def In64BitMode  : Predicate<"Subtarget->isPPC64()">;
 def IsBookE  : Predicate<"Subtarget->isBookE()">;
 def IsNotBookE  : Predicate<"!Subtarget->isBookE()">;
 def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">;
 def HasSYNC   : Predicate<"!Subtarget->hasOnlyMSYNC()">;

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-atomics.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-unknown \
+; RUN:   -ppc-asm-full-reg-names -global-isel -o - < %s | FileCheck %s
+
+define i64 @atomic_add_i64(ptr %p, i64 %diff) {
+; CHECK-LABEL: atomic_add_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sync
+; CHECK-NEXT:  .LBB0_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    ldarx r5, 0, r3
+; CHECK-NEXT:    add r6, r4, r5
+; CHECK-NEXT:    stdcx. r6, 0, r3
+; CHECK-NEXT:    bne cr0, .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    mr r3, r5
+; CHECK-NEXT:    lwsync
+; CHECK-NEXT:    blr
+entry:
+  %ret = atomicrmw add ptr %p, i64 %diff seq_cst, align 8
+  ret i64 %ret
+}