This is an archive of the discontinued LLVM Phabricator instance.

Differential D143954

[ValueTracking] It is not safe to execute FDIV/FREM speculatively
AbandonedPublic

Authored by Carrot on Feb 13 2023, 2:56 PM.

Details

Reviewers
nikic
Summary

In function isSafeToSpeculativelyExecuteWithOpcode, integer DIV/REM is marked as unsafe to execute speculatively, but floating point FDIV/FREM is not checked. They are also unsafe for the same reason.

There are some optimization regressions with this patch, such as select.ll. It is because function isSafeToSpeculativelyExecuteWithOpcode is called in several different kinds of speculations.

1 The dest block may be executed but the src block is not executed, like the new test case, it is danger for FDIV.
2 The src block is executed by the dest may not be executed, like select.ll, it is safe for FDIV.

In future we may split isSafeToSpeculativelyExecuteWithOpcode for different speculations to get most optimization opportunities.

Diff Detail

Event Timeline

Carrot created this revision.Feb 13 2023, 2:56 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 13 2023, 2:56 PM
Herald added subscribers: wenlei, hiraditya. · View Herald Transcript
Carrot requested review of this revision.Feb 13 2023, 2:56 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 13 2023, 2:56 PM
Herald added subscribers: llvm-commits, • pcwang-thead. · View Herald Transcript
craig.topper added a subscriber: craig.topper.Feb 13 2023, 3:19 PM
craig.topper added inline comments.
llvm/lib/Analysis/ValueTracking.cpp
4837

I don't think this is correct. x/0.0 is infinity or negative infinity. Unless x is 0.0 in which case it's nan. But in any case its not undefined.

craig.topper added inline comments.Feb 13 2023, 3:20 PM
llvm/lib/Analysis/ValueTracking.cpp
4837

I don't think this is correct. x/0.0 is infinity or negative infinity. Unless x is 0.0 in which case it's nan. But in any case its not undefined.

4837

So I don't understand why this patch is needed. There's nothing undefined about fdiv/frem.

Carrot added inline comments.Feb 13 2023, 3:40 PM
llvm/lib/Analysis/ValueTracking.cpp
4837

I copied it from the following UDiv/URem case. It should be changed to

// x / y causes exception if y == 0.0.
craig.topper added inline comments.Feb 13 2023, 3:51 PM
llvm/lib/Analysis/ValueTracking.cpp
4837

Exceptions are assumed to be masked in the default FP environment. If exceptions aren't masked we wouldn't be able to speculate any FP instruction not just fdiv/frem.

Harbormaster completed remote builds in B213519: Diff 497115.Feb 13 2023, 4:12 PM
nikic requested changes to this revision.Feb 14 2023, 3:51 AM
nikic added a subscriber: nikic.

As pointed out by @craig.topper, the premise of this patch is incorrect. We can't (generally) speculate a constrained fdiv intrinsic, but we already don't do that.

This revision now requires changes to proceed.Feb 14 2023, 3:51 AM
Herald added a subscriber: StephenFan. · View Herald TranscriptFeb 14 2023, 3:51 AM
Carrot abandoned this revision.Feb 14 2023, 7:53 PM

Revision Contents

PathSize
llvm/
lib/
Analysis/
8 lines
test/
Transforms/
CodeGenPrepare/
X86/
148 lines
InstCombine/
24 lines
12 lines
PGOProfile/
32 lines
Reassociate/
2 lines
38 lines
SLPVectorizer/
X86/
36 lines
10 lines
SimplifyCFG/
ARM/
66 lines
22 lines
46 lines
SpeculativeExecution/
6 lines

Diff 497115

llvm/lib/Analysis/ValueTracking.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,826 Lines • ▼ Show 20 Lines if (Inst->getOpcode() != Opcode) {
assert(!Instruction::isUnaryOp(Opcode) || assert(!Instruction::isUnaryOp(Opcode) ||
hasEqualReturnAndLeadingOperandTypes(Inst, 1)); hasEqualReturnAndLeadingOperandTypes(Inst, 1));
} }
#endif #endif
switch (Opcode) { switch (Opcode) {
default: default:
return true; return true;
case Instruction::FDiv:
case Instruction::FRem: {
// x / y is undefined if y == 0.0.
craig.topperUnsubmitted
Not Done
ReplyInline Actions

I don't think this is correct. x/0.0 is infinity or negative infinity. Unless x is 0.0 in which case it's nan. But in any case its not undefined.

craig.topper: I don't think this is correct. x/0.0 is infinity or negative infinity. Unless x is 0.0 in which…
craig.topperUnsubmitted
Not Done
ReplyInline Actions

I don't think this is correct. x/0.0 is infinity or negative infinity. Unless x is 0.0 in which case it's nan. But in any case its not undefined.

craig.topper: > I don't think this is correct. x/0.0 is infinity or negative infinity. Unless x is 0.0 in…
craig.topperUnsubmitted
Not Done
ReplyInline Actions

So I don't understand why this patch is needed. There's nothing undefined about fdiv/frem.

craig.topper: So I don't understand why this patch is needed. There's nothing undefined about fdiv/frem.
CarrotAuthorUnsubmitted
Done
ReplyInline Actions

I copied it from the following UDiv/URem case. It should be changed to

// x / y causes exception if y == 0.0.
Carrot: I copied it from the following UDiv/URem case. It should be changed to // x / y causes…
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Exceptions are assumed to be masked in the default FP environment. If exceptions aren't masked we wouldn't be able to speculate any FP instruction not just fdiv/frem.

craig.topper: Exceptions are assumed to be masked in the default FP environment. If exceptions aren't masked…
const APFloat *V;
if (match(Inst->getOperand(1), m_APFloat(V)))
return V->isNonZero();
return false;
}
case Instruction::UDiv: case Instruction::UDiv:
case Instruction::URem: { case Instruction::URem: {
// x / y is undefined if y == 0. // x / y is undefined if y == 0.
const APInt *V; const APInt *V;
if (match(Inst->getOperand(1), m_APInt(V))) if (match(Inst->getOperand(1), m_APInt(V)))
return *V != 0; return *V != 0;
return false; return false;
} }
▲ Show 20 Lines • Show All 2,692 Lines • Show Last 20 Lines

llvm/test/Transforms/CodeGenPrepare/X86/select.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -codegenprepare -S < %s | FileCheck %s ; RUN: opt -codegenprepare -S < %s | FileCheck %s
; RUN: opt -debugify -codegenprepare -S < %s | FileCheck %s -check-prefix=DEBUG ; RUN: opt -debugify -codegenprepare -S < %s | FileCheck %s -check-prefix=DEBUG
target triple = "x86_64-unknown-unknown" target triple = "x86_64-unknown-unknown"
; Nothing to sink and convert here. ; Nothing to sink and convert here.
define i32 @no_sink(double %a, ptr %b, i32 %x, i32 %y) { define i32 @no_sink(double %a, ptr %b, i32 %x, i32 %y) {
; CHECK-LABEL: @no_sink( ; CHECK-LABEL: @no_sink(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOAD:%.*]] = load double, ptr [[B:%.*]], align 8 ; CHECK-NEXT: [[LOAD:%.*]] = load double, ptr [[B:%.*]], align 8
; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[LOAD]], [[A:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[LOAD]], [[A:%.*]]
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[X:%.*]], i32 [[Y:%.*]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[X:%.*]], i32 [[Y:%.*]]
; CHECK-NEXT: ret i32 [[SEL]] ; CHECK-NEXT: ret i32 [[SEL]]
; ;
; DEBUG-LABEL: @no_sink(
; DEBUG-NEXT: entry:
; DEBUG-NEXT: [[LOAD:%.*]] = load double, ptr [[B:%.*]], align 8, !dbg [[DBG15:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata double [[LOAD]], metadata [[META9:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15]]
; DEBUG-NEXT: [[CMP:%.*]] = fcmp olt double [[LOAD]], [[A:%.*]], !dbg [[DBG16:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG16]]
; DEBUG-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[X:%.*]], i32 [[Y:%.*]], !dbg [[DBG17:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i32 [[SEL]], metadata [[META13:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17]]
; DEBUG-NEXT: ret i32 [[SEL]], !dbg [[DBG18:![0-9]+]]
;
entry: entry:
%load = load double, ptr %b, align 8 %load = load double, ptr %b, align 8
%cmp = fcmp olt double %load, %a %cmp = fcmp olt double %load, %a
%sel = select i1 %cmp, i32 %x, i32 %y %sel = select i1 %cmp, i32 %x, i32 %y
ret i32 %sel ret i32 %sel
} }
; An 'fdiv' is expensive, so sink it rather than speculatively execute it. ; An 'fdiv' is expensive, so sink it rather than speculatively execute it.
define float @fdiv_true_sink(float %a, float %b) { define float @fdiv_true_sink(float %a, float %b) {
; CHECK-LABEL: @fdiv_true_sink( ; CHECK-LABEL: @fdiv_true_sink(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SEL_FR:%.*]] = freeze float [[A:%.*]] ; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[SEL_FR]], 1.000000e+00 ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[A]], 1.000000e+00
; CHECK-NEXT: br i1 [[CMP]], label [[SELECT_TRUE_SINK:%.*]], label [[SELECT_END:%.*]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[DIV]], float 2.000000e+00
; CHECK: select.true.sink:
; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[A]], [[B:%.*]]
; CHECK-NEXT: br label [[SELECT_END]]
; CHECK: select.end:
; CHECK-NEXT: [[SEL:%.*]] = phi float [ [[DIV]], [[SELECT_TRUE_SINK]] ], [ 2.000000e+00, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret float [[SEL]] ; CHECK-NEXT: ret float [[SEL]]
; ;
; DEBUG-LABEL: @fdiv_true_sink( ; DEBUG-LABEL: @fdiv_true_sink(
; DEBUG-NEXT: entry: ; DEBUG-NEXT: entry:
; DEBUG-NEXT: [[SEL_FR:%.*]] = freeze float [[A:%.*]] ; DEBUG-NEXT: [[DIV:%.*]] = fdiv float [[A:%.*]], [[B:%.*]], !dbg [[DBG24:![0-9]+]]
; DEBUG-NEXT: [[CMP:%.*]] = fcmp ogt float [[SEL_FR]], 1.000000e+00, !dbg !24 ; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[DIV]], metadata [[META21:![0-9]+]], metadata !DIExpression()), !dbg [[DBG24]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]] ; DEBUG-NEXT: [[CMP:%.*]] = fcmp ogt float [[A]], 1.000000e+00, !dbg [[DBG25:![0-9]+]]
; DEBUG-NEXT: br i1 [[CMP]], label [[SELECT_TRUE_SINK:%.*]], label [[SELECT_END:%.*]], !dbg ; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META22:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25]]
; DEBUG: select.true.sink: ; DEBUG-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[DIV]], float 2.000000e+00, !dbg [[DBG26:![0-9]+]]
; DEBUG-NEXT: [[DIV:%.*]] = fdiv float [[A]], [[B:%.*]] ; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[SEL]], metadata [[META23:![0-9]+]], metadata !DIExpression()), !dbg [[DBG26]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[DIV]] ; DEBUG-NEXT: ret float [[SEL]], !dbg [[DBG27:![0-9]+]]
; DEBUG-NEXT: br label [[SELECT_END]], !dbg
; DEBUG: select.end:
; DEBUG-NEXT: [[SEL:%.*]] = phi float [ [[DIV]], [[SELECT_TRUE_SINK]] ], [ 2.000000e+00, [[ENTRY:%.*]] ], !dbg
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[SEL]]
; DEBUG-NEXT: ret float [[SEL]]
; ;
entry: entry:
%div = fdiv float %a, %b %div = fdiv float %a, %b
%cmp = fcmp ogt float %a, 1.0 %cmp = fcmp ogt float %a, 1.0
%sel = select i1 %cmp, float %div, float 2.0 %sel = select i1 %cmp, float %div, float 2.0
ret float %sel ret float %sel
} }
define float @fdiv_false_sink(float %a, float %b) { define float @fdiv_false_sink(float %a, float %b) {
; CHECK-LABEL: @fdiv_false_sink( ; CHECK-LABEL: @fdiv_false_sink(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SEL_FR:%.*]] = freeze float [[A:%.*]] ; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[SEL_FR]], 3.000000e+00 ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[A]], 3.000000e+00
; CHECK-NEXT: br i1 [[CMP]], label [[SELECT_END:%.*]], label [[SELECT_FALSE_SINK:%.*]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float 4.000000e+00, float [[DIV]]
; CHECK: select.false.sink:
; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[A]], [[B:%.*]]
; CHECK-NEXT: br label [[SELECT_END]]
; CHECK: select.end:
; CHECK-NEXT: [[SEL:%.*]] = phi float [ 4.000000e+00, [[ENTRY:%.*]] ], [ [[DIV]], [[SELECT_FALSE_SINK]] ]
; CHECK-NEXT: ret float [[SEL]] ; CHECK-NEXT: ret float [[SEL]]
; ;
; DEBUG-LABEL: @fdiv_false_sink( ; DEBUG-LABEL: @fdiv_false_sink(
; DEBUG-NEXT: entry: ; DEBUG-NEXT: entry:
; DEBUG-NEXT: [[SEL_FR:%.*]] = freeze float [[A:%.*]] ; DEBUG-NEXT: [[DIV:%.*]] = fdiv float [[A:%.*]], [[B:%.*]], !dbg [[DBG33:![0-9]+]]
; DEBUG-NEXT: [[CMP:%.*]] = fcmp ogt float [[SEL_FR]], 3.000000e+00, !dbg !33 ; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[DIV]], metadata [[META30:![0-9]+]], metadata !DIExpression()), !dbg [[DBG33]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]] ; DEBUG-NEXT: [[CMP:%.*]] = fcmp ogt float [[A]], 3.000000e+00, !dbg [[DBG34:![0-9]+]]
; DEBUG-NEXT: br i1 [[CMP]], label [[SELECT_END:%.*]], label [[SELECT_FALSE_SINK:%.*]], !dbg ; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META31:![0-9]+]], metadata !DIExpression()), !dbg [[DBG34]]
; DEBUG: select.false.sink: ; DEBUG-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float 4.000000e+00, float [[DIV]], !dbg [[DBG35:![0-9]+]]
; DEBUG-NEXT: [[DIV:%.*]] = fdiv float [[A]], [[B:%.*]] ; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[SEL]], metadata [[META32:![0-9]+]], metadata !DIExpression()), !dbg [[DBG35]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[DIV]] ; DEBUG-NEXT: ret float [[SEL]], !dbg [[DBG36:![0-9]+]]
; DEBUG-NEXT: br label [[SELECT_END]], !dbg
; DEBUG: select.end:
; DEBUG-NEXT: [[SEL:%.*]] = phi float [ 4.000000e+00, [[ENTRY:%.*]] ], [ [[DIV]], [[SELECT_FALSE_SINK]] ], !dbg
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[SEL]]
; DEBUG-NEXT: ret float [[SEL]], !dbg
; ;
entry: entry:
%div = fdiv float %a, %b %div = fdiv float %a, %b
%cmp = fcmp ogt float %a, 3.0 %cmp = fcmp ogt float %a, 3.0
%sel = select i1 %cmp, float 4.0, float %div %sel = select i1 %cmp, float 4.0, float %div
ret float %sel ret float %sel
} }
define float @fdiv_both_sink(float %a, float %b) { define float @fdiv_both_sink(float %a, float %b) {
; CHECK-LABEL: @fdiv_both_sink( ; CHECK-LABEL: @fdiv_both_sink(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SEL_FR:%.*]] = freeze float [[A:%.*]] ; CHECK-NEXT: [[DIV1:%.*]] = fdiv float [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[SEL_FR]], 5.000000e+00
; CHECK-NEXT: br i1 [[CMP]], label [[SELECT_TRUE_SINK:%.*]], label [[SELECT_FALSE_SINK:%.*]]
; CHECK: select.true.sink:
; CHECK-NEXT: [[DIV1:%.*]] = fdiv float [[A]], [[B:%.*]]
; CHECK-NEXT: br label [[SELECT_END:%.*]]
; CHECK: select.false.sink:
; CHECK-NEXT: [[DIV2:%.*]] = fdiv float [[B]], [[A]] ; CHECK-NEXT: [[DIV2:%.*]] = fdiv float [[B]], [[A]]
; CHECK-NEXT: br label [[SELECT_END]] ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[A]], 5.000000e+00
; CHECK: select.end: ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[DIV1]], float [[DIV2]]
; CHECK-NEXT: [[SEL:%.*]] = phi float [ [[DIV1]], [[SELECT_TRUE_SINK]] ], [ [[DIV2]], [[SELECT_FALSE_SINK]] ]
; CHECK-NEXT: ret float [[SEL]] ; CHECK-NEXT: ret float [[SEL]]
; ;
; DEBUG-LABEL: @fdiv_both_sink(
; DEBUG-NEXT: entry:
; DEBUG-NEXT: [[DIV1:%.*]] = fdiv float [[A:%.*]], [[B:%.*]], !dbg [[DBG43:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[DIV1]], metadata [[META39:![0-9]+]], metadata !DIExpression()), !dbg [[DBG43]]
; DEBUG-NEXT: [[DIV2:%.*]] = fdiv float [[B]], [[A]], !dbg [[DBG44:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[DIV2]], metadata [[META40:![0-9]+]], metadata !DIExpression()), !dbg [[DBG44]]
; DEBUG-NEXT: [[CMP:%.*]] = fcmp ogt float [[A]], 5.000000e+00, !dbg [[DBG45:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META41:![0-9]+]], metadata !DIExpression()), !dbg [[DBG45]]
; DEBUG-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[DIV1]], float [[DIV2]], !dbg [[DBG46:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[SEL]], metadata [[META42:![0-9]+]], metadata !DIExpression()), !dbg [[DBG46]]
; DEBUG-NEXT: ret float [[SEL]], !dbg [[DBG47:![0-9]+]]
;
entry: entry:
%div1 = fdiv float %a, %b %div1 = fdiv float %a, %b
%div2 = fdiv float %b, %a %div2 = fdiv float %b, %a
%cmp = fcmp ogt float %a, 5.0 %cmp = fcmp ogt float %a, 5.0
%sel = select i1 %cmp, float %div1, float %div2 %sel = select i1 %cmp, float %div1, float %div2
ret float %sel ret float %sel
} }
; But if the select is marked unpredictable, then don't turn it into a branch. ; But if the select is marked unpredictable, then don't turn it into a branch.
define float @unpredictable_select(float %a, float %b) { define float @unpredictable_select(float %a, float %b) {
; CHECK-LABEL: @unpredictable_select( ; CHECK-LABEL: @unpredictable_select(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[A]], 1.000000e+00 ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[A]], 1.000000e+00
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[DIV]], float 2.000000e+00, !unpredictable !0 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[DIV]], float 2.000000e+00, !unpredictable !0
; CHECK-NEXT: ret float [[SEL]] ; CHECK-NEXT: ret float [[SEL]]
; ;
; DEBUG-LABEL: @unpredictable_select(
; DEBUG-NEXT: entry:
; DEBUG-NEXT: [[DIV:%.*]] = fdiv float [[A:%.*]], [[B:%.*]], !dbg [[DBG53:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[DIV]], metadata [[META50:![0-9]+]], metadata !DIExpression()), !dbg [[DBG53]]
; DEBUG-NEXT: [[CMP:%.*]] = fcmp ogt float [[A]], 1.000000e+00, !dbg [[DBG54:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META51:![0-9]+]], metadata !DIExpression()), !dbg [[DBG54]]
; DEBUG-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[DIV]], float 2.000000e+00, !dbg [[DBG55:![0-9]+]], !unpredictable !7
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[SEL]], metadata [[META52:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]]
; DEBUG-NEXT: ret float [[SEL]], !dbg [[DBG56:![0-9]+]]
;
entry: entry:
%div = fdiv float %a, %b %div = fdiv float %a, %b
%cmp = fcmp ogt float %a, 1.0 %cmp = fcmp ogt float %a, 1.0
%sel = select i1 %cmp, float %div, float 2.0, !unpredictable !0 %sel = select i1 %cmp, float %div, float 2.0, !unpredictable !0
ret float %sel ret float %sel
} }
!0 = !{} !0 = !{}
; An 'fadd' is not too expensive, so it's ok to speculate. ; An 'fadd' is not too expensive, so it's ok to speculate.
define float @fadd_no_sink(float %a, float %b) { define float @fadd_no_sink(float %a, float %b) {
; CHECK-LABEL: @fadd_no_sink( ; CHECK-LABEL: @fadd_no_sink(
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float 6.000000e+00, [[A]] ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float 6.000000e+00, [[A]]
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[ADD]], float 7.000000e+00 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[ADD]], float 7.000000e+00
; CHECK-NEXT: ret float [[SEL]] ; CHECK-NEXT: ret float [[SEL]]
; ;
; DEBUG-LABEL: @fadd_no_sink(
; DEBUG-NEXT: [[ADD:%.*]] = fadd float [[A:%.*]], [[B:%.*]], !dbg [[DBG62:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[ADD]], metadata [[META59:![0-9]+]], metadata !DIExpression()), !dbg [[DBG62]]
; DEBUG-NEXT: [[CMP:%.*]] = fcmp ogt float 6.000000e+00, [[A]], !dbg [[DBG63:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META60:![0-9]+]], metadata !DIExpression()), !dbg [[DBG63]]
; DEBUG-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[ADD]], float 7.000000e+00, !dbg [[DBG64:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[SEL]], metadata [[META61:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]]
; DEBUG-NEXT: ret float [[SEL]], !dbg [[DBG65:![0-9]+]]
;
%add = fadd float %a, %b %add = fadd float %a, %b
%cmp = fcmp ogt float 6.0, %a %cmp = fcmp ogt float 6.0, %a
%sel = select i1 %cmp, float %add, float 7.0 %sel = select i1 %cmp, float %add, float 7.0
ret float %sel ret float %sel
} }
; Possible enhancement: sinkability is only calculated with the direct ; Possible enhancement: sinkability is only calculated with the direct
; operand of the select, so we don't try to sink this. The fdiv cost is not ; operand of the select, so we don't try to sink this. The fdiv cost is not
; taken into account. ; taken into account.
define float @fdiv_no_sink(float %a, float %b) { define float @fdiv_no_sink(float %a, float %b) {
; CHECK-LABEL: @fdiv_no_sink( ; CHECK-LABEL: @fdiv_no_sink(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[DIV]], [[B]] ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[DIV]], [[B]]
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[A]], 1.000000e+00 ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[A]], 1.000000e+00
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[ADD]], float 8.000000e+00 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[ADD]], float 8.000000e+00
; CHECK-NEXT: ret float [[SEL]] ; CHECK-NEXT: ret float [[SEL]]
; ;
; DEBUG-LABEL: @fdiv_no_sink(
; DEBUG-NEXT: entry:
; DEBUG-NEXT: [[DIV:%.*]] = fdiv float [[A:%.*]], [[B:%.*]], !dbg [[DBG72:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[DIV]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG72]]
; DEBUG-NEXT: [[ADD:%.*]] = fadd float [[DIV]], [[B]], !dbg [[DBG73:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[ADD]], metadata [[META69:![0-9]+]], metadata !DIExpression()), !dbg [[DBG73]]
; DEBUG-NEXT: [[CMP:%.*]] = fcmp ogt float [[A]], 1.000000e+00, !dbg [[DBG74:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG74]]
; DEBUG-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[ADD]], float 8.000000e+00, !dbg [[DBG75:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata float [[SEL]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG75]]
; DEBUG-NEXT: ret float [[SEL]], !dbg [[DBG76:![0-9]+]]
;
entry: entry:
%div = fdiv float %a, %b %div = fdiv float %a, %b
%add = fadd float %div, %b %add = fadd float %div, %b
%cmp = fcmp ogt float %a, 1.0 %cmp = fcmp ogt float %a, 1.0
%sel = select i1 %cmp, float %add, float 8.0 %sel = select i1 %cmp, float %add, float 8.0
ret float %sel ret float %sel
} }
; Do not transform the CFG if the select operands may have side effects. ; Do not transform the CFG if the select operands may have side effects.
declare ptr @bar(i32, i32, i32) declare ptr @bar(i32, i32, i32)
declare ptr @baz(i32, i32, i32) declare ptr @baz(i32, i32, i32)
define ptr @calls_no_sink(i32 %in) { define ptr @calls_no_sink(i32 %in) {
; CHECK-LABEL: @calls_no_sink( ; CHECK-LABEL: @calls_no_sink(
; CHECK-NEXT: [[CALL1:%.*]] = call ptr @bar(i32 1, i32 2, i32 3) ; CHECK-NEXT: [[CALL1:%.*]] = call ptr @bar(i32 1, i32 2, i32 3)
; CHECK-NEXT: [[CALL2:%.*]] = call ptr @baz(i32 1, i32 2, i32 3) ; CHECK-NEXT: [[CALL2:%.*]] = call ptr @baz(i32 1, i32 2, i32 3)
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[IN:%.*]], 0 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[IN:%.*]], 0
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[TOBOOL]], ptr [[CALL1]], ptr [[CALL2]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[TOBOOL]], ptr [[CALL1]], ptr [[CALL2]]
; CHECK-NEXT: ret ptr [[SEL]] ; CHECK-NEXT: ret ptr [[SEL]]
; ;
; DEBUG-LABEL: @calls_no_sink(
; DEBUG-NEXT: [[CALL1:%.*]] = call ptr @bar(i32 1, i32 2, i32 3), !dbg [[DBG83:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata ptr [[CALL1]], metadata [[META79:![0-9]+]], metadata !DIExpression()), !dbg [[DBG83]]
; DEBUG-NEXT: [[CALL2:%.*]] = call ptr @baz(i32 1, i32 2, i32 3), !dbg [[DBG84:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata ptr [[CALL2]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG84]]
; DEBUG-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[IN:%.*]], 0, !dbg [[DBG85:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[TOBOOL]], metadata [[META81:![0-9]+]], metadata !DIExpression()), !dbg [[DBG85]]
; DEBUG-NEXT: [[SEL:%.*]] = select i1 [[TOBOOL]], ptr [[CALL1]], ptr [[CALL2]], !dbg [[DBG86:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata ptr [[SEL]], metadata [[META82:![0-9]+]], metadata !DIExpression()), !dbg [[DBG86]]
; DEBUG-NEXT: ret ptr [[SEL]], !dbg [[DBG87:![0-9]+]]
;
%call1 = call ptr @bar(i32 1, i32 2, i32 3) %call1 = call ptr @bar(i32 1, i32 2, i32 3)
%call2 = call ptr @baz(i32 1, i32 2, i32 3) %call2 = call ptr @baz(i32 1, i32 2, i32 3)
%tobool = icmp ne i32 %in, 0 %tobool = icmp ne i32 %in, 0
%sel = select i1 %tobool, ptr %call1, ptr %call2 %sel = select i1 %tobool, ptr %call1, ptr %call2
ret ptr %sel ret ptr %sel
} }
define i32 @sdiv_no_sink(i32 %a, i32 %b) { define i32 @sdiv_no_sink(i32 %a, i32 %b) {
; CHECK-LABEL: @sdiv_no_sink( ; CHECK-LABEL: @sdiv_no_sink(
; CHECK-NEXT: [[DIV1:%.*]] = sdiv i32 [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[DIV1:%.*]] = sdiv i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[DIV2:%.*]] = sdiv i32 [[B]], [[A]] ; CHECK-NEXT: [[DIV2:%.*]] = sdiv i32 [[B]], [[A]]
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], 5 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], 5
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[DIV1]], i32 [[DIV2]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[DIV1]], i32 [[DIV2]]
; CHECK-NEXT: ret i32 [[SEL]] ; CHECK-NEXT: ret i32 [[SEL]]
; ;
; DEBUG-LABEL: @sdiv_no_sink(
; DEBUG-NEXT: [[DIV1:%.*]] = sdiv i32 [[A:%.*]], [[B:%.*]], !dbg [[DBG94:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i32 [[DIV1]], metadata [[META90:![0-9]+]], metadata !DIExpression()), !dbg [[DBG94]]
; DEBUG-NEXT: [[DIV2:%.*]] = sdiv i32 [[B]], [[A]], !dbg [[DBG95:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i32 [[DIV2]], metadata [[META91:![0-9]+]], metadata !DIExpression()), !dbg [[DBG95]]
; DEBUG-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], 5, !dbg [[DBG96:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META92:![0-9]+]], metadata !DIExpression()), !dbg [[DBG96]]
; DEBUG-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[DIV1]], i32 [[DIV2]], !dbg [[DBG97:![0-9]+]]
; DEBUG-NEXT: call void @llvm.dbg.value(metadata i32 [[SEL]], metadata [[META93:![0-9]+]], metadata !DIExpression()), !dbg [[DBG97]]
; DEBUG-NEXT: ret i32 [[SEL]], !dbg [[DBG98:![0-9]+]]
;
%div1 = sdiv i32 %a, %b %div1 = sdiv i32 %a, %b
%div2 = sdiv i32 %b, %a %div2 = sdiv i32 %b, %a
%cmp = icmp sgt i32 %a, 5 %cmp = icmp sgt i32 %a, 5
%sel = select i1 %cmp, i32 %div1, i32 %div2 %sel = select i1 %cmp, i32 %div1, i32 %div2
ret i32 %sel ret i32 %sel
} }

llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll

Show First 20 Lines • Show All 225 Lines • ▼ Show 20 Lines;
%extract_subv = shufflevector <5 x i8> %shuf, <5 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> %extract_subv = shufflevector <5 x i8> %shuf, <5 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
ret <4 x i8> %extract_subv ret <4 x i8> %extract_subv
} }
define <2 x i8> @test13a(i8 %x1, i8 %x2) { define <2 x i8> @test13a(i8 %x1, i8 %x2) {
; CHECK-LABEL: @test13a( ; CHECK-LABEL: @test13a(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> undef, i8 [[X2:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> undef, i8 [[X2:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X1:%.*]], i64 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X1:%.*]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i8> [[TMP2]], <i8 7, i8 5> ; CHECK-NEXT: [[D:%.*]] = add <2 x i8> [[TMP2]], <i8 7, i8 5>
; CHECK-NEXT: ret <2 x i8> [[TMP3]] ; CHECK-NEXT: ret <2 x i8> [[D]]
; ;
%A = insertelement <2 x i8> poison, i8 %x1, i32 0 %A = insertelement <2 x i8> poison, i8 %x1, i32 0
%B = insertelement <2 x i8> %A, i8 %x2, i32 1 %B = insertelement <2 x i8> %A, i8 %x2, i32 1
%C = add <2 x i8> %B, <i8 5, i8 7> %C = add <2 x i8> %B, <i8 5, i8 7>
%D = shufflevector <2 x i8> %C, <2 x i8> poison, <2 x i32> <i32 1, i32 0> %D = shufflevector <2 x i8> %C, <2 x i8> poison, <2 x i32> <i32 1, i32 0>
ret <2 x i8> %D ret <2 x i8> %D
} }
Show All 31 Lines;
ret <3 x i32> %ext ret <3 x i32> %ext
} }
; Increasing length of insertelements (no math ops) is a good canonicalization. ; Increasing length of insertelements (no math ops) is a good canonicalization.
define <3 x i8> @fold_inselts_with_widening_shuffle(i8 %x, i8 %y) { define <3 x i8> @fold_inselts_with_widening_shuffle(i8 %x, i8 %y) {
; CHECK-LABEL: @fold_inselts_with_widening_shuffle( ; CHECK-LABEL: @fold_inselts_with_widening_shuffle(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i8> undef, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i8> [[TMP1]], i8 [[Y:%.*]], i64 1 ; CHECK-NEXT: [[WIDEN:%.*]] = insertelement <3 x i8> [[TMP1]], i8 [[Y:%.*]], i64 1
; CHECK-NEXT: ret <3 x i8> [[TMP2]] ; CHECK-NEXT: ret <3 x i8> [[WIDEN]]
; ;
%ins0 = insertelement <2 x i8> poison, i8 %x, i32 0 %ins0 = insertelement <2 x i8> poison, i8 %x, i32 0
%ins1 = insertelement <2 x i8> %ins0, i8 %y, i32 1 %ins1 = insertelement <2 x i8> %ins0, i8 %y, i32 1
%widen = shufflevector <2 x i8> %ins1, <2 x i8> poison, <3 x i32> <i32 0, i32 1, i32 undef> %widen = shufflevector <2 x i8> %ins1, <2 x i8> poison, <3 x i32> <i32 0, i32 1, i32 undef>
ret <3 x i8> %widen ret <3 x i8> %widen
} }
define <2 x i8> @test13b(i8 %x) { define <2 x i8> @test13b(i8 %x) {
; CHECK-LABEL: @test13b( ; CHECK-LABEL: @test13b(
; CHECK-NEXT: [[B:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[B:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i64 1
; CHECK-NEXT: ret <2 x i8> [[B]] ; CHECK-NEXT: ret <2 x i8> [[B]]
; ;
%A = insertelement <2 x i8> poison, i8 %x, i32 0 %A = insertelement <2 x i8> poison, i8 %x, i32 0
%B = shufflevector <2 x i8> %A, <2 x i8> poison, <2 x i32> <i32 undef, i32 0> %B = shufflevector <2 x i8> %A, <2 x i8> poison, <2 x i32> <i32 undef, i32 0>
ret <2 x i8> %B ret <2 x i8> %B
} }
define <2 x i8> @test13c(i8 %x1, i8 %x2) { define <2 x i8> @test13c(i8 %x1, i8 %x2) {
; CHECK-LABEL: @test13c( ; CHECK-LABEL: @test13c(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> undef, i8 [[X1:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> undef, i8 [[X1:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X2:%.*]], i64 1 ; CHECK-NEXT: [[C:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X2:%.*]], i64 1
; CHECK-NEXT: ret <2 x i8> [[TMP2]] ; CHECK-NEXT: ret <2 x i8> [[C]]
; ;
%A = insertelement <4 x i8> poison, i8 %x1, i32 0 %A = insertelement <4 x i8> poison, i8 %x1, i32 0
%B = insertelement <4 x i8> %A, i8 %x2, i32 2 %B = insertelement <4 x i8> %A, i8 %x2, i32 2
%C = shufflevector <4 x i8> %B, <4 x i8> poison, <2 x i32> <i32 0, i32 2> %C = shufflevector <4 x i8> %B, <4 x i8> poison, <2 x i32> <i32 0, i32 2>
ret <2 x i8> %C ret <2 x i8> %C
} }
define void @test14(i16 %conv10) { define void @test14(i16 %conv10) {
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines;
%t2 = shufflevector <2 x float> %v2, <2 x float> poison, <2 x i32> <i32 1, i32 0> %t2 = shufflevector <2 x float> %v2, <2 x float> poison, <2 x i32> <i32 1, i32 0>
%r = fadd <2 x float> %t1, %t2 %r = fadd <2 x float> %t1, %t2
call void @use(<2 x float> %t1) call void @use(<2 x float> %t1)
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @shuffle_fdiv_multiuse(<2 x float> %v1, <2 x float> %v2) { define <2 x float> @shuffle_fdiv_multiuse(<2 x float> %v1, <2 x float> %v2) {
; CHECK-LABEL: @shuffle_fdiv_multiuse( ; CHECK-LABEL: @shuffle_fdiv_multiuse(
; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x float> [[V1:%.*]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[T2:%.*]] = shufflevector <2 x float> [[V2:%.*]], <2 x float> poison, <2 x i32> <i32 1, i32 0> ; CHECK-NEXT: [[T2:%.*]] = shufflevector <2 x float> [[V2:%.*]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[TMP1:%.*]] = fdiv <2 x float> [[V1:%.*]], [[V2]] ; CHECK-NEXT: [[R:%.*]] = fdiv <2 x float> [[T1]], [[T2]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: call void @use(<2 x float> [[T2]]) ; CHECK-NEXT: call void @use(<2 x float> [[T2]])
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%t1 = shufflevector <2 x float> %v1, <2 x float> poison, <2 x i32> <i32 1, i32 0> %t1 = shufflevector <2 x float> %v1, <2 x float> poison, <2 x i32> <i32 1, i32 0>
%t2 = shufflevector <2 x float> %v2, <2 x float> poison, <2 x i32> <i32 1, i32 0> %t2 = shufflevector <2 x float> %v2, <2 x float> poison, <2 x i32> <i32 1, i32 0>
%r = fdiv <2 x float> %t1, %t2 %r = fdiv <2 x float> %t1, %t2
call void @use(<2 x float> %t2) call void @use(<2 x float> %t2)
ret <2 x float> %r ret <2 x float> %r
▲ Show 20 Lines • Show All 857 Lines • ▼ Show 20 Lines
; ;
%splat = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> zeroinitializer %splat = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> zeroinitializer
%r = fmul <2 x float> %splat, <float 42.0, float 42.0> %r = fmul <2 x float> %splat, <float 42.0, float 42.0>
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @fdiv_splat_constant0(<2 x float> %x) { define <2 x float> @fdiv_splat_constant0(<2 x float> %x) {
; CHECK-LABEL: @fdiv_splat_constant0( ; CHECK-LABEL: @fdiv_splat_constant0(
; CHECK-NEXT: [[TMP1:%.*]] = fdiv <2 x float> <float 4.200000e+01, float poison>, [[X:%.*]] ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = fdiv <2 x float> <float 4.200000e+01, float 4.200000e+01>, [[SPLAT]]
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%splat = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> zeroinitializer %splat = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> zeroinitializer
%r = fdiv <2 x float> <float 42.0, float 42.0>, %splat %r = fdiv <2 x float> <float 42.0, float 42.0>, %splat
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @fdiv_splat_constant1(<2 x float> %x) { define <2 x float> @fdiv_splat_constant1(<2 x float> %x) {
; CHECK-LABEL: @fdiv_splat_constant1( ; CHECK-LABEL: @fdiv_splat_constant1(
; CHECK-NEXT: [[TMP1:%.*]] = fdiv <2 x float> [[X:%.*]], <float 4.200000e+01, float poison> ; CHECK-NEXT: [[TMP1:%.*]] = fdiv <2 x float> [[X:%.*]], <float 4.200000e+01, float poison>
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%splat = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> zeroinitializer %splat = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> zeroinitializer
%r = fdiv <2 x float> %splat, <float 42.0, float 42.0> %r = fdiv <2 x float> %splat, <float 42.0, float 42.0>
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @frem_splat_constant0(<2 x float> %x) { define <2 x float> @frem_splat_constant0(<2 x float> %x) {
; CHECK-LABEL: @frem_splat_constant0( ; CHECK-LABEL: @frem_splat_constant0(
; CHECK-NEXT: [[TMP1:%.*]] = frem <2 x float> <float 4.200000e+01, float poison>, [[X:%.*]] ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = frem <2 x float> <float 4.200000e+01, float 4.200000e+01>, [[SPLAT]]
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%splat = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> zeroinitializer %splat = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> zeroinitializer
%r = frem <2 x float> <float 42.0, float 42.0>, %splat %r = frem <2 x float> <float 42.0, float 42.0>, %splat
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @frem_splat_constant1(<2 x float> %x) { define <2 x float> @frem_splat_constant1(<2 x float> %x) {
▲ Show 20 Lines • Show All 457 Lines • Show Last 20 Lines

llvm/test/Transforms/InstCombine/vec_shuffle.ll

Show First 20 Lines • Show All 424 Lines • ▼ Show 20 Lines;
%t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0> %t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0>
%r = fadd <2 x float> %t1, %t2 %r = fadd <2 x float> %t1, %t2
call void @use(<2 x float> %t1) call void @use(<2 x float> %t1)
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @shuffle_fdiv_multiuse(<2 x float> %v1, <2 x float> %v2) { define <2 x float> @shuffle_fdiv_multiuse(<2 x float> %v1, <2 x float> %v2) {
; CHECK-LABEL: @shuffle_fdiv_multiuse( ; CHECK-LABEL: @shuffle_fdiv_multiuse(
; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x float> [[V1:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[T2:%.*]] = shufflevector <2 x float> [[V2:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0> ; CHECK-NEXT: [[T2:%.*]] = shufflevector <2 x float> [[V2:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[TMP1:%.*]] = fdiv <2 x float> [[V1:%.*]], [[V2]] ; CHECK-NEXT: [[R:%.*]] = fdiv <2 x float> [[T1]], [[T2]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: call void @use(<2 x float> [[T2]]) ; CHECK-NEXT: call void @use(<2 x float> [[T2]])
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%t1 = shufflevector <2 x float> %v1, <2 x float> undef, <2 x i32> <i32 1, i32 0> %t1 = shufflevector <2 x float> %v1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
%t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0> %t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0>
%r = fdiv <2 x float> %t1, %t2 %r = fdiv <2 x float> %t1, %t2
call void @use(<2 x float> %t2) call void @use(<2 x float> %t2)
ret <2 x float> %r ret <2 x float> %r
▲ Show 20 Lines • Show All 857 Lines • ▼ Show 20 Lines
; ;
%splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
%r = fmul <2 x float> %splat, <float 42.0, float 42.0> %r = fmul <2 x float> %splat, <float 42.0, float 42.0>
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @fdiv_splat_constant0(<2 x float> %x) { define <2 x float> @fdiv_splat_constant0(<2 x float> %x) {
; CHECK-LABEL: @fdiv_splat_constant0( ; CHECK-LABEL: @fdiv_splat_constant0(
; CHECK-NEXT: [[TMP1:%.*]] = fdiv <2 x float> <float 4.200000e+01, float poison>, [[X:%.*]] ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> undef, <2 x i32> zeroinitializer
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = fdiv <2 x float> <float 4.200000e+01, float 4.200000e+01>, [[SPLAT]]
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
%r = fdiv <2 x float> <float 42.0, float 42.0>, %splat %r = fdiv <2 x float> <float 42.0, float 42.0>, %splat
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @fdiv_splat_constant1(<2 x float> %x) { define <2 x float> @fdiv_splat_constant1(<2 x float> %x) {
; CHECK-LABEL: @fdiv_splat_constant1( ; CHECK-LABEL: @fdiv_splat_constant1(
; CHECK-NEXT: [[TMP1:%.*]] = fdiv <2 x float> [[X:%.*]], <float 4.200000e+01, float poison> ; CHECK-NEXT: [[TMP1:%.*]] = fdiv <2 x float> [[X:%.*]], <float 4.200000e+01, float poison>
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
%r = fdiv <2 x float> %splat, <float 42.0, float 42.0> %r = fdiv <2 x float> %splat, <float 42.0, float 42.0>
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @frem_splat_constant0(<2 x float> %x) { define <2 x float> @frem_splat_constant0(<2 x float> %x) {
; CHECK-LABEL: @frem_splat_constant0( ; CHECK-LABEL: @frem_splat_constant0(
; CHECK-NEXT: [[TMP1:%.*]] = frem <2 x float> <float 4.200000e+01, float poison>, [[X:%.*]] ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> undef, <2 x i32> zeroinitializer
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = frem <2 x float> <float 4.200000e+01, float 4.200000e+01>, [[SPLAT]]
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
%r = frem <2 x float> <float 42.0, float 42.0>, %splat %r = frem <2 x float> <float 42.0, float 42.0>, %splat
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @frem_splat_constant1(<2 x float> %x) { define <2 x float> @frem_splat_constant1(<2 x float> %x) {
▲ Show 20 Lines • Show All 994 Lines • Show Last 20 Lines

llvm/test/Transforms/PGOProfile/chr.ll

Show First 20 Lines • Show All 1,110 Lines • ▼ Show 20 Lines
; if ((1.0 / t0) * t0 < 1) // Likely true ; if ((1.0 / t0) * t0 < 1) // Likely true
; foo() ; foo()
; } ; }
define void @test_chr_11(ptr %i, i32 %x) !prof !14 { define void @test_chr_11(ptr %i, i32 %x) !prof !14 {
; CHECK-LABEL: @test_chr_11( ; CHECK-LABEL: @test_chr_11(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 1 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 1
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: br i1 [[TMP2]], label [[BB1:%.*]], label [[BB0:%.*]], !prof [[PROF16]]
; CHECK: bb0:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[BB1]]
; CHECK: bb1:
; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to double ; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to double
; CHECK-NEXT: [[DIV:%.*]] = fdiv double 1.000000e+00, [[CONV]] ; CHECK-NEXT: [[DIV:%.*]] = fdiv double 1.000000e+00, [[CONV]]
; CHECK-NEXT: [[MUL16:%.*]] = fmul double [[DIV]], [[CONV]] ; CHECK-NEXT: [[MUL16:%.*]] = fmul double [[DIV]], [[CONV]]
; CHECK-NEXT: [[CONV717:%.*]] = fptosi double [[MUL16]] to i32 ; CHECK-NEXT: [[CONV717:%.*]] = fptosi double [[MUL16]] to i32
; CHECK-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[CONV717]], 0 ; CHECK-NEXT: [[CMP18:%.*]] = icmp slt i32 [[CONV717]], 1
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i1 [[CMP18]], i1 false ; CHECK-NEXT: br i1 [[CMP18]], label [[BB3:%.*]], label [[BB2:%.*]], !prof [[PROF16]]
; CHECK-NEXT: br i1 [[TMP3]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]] ; CHECK: bb2:
; CHECK: bb0:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: entry.split.nonchr:
; CHECK-NEXT: br i1 [[TMP2]], label [[BB0_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF18:![0-9]+]]
; CHECK: bb0.nonchr:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[BB1_NONCHR]]
; CHECK: bb1.nonchr:
; CHECK-NEXT: [[CONV_NONCHR:%.*]] = sitofp i32 [[TMP0]] to double
; CHECK-NEXT: [[DIV_NONCHR:%.*]] = fdiv double 1.000000e+00, [[CONV_NONCHR]]
; CHECK-NEXT: [[MUL16_NONCHR:%.*]] = fmul double [[DIV_NONCHR]], [[CONV_NONCHR]]
; CHECK-NEXT: [[CONV717_NONCHR:%.*]] = fptosi double [[MUL16_NONCHR]] to i32
; CHECK-NEXT: [[CMP18_NONCHR:%.*]] = icmp slt i32 [[CONV717_NONCHR]], 1
; CHECK-NEXT: br i1 [[CMP18_NONCHR]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
; CHECK: bb2.nonchr:
; CHECK-NEXT: call void @foo() ; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[BB3]] ; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%0 = load i32, ptr %i %0 = load i32, ptr %i
%1 = and i32 %0, 1 %1 = and i32 %0, 1
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[TMP11:%.*]] = and i32 [[DOTFR1]], 8 ; CHECK-NEXT: [[TMP11:%.*]] = and i32 [[DOTFR1]], 8
; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 ; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
; CHECK-NEXT: [[TMP13:%.*]] = and i1 [[TMP10]], [[TMP12]] ; CHECK-NEXT: [[TMP13:%.*]] = and i1 [[TMP10]], [[TMP12]]
; CHECK-NEXT: br i1 [[TMP13]], label [[BB1:%.*]], label [[BB0_SPLIT_NONCHR:%.*]], !prof [[PROF15]] ; CHECK-NEXT: br i1 [[TMP13]], label [[BB1:%.*]], label [[BB0_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[SUM2]], 88 ; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[SUM2]], 88
; CHECK-NEXT: br label [[BB3]] ; CHECK-NEXT: br label [[BB3]]
; CHECK: bb0.split.nonchr: ; CHECK: bb0.split.nonchr:
; CHECK-NEXT: br i1 [[TMP10]], label [[BB1_NONCHR:%.*]], label [[BB3]], !prof [[PROF18]] ; CHECK-NEXT: br i1 [[TMP10]], label [[BB1_NONCHR:%.*]], label [[BB3]], !prof [[PROF18:![0-9]+]]
; CHECK: bb1.nonchr: ; CHECK: bb1.nonchr:
; CHECK-NEXT: [[TMP15:%.*]] = and i32 [[DOTFR1]], 8 ; CHECK-NEXT: [[TMP15:%.*]] = and i32 [[DOTFR1]], 8
; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0 ; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0
; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP16]], i32 44, i32 88, !prof [[PROF16]] ; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP16]], i32 44, i32 88, !prof [[PROF16]]
; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2]], [[SUM4_NONCHR_V]] ; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2]], [[SUM4_NONCHR_V]]
; CHECK-NEXT: br label [[BB3]] ; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[SUM0]], [[ENTRY:%.*]] ], [ [[TMP14]], [[BB1]] ], [ [[SUM2]], [[BB0_SPLIT_NONCHR]] ], [ [[SUM4_NONCHR]], [[BB1_NONCHR]] ] ; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[SUM0]], [[ENTRY:%.*]] ], [ [[TMP14]], [[BB1]] ], [ [[SUM2]], [[BB0_SPLIT_NONCHR]] ], [ [[SUM4_NONCHR]], [[BB1_NONCHR]] ]
▲ Show 20 Lines • Show All 1,473 Lines • Show Last 20 Lines

llvm/test/Transforms/Reassociate/2019-08-22-FNegAssert.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=reassociate -S | FileCheck %s ; RUN: opt < %s -passes=reassociate -S | FileCheck %s
; D61675 ; D61675
define float @test1(float %arg, float %arg1, float %arg2, float %arg3) { define float @test1(float %arg, float %arg1, float %arg2, float %arg3) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: [[TMP5:%.*]] = fneg fast float [[ARG:%.*]] ; CHECK-NEXT: [[TMP5:%.*]] = fneg fast float [[ARG:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = fsub fast float [[ARG3:%.*]], [[ARG2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = fsub fast float [[ARG3:%.*]], [[ARG2:%.*]]
; CHECK-NEXT: [[TMP2_NEG:%.*]] = fadd fast float [[TMP5]], 5.000000e+02 ; CHECK-NEXT: [[TMP2_NEG:%.*]] = fadd fast float [[TMP5]], 5.000000e+02
; CHECK-NEXT: [[TMP3:%.*]] = fadd fast float [[TMP2_NEG]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = fadd fast float [[TMP2_NEG]], [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = fmul fast float [[TMP3]], [[TMP3]] ; CHECK-NEXT: [[TMP4:%.*]] = fmul fast float [[TMP3]], [[TMP3]]
; CHECK-NEXT: [[TMP6:%.*]] = fdiv fast float [[TMP5]], [[ARG1:%.*]] ; CHECK-NEXT: [[TMP6:%.*]] = fdiv fast float [[TMP5]], [[ARG1:%.*]]
; CHECK-NEXT: [[TMP7:%.*]] = fadd fast float [[TMP4]], [[TMP6]] ; CHECK-NEXT: [[TMP7:%.*]] = fadd fast float [[TMP6]], [[TMP4]]
; CHECK-NEXT: ret float [[TMP7]] ; CHECK-NEXT: ret float [[TMP7]]
; ;
%tmp1 = fsub fast float %arg3, %arg2 %tmp1 = fsub fast float %arg3, %arg2
%tmp2 = fadd fast float %arg, -5.000000e+02 %tmp2 = fadd fast float %arg, -5.000000e+02
%tmp3 = fsub fast float %tmp1, %tmp2 %tmp3 = fsub fast float %tmp1, %tmp2
%tmp4 = fmul fast float %tmp3, %tmp3 %tmp4 = fmul fast float %tmp3, %tmp3
%tmp5 = fneg fast float %arg %tmp5 = fneg fast float %arg
%tmp6 = fdiv fast float %tmp5, %arg1 %tmp6 = fdiv fast float %tmp5, %arg1
%tmp7 = fadd fast float %tmp6, %tmp4 %tmp7 = fadd fast float %tmp6, %tmp4
ret float %tmp7 ret float %tmp7
} }

llvm/test/Transforms/Reassociate/canonicalize-neg-const.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=reassociate,gvn -S < %s | FileCheck %s ; RUN: opt -passes=reassociate,gvn -S < %s | FileCheck %s
; (x + 0.1234 * y) * (x + -0.1234 * y) -> (x + 0.1234 * y) * (x - 0.1234 * y) ; (x + 0.1234 * y) * (x + -0.1234 * y) -> (x + 0.1234 * y) * (x - 0.1234 * y)
define double @test1(double %x, double %y) { define double @test1(double %x, double %y) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: [[MUL:%.*]] = fmul double [[Y:%.*]], 1.234000e-01 ; CHECK-NEXT: [[MUL:%.*]] = fmul double [[Y:%.*]], 1.234000e-01
; CHECK-NEXT: [[ADD:%.*]] = fadd double [[X:%.*]], [[MUL]] ; CHECK-NEXT: [[ADD:%.*]] = fadd double [[X:%.*]], [[MUL]]
; CHECK-NEXT: [[ADD21:%.*]] = fsub double [[X]], [[MUL]] ; CHECK-NEXT: [[TMP1:%.*]] = fsub double [[X]], [[MUL]]
; CHECK-NEXT: [[MUL3:%.*]] = fmul double [[ADD]], [[ADD21]] ; CHECK-NEXT: [[MUL3:%.*]] = fmul double [[ADD]], [[TMP1]]
; CHECK-NEXT: ret double [[MUL3]] ; CHECK-NEXT: ret double [[MUL3]]
; ;
%mul = fmul double 1.234000e-01, %y %mul = fmul double 1.234000e-01, %y
%add = fadd double %mul, %x %add = fadd double %mul, %x
%mul1 = fmul double -1.234000e-01, %y %mul1 = fmul double -1.234000e-01, %y
%add2 = fadd double %mul1, %x %add2 = fadd double %mul1, %x
%mul3 = fmul double %add, %add2 %mul3 = fmul double %add, %add2
ret double %mul3 ret double %mul3
} }
; (x + -0.1234 * y) * (x + -0.1234 * y) -> (x - 0.1234 * y) * (x - 0.1234 * y) ; (x + -0.1234 * y) * (x + -0.1234 * y) -> (x - 0.1234 * y) * (x - 0.1234 * y)
define double @test2(double %x, double %y) { define double @test2(double %x, double %y) {
; CHECK-LABEL: @test2( ; CHECK-LABEL: @test2(
; CHECK-NEXT: [[MUL:%.*]] = fmul double [[Y:%.*]], 1.234000e-01 ; CHECK-NEXT: [[MUL:%.*]] = fmul double [[Y:%.*]], 1.234000e-01
; CHECK-NEXT: [[ADD1:%.*]] = fsub double [[X:%.*]], [[MUL]] ; CHECK-NEXT: [[TMP1:%.*]] = fsub double [[X:%.*]], [[MUL]]
; CHECK-NEXT: [[MUL3:%.*]] = fmul double [[ADD1]], [[ADD1]] ; CHECK-NEXT: [[MUL3:%.*]] = fmul double [[TMP1]], [[TMP1]]
; CHECK-NEXT: ret double [[MUL3]] ; CHECK-NEXT: ret double [[MUL3]]
; ;
%mul = fmul double %y, -1.234000e-01 %mul = fmul double %y, -1.234000e-01
%add = fadd double %mul, %x %add = fadd double %mul, %x
%mul1 = fmul double %y, -1.234000e-01 %mul1 = fmul double %y, -1.234000e-01
%add2 = fadd double %mul1, %x %add2 = fadd double %mul1, %x
%mul3 = fmul double %add, %add2 %mul3 = fmul double %add, %add2
ret double %mul3 ret double %mul3
Show All 14 Lines;
%mul3 = fmul double %add, %add2 %mul3 = fmul double %add, %add2
ret double %mul3 ret double %mul3
} }
; Canonicalize (x - -0.1234 * y) ; Canonicalize (x - -0.1234 * y)
define double @test5(double %x, double %y) { define double @test5(double %x, double %y) {
; CHECK-LABEL: @test5( ; CHECK-LABEL: @test5(
; CHECK-NEXT: [[MUL:%.*]] = fmul double [[Y:%.*]], 1.234000e-01 ; CHECK-NEXT: [[MUL:%.*]] = fmul double [[Y:%.*]], 1.234000e-01
; CHECK-NEXT: [[SUB1:%.*]] = fadd double [[X:%.*]], [[MUL]] ; CHECK-NEXT: [[TMP1:%.*]] = fadd double [[X:%.*]], [[MUL]]
; CHECK-NEXT: ret double [[SUB1]] ; CHECK-NEXT: ret double [[TMP1]]
; ;
%mul = fmul double -1.234000e-01, %y %mul = fmul double -1.234000e-01, %y
%sub = fsub double %x, %mul %sub = fsub double %x, %mul
ret double %sub ret double %sub
} }
; Don't modify (-0.1234 * y - x) ; Don't modify (-0.1234 * y - x)
define double @test6(double %x, double %y) { define double @test6(double %x, double %y) {
; CHECK-LABEL: @test6( ; CHECK-LABEL: @test6(
; CHECK-NEXT: [[MUL:%.*]] = fmul double [[Y:%.*]], -1.234000e-01 ; CHECK-NEXT: [[MUL:%.*]] = fmul double [[Y:%.*]], -1.234000e-01
; CHECK-NEXT: [[SUB:%.*]] = fsub double [[MUL]], [[X:%.*]] ; CHECK-NEXT: [[SUB:%.*]] = fsub double [[MUL]], [[X:%.*]]
; CHECK-NEXT: ret double [[SUB]] ; CHECK-NEXT: ret double [[SUB]]
; ;
%mul = fmul double -1.234000e-01, %y %mul = fmul double -1.234000e-01, %y
%sub = fsub double %mul, %x %sub = fsub double %mul, %x
ret double %sub ret double %sub
} }
; Canonicalize (-0.1234 * y + x) -> (x - 0.1234 * y) ; Canonicalize (-0.1234 * y + x) -> (x - 0.1234 * y)
define double @test7(double %x, double %y) { define double @test7(double %x, double %y) {
; CHECK-LABEL: @test7( ; CHECK-LABEL: @test7(
; CHECK-NEXT: [[MUL:%.*]] = fmul double [[Y:%.*]], 1.234000e-01 ; CHECK-NEXT: [[MUL:%.*]] = fmul double [[Y:%.*]], 1.234000e-01
; CHECK-NEXT: [[ADD1:%.*]] = fsub double [[X:%.*]], [[MUL]] ; CHECK-NEXT: [[TMP1:%.*]] = fsub double [[X:%.*]], [[MUL]]
; CHECK-NEXT: ret double [[ADD1]] ; CHECK-NEXT: ret double [[TMP1]]
; ;
%mul = fmul double -1.234000e-01, %y %mul = fmul double -1.234000e-01, %y
%add = fadd double %mul, %x %add = fadd double %mul, %x
ret double %add ret double %add
} }
; Canonicalize (y * -0.1234 + x) -> (x - 0.1234 * y) ; Canonicalize (y * -0.1234 + x) -> (x - 0.1234 * y)
define double @test8(double %x, double %y) { define double @test8(double %x, double %y) {
; CHECK-LABEL: @test8( ; CHECK-LABEL: @test8(
; CHECK-NEXT: [[MUL:%.*]] = fmul double [[Y:%.*]], 1.234000e-01 ; CHECK-NEXT: [[MUL:%.*]] = fmul double [[Y:%.*]], 1.234000e-01
; CHECK-NEXT: [[ADD1:%.*]] = fsub double [[X:%.*]], [[MUL]] ; CHECK-NEXT: [[TMP1:%.*]] = fsub double [[X:%.*]], [[MUL]]
; CHECK-NEXT: ret double [[ADD1]] ; CHECK-NEXT: ret double [[TMP1]]
; ;
%mul = fmul double %y, -1.234000e-01 %mul = fmul double %y, -1.234000e-01
%add = fadd double %mul, %x %add = fadd double %mul, %x
ret double %add ret double %add
} }
; Canonicalize (x - -0.1234 / y) ; Canonicalize (x - -0.1234 / y)
define double @test9(double %x, double %y) { define double @test9(double %x, double %y) {
; CHECK-LABEL: @test9( ; CHECK-LABEL: @test9(
; CHECK-NEXT: [[DIV:%.*]] = fdiv double 1.234000e-01, [[Y:%.*]] ; CHECK-NEXT: [[DIV:%.*]] = fdiv double 1.234000e-01, [[Y:%.*]]
; CHECK-NEXT: [[SUB1:%.*]] = fadd double [[X:%.*]], [[DIV]] ; CHECK-NEXT: [[TMP1:%.*]] = fadd double [[X:%.*]], [[DIV]]
; CHECK-NEXT: ret double [[SUB1]] ; CHECK-NEXT: ret double [[TMP1]]
; ;
%div = fdiv double -1.234000e-01, %y %div = fdiv double -1.234000e-01, %y
%sub = fsub double %x, %div %sub = fsub double %x, %div
ret double %sub ret double %sub
} }
; Don't modify (-0.1234 / y - x) ; Don't modify (-0.1234 / y - x)
define double @test10(double %x, double %y) { define double @test10(double %x, double %y) {
; CHECK-LABEL: @test10( ; CHECK-LABEL: @test10(
; CHECK-NEXT: [[DIV:%.*]] = fdiv double -1.234000e-01, [[Y:%.*]] ; CHECK-NEXT: [[DIV:%.*]] = fdiv double -1.234000e-01, [[Y:%.*]]
; CHECK-NEXT: [[SUB:%.*]] = fsub double [[DIV]], [[X:%.*]] ; CHECK-NEXT: [[SUB:%.*]] = fsub double [[DIV]], [[X:%.*]]
; CHECK-NEXT: ret double [[SUB]] ; CHECK-NEXT: ret double [[SUB]]
; ;
%div = fdiv double -1.234000e-01, %y %div = fdiv double -1.234000e-01, %y
%sub = fsub double %div, %x %sub = fsub double %div, %x
ret double %sub ret double %sub
} }
; Canonicalize (-0.1234 / y + x) -> (x - 0.1234 / y) ; Canonicalize (-0.1234 / y + x) -> (x - 0.1234 / y)
define double @test11(double %x, double %y) { define double @test11(double %x, double %y) {
; CHECK-LABEL: @test11( ; CHECK-LABEL: @test11(
; CHECK-NEXT: [[DIV:%.*]] = fdiv double 1.234000e-01, [[Y:%.*]] ; CHECK-NEXT: [[DIV:%.*]] = fdiv double 1.234000e-01, [[Y:%.*]]
; CHECK-NEXT: [[ADD1:%.*]] = fsub double [[X:%.*]], [[DIV]] ; CHECK-NEXT: [[TMP1:%.*]] = fsub double [[X:%.*]], [[DIV]]
; CHECK-NEXT: ret double [[ADD1]] ; CHECK-NEXT: ret double [[TMP1]]
; ;
%div = fdiv double -1.234000e-01, %y %div = fdiv double -1.234000e-01, %y
%add = fadd double %div, %x %add = fadd double %div, %x
ret double %add ret double %add
} }
; Canonicalize (y / -0.1234 + x) -> (x - y / 0.1234) ; Canonicalize (y / -0.1234 + x) -> (x - y / 0.1234)
define double @test12(double %x, double %y) { define double @test12(double %x, double %y) {
; CHECK-LABEL: @test12( ; CHECK-LABEL: @test12(
; CHECK-NEXT: [[DIV:%.*]] = fdiv double [[Y:%.*]], 1.234000e-01 ; CHECK-NEXT: [[DIV:%.*]] = fdiv double [[Y:%.*]], 1.234000e-01
; CHECK-NEXT: [[ADD1:%.*]] = fsub double [[X:%.*]], [[DIV]] ; CHECK-NEXT: [[TMP1:%.*]] = fsub double [[X:%.*]], [[DIV]]
; CHECK-NEXT: ret double [[ADD1]] ; CHECK-NEXT: ret double [[TMP1]]
; ;
%div = fdiv double %y, -1.234000e-01 %div = fdiv double %y, -1.234000e-01
%add = fadd double %div, %x %add = fadd double %div, %x
ret double %add ret double %add
} }
; Don't create an NSW violation ; Don't create an NSW violation
define i4 @test13(i4 %x) { define i4 @test13(i4 %x) {
▲ Show 20 Lines • Show All 225 Lines • ▼ Show 20 Lines;
%div1 = fdiv double %mul0, %c %div1 = fdiv double %mul0, %c
%add = fadd double %div1, %a %add = fadd double %div1, %a
ret double %add ret double %add
} }
define double @fadd_mix_neg_const2(double %a, double %b, double %c) { define double @fadd_mix_neg_const2(double %a, double %b, double %c) {
; CHECK-LABEL: @fadd_mix_neg_const2( ; CHECK-LABEL: @fadd_mix_neg_const2(
; CHECK-NEXT: [[DIV0:%.*]] = fdiv double 3.000000e+00, [[A:%.*]] ; CHECK-NEXT: [[DIV0:%.*]] = fdiv double 3.000000e+00, [[A:%.*]]
; CHECK-NEXT: [[MUL1:%.*]] = fmul double [[DIV0]], [[B:%.*]] ; CHECK-NEXT: [[MUL1:%.*]] = fmul double [[B:%.*]], [[DIV0]]
; CHECK-NEXT: [[DIV2:%.*]] = fdiv double [[MUL1]], 5.000000e+00 ; CHECK-NEXT: [[DIV2:%.*]] = fdiv double [[MUL1]], 5.000000e+00
; CHECK-NEXT: [[ADD:%.*]] = fadd double [[A]], [[DIV2]] ; CHECK-NEXT: [[ADD:%.*]] = fadd double [[A]], [[DIV2]]
; CHECK-NEXT: ret double [[ADD]] ; CHECK-NEXT: ret double [[ADD]]
; ;
%div0 = fdiv double -3.0, %a %div0 = fdiv double -3.0, %a
%mul1 = fmul double %div0, %b %mul1 = fmul double %div0, %b
%div2 = fdiv double %mul1, -5.0 %div2 = fdiv double %mul1, -5.0
%add = fadd double %div2, %a %add = fadd double %div2, %a
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines;
%mul2 = fmul double %div1, -5.0 %mul2 = fmul double %div1, -5.0
%sub = fsub double %a, %mul2 %sub = fsub double %a, %mul2
ret double %sub ret double %sub
} }
define double @fsub_mix_neg_const3(double %a, double %b, double %c) { define double @fsub_mix_neg_const3(double %a, double %b, double %c) {
; CHECK-LABEL: @fsub_mix_neg_const3( ; CHECK-LABEL: @fsub_mix_neg_const3(
; CHECK-NEXT: [[DIV0:%.*]] = fdiv double 3.000000e+00, [[A:%.*]] ; CHECK-NEXT: [[DIV0:%.*]] = fdiv double 3.000000e+00, [[A:%.*]]
; CHECK-NEXT: [[MUL1:%.*]] = fmul double [[DIV0]], [[B:%.*]] ; CHECK-NEXT: [[MUL1:%.*]] = fmul double [[B:%.*]], [[DIV0]]
; CHECK-NEXT: [[DIV2:%.*]] = fdiv double [[MUL1]], 7.000000e+00 ; CHECK-NEXT: [[DIV2:%.*]] = fdiv double [[MUL1]], 7.000000e+00
; CHECK-NEXT: [[MUL3:%.*]] = fmul double [[DIV2]], 5.000000e+00 ; CHECK-NEXT: [[MUL3:%.*]] = fmul double [[DIV2]], 5.000000e+00
; CHECK-NEXT: [[TMP1:%.*]] = fadd double [[C:%.*]], [[MUL3]] ; CHECK-NEXT: [[TMP1:%.*]] = fadd double [[C:%.*]], [[MUL3]]
; CHECK-NEXT: ret double [[TMP1]] ; CHECK-NEXT: ret double [[TMP1]]
; ;
%div0 = fdiv double -3.0, %a %div0 = fdiv double -3.0, %a
%mul1 = fmul double %div0, %b %mul1 = fmul double %div0, %b
%div2 = fdiv double %mul1, -7.0 %div2 = fdiv double %mul1, -7.0
Show All 17 Lines;
%div3 = fdiv double %mul2, %c %div3 = fdiv double %mul2, %c
%add = fadd double %div1, %div3 %add = fadd double %div1, %div3
ret double %add ret double %add
} }
define double @fadd_both_ops_mix_neg_const2(double %a, double %b, double %c) { define double @fadd_both_ops_mix_neg_const2(double %a, double %b, double %c) {
; CHECK-LABEL: @fadd_both_ops_mix_neg_const2( ; CHECK-LABEL: @fadd_both_ops_mix_neg_const2(
; CHECK-NEXT: [[DIV0:%.*]] = fdiv double 3.000000e+00, [[A:%.*]] ; CHECK-NEXT: [[DIV0:%.*]] = fdiv double 3.000000e+00, [[A:%.*]]
; CHECK-NEXT: [[MUL1:%.*]] = fmul double [[DIV0]], [[B:%.*]] ; CHECK-NEXT: [[MUL1:%.*]] = fmul double [[B:%.*]], [[DIV0]]
; CHECK-NEXT: [[DIV2:%.*]] = fdiv double [[MUL1]], 7.000000e+00 ; CHECK-NEXT: [[DIV2:%.*]] = fdiv double [[MUL1]], 7.000000e+00
; CHECK-NEXT: [[DIV3:%.*]] = fdiv double 5.000000e+00, [[C:%.*]] ; CHECK-NEXT: [[DIV3:%.*]] = fdiv double 5.000000e+00, [[C:%.*]]
; CHECK-NEXT: [[MUL4:%.*]] = fmul double [[B]], [[DIV3]] ; CHECK-NEXT: [[MUL4:%.*]] = fmul double [[B]], [[DIV3]]
; CHECK-NEXT: [[DIV5:%.*]] = fdiv double [[MUL4]], 6.000000e+00 ; CHECK-NEXT: [[DIV5:%.*]] = fdiv double [[MUL4]], 6.000000e+00
; CHECK-NEXT: [[ADD:%.*]] = fadd double [[DIV2]], [[DIV5]] ; CHECK-NEXT: [[ADD:%.*]] = fadd double [[DIV2]], [[DIV5]]
; CHECK-NEXT: ret double [[ADD]] ; CHECK-NEXT: ret double [[ADD]]
; ;
%div0 = fdiv double -3.0, %a %div0 = fdiv double -3.0, %a
Show All 33 Lines

llvm/test/Transforms/SLPVectorizer/X86/crash_exceed_scheduling.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=slp-vectorizer -slp-min-tree-size=2 -slp-threshold=-1000 -slp-max-look-ahead-depth=1 -slp-schedule-budget=27 -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; RUN: opt < %s -passes=slp-vectorizer -slp-min-tree-size=2 -slp-threshold=-1000 -slp-max-look-ahead-depth=1 -slp-schedule-budget=27 -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
define void @exceed(double %0, double %1) { define void @exceed(double %0, double %1) {
; CHECK-LABEL: @exceed( ; CHECK-LABEL: @exceed(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i32 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[TMP1:%.*]], i32 0
; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = fdiv fast <2 x double> [[SHUFFLE]], [[SHUFFLE1]]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
; CHECK-NEXT: [[IX:%.*]] = fmul double [[TMP5]], undef
; CHECK-NEXT: [[IXX0:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX0:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX1:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX1:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX2:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX2:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX3:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX3:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX4:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX4:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX5:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX5:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IX1:%.*]] = fmul double [[TMP5]], undef
; CHECK-NEXT: [[IXX10:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX10:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX11:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX11:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX12:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX12:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX13:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX13:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX14:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX14:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX15:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX15:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX20:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX20:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX21:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX21:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[IXX22:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX22:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i32 0 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i32 0
; CHECK-NEXT: [[IX2:%.*]] = fmul double [[TMP6]], [[TMP6]] ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = fadd fast <2 x double> [[SHUFFLE]], [[SHUFFLE1]] ; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[TMP1:%.*]], i32 0
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x double> [[TMP2]], double [[TMP1]], i32 1 ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP9:%.*]] = fadd fast <2 x double> [[TMP4]], [[TMP8]] ; CHECK-NEXT: [[TMP6:%.*]] = fadd fast <2 x double> [[TMP3]], [[TMP5]]
; CHECK-NEXT: [[TMP10:%.*]] = fmul fast <2 x double> [[TMP9]], [[TMP7]] ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast <2 x double> [[TMP3]], [[TMP5]]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP7]], i32 1
; CHECK-NEXT: [[IX:%.*]] = fmul double [[TMP8]], undef
; CHECK-NEXT: [[IX1:%.*]] = fmul double [[TMP8]], undef
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP7]], i32 0
; CHECK-NEXT: [[IX2:%.*]] = fmul double [[TMP9]], [[TMP9]]
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x double> [[TMP2]], double [[TMP1]], i32 1
; CHECK-NEXT: [[TMP11:%.*]] = fadd fast <2 x double> [[TMP7]], [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = fmul fast <2 x double> [[TMP11]], [[TMP6]]
; CHECK-NEXT: [[IXX101:%.*]] = fsub double undef, undef ; CHECK-NEXT: [[IXX101:%.*]] = fsub double undef, undef
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x double> poison, double [[TMP1]], i32 1 ; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x double> poison, double [[TMP1]], i32 1
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x double> [[TMP11]], <2 x double> [[TMP4]], <2 x i32> <i32 3, i32 1> ; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x double> [[TMP13]], <2 x double> [[TMP7]], <2 x i32> <i32 3, i32 1>
; CHECK-NEXT: [[TMP13:%.*]] = fmul fast <2 x double> [[TMP12]], undef ; CHECK-NEXT: [[TMP15:%.*]] = fmul fast <2 x double> [[TMP14]], undef
; CHECK-NEXT: switch i32 undef, label [[BB1:%.*]] [ ; CHECK-NEXT: switch i32 undef, label [[BB1:%.*]] [
; CHECK-NEXT: i32 0, label [[BB2:%.*]] ; CHECK-NEXT: i32 0, label [[BB2:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: br label [[LABEL:%.*]] ; CHECK-NEXT: br label [[LABEL:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br label [[LABEL]] ; CHECK-NEXT: br label [[LABEL]]
; CHECK: label: ; CHECK: label:
; CHECK-NEXT: [[TMP14:%.*]] = phi <2 x double> [ [[TMP10]], [[BB1]] ], [ [[TMP13]], [[BB2]] ] ; CHECK-NEXT: [[TMP16:%.*]] = phi <2 x double> [ [[TMP12]], [[BB1]] ], [ [[TMP15]], [[BB2]] ]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%i10 = fdiv fast double %0, %1 %i10 = fdiv fast double %0, %1
%ix = fmul double %i10, undef %ix = fmul double %i10, undef
%ixx0 = fsub double undef, undef %ixx0 = fsub double undef, undef
%ixx1 = fsub double undef, undef %ixx1 = fsub double undef, undef
%ixx2 = fsub double undef, undef %ixx2 = fsub double undef, undef
Show All 39 Lines

llvm/test/Transforms/SLPVectorizer/X86/reuse-extracts-in-wider-vect.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux -mcpu=core-avx2 | FileCheck %s ; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux -mcpu=core-avx2 | FileCheck %s
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
%struct.S = type { [3 x float], [3 x float], [4 x float] } %struct.S = type { [3 x float], [3 x float], [4 x float] }
define i32 @foo(i32 %0, ptr %1, ptr %2) { define i32 @foo(i32 %0, ptr %1, ptr %2) {
; CHECK-LABEL: @foo( ; CHECK-LABEL: @foo(
; CHECK-NEXT: [[T4:%.*]] = alloca [[STRUCT_S:%.*]], align 8 ; CHECK-NEXT: [[T4:%.*]] = alloca [[STRUCT_S:%.*]], align 8
; CHECK-NEXT: [[T8:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[T4]], i64 0, i32 1 ; CHECK-NEXT: [[T8:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[T4]], i64 0, i32 1
; CHECK-NEXT: [[T9:%.*]] = getelementptr inbounds [3 x float], ptr [[T8]], i64 1, i64 0 ; CHECK-NEXT: [[T9:%.*]] = getelementptr inbounds [3 x float], ptr [[T8]], i64 1, i64 0
; CHECK-NEXT: [[T14:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[T4]], i64 0, i32 1, i64 0 ; CHECK-NEXT: [[T14:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[T4]], i64 0, i32 1, i64 0
; CHECK-NEXT: [[TMP5:%.*]] = load <2 x float>, ptr [[T14]], align 4 ; CHECK-NEXT: [[TMP4:%.*]] = load <2 x float>, ptr [[T14]], align 4
; CHECK-NEXT: br label [[T37:%.*]] ; CHECK-NEXT: br label [[T37:%.*]]
; CHECK: t37: ; CHECK: t37:
; CHECK-NEXT: [[TMP6:%.*]] = phi <2 x float> [ [[TMP5]], [[TMP3:%.*]] ], [ [[T89:%.*]], [[T37]] ] ; CHECK-NEXT: [[TMP5:%.*]] = phi <2 x float> [ [[TMP4]], [[TMP3:%.*]] ], [ [[T89:%.*]], [[T37]] ]
; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast <2 x float> <float 1.000000e+00, float 1.000000e+00>, [[TMP6]]
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x float> [[TMP7]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[T21:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[T4]], i64 0, i32 2, i64 0 ; CHECK-NEXT: [[T21:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[T4]], i64 0, i32 2, i64 0
; CHECK-NEXT: store <4 x float> [[SHUFFLE]], ptr [[T21]], align 4 ; CHECK-NEXT: [[TMP6:%.*]] = fdiv fast <2 x float> <float 1.000000e+00, float 1.000000e+00>, [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; CHECK-NEXT: store <4 x float> [[TMP7]], ptr [[T21]], align 4
; CHECK-NEXT: [[T89]] = load <2 x float>, ptr [[T9]], align 4 ; CHECK-NEXT: [[T89]] = load <2 x float>, ptr [[T9]], align 4
; CHECK-NEXT: br i1 undef, label [[T37]], label [[T55:%.*]] ; CHECK-NEXT: br i1 undef, label [[T37]], label [[T55:%.*]]
; CHECK: t55: ; CHECK: t55:
; CHECK-NEXT: ret i32 0 ; CHECK-NEXT: ret i32 0
; ;
%t4 = alloca %struct.S, align 8 %t4 = alloca %struct.S, align 8
%t8 = getelementptr inbounds %struct.S, ptr %t4, i64 0, i32 1 %t8 = getelementptr inbounds %struct.S, ptr %t4, i64 0, i32 1
%t9 = getelementptr inbounds [3 x float], ptr %t8, i64 1, i64 0 %t9 = getelementptr inbounds [3 x float], ptr %t8, i64 1, i64 0
Show All 31 Lines

llvm/test/Transforms/SimplifyCFG/ARM/speculate-math.ll

Show All 10 Lines
declare float @llvm.maxnum.f32(float, float) nounwind readonly declare float @llvm.maxnum.f32(float, float) nounwind readonly
declare float @llvm.minimum.f32(float, float) nounwind readonly declare float @llvm.minimum.f32(float, float) nounwind readonly
declare float @llvm.maximum.f32(float, float) nounwind readonly declare float @llvm.maximum.f32(float, float) nounwind readonly
define double @fdiv_test(double %a, double %b) { define double @fdiv_test(double %a, double %b) {
; CHECK-MVE-LABEL: @fdiv_test( ; CHECK-MVE-LABEL: @fdiv_test(
; CHECK-MVE-NEXT: entry: ; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00 ; CHECK-MVE-NEXT: [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_END:%.*]]
; CHECK-MVE: cond.true:
; CHECK-MVE-NEXT: [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]] ; CHECK-MVE-NEXT: [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]]
; CHECK-MVE-NEXT: [[COND:%.*]] = select nsz i1 [[CMP]], double [[DIV]], double 0.000000e+00 ; CHECK-MVE-NEXT: br label [[COND_END]]
; CHECK-MVE: cond.end:
; CHECK-MVE-NEXT: [[COND:%.*]] = phi nsz double [ [[DIV]], [[COND_TRUE]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; CHECK-MVE-NEXT: ret double [[COND]] ; CHECK-MVE-NEXT: ret double [[COND]]
; ;
; CHECK-V8M-MAIN-LABEL: @fdiv_test( ; CHECK-V8M-MAIN-LABEL: @fdiv_test(
; CHECK-V8M-MAIN-NEXT: entry: ; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00 ; CHECK-V8M-MAIN-NEXT: [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_END:%.*]]
; CHECK-V8M-MAIN: cond.true:
; CHECK-V8M-MAIN-NEXT: [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]] ; CHECK-V8M-MAIN-NEXT: [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]]
; CHECK-V8M-MAIN-NEXT: [[COND:%.*]] = select nsz i1 [[CMP]], double [[DIV]], double 0.000000e+00 ; CHECK-V8M-MAIN-NEXT: br label [[COND_END]]
; CHECK-V8M-MAIN: cond.end:
; CHECK-V8M-MAIN-NEXT: [[COND:%.*]] = phi nsz double [ [[DIV]], [[COND_TRUE]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; CHECK-V8M-MAIN-NEXT: ret double [[COND]] ; CHECK-V8M-MAIN-NEXT: ret double [[COND]]
; ;
; CHECK-V8M-BASE-LABEL: @fdiv_test( ; CHECK-V8M-BASE-LABEL: @fdiv_test(
; CHECK-V8M-BASE-NEXT: entry: ; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00 ; CHECK-V8M-BASE-NEXT: [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_END:%.*]]
; CHECK-V8M-BASE: cond.true:
; CHECK-V8M-BASE-NEXT: [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]] ; CHECK-V8M-BASE-NEXT: [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]]
; CHECK-V8M-BASE-NEXT: [[COND:%.*]] = select nsz i1 [[CMP]], double [[DIV]], double 0.000000e+00 ; CHECK-V8M-BASE-NEXT: br label [[COND_END]]
; CHECK-V8M-BASE: cond.end:
; CHECK-V8M-BASE-NEXT: [[COND:%.*]] = phi nsz double [ [[DIV]], [[COND_TRUE]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; CHECK-V8M-BASE-NEXT: ret double [[COND]] ; CHECK-V8M-BASE-NEXT: ret double [[COND]]
; ;
entry: entry:
%cmp = fcmp ogt double %a, 0.0 %cmp = fcmp ogt double %a, 0.0
br i1 %cmp, label %cond.true, label %cond.end br i1 %cmp, label %cond.true, label %cond.end
cond.true: cond.true:
%div = fdiv double %b, %a %div = fdiv double %b, %a
br label %cond.end br label %cond.end
cond.end: cond.end:
%cond = phi nsz double [ %div, %cond.true ], [ 0.0, %entry ] %cond = phi nsz double [ %div, %cond.true ], [ 0.0, %entry ]
ret double %cond ret double %cond
} }
define void @sqrt_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwind { define void @sqrt_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwind {
; CHECK-MVE-LABEL: @sqrt_test( ; CHECK-MVE-LABEL: @sqrt_test(
; CHECK-MVE-NEXT: entry: ; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #3 ; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #[[ATTR3:[0-9]+]]
; CHECK-MVE-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-MVE-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void ; CHECK-MVE-NEXT: ret void
; ;
; CHECK-V8M-MAIN-LABEL: @sqrt_test( ; CHECK-V8M-MAIN-LABEL: @sqrt_test(
; CHECK-V8M-MAIN-NEXT: entry: ; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #2 ; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #[[ATTR2:[0-9]+]]
; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void ; CHECK-V8M-MAIN-NEXT: ret void
; ;
; CHECK-V8M-BASE-LABEL: @sqrt_test( ; CHECK-V8M-BASE-LABEL: @sqrt_test(
; CHECK-V8M-BASE-NEXT: entry: ; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #2 ; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #[[ATTR2:[0-9]+]]
; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void ; CHECK-V8M-BASE-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_sqrt.exit, label %cond.else.i br i1 %cmp.i, label %test_sqrt.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.sqrt.f32(float %a) nounwind readnone %0 = tail call float @llvm.sqrt.f32(float %a) nounwind readnone
br label %test_sqrt.exit br label %test_sqrt.exit
test_sqrt.exit: ; preds = %cond.else.i, %entry test_sqrt.exit: ; preds = %cond.else.i, %entry
%cond.i = phi afn float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi afn float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @fabs_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwind { define void @fabs_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwind {
; CHECK-MVE-LABEL: @fabs_test( ; CHECK-MVE-LABEL: @fabs_test(
; CHECK-MVE-NEXT: entry: ; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #3 ; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #[[ATTR3]]
; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void ; CHECK-MVE-NEXT: ret void
; ;
; CHECK-V8M-MAIN-LABEL: @fabs_test( ; CHECK-V8M-MAIN-LABEL: @fabs_test(
; CHECK-V8M-MAIN-NEXT: entry: ; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #2 ; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #[[ATTR2]]
; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void ; CHECK-V8M-MAIN-NEXT: ret void
; ;
; CHECK-V8M-BASE-LABEL: @fabs_test( ; CHECK-V8M-BASE-LABEL: @fabs_test(
; CHECK-V8M-BASE-NEXT: entry: ; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #2 ; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #[[ATTR2]]
; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void ; CHECK-V8M-BASE-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_fabs.exit, label %cond.else.i br i1 %cmp.i, label %test_fabs.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.fabs.f32(float %a) nounwind readnone %0 = tail call float @llvm.fabs.f32(float %a) nounwind readnone
br label %test_fabs.exit br label %test_fabs.exit
test_fabs.exit: ; preds = %cond.else.i, %entry test_fabs.exit: ; preds = %cond.else.i, %entry
%cond.i = phi reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @fma_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b, float %c) nounwind { define void @fma_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b, float %c) nounwind {
; CHECK-MVE-LABEL: @fma_test( ; CHECK-MVE-LABEL: @fma_test(
; CHECK-MVE-NEXT: entry: ; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #3 ; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR3]]
; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void ; CHECK-MVE-NEXT: ret void
; ;
; CHECK-V8M-MAIN-LABEL: @fma_test( ; CHECK-V8M-MAIN-LABEL: @fma_test(
; CHECK-V8M-MAIN-NEXT: entry: ; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2 ; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR2]]
; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void ; CHECK-V8M-MAIN-NEXT: ret void
; ;
; CHECK-V8M-BASE-LABEL: @fma_test( ; CHECK-V8M-BASE-LABEL: @fma_test(
; CHECK-V8M-BASE-NEXT: entry: ; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2 ; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR2]]
; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void ; CHECK-V8M-BASE-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_fma.exit, label %cond.else.i br i1 %cmp.i, label %test_fma.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone %0 = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone
br label %test_fma.exit br label %test_fma.exit
test_fma.exit: ; preds = %cond.else.i, %entry test_fma.exit: ; preds = %cond.else.i, %entry
%cond.i = phi nsz reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi nsz reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @fmuladd_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b, float %c) nounwind { define void @fmuladd_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b, float %c) nounwind {
; CHECK-MVE-LABEL: @fmuladd_test( ; CHECK-MVE-LABEL: @fmuladd_test(
; CHECK-MVE-NEXT: entry: ; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #3 ; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR3]]
; CHECK-MVE-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-MVE-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void ; CHECK-MVE-NEXT: ret void
; ;
; CHECK-V8M-MAIN-LABEL: @fmuladd_test( ; CHECK-V8M-MAIN-LABEL: @fmuladd_test(
; CHECK-V8M-MAIN-NEXT: entry: ; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2 ; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR2]]
; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void ; CHECK-V8M-MAIN-NEXT: ret void
; ;
; CHECK-V8M-BASE-LABEL: @fmuladd_test( ; CHECK-V8M-BASE-LABEL: @fmuladd_test(
; CHECK-V8M-BASE-NEXT: entry: ; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2 ; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR2]]
; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void ; CHECK-V8M-BASE-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_fmuladd.exit, label %cond.else.i br i1 %cmp.i, label %test_fmuladd.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.fmuladd.f32(float %a, float %b, float %c) nounwind readnone %0 = tail call float @llvm.fmuladd.f32(float %a, float %b, float %c) nounwind readnone
br label %test_fmuladd.exit br label %test_fmuladd.exit
test_fmuladd.exit: ; preds = %cond.else.i, %entry test_fmuladd.exit: ; preds = %cond.else.i, %entry
%cond.i = phi ninf float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi ninf float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @minnum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind { define void @minnum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind {
; CHECK-MVE-LABEL: @minnum_test( ; CHECK-MVE-LABEL: @minnum_test(
; CHECK-MVE-NEXT: entry: ; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #3 ; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR3]]
; CHECK-MVE-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-MVE-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void ; CHECK-MVE-NEXT: ret void
; ;
; CHECK-V8M-MAIN-LABEL: @minnum_test( ; CHECK-V8M-MAIN-LABEL: @minnum_test(
; CHECK-V8M-MAIN-NEXT: entry: ; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #2 ; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void ; CHECK-V8M-MAIN-NEXT: ret void
; ;
; CHECK-V8M-BASE-LABEL: @minnum_test( ; CHECK-V8M-BASE-LABEL: @minnum_test(
; CHECK-V8M-BASE-NEXT: entry: ; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #2 ; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void ; CHECK-V8M-BASE-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_minnum.exit, label %cond.else.i br i1 %cmp.i, label %test_minnum.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.minnum.f32(float %a, float %b) nounwind readnone %0 = tail call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
br label %test_minnum.exit br label %test_minnum.exit
test_minnum.exit: ; preds = %cond.else.i, %entry test_minnum.exit: ; preds = %cond.else.i, %entry
%cond.i = phi float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @maxnum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind { define void @maxnum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind {
; CHECK-MVE-LABEL: @maxnum_test( ; CHECK-MVE-LABEL: @maxnum_test(
; CHECK-MVE-NEXT: entry: ; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #3 ; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR3]]
; CHECK-MVE-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-MVE-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void ; CHECK-MVE-NEXT: ret void
; ;
; CHECK-V8M-MAIN-LABEL: @maxnum_test( ; CHECK-V8M-MAIN-LABEL: @maxnum_test(
; CHECK-V8M-MAIN-NEXT: entry: ; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #2 ; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void ; CHECK-V8M-MAIN-NEXT: ret void
; ;
; CHECK-V8M-BASE-LABEL: @maxnum_test( ; CHECK-V8M-BASE-LABEL: @maxnum_test(
; CHECK-V8M-BASE-NEXT: entry: ; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #2 ; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void ; CHECK-V8M-BASE-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_maxnum.exit, label %cond.else.i br i1 %cmp.i, label %test_maxnum.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone %0 = tail call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone
br label %test_maxnum.exit br label %test_maxnum.exit
test_maxnum.exit: ; preds = %cond.else.i, %entry test_maxnum.exit: ; preds = %cond.else.i, %entry
%cond.i = phi ninf nsz float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi ninf nsz float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @minimum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind { define void @minimum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind {
; CHECK-MVE-LABEL: @minimum_test( ; CHECK-MVE-LABEL: @minimum_test(
; CHECK-MVE-NEXT: entry: ; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #3 ; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #[[ATTR3]]
; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void ; CHECK-MVE-NEXT: ret void
; ;
; CHECK-V8M-MAIN-LABEL: @minimum_test( ; CHECK-V8M-MAIN-LABEL: @minimum_test(
; CHECK-V8M-MAIN-NEXT: entry: ; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #2 ; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void ; CHECK-V8M-MAIN-NEXT: ret void
; ;
; CHECK-V8M-BASE-LABEL: @minimum_test( ; CHECK-V8M-BASE-LABEL: @minimum_test(
; CHECK-V8M-BASE-NEXT: entry: ; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #2 ; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void ; CHECK-V8M-BASE-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_minimum.exit, label %cond.else.i br i1 %cmp.i, label %test_minimum.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.minimum.f32(float %a, float %b) nounwind readnone %0 = tail call float @llvm.minimum.f32(float %a, float %b) nounwind readnone
br label %test_minimum.exit br label %test_minimum.exit
test_minimum.exit: ; preds = %cond.else.i, %entry test_minimum.exit: ; preds = %cond.else.i, %entry
%cond.i = phi reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @maximum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind { define void @maximum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind {
; CHECK-MVE-LABEL: @maximum_test( ; CHECK-MVE-LABEL: @maximum_test(
; CHECK-MVE-NEXT: entry: ; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #3 ; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #[[ATTR3]]
; CHECK-MVE-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-MVE-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void ; CHECK-MVE-NEXT: ret void
; ;
; CHECK-V8M-MAIN-LABEL: @maximum_test( ; CHECK-V8M-MAIN-LABEL: @maximum_test(
; CHECK-V8M-MAIN-NEXT: entry: ; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #2 ; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void ; CHECK-V8M-MAIN-NEXT: ret void
; ;
; CHECK-V8M-BASE-LABEL: @maximum_test( ; CHECK-V8M-BASE-LABEL: @maximum_test(
; CHECK-V8M-BASE-NEXT: entry: ; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #2 ; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void ; CHECK-V8M-BASE-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_maximum.exit, label %cond.else.i br i1 %cmp.i, label %test_maximum.exit, label %cond.else.i
Show All 9 Lines

llvm/test/Transforms/SimplifyCFG/speculate-math.ll

Show All 9 Lines
declare float @llvm.maxnum.f32(float, float) nounwind readonly declare float @llvm.maxnum.f32(float, float) nounwind readonly
declare float @llvm.minimum.f32(float, float) nounwind readonly declare float @llvm.minimum.f32(float, float) nounwind readonly
declare float @llvm.maximum.f32(float, float) nounwind readonly declare float @llvm.maximum.f32(float, float) nounwind readonly
define double @fdiv_test(double %a, double %b) { define double @fdiv_test(double %a, double %b) {
; CHECK-LABEL: @fdiv_test( ; CHECK-LABEL: @fdiv_test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00 ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00
; CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_END:%.*]]
; CHECK: cond.true:
; CHECK-NEXT: [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]] ; CHECK-NEXT: [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]]
; CHECK-NEXT: [[COND:%.*]] = select nsz i1 [[CMP]], double [[DIV]], double 0.000000e+00 ; CHECK-NEXT: br label [[COND_END]]
; CHECK: cond.end:
; CHECK-NEXT: [[COND:%.*]] = phi nsz double [ [[DIV]], [[COND_TRUE]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret double [[COND]] ; CHECK-NEXT: ret double [[COND]]
; ;
entry: entry:
%cmp = fcmp ogt double %a, 0.0 %cmp = fcmp ogt double %a, 0.0
br i1 %cmp, label %cond.true, label %cond.end br i1 %cmp, label %cond.true, label %cond.end
cond.true: cond.true:
%div = fdiv double %b, %a %div = fdiv double %b, %a
br label %cond.end br label %cond.end
cond.end: cond.end:
%cond = phi nsz double [ %div, %cond.true ], [ 0.0, %entry ] %cond = phi nsz double [ %div, %cond.true ], [ 0.0, %entry ]
ret double %cond ret double %cond
} }
define void @sqrt_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwind { define void @sqrt_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwind {
; CHECK-LABEL: @sqrt_test( ; CHECK-LABEL: @sqrt_test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #2 ; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #[[ATTR2:[0-9]+]]
; CHECK-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_sqrt.exit, label %cond.else.i br i1 %cmp.i, label %test_sqrt.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.sqrt.f32(float %a) nounwind readnone %0 = tail call float @llvm.sqrt.f32(float %a) nounwind readnone
br label %test_sqrt.exit br label %test_sqrt.exit
test_sqrt.exit: ; preds = %cond.else.i, %entry test_sqrt.exit: ; preds = %cond.else.i, %entry
%cond.i = phi afn float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi afn float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @fabs_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwind { define void @fabs_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwind {
; CHECK-LABEL: @fabs_test( ; CHECK-LABEL: @fabs_test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #2 ; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #[[ATTR2]]
; CHECK-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_fabs.exit, label %cond.else.i br i1 %cmp.i, label %test_fabs.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.fabs.f32(float %a) nounwind readnone %0 = tail call float @llvm.fabs.f32(float %a) nounwind readnone
br label %test_fabs.exit br label %test_fabs.exit
test_fabs.exit: ; preds = %cond.else.i, %entry test_fabs.exit: ; preds = %cond.else.i, %entry
%cond.i = phi reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @fma_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b, float %c) nounwind { define void @fma_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b, float %c) nounwind {
; CHECK-LABEL: @fma_test( ; CHECK-LABEL: @fma_test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2 ; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR2]]
; CHECK-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_fma.exit, label %cond.else.i br i1 %cmp.i, label %test_fma.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone %0 = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone
br label %test_fma.exit br label %test_fma.exit
test_fma.exit: ; preds = %cond.else.i, %entry test_fma.exit: ; preds = %cond.else.i, %entry
%cond.i = phi nsz reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi nsz reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @fmuladd_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b, float %c) nounwind { define void @fmuladd_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b, float %c) nounwind {
; CHECK-LABEL: @fmuladd_test( ; CHECK-LABEL: @fmuladd_test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2 ; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR2]]
; CHECK-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_fmuladd.exit, label %cond.else.i br i1 %cmp.i, label %test_fmuladd.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.fmuladd.f32(float %a, float %b, float %c) nounwind readnone %0 = tail call float @llvm.fmuladd.f32(float %a, float %b, float %c) nounwind readnone
br label %test_fmuladd.exit br label %test_fmuladd.exit
test_fmuladd.exit: ; preds = %cond.else.i, %entry test_fmuladd.exit: ; preds = %cond.else.i, %entry
%cond.i = phi ninf float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi ninf float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @minnum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind { define void @minnum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind {
; CHECK-LABEL: @minnum_test( ; CHECK-LABEL: @minnum_test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #2 ; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
; CHECK-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_minnum.exit, label %cond.else.i br i1 %cmp.i, label %test_minnum.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.minnum.f32(float %a, float %b) nounwind readnone %0 = tail call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
br label %test_minnum.exit br label %test_minnum.exit
test_minnum.exit: ; preds = %cond.else.i, %entry test_minnum.exit: ; preds = %cond.else.i, %entry
%cond.i = phi float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @maxnum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind { define void @maxnum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind {
; CHECK-LABEL: @maxnum_test( ; CHECK-LABEL: @maxnum_test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #2 ; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
; CHECK-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_maxnum.exit, label %cond.else.i br i1 %cmp.i, label %test_maxnum.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone %0 = tail call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone
br label %test_maxnum.exit br label %test_maxnum.exit
test_maxnum.exit: ; preds = %cond.else.i, %entry test_maxnum.exit: ; preds = %cond.else.i, %entry
%cond.i = phi ninf nsz float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi ninf nsz float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @minimum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind { define void @minimum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind {
; CHECK-LABEL: @minimum_test( ; CHECK-LABEL: @minimum_test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #2 ; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
; CHECK-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_minimum.exit, label %cond.else.i br i1 %cmp.i, label %test_minimum.exit, label %cond.else.i
cond.else.i: ; preds = %entry cond.else.i: ; preds = %entry
%0 = tail call float @llvm.minimum.f32(float %a, float %b) nounwind readnone %0 = tail call float @llvm.minimum.f32(float %a, float %b) nounwind readnone
br label %test_minimum.exit br label %test_minimum.exit
test_minimum.exit: ; preds = %cond.else.i, %entry test_minimum.exit: ; preds = %cond.else.i, %entry
%cond.i = phi reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] %cond.i = phi reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
store float %cond.i, ptr addrspace(1) %out, align 4 store float %cond.i, ptr addrspace(1) %out, align 4
ret void ret void
} }
define void @maximum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind { define void @maximum_test(ptr addrspace(1) noalias nocapture %out, float %a, float %b) nounwind {
; CHECK-LABEL: @maximum_test( ; CHECK-LABEL: @maximum_test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00 ; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #2 ; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
; CHECK-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]] ; CHECK-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%cmp.i = fcmp olt float %a, 0.000000e+00 %cmp.i = fcmp olt float %a, 0.000000e+00
br i1 %cmp.i, label %test_maximum.exit, label %cond.else.i br i1 %cmp.i, label %test_maximum.exit, label %cond.else.i
Show All 9 Lines

llvm/test/Transforms/SimplifyCFG/unsafe-speculate.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=simplifycfg -S | FileCheck %s
declare void @foo()
declare void @bar()
; Move fdiv to entry block is unsafe.
define void @test(x86_fp80 %divisor, ptr %p1) {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[COND1:%.*]] = fcmp ogt x86_fp80 [[DIVISOR:%.*]], 0xK3FFF8000000000000000
; CHECK-NEXT: [[F2:%.*]] = load x86_fp80, ptr [[P1:%.*]], align 16
; CHECK-NEXT: br i1 [[COND1]], label [[BB1:%.*]], label [[BB3:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[F3:%.*]] = fdiv x86_fp80 0xK7FFEFFFFFFFFFFFFFFFF, [[DIVISOR]]
; CHECK-NEXT: [[COND2:%.*]] = fcmp olt x86_fp80 [[F3]], [[F2]]
; CHECK-NEXT: br i1 [[COND2]], label [[BB2:%.*]], label [[BB3]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: bb2:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: bb3:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[COMMON_RET]]
;
entry:
%cond1 = fcmp ogt x86_fp80 %divisor, 0xK3FFF8000000000000000
%f2 = load x86_fp80, ptr %p1, align 16
br i1 %cond1, label %bb1, label %bb3
bb1:
%f3 = fdiv x86_fp80 0xK7FFEFFFFFFFFFFFFFFFF, %divisor
%cond2 = fcmp olt x86_fp80 %f3, %f2
br i1 %cond2, label %bb2, label %bb3
bb2:
call void @foo()
ret void
bb3:
call void @bar()
ret void
}

llvm/test/Transforms/SpeculativeExecution/spec-fp.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Linesa:
%x = fmul float undef, undef %x = fmul float undef, undef
br label %b br label %b
b: b:
ret void ret void
} }
; CHECK-LABEL: @ifThen_fdiv( ; CHECK-LABEL: @ifThen_fdiv(
; CHECK: fdiv
; CHECK: br i1 true ; CHECK: br i1 true
; CHECK: a:
; CHECK: fdiv
define void @ifThen_fdiv() { define void @ifThen_fdiv() {
br i1 true, label %a, label %b br i1 true, label %a, label %b
a: a:
%x = fdiv float undef, undef %x = fdiv float undef, undef
br label %b br label %b
b: b:
ret void ret void
} }
; CHECK-LABEL: @ifThen_frem( ; CHECK-LABEL: @ifThen_frem(
; CHECK: frem
; CHECK: br i1 true ; CHECK: br i1 true
; CHECK: a:
; CHECK: frem
define void @ifThen_frem() { define void @ifThen_frem() {
br i1 true, label %a, label %b br i1 true, label %a, label %b
a: a:
%x = frem float undef, undef %x = frem float undef, undef
br label %b br label %b
b: b:
ret void ret void
} }