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Differential D143740

[AMDGPU] Add GFX11 HW_REG_PERF_SNAPSHOT_*
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Authored by foad on Feb 10 2023, 7:47 AM.

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rampitec
Joe_Nash
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rG811d11b064f7: [AMDGPU] Add GFX11 HW_REG_PERF_SNAPSHOT_*
Summary

These are similar to hardware registers already added for GFX940,
but with different numbers and slightly different names.

Diff Detail

Event Timeline

foad created this revision.Feb 10 2023, 7:47 AM
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foad requested review of this revision.Feb 10 2023, 7:47 AM
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Harbormaster completed remote builds in B213054: Diff 496472.Feb 10 2023, 9:03 AM
rampitec accepted this revision.Feb 10 2023, 11:03 AM
This revision is now accepted and ready to land.Feb 10 2023, 11:03 AM
This revision was landed with ongoing or failed builds.Feb 10 2023, 12:40 PM
Closed by commit rG811d11b064f7: [AMDGPU] Add GFX11 HW_REG_PERF_SNAPSHOT_* (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rG811d11b064f7: [AMDGPU] Add GFX11 HW_REG_PERF_SNAPSHOT_*.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
17 lines
Utils/
6 lines
test/
MC/
AMDGPU/
9 lines
8 lines
Disassembler/
AMDGPU/
9 lines

Diff 496584

llvm/lib/Target/AMDGPU/SIDefines.h

Show First 20 Lines • Show All 398 Lines • ▼ Show 20 Linesenum Id { // HwRegCode, (6) [5:0]
ID_GPR_ALLOC = 5, ID_GPR_ALLOC = 5,
ID_LDS_ALLOC = 6, ID_LDS_ALLOC = 6,
ID_IB_STS = 7, ID_IB_STS = 7,
ID_MEM_BASES = 15, ID_MEM_BASES = 15,
ID_TBA_LO = 16, ID_TBA_LO = 16,
ID_TBA_HI = 17, ID_TBA_HI = 17,
ID_TMA_LO = 18, ID_TMA_LO = 18,
ID_TMA_HI = 19, ID_TMA_HI = 19,
ID_XCC_ID = 20,
ID_SQ_PERF_SNAPSHOT_DATA = 21,
ID_SQ_PERF_SNAPSHOT_DATA1 = 22,
ID_SQ_PERF_SNAPSHOT_PC_LO = 23,
ID_SQ_PERF_SNAPSHOT_PC_HI = 24,
ID_FLAT_SCR_LO = 20, ID_FLAT_SCR_LO = 20,
ID_FLAT_SCR_HI = 21, ID_FLAT_SCR_HI = 21,
ID_XNACK_MASK = 22, ID_XNACK_MASK = 22,
ID_HW_ID1 = 23, ID_HW_ID1 = 23,
ID_HW_ID2 = 24, ID_HW_ID2 = 24,
ID_POPS_PACKER = 25, ID_POPS_PACKER = 25,
ID_PERF_SNAPSHOT_DATA = 27,
ID_SHADER_CYCLES = 29, ID_SHADER_CYCLES = 29,
// Register numbers reused in GFX11+
ID_PERF_SNAPSHOT_PC_LO = 18,
ID_PERF_SNAPSHOT_PC_HI = 19,
// GFX940 specific registers
ID_XCC_ID = 20,
ID_SQ_PERF_SNAPSHOT_DATA = 21,
ID_SQ_PERF_SNAPSHOT_DATA1 = 22,
ID_SQ_PERF_SNAPSHOT_PC_LO = 23,
ID_SQ_PERF_SNAPSHOT_PC_HI = 24,
ID_SHIFT_ = 0, ID_SHIFT_ = 0,
ID_WIDTH_ = 6, ID_WIDTH_ = 6,
ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
}; };
enum Offset : unsigned { // Offset, (5) [10:6] enum Offset : unsigned { // Offset, (5) [10:6]
OFFSET_DEFAULT_ = 0, OFFSET_DEFAULT_ = 0,
OFFSET_SHIFT_ = 6, OFFSET_SHIFT_ = 6,
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llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Linesconst CustomOperand<const MCSubtargetInfo &> Opr[] = {
{{"HW_REG_TMA_HI"}, ID_TMA_HI, isGFX9_GFX10}, {{"HW_REG_TMA_HI"}, ID_TMA_HI, isGFX9_GFX10},
{{"HW_REG_FLAT_SCR_LO"}, ID_FLAT_SCR_LO, isGFX10Plus}, {{"HW_REG_FLAT_SCR_LO"}, ID_FLAT_SCR_LO, isGFX10Plus},
{{"HW_REG_FLAT_SCR_HI"}, ID_FLAT_SCR_HI, isGFX10Plus}, {{"HW_REG_FLAT_SCR_HI"}, ID_FLAT_SCR_HI, isGFX10Plus},
{{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK, isGFX10Before1030}, {{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK, isGFX10Before1030},
{{"HW_REG_HW_ID1"}, ID_HW_ID1, isGFX10Plus}, {{"HW_REG_HW_ID1"}, ID_HW_ID1, isGFX10Plus},
{{"HW_REG_HW_ID2"}, ID_HW_ID2, isGFX10Plus}, {{"HW_REG_HW_ID2"}, ID_HW_ID2, isGFX10Plus},
{{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10}, {{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10},
{{""}}, {{""}},
{{""}}, {{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA, isGFX11Plus},
{{""}}, {{""}},
{{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_BEncoding}, {{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_BEncoding},
// Register numbers reused in GFX11+
{{"HW_REG_PERF_SNAPSHOT_PC_LO"}, ID_PERF_SNAPSHOT_PC_LO, isGFX11Plus},
{{"HW_REG_PERF_SNAPSHOT_PC_HI"}, ID_PERF_SNAPSHOT_PC_HI, isGFX11Plus},
// GFX940 specific registers // GFX940 specific registers
{{"HW_REG_XCC_ID"}, ID_XCC_ID, isGFX940}, {{"HW_REG_XCC_ID"}, ID_XCC_ID, isGFX940},
{{"HW_REG_SQ_PERF_SNAPSHOT_DATA"}, ID_SQ_PERF_SNAPSHOT_DATA, isGFX940}, {{"HW_REG_SQ_PERF_SNAPSHOT_DATA"}, ID_SQ_PERF_SNAPSHOT_DATA, isGFX940},
{{"HW_REG_SQ_PERF_SNAPSHOT_DATA1"}, ID_SQ_PERF_SNAPSHOT_DATA1, isGFX940}, {{"HW_REG_SQ_PERF_SNAPSHOT_DATA1"}, ID_SQ_PERF_SNAPSHOT_DATA1, isGFX940},
{{"HW_REG_SQ_PERF_SNAPSHOT_PC_LO"}, ID_SQ_PERF_SNAPSHOT_PC_LO, isGFX940}, {{"HW_REG_SQ_PERF_SNAPSHOT_PC_LO"}, ID_SQ_PERF_SNAPSHOT_PC_LO, isGFX940},
{{"HW_REG_SQ_PERF_SNAPSHOT_PC_HI"}, ID_SQ_PERF_SNAPSHOT_PC_HI, isGFX940}, {{"HW_REG_SQ_PERF_SNAPSHOT_PC_HI"}, ID_SQ_PERF_SNAPSHOT_PC_HI, isGFX940},
// Aliases // Aliases
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llvm/test/MC/AMDGPU/gfx11_asm_sopk.s

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s_subvector_loop_end vcc_lo, 0x1234 s_subvector_loop_end vcc_lo, 0x1234
// GFX11: encoding: [0x34,0x12,0xea,0xbb] // GFX11: encoding: [0x34,0x12,0xea,0xbb]
s_subvector_loop_end vcc_hi, 0x1234 s_subvector_loop_end vcc_hi, 0x1234
// GFX11: encoding: [0x34,0x12,0xeb,0xbb] // GFX11: encoding: [0x34,0x12,0xeb,0xbb]
s_subvector_loop_end m0, 0x1234 s_subvector_loop_end m0, 0x1234
// GFX11: encoding: [0x34,0x12,0xfd,0xbb] // GFX11: encoding: [0x34,0x12,0xfd,0xbb]
s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_LO)
// GFX11: encoding: [0x12,0xf8,0x80,0xb8]
s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_HI)
// GFX11: encoding: [0x13,0xf8,0x80,0xb8]
s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA)
// GFX11: encoding: [0x1b,0xf8,0x80,0xb8]

llvm/test/MC/AMDGPU/sopk.s

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// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
// GFX11: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8] // GFX11: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x82,0xb8] // GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x82,0xb8]
// VI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8] // VI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(18) s_getreg_b32 s2, hwreg(18)
// SICI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x02,0xb9]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
// GFX11: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8] // GFX11: s_getreg_b32 s2, hwreg(HW_REG_PERF_SNAPSHOT_PC_LO) ; encoding: [0x12,0xf8,0x82,0xb8]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x82,0xb8] // GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x82,0xb8]
// VI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8] // VI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(19) s_getreg_b32 s2, hwreg(19)
// SICI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x02,0xb9]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
// GFX11: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8] // GFX11: s_getreg_b32 s2, hwreg(HW_REG_PERF_SNAPSHOT_PC_HI) ; encoding: [0x13,0xf8,0x82,0xb8]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x82,0xb8] // GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x82,0xb8]
// VI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8] // VI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8]
// GFX10+ registers // GFX10+ registers
s_getreg_b32 s2, hwreg(20) s_getreg_b32 s2, hwreg(20)
// SICI: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x82,0xb8] // VI9: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]
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// GFX10: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x82,0xb9]
// GFX11: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9] // GFX11: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x02,0xb9] // GFX9: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
// VI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9] // VI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
s_setreg_b32 hwreg(18), s2 s_setreg_b32 hwreg(18), s2
// SICI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x82,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x82,0xb9]
// GFX11: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9] // GFX11: s_setreg_b32 hwreg(HW_REG_PERF_SNAPSHOT_PC_LO), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x02,0xb9] // GFX9: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
// VI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9] // VI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
s_setreg_b32 hwreg(19), s2 s_setreg_b32 hwreg(19), s2
// SICI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x82,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x82,0xb9]
// GFX11: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9] // GFX11: s_setreg_b32 hwreg(HW_REG_PERF_SNAPSHOT_PC_HI), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x02,0xb9] // GFX9: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
// VI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9] // VI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
// GFX10+ registers // GFX10+ registers
s_setreg_b32 hwreg(20), s2 s_setreg_b32 hwreg(20), s2
// SICI: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x02,0xb9] // VI9: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; encoding: [0x14,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; encoding: [0x14,0xf8,0x82,0xb9]
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llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopk.txt

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# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_FLAT_SCR_HI), 0xaf123456 ; encoding: [0x15,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf] # GFX11: s_setreg_imm32_b32 hwreg(HW_REG_FLAT_SCR_HI), 0xaf123456 ; encoding: [0x15,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
0x15,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf 0x15,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_HW_ID1), 0xaf123456 ; encoding: [0x17,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf] # GFX11: s_setreg_imm32_b32 hwreg(HW_REG_HW_ID1), 0xaf123456 ; encoding: [0x17,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
0x17,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf 0x17,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_HW_ID2), 0xaf123456 ; encoding: [0x18,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf] # GFX11: s_setreg_imm32_b32 hwreg(HW_REG_HW_ID2), 0xaf123456 ; encoding: [0x18,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
0x18,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf 0x18,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
# GFX11: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_LO) ; encoding: [0x12,0xf8,0x80,0xb8]
0x12,0xf8,0x80,0xb8
# GFX11: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_HI) ; encoding: [0x13,0xf8,0x80,0xb8]
0x13,0xf8,0x80,0xb8
# GFX11: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA) ; encoding: [0x1b,0xf8,0x80,0xb8]
0x1b,0xf8,0x80,0xb8