[AArch64] Add A+B+1 and A-B-1 macro fusion for Ampere1A

[philipp.tomsich]

Summary

The Ampere1A core supports a new fusion pattern that optimises the
case of A+B+1 and A-B-1. Add support.

Depends on D142396

[dmgreen]

Can you add some tests. Possibly with a mir test?

llvm/lib/Target/AArch64/AArch64.td

293

HasFuseeAddSub2RegAndConstOne -> HasFuseAddSub2RegAndConstOne

1313

These look unrelated to the macro fusion.

llvm/lib/Target/AArch64/AArch64MacroFusion.cpp

382

It may be useful to add brackets for clarity, if it works this way: "(A + B) + 1" or "(A - B) - 1"
Do you know if the first is commutative?

385

Capitalize Polarity

[philipp.tomsich]

• added MIR test case
• rewrote idiom-matcher: + fixes issues with the "subtract" case + recognizes ADD[XW]rs

[philipp.tomsich]

• clarify comment

[dmgreen]

llvm/lib/Target/AArch64/AArch64.td

1313

Should these be part of another patch?

[philipp.tomsich]

llvm/lib/Target/AArch64/AArch64.td

1313

Looks like I picked these up by accident. Will split them off again.
Sorry, the tooling with 'arc' is (still) killing me as I am used to patman.

[dmgreen]

If you remove the extra FeatureSB changes, then this LGTM

llvm/lib/Target/AArch64/AArch64.td

293

Remove this extra e too.

llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir

1 ↗

(On Diff #492293)

It may be worth adding more tests for more combos of instructions.

[philipp.tomsich]

Addresses review comments (so the landed version is the same as here).

[philipp.tomsich]

llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir

1 ↗

(On Diff #492293)

Agreed. We'll defer this to a later change, and I'll land this with the single test.

llvm/lib/Target/AArch64/AArch64.td

 def FeatureFuseAdrpAdd : SubtargetFeature<
     "fuse-adrp-add", "HasFuseAdrpAdd", "true",
     "CPU fuses adrp+add operations">;
 
 def FeatureFuseLiterals : SubtargetFeature<
     "fuse-literals", "HasFuseLiterals", "true",
     "CPU fuses literal generation operations">;
 
+def FeatureFuseAddSub2RegAndConstOne : SubtargetFeature<
+   "fuse-addsub-2reg-const1", "HasFuseeAddSub2RegAndConstOne", "true",
+   "CPU fuses (a + b + 1) and (a - b - 1)">;
+
 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
     "Disable latency scheduling heuristic">;
 
 def FeatureForce32BitJumpTables
    : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
                       "Force jump table entries to be 32-bits wide except at MinSize">;
 
list<SubtargetFeature> ThunderX2T99  = [HasV8_1aOps, FeatureCRC, FeatureCrypto,
                                           FeatureFPARMv8, FeatureNEON, FeatureLSE];
   list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto,
                                           FeatureFPARMv8, FeatureNEON, FeatureLSE,
                                           FeaturePAuth, FeaturePerfMon];
   list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
                                    FeatureNEON, FeaturePerfMon, FeatureSPE,
                                    FeatureFullFP16, FeatureFP16FML, FeatureDotProd];
   list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
-                                    FeatureSSBS, FeatureRandGen, FeatureSB,
-                                    FeatureSHA2, FeatureSHA3, FeatureAES];
+                                    FeatureSSBS, FeatureRandGen, FeatureSHA2,
+                                    FeatureSHA3, FeatureAES];
   list<SubtargetFeature> Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
                                      FeatureMTE, FeatureSSBS, FeatureRandGen,
-                                     FeatureSB, FeatureSM4, FeatureSHA2,
-                                     FeatureSHA3, FeatureAES];
+                                     FeatureSM4, FeatureSHA2, FeatureSHA3,
+                                     FeatureAES];
 
   // ETE and TRBE are future architecture extensions. We temporarily enable them
   // by default for users targeting generic AArch64. The extensions do not
   // affect code generated by the compiler and can be used only by explicitly
   // mentioning the new system register names in assembly.
   list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
 }
 

llvm/lib/Target/AArch64/AArch64MacroFusion.cpp

case AArch64::SUBXrs:
       return !AArch64InstrInfo::hasShiftedReg(*FirstMI);
     }
     break;
   }
 
   return false;
 }
 
+// "A + B + 1" or "A - B - 1"
+static bool isAddSub2RegAndConstOnePair(const MachineInstr *FirstMI,
+                                        const MachineInstr &SecondMI) {
+  int polarity = 1;
+
+  switch (SecondMI.getOpcode()) {
+  case AArch64::SUBWri:
+  case AArch64::SUBXri:
+    polarity = -1;
+    // fallthrough
+  case AArch64::ADDWri:
+  case AArch64::ADDXri:
+    if (!SecondMI.getOperand(2).isImm() ||
+        SecondMI.getOperand(2).getImm() != polarity)
+      return false;
+
+    // Assume the 1st instr to be a wildcard if it is unspecified.
+    if (FirstMI == nullptr) {
+      return true;
+    }
+    break;
+
+  default:
+    return false;
+  }
+
+  switch (FirstMI->getOpcode()) {
+  case AArch64::SUBWrr:
+  case AArch64::SUBXrr:
+    if (polarity == -1)
+      return true;
+    break;
+
+  case AArch64::ADDWrr:
+  case AArch64::ADDXrr:
+    if (polarity == 1)
+      return true;
+    break;
+  }
+
+  return false;
+}
+
 /// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
 /// together. Given SecondMI, when FirstMI is unspecified, then check if
 /// SecondMI may be part of a fused pair at all.
 static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
                                    const TargetSubtargetInfo &TSI,
                                    const MachineInstr *FirstMI,
                                    const MachineInstr &SecondMI) {
   const AArch64Subtarget &ST = static_cast<const AArch64Subtarget&>(TSI);
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
   if (ST.hasFuseLiterals() && isLiteralsPair(FirstMI, SecondMI))
     return true;
   if (ST.hasFuseAddress() && isAddressLdStPair(FirstMI, SecondMI))
     return true;
   if (ST.hasFuseCCSelect() && isCCSelectPair(FirstMI, SecondMI))
     return true;
   if (ST.hasFuseArithmeticLogic() && isArithmeticLogicPair(FirstMI, SecondMI))
     return true;
+  if (ST.hasFuseeAddSub2RegAndConstOne() &&
+      isAddSub2RegAndConstOnePair(FirstMI, SecondMI))
+    return true;
 
   return false;
 }
 
 std::unique_ptr<ScheduleDAGMutation>
 llvm::createAArch64MacroFusionDAGMutation() {
   return createMacroFusionDAGMutation(shouldScheduleAdjacent);
 }