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Differential D141728

[AMDGPU] Tune scheduler on GFX10 and GFX11
AbandonedPublic

Authored by rampitec on Jan 13 2023, 2:17 PM.

Details

Reviewers
kerbowa
foad
Summary

Unlike older ASICs GFX10+ have a lot of VGPRs. Therefore, it is possible
to achieve high occupancy even with all or almost all addressable VGPRs
used. Our scheduler was never tuned for this scenario. The VGPR Critical
Limit threshold always comes very high, even if maximum occupancy is
targeted. For example on gfx1100 it is set to 192 registers even with
the requested occupancy 16. As a result scheduler starts prioritizing
register pressure reduction very late and we easily end up spilling.

This patch makes scheduling on new targets much closer to GFX9. The
value of VGPR critical limit is based on the number of addressable
registers and not on a total VGPR budget.

The intent of the patch is to have no impact on GFX9 and older targets,
a massive lit tests update shows no changes on these.

Diff Detail

Unit TestsFailed

TimeTest
60,340 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded::vloxseg.c
60,510 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded::vluxseg.c
60,350 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded::vloxseg.c
60,390 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded::vluxseg.c
50 msx64 debian > LLVM.CodeGen/LoongArch::O0-pipeline.ll
View Full Test Results (7 Failed)

Event Timeline

rampitec created this revision.Jan 13 2023, 2:17 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 13 2023, 2:17 PM
Herald added subscribers: kosarev, StephenFan, wenlei and 10 others. · View Herald Transcript
rampitec requested review of this revision.Jan 13 2023, 2:17 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 13 2023, 2:17 PM
Herald added a subscriber: wdng. · View Herald Transcript
Harbormaster completed remote builds in B207726: Diff 489121.Jan 13 2023, 3:08 PM
kerbowa added a comment.Jan 15 2023, 11:53 PM

I think this makes sense, but it also makes the concept of an occupancy target a misnomer.

Additionally, I worry that we may be over-prioritizing RP reduction when we consistently see cases where higher RP isn't necessarily leading to better performance.

This situation is basically why the HighRPReschedule stage exists - where we target a higher occupancy to see if occupancy was dropped because the heuristics are not focusing RP reduction soon enough. This HighRP stage will only increase the target occupancy by one and decrease the critical register limit by an additional 10. We could probably be more aggressive with these numbers in cases where we have spilling. For example, setting the HighRPErrorMargin to something very high like 200 also eliminates the spilling in the testcase for the relevant ticket (SWDEV-377300).

That may be a more targeted change, but if your feeling is that this patch will be a more general improvement it looks good to me.

rampitec added a comment.Jan 16 2023, 10:55 AM
In D141728#4055501, @kerbowa wrote:

I think this makes sense, but it also makes the concept of an occupancy target a misnomer.

Additionally, I worry that we may be over-prioritizing RP reduction when we consistently see cases where higher RP isn't necessarily leading to better performance.

This situation is basically why the HighRPReschedule stage exists - where we target a higher occupancy to see if occupancy was dropped because the heuristics are not focusing RP reduction soon enough. This HighRP stage will only increase the target occupancy by one and decrease the critical register limit by an additional 10. We could probably be more aggressive with these numbers in cases where we have spilling. For example, setting the HighRPErrorMargin to something very high like 200 also eliminates the spilling in the testcase for the relevant ticket (SWDEV-377300).

That may be a more targeted change, but if your feeling is that this patch will be a more general improvement it looks good to me.

Austin, thanks for the review. I agree this makes concept of occupancy based scheduling somewhat dissolved, although I do not think it completely misrepresents the pass now. This only changes a single threshold while others still use occupancy. This is more of a wording issue to me anyway, but I certainly will try to play with HighRPReschedule, mainly because I am a bit afraid of the amount of gfx10/gfx11 scheduling changes and their potential impact. If that is possible to only tackle high RP issue when we really hit spilling and prioritize ILP otherwise, that would be ideal for sure.

Meanwhile, it would be interesting to see an overall impact of this patch as it is on graphics and gfx10 (possibly gfx11 too). @foad do you mind to help with that? If we see it has an overall improvement we may prefer current approach anyway. That said the issue shall affect wave64 kernels less than wave32.

rampitec added a comment.Jan 16 2023, 2:01 PM
In D141728#4055501, @kerbowa wrote:

This situation is basically why the HighRPReschedule stage exists - where we target a higher occupancy to see if occupancy was dropped because the heuristics are not focusing RP reduction soon enough. This HighRP stage will only increase the target occupancy by one and decrease the critical register limit by an additional 10. We could probably be more aggressive with these numbers in cases where we have spilling. For example, setting the HighRPErrorMargin to something very high like 200 also eliminates the spilling in the testcase for the relevant ticket (SWDEV-377300).

In fact ErrorMargin is completely misused by the HighRPReschedule. This number is to account for the RPTracker inaccuracy, not to bias the limits. In this case it certainly does not help to bias SGPR limit by something like 200. I.e. it is possible to do it in the HighRPReschedule but it needs some better infrastructure.

The other consideration is that doing so only in the regions with high RP may leave little room for improvement. In the testcase discussed there is high enough livein pressure and it will not be affected as it comes from a block with a lesser pressure. On the other hand doing this math always makes it more balanced.

rampitec added a comment.Jan 16 2023, 2:14 PM
In D141728#4057199, @rampitec wrote:
In D141728#4055501, @kerbowa wrote:

This situation is basically why the HighRPReschedule stage exists - where we target a higher occupancy to see if occupancy was dropped because the heuristics are not focusing RP reduction soon enough. This HighRP stage will only increase the target occupancy by one and decrease the critical register limit by an additional 10. We could probably be more aggressive with these numbers in cases where we have spilling. For example, setting the HighRPErrorMargin to something very high like 200 also eliminates the spilling in the testcase for the relevant ticket (SWDEV-377300).

In fact ErrorMargin is completely misused by the HighRPReschedule. This number is to account for the RPTracker inaccuracy, not to bias the limits. In this case it certainly does not help to bias SGPR limit by something like 200. I.e. it is possible to do it in the HighRPReschedule but it needs some better infrastructure.

The other consideration is that doing so only in the regions with high RP may leave little room for improvement. In the testcase discussed there is high enough livein pressure and it will not be affected as it comes from a block with a lesser pressure. On the other hand doing this math always makes it more balanced.

The other consideration is that we do not really need to go unclustered here, just make adequate thresholds.

rampitec mentioned this in D141876: [AMDGPU] Tune scheduler on GFX10 and GFX11 for regions with spilling.Jan 16 2023, 3:32 PM

There is a conservative alternative which might be better: D141876. That one should not affect kernels which do not currently spill. I am keeping this one for the time being in case we decide it is overall better.

rampitec abandoned this revision.Jan 20 2023, 11:11 AM

Testing showed negative performance impact. D141876 is the way to go.

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Diff 489121

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Linesvoid GCNSchedStrategy::initialize(ScheduleDAGMI *DAG) {
SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>(); SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
// Set the initial TargetOccupnacy to the maximum occupancy that we can // Set the initial TargetOccupnacy to the maximum occupancy that we can
// achieve for this function. This effectively sets a lower bound on the // achieve for this function. This effectively sets a lower bound on the
// 'Critical' register limits in the scheduler. // 'Critical' register limits in the scheduler.
TargetOccupancy = MFI.getOccupancy(); TargetOccupancy = MFI.getOccupancy();
SGPRCriticalLimit = SGPRCriticalLimit =
std::min(ST.getMaxNumSGPRs(TargetOccupancy, true), SGPRExcessLimit); std::min(ST.getMaxNumSGPRs(TargetOccupancy, true), SGPRExcessLimit);
VGPRCriticalLimit =
std::min(ST.getMaxNumVGPRs(TargetOccupancy), VGPRExcessLimit); // This is similar to ST.getMaxNumVGPRs(TargetOccupancy) result except returns
// a reasonably small number for targets with lots of VGPRs, such as GFX10 and
// GFX11.
unsigned Granule = AMDGPU::IsaInfo::getVGPRAllocGranule(&ST);
unsigned VGPRBudget =
alignDown(AMDGPU::IsaInfo::getAddressableNumVGPRs(&ST) / TargetOccupancy,
Granule);
VGPRBudget = std::max(VGPRBudget, Granule);
VGPRCriticalLimit = std::min(VGPRBudget, VGPRExcessLimit);
// Subtract error margin from register limits and avoid overflow. // Subtract error margin from register limits and avoid overflow.
SGPRCriticalLimit = SGPRCriticalLimit =
std::min(SGPRCriticalLimit - ErrorMargin, SGPRCriticalLimit); std::min(SGPRCriticalLimit - ErrorMargin, SGPRCriticalLimit);
VGPRCriticalLimit = VGPRCriticalLimit =
std::min(VGPRCriticalLimit - ErrorMargin, VGPRCriticalLimit); std::min(VGPRCriticalLimit - ErrorMargin, VGPRCriticalLimit);
SGPRExcessLimit = std::min(SGPRExcessLimit - ErrorMargin, SGPRExcessLimit); SGPRExcessLimit = std::min(SGPRExcessLimit - ErrorMargin, SGPRExcessLimit);
VGPRExcessLimit = std::min(VGPRExcessLimit - ErrorMargin, VGPRExcessLimit); VGPRExcessLimit = std::min(VGPRExcessLimit - ErrorMargin, VGPRExcessLimit);
▲ Show 20 Lines • Show All 991 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

Show First 20 Lines • Show All 499 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_ashrrev_i32_e32 v15, v16, v15 ; GCN-NEXT: v_ashrrev_i32_e32 v15, v16, v15
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_ashr_v16i32: ; GFX10-LABEL: v_ashr_v16i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_ashrrev_i32_e32 v0, v16, v0 ; GFX10-NEXT: v_ashrrev_i32_e32 v0, v16, v0
; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GFX10-NEXT: v_ashrrev_i32_e32 v1, v17, v1 ; GFX10-NEXT: v_ashrrev_i32_e32 v1, v17, v1
; GFX10-NEXT: v_ashrrev_i32_e32 v2, v18, v2 ; GFX10-NEXT: v_ashrrev_i32_e32 v2, v18, v2
; GFX10-NEXT: v_ashrrev_i32_e32 v3, v19, v3 ; GFX10-NEXT: v_ashrrev_i32_e32 v3, v19, v3
; GFX10-NEXT: v_ashrrev_i32_e32 v4, v20, v4 ; GFX10-NEXT: v_ashrrev_i32_e32 v4, v20, v4
; GFX10-NEXT: v_ashrrev_i32_e32 v5, v21, v5 ; GFX10-NEXT: v_ashrrev_i32_e32 v5, v21, v5
; GFX10-NEXT: v_ashrrev_i32_e32 v6, v22, v6 ; GFX10-NEXT: v_ashrrev_i32_e32 v6, v22, v6
; GFX10-NEXT: v_ashrrev_i32_e32 v7, v23, v7 ; GFX10-NEXT: v_ashrrev_i32_e32 v7, v23, v7
; GFX10-NEXT: v_ashrrev_i32_e32 v8, v24, v8 ; GFX10-NEXT: v_ashrrev_i32_e32 v8, v24, v8
; GFX10-NEXT: v_ashrrev_i32_e32 v9, v25, v9 ; GFX10-NEXT: v_ashrrev_i32_e32 v9, v25, v9
; GFX10-NEXT: v_ashrrev_i32_e32 v10, v26, v10 ; GFX10-NEXT: v_ashrrev_i32_e32 v10, v26, v10
; GFX10-NEXT: v_ashrrev_i32_e32 v11, v27, v11 ; GFX10-NEXT: v_ashrrev_i32_e32 v11, v27, v11
; GFX10-NEXT: v_ashrrev_i32_e32 v12, v28, v12 ; GFX10-NEXT: v_ashrrev_i32_e32 v12, v28, v12
; GFX10-NEXT: v_ashrrev_i32_e32 v13, v29, v13 ; GFX10-NEXT: v_ashrrev_i32_e32 v13, v29, v13
; GFX10-NEXT: v_ashrrev_i32_e32 v14, v30, v14 ; GFX10-NEXT: v_ashrrev_i32_e32 v14, v30, v14
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_ashrrev_i32_e32 v15, v31, v15 ; GFX10-NEXT: v_ashrrev_i32_e32 v15, v16, v15
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_ashr_v16i32: ; GFX11-LABEL: v_ashr_v16i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_ashrrev_i32_e32 v0, v16, v0 ; GFX11-NEXT: v_ashrrev_i32_e32 v0, v16, v0
; GFX11-NEXT: scratch_load_b32 v16, off, s32
; GFX11-NEXT: v_ashrrev_i32_e32 v1, v17, v1 ; GFX11-NEXT: v_ashrrev_i32_e32 v1, v17, v1
; GFX11-NEXT: v_ashrrev_i32_e32 v2, v18, v2 ; GFX11-NEXT: v_ashrrev_i32_e32 v2, v18, v2
; GFX11-NEXT: v_ashrrev_i32_e32 v3, v19, v3 ; GFX11-NEXT: v_ashrrev_i32_e32 v3, v19, v3
; GFX11-NEXT: v_ashrrev_i32_e32 v4, v20, v4 ; GFX11-NEXT: v_ashrrev_i32_e32 v4, v20, v4
; GFX11-NEXT: v_ashrrev_i32_e32 v5, v21, v5 ; GFX11-NEXT: v_ashrrev_i32_e32 v5, v21, v5
; GFX11-NEXT: v_ashrrev_i32_e32 v6, v22, v6 ; GFX11-NEXT: v_ashrrev_i32_e32 v6, v22, v6
; GFX11-NEXT: v_ashrrev_i32_e32 v7, v23, v7 ; GFX11-NEXT: v_ashrrev_i32_e32 v7, v23, v7
; GFX11-NEXT: v_ashrrev_i32_e32 v8, v24, v8 ; GFX11-NEXT: v_ashrrev_i32_e32 v8, v24, v8
; GFX11-NEXT: v_ashrrev_i32_e32 v9, v25, v9 ; GFX11-NEXT: v_ashrrev_i32_e32 v9, v25, v9
; GFX11-NEXT: v_ashrrev_i32_e32 v10, v26, v10 ; GFX11-NEXT: v_ashrrev_i32_e32 v10, v26, v10
; GFX11-NEXT: v_ashrrev_i32_e32 v11, v27, v11 ; GFX11-NEXT: v_ashrrev_i32_e32 v11, v27, v11
; GFX11-NEXT: v_ashrrev_i32_e32 v12, v28, v12 ; GFX11-NEXT: v_ashrrev_i32_e32 v12, v28, v12
; GFX11-NEXT: v_ashrrev_i32_e32 v13, v29, v13 ; GFX11-NEXT: v_ashrrev_i32_e32 v13, v29, v13
; GFX11-NEXT: v_ashrrev_i32_e32 v14, v30, v14 ; GFX11-NEXT: v_ashrrev_i32_e32 v14, v30, v14
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_ashrrev_i32_e32 v15, v31, v15 ; GFX11-NEXT: v_ashrrev_i32_e32 v15, v16, v15
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = ashr <16 x i32> %value, %amount %result = ashr <16 x i32> %value, %amount
ret <16 x i32> %result ret <16 x i32> %result
} }
define amdgpu_ps <16 x i32> @s_ashr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) { define amdgpu_ps <16 x i32> @s_ashr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) {
; GCN-LABEL: s_ashr_v16i32: ; GCN-LABEL: s_ashr_v16i32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
▲ Show 20 Lines • Show All 1,199 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_ashr_i65: ; GFX10-LABEL: v_ashr_i65:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_bfe_i32 v4, v2, 0, 1 ; GFX10-NEXT: v_bfe_i32 v4, v2, 0, 1
; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v3 ; GFX10-NEXT: v_lshrrev_b64 v[8:9], v3, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3 ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3
; GFX10-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v3
; GFX10-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5] ; GFX10-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX10-NEXT: v_ashrrev_i64 v[10:11], v10, v[4:5] ; GFX10-NEXT: v_lshlrev_b64 v[6:7], v2, v[4:5]
; GFX10-NEXT: v_or_b32_e32 v2, v6, v8 ; GFX10-NEXT: v_or_b32_e32 v2, v8, v6
; GFX10-NEXT: v_or_b32_e32 v8, v7, v9 ; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 64, v3
; GFX10-NEXT: v_ashrrev_i64 v[6:7], v3, v[4:5] ; GFX10-NEXT: v_or_b32_e32 v8, v9, v7
; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v5 ; GFX10-NEXT: v_ashrrev_i64 v[6:7], v6, v[4:5]
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v11, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v4, v1, s4 ; GFX10-NEXT: v_ashrrev_i64 v[2:3], v3, v[4:5]
; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc_lo ; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX10-NEXT: v_cndmask_b32_e64 v1, v6, v1, s4
; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_ashr_i65: ; GFX11-LABEL: v_ashr_i65:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_bfe_i32 v4, v2, 0, 1 ; GFX11-NEXT: v_bfe_i32 v4, v2, 0, 1
; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v3 ; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v3
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_bfe_i32 v1, v2, 0, 1 ; GFX9-NEXT: v_bfe_i32 v1, v2, 0, 1
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2] ; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0 ; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 1, v2 ; GFX9-NEXT: v_ashrrev_i32_e32 v2, 1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10PLUS-LABEL: v_ashr_i65_33: ; GFX10-LABEL: v_ashr_i65_33:
; GFX10PLUS: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10PLUS-NEXT: v_mov_b32_e32 v3, v1 ; GFX10-NEXT: v_bfe_i32 v0, v2, 0, 1
; GFX10PLUS-NEXT: v_bfe_i32 v1, v2, 0, 1 ; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, 1, v3 ; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 1, v3
; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2] ; GFX10-NEXT: v_ashrrev_i32_e32 v2, 1, v1
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 1, v2 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]
; GFX10PLUS-NEXT: v_or_b32_e32 v0, v3, v0 ; GFX10-NEXT: v_or_b32_e32 v0, v3, v0
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_ashr_i65_33:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_mov_b32_e32 v3, v1
; GFX11-NEXT: v_bfe_i32 v1, v2, 0, 1
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 1, v3
; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
; GFX11-NEXT: v_ashrrev_i32_e32 v2, 1, v2
; GFX11-NEXT: v_or_b32_e32 v0, v3, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = ashr i65 %value, 33 %result = ashr i65 %value, 33
ret i65 %result ret i65 %result
} }
define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) { define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) {
; GCN-LABEL: s_ashr_i65: ; GCN-LABEL: s_ashr_i65:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000 ; GCN-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
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llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll

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; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v9 ; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v9
; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v2, v10 ; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v2, v10
; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v3, v11 ; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v3, v11
; GFX9-DENORM-NEXT: ; return to shader part epilog ; GFX9-DENORM-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: test_v4f16_v4f32_add_fma_ext_mul: ; GFX10-LABEL: test_v4f16_v4f32_add_fma_ext_mul:
; GFX10: ; %bb.0: ; %.entry ; GFX10: ; %bb.0: ; %.entry
; GFX10-NEXT: v_pk_mul_f16 v12, v12, v14 ; GFX10-NEXT: v_pk_mul_f16 v12, v12, v14
; GFX10-NEXT: v_pk_mul_f16 v13, v13, v15
; GFX10-NEXT: v_fma_mix_f32 v0, v0, v4, v12 op_sel_hi:[0,0,1] ; GFX10-NEXT: v_fma_mix_f32 v0, v0, v4, v12 op_sel_hi:[0,0,1]
; GFX10-NEXT: v_pk_mul_f16 v4, v13, v15
; GFX10-NEXT: v_fma_mix_f32 v1, v1, v5, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1] ; GFX10-NEXT: v_fma_mix_f32 v1, v1, v5, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-NEXT: v_fma_mix_f32 v2, v2, v6, v13 op_sel_hi:[0,0,1]
; GFX10-NEXT: v_fma_mix_f32 v3, v3, v7, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-NEXT: v_add_f32_e32 v0, v0, v8 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v8
; GFX10-NEXT: v_fma_mix_f32 v2, v2, v6, v4 op_sel_hi:[0,0,1]
; GFX10-NEXT: v_fma_mix_f32 v3, v3, v7, v4 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-NEXT: v_add_f32_e32 v1, v1, v9 ; GFX10-NEXT: v_add_f32_e32 v1, v1, v9
; GFX10-NEXT: v_add_f32_e32 v2, v2, v10 ; GFX10-NEXT: v_add_f32_e32 v2, v2, v10
; GFX10-NEXT: v_add_f32_e32 v3, v3, v11 ; GFX10-NEXT: v_add_f32_e32 v3, v3, v11
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_fma_ext_mul: ; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_fma_ext_mul:
; GFX10-CONTRACT: ; %bb.0: ; %.entry ; GFX10-CONTRACT: ; %bb.0: ; %.entry
; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v12, v12, v14 ; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v12, v12, v14
; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v13, v13, v15
; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v0, v4, v12 op_sel_hi:[0,0,1] ; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v0, v4, v12 op_sel_hi:[0,0,1]
; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v4, v13, v15
; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v1, v1, v5, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1] ; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v1, v1, v5, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v2, v2, v6, v13 op_sel_hi:[0,0,1]
; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v3, v3, v7, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v8 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v8
; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v2, v2, v6, v4 op_sel_hi:[0,0,1]
; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v3, v3, v7, v4 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v9 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v9
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v10 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v10
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v11 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v11
; GFX10-CONTRACT-NEXT: ; return to shader part epilog ; GFX10-CONTRACT-NEXT: ; return to shader part epilog
; ;
; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_fma_ext_mul: ; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_fma_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %.entry ; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_pk_mul_f16 v12, v12, v14 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v12, v12, v14
; GFX10-DENORM-NEXT: v_pk_mul_f16 v13, v13, v15
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v4, v12 op_sel_hi:[0,0,1] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v4, v12 op_sel_hi:[0,0,1]
; GFX10-DENORM-NEXT: v_pk_mul_f16 v4, v13, v15
; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, v1, v5, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, v1, v5, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v2, v6, v13 op_sel_hi:[0,0,1]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v3, v7, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v8 ; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v8
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v2, v6, v4 op_sel_hi:[0,0,1]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v3, v7, v4 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v9 ; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v9
; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v2, v10 ; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v2, v10
; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v3, v11 ; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v3, v11
; GFX10-DENORM-NEXT: ; return to shader part epilog ; GFX10-DENORM-NEXT: ; return to shader part epilog
.entry: .entry:
%a = fmul <4 x half> %u, %v %a = fmul <4 x half> %u, %v
%b = fpext <4 x half> %a to <4 x float> %b = fpext <4 x half> %a to <4 x float>
%c = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %b) %c = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %b)
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; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v3, v5 ; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v3, v5
; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v8, v6 ; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v8, v6
; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v9, v7 ; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v9, v7
; GFX9-DENORM-NEXT: ; return to shader part epilog ; GFX9-DENORM-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: test_v4f16_v4f32_add_ext_fma_mul: ; GFX10-LABEL: test_v4f16_v4f32_add_ext_fma_mul:
; GFX10: ; %bb.0: ; %.entry ; GFX10: ; %bb.0: ; %.entry
; GFX10-NEXT: v_pk_mul_f16 v8, v8, v10 ; GFX10-NEXT: v_pk_mul_f16 v8, v8, v10
; GFX10-NEXT: v_pk_mul_f16 v9, v9, v11 ; GFX10-NEXT: v_pk_fma_f16 v2, v0, v2, v8
; GFX10-NEXT: v_pk_fma_f16 v0, v0, v2, v8 ; GFX10-NEXT: v_pk_mul_f16 v0, v9, v11
; GFX10-NEXT: v_pk_fma_f16 v1, v1, v3, v9 ; GFX10-NEXT: v_pk_fma_f16 v3, v1, v3, v0
; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0 ; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v2
; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v1 ; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v3
; GFX10-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_add_f32_e32 v0, v2, v4 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v4
; GFX10-NEXT: v_add_f32_e32 v1, v3, v5 ; GFX10-NEXT: v_add_f32_e32 v1, v1, v5
; GFX10-NEXT: v_add_f32_e32 v2, v8, v6 ; GFX10-NEXT: v_add_f32_e32 v2, v2, v6
; GFX10-NEXT: v_add_f32_e32 v3, v9, v7 ; GFX10-NEXT: v_add_f32_e32 v3, v3, v7
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_ext_fma_mul: ; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_ext_fma_mul:
; GFX10-CONTRACT: ; %bb.0: ; %.entry ; GFX10-CONTRACT: ; %bb.0: ; %.entry
; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v8, v8, v10 ; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v8, v8, v10
; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v9, v9, v11 ; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v2, v0, v2, v8
; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v0, v0, v2, v8 ; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v0, v9, v11
; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v1, v1, v3, v9 ; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v3, v1, v3, v0
; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v2, v0 ; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v0, v2
; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v8, v1 ; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v2, v3
; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v2, v4 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v4
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v3, v5 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v5
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v8, v6 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v6
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v9, v7 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v7
; GFX10-CONTRACT-NEXT: ; return to shader part epilog ; GFX10-CONTRACT-NEXT: ; return to shader part epilog
; ;
; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_ext_fma_mul: ; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_ext_fma_mul:
; GFX10-DENORM: ; %bb.0: ; %.entry ; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_pk_mul_f16 v8, v8, v10 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v8, v8, v10
; GFX10-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2
; GFX10-DENORM-NEXT: v_pk_mul_f16 v2, v9, v11 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v2, v9, v11
; GFX10-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3
; GFX10-DENORM-NEXT: v_pk_add_f16 v0, v0, v8 ; GFX10-DENORM-NEXT: v_pk_add_f16 v3, v0, v8
; GFX10-DENORM-NEXT: v_pk_add_f16 v1, v1, v2 ; GFX10-DENORM-NEXT: v_pk_add_f16 v8, v1, v2
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v0 ; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v3
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v1 ; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v8
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v2, v4 ; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v4
; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v3, v5 ; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v5
; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v8, v6 ; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v2, v6
; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v9, v7 ; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v3, v7
; GFX10-DENORM-NEXT: ; return to shader part epilog ; GFX10-DENORM-NEXT: ; return to shader part epilog
.entry: .entry:
%a = fmul <4 x half> %u, %v %a = fmul <4 x half> %u, %v
%b = call <4 x half> @llvm.fmuladd.v4f16(<4 x half> %x, <4 x half> %y, <4 x half> %a) %b = call <4 x half> @llvm.fmuladd.v4f16(<4 x half> %x, <4 x half> %y, <4 x half> %a)
%c = fpext <4 x half> %b to <4 x float> %c = fpext <4 x half> %b to <4 x float>
%d = fadd <4 x float> %c, %z %d = fadd <4 x float> %c, %z
ret <4 x float> %d ret <4 x float> %d
} }
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; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v5 ; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v5
; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v2, v6 ; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v2, v6
; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v3, v7 ; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v3, v7
; GFX9-DENORM-NEXT: ; return to shader part epilog ; GFX9-DENORM-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: test_v4f16_v4f32_add_fma_ext_mul_rhs: ; GFX10-LABEL: test_v4f16_v4f32_add_fma_ext_mul_rhs:
; GFX10: ; %bb.0: ; %.entry ; GFX10: ; %bb.0: ; %.entry
; GFX10-NEXT: v_pk_mul_f16 v12, v12, v14 ; GFX10-NEXT: v_pk_mul_f16 v12, v12, v14
; GFX10-NEXT: v_pk_mul_f16 v13, v13, v15
; GFX10-NEXT: v_fma_mix_f32 v4, v4, v8, v12 op_sel_hi:[0,0,1] ; GFX10-NEXT: v_fma_mix_f32 v4, v4, v8, v12 op_sel_hi:[0,0,1]
; GFX10-NEXT: v_pk_mul_f16 v8, v13, v15
; GFX10-NEXT: v_fma_mix_f32 v5, v5, v9, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1] ; GFX10-NEXT: v_fma_mix_f32 v5, v5, v9, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-NEXT: v_fma_mix_f32 v6, v6, v10, v13 op_sel_hi:[0,0,1]
; GFX10-NEXT: v_fma_mix_f32 v7, v7, v11, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-NEXT: v_add_f32_e32 v0, v0, v4 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v4
; GFX10-NEXT: v_fma_mix_f32 v6, v6, v10, v8 op_sel_hi:[0,0,1]
; GFX10-NEXT: v_fma_mix_f32 v7, v7, v11, v8 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-NEXT: v_add_f32_e32 v1, v1, v5 ; GFX10-NEXT: v_add_f32_e32 v1, v1, v5
; GFX10-NEXT: v_add_f32_e32 v2, v2, v6 ; GFX10-NEXT: v_add_f32_e32 v2, v2, v6
; GFX10-NEXT: v_add_f32_e32 v3, v3, v7 ; GFX10-NEXT: v_add_f32_e32 v3, v3, v7
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_fma_ext_mul_rhs: ; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_fma_ext_mul_rhs:
; GFX10-CONTRACT: ; %bb.0: ; %.entry ; GFX10-CONTRACT: ; %bb.0: ; %.entry
; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v12, v12, v14 ; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v12, v12, v14
; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v13, v13, v15
; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v4, v4, v8, v12 op_sel_hi:[0,0,1] ; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v4, v4, v8, v12 op_sel_hi:[0,0,1]
; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v8, v13, v15
; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v5, v5, v9, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1] ; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v5, v5, v9, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v6, v6, v10, v13 op_sel_hi:[0,0,1]
; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v7, v7, v11, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v4 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v4
; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v6, v6, v10, v8 op_sel_hi:[0,0,1]
; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v7, v7, v11, v8 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v5 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v5
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v6 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v6
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v7 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v7
; GFX10-CONTRACT-NEXT: ; return to shader part epilog ; GFX10-CONTRACT-NEXT: ; return to shader part epilog
; ;
; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_fma_ext_mul_rhs: ; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_fma_ext_mul_rhs:
; GFX10-DENORM: ; %bb.0: ; %.entry ; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_pk_mul_f16 v12, v12, v14 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v12, v12, v14
; GFX10-DENORM-NEXT: v_pk_mul_f16 v13, v13, v15
; GFX10-DENORM-NEXT: v_fma_mix_f32 v4, v4, v8, v12 op_sel_hi:[0,0,1] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v4, v4, v8, v12 op_sel_hi:[0,0,1]
; GFX10-DENORM-NEXT: v_pk_mul_f16 v8, v13, v15
; GFX10-DENORM-NEXT: v_fma_mix_f32 v5, v5, v9, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v5, v5, v9, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v6, v6, v10, v13 op_sel_hi:[0,0,1]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v7, v7, v11, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v4 ; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v4
; GFX10-DENORM-NEXT: v_fma_mix_f32 v6, v6, v10, v8 op_sel_hi:[0,0,1]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v7, v7, v11, v8 op_sel:[0,0,1] op_sel_hi:[0,0,1]
; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v5 ; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v5
; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v2, v6 ; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v2, v6
; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v3, v7 ; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v3, v7
; GFX10-DENORM-NEXT: ; return to shader part epilog ; GFX10-DENORM-NEXT: ; return to shader part epilog
.entry: .entry:
%a = fmul <4 x half> %u, %v %a = fmul <4 x half> %u, %v
%b = fpext <4 x half> %a to <4 x float> %b = fpext <4 x half> %a to <4 x float>
%c = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y, <4 x float> %z, <4 x float> %b) %c = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y, <4 x float> %z, <4 x float> %b)
Show All 19 Lines
; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v4 ; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v4
; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v2, v7 ; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v2, v7
; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v3, v5 ; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v3, v5
; GFX9-DENORM-NEXT: ; return to shader part epilog ; GFX9-DENORM-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs: ; GFX10-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs:
; GFX10: ; %bb.0: ; %.entry ; GFX10: ; %bb.0: ; %.entry
; GFX10-NEXT: v_pk_mul_f16 v8, v8, v10 ; GFX10-NEXT: v_pk_mul_f16 v8, v8, v10
; GFX10-NEXT: v_pk_mul_f16 v9, v9, v11
; GFX10-NEXT: v_pk_fma_f16 v4, v4, v6, v8 ; GFX10-NEXT: v_pk_fma_f16 v4, v4, v6, v8
; GFX10-NEXT: v_pk_fma_f16 v5, v5, v7, v9 ; GFX10-NEXT: v_pk_mul_f16 v6, v9, v11
; GFX10-NEXT: v_pk_fma_f16 v5, v5, v7, v6
; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v4 ; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v4
; GFX10-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v5
; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_add_f32_e32 v0, v0, v6 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v6
; GFX10-NEXT: v_add_f32_e32 v1, v1, v4 ; GFX10-NEXT: v_add_f32_e32 v1, v1, v4
; GFX10-NEXT: v_add_f32_e32 v2, v2, v7 ; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v5
; GFX10-NEXT: v_add_f32_e32 v3, v3, v5 ; GFX10-NEXT: v_add_f32_e32 v2, v2, v4
; GFX10-NEXT: v_cvt_f32_f16_sdwa v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_add_f32_e32 v3, v3, v4
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs: ; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs:
; GFX10-CONTRACT: ; %bb.0: ; %.entry ; GFX10-CONTRACT: ; %bb.0: ; %.entry
; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v8, v8, v10 ; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v8, v8, v10
; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v9, v9, v11
; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v4, v4, v6, v8 ; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v4, v4, v6, v8
; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v5, v5, v7, v9 ; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v6, v9, v11
; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v5, v5, v7, v6
; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v6, v4 ; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v6, v4
; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v7, v5
; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v6 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v6
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v4 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v4
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v7 ; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v4, v5
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v5 ; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v4
; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v4
; GFX10-CONTRACT-NEXT: ; return to shader part epilog ; GFX10-CONTRACT-NEXT: ; return to shader part epilog
; ;
; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs: ; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs:
; GFX10-DENORM: ; %bb.0: ; %.entry ; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_pk_mul_f16 v8, v8, v10 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v8, v8, v10
; GFX10-DENORM-NEXT: v_pk_mul_f16 v4, v4, v6 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v4, v4, v6
; GFX10-DENORM-NEXT: v_pk_mul_f16 v6, v9, v11 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v6, v9, v11
; GFX10-DENORM-NEXT: v_pk_mul_f16 v5, v5, v7 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v5, v5, v7
; GFX10-DENORM-NEXT: v_pk_add_f16 v4, v4, v8 ; GFX10-DENORM-NEXT: v_pk_add_f16 v4, v4, v8
; GFX10-DENORM-NEXT: v_pk_add_f16 v5, v5, v6 ; GFX10-DENORM-NEXT: v_pk_add_f16 v5, v5, v6
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v6, v4 ; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v6, v4
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v5
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v6 ; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v6
; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v4 ; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v4
; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v2, v7 ; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v4, v5
; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v3, v5 ; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v2, v4
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v3, v4
; GFX10-DENORM-NEXT: ; return to shader part epilog ; GFX10-DENORM-NEXT: ; return to shader part epilog
.entry: .entry:
%a = fmul <4 x half> %u, %v %a = fmul <4 x half> %u, %v
%b = call <4 x half> @llvm.fmuladd.v4f16(<4 x half> %y, <4 x half> %z, <4 x half> %a) %b = call <4 x half> @llvm.fmuladd.v4f16(<4 x half> %y, <4 x half> %z, <4 x half> %a)
%c = fpext <4 x half> %b to <4 x float> %c = fpext <4 x half> %b to <4 x float>
%d = fadd <4 x float> %x, %c %d = fadd <4 x float> %x, %c
ret <4 x float> %d ret <4 x float> %d
} }
declare float @llvm.fmuladd.f32(float, float, float) #0 declare float @llvm.fmuladd.f32(float, float, float) #0
declare half @llvm.fmuladd.f16(half, half, half) #0 declare half @llvm.fmuladd.f16(half, half, half) #0
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0 declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0
declare <4 x half> @llvm.fmuladd.v4f16(<4 x half>, <4 x half>, <4 x half>) #0 declare <4 x half> @llvm.fmuladd.v4f16(<4 x half>, <4 x half>, <4 x half>) #0
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll

Show First 20 Lines • Show All 546 Lines • ▼ Show 20 Lines
; GFX9-DENORM-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], v[24:25] ; GFX9-DENORM-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], v[24:25]
; GFX9-DENORM-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23] ; GFX9-DENORM-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23]
; GFX9-DENORM-NEXT: s_setpc_b64 s[30:31] ; GFX9-DENORM-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-CONTRACT-LABEL: test_f64_add_mul: ; GFX10-CONTRACT-LABEL: test_f64_add_mul:
; GFX10-CONTRACT: ; %bb.0: ; %.entry ; GFX10-CONTRACT: ; %bb.0: ; %.entry
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-CONTRACT-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CONTRACT-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-CONTRACT-NEXT: s_clause 0x8 ; GFX10-CONTRACT-NEXT: s_clause 0x6
; GFX10-CONTRACT-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
; GFX10-CONTRACT-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
; GFX10-CONTRACT-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:12
; GFX10-CONTRACT-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16
; GFX10-CONTRACT-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:20
; GFX10-CONTRACT-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:24
; GFX10-CONTRACT-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:28
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(5)
; GFX10-CONTRACT-NEXT: v_fma_f64 v[16:17], v[16:17], v[24:25], v[31:32]
; GFX10-CONTRACT-NEXT: s_clause 0x1
; GFX10-CONTRACT-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; GFX10-CONTRACT-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-CONTRACT-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 ; GFX10-CONTRACT-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:32
; GFX10-CONTRACT-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 ; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(5)
; GFX10-CONTRACT-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 ; GFX10-CONTRACT-NEXT: v_fma_f64 v[18:19], v[18:19], v[26:27], v[33:34]
; GFX10-CONTRACT-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:16 ; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(3)
; GFX10-CONTRACT-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:20 ; GFX10-CONTRACT-NEXT: v_fma_f64 v[20:21], v[20:21], v[28:29], v[35:36]
; GFX10-CONTRACT-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:24
; GFX10-CONTRACT-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:28
; GFX10-CONTRACT-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:32
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(6)
; GFX10-CONTRACT-NEXT: v_fma_f64 v[16:17], v[16:17], v[24:25], v[32:33]
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(4)
; GFX10-CONTRACT-NEXT: v_fma_f64 v[18:19], v[18:19], v[26:27], v[34:35]
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(2)
; GFX10-CONTRACT-NEXT: v_fma_f64 v[20:21], v[20:21], v[28:29], v[36:37]
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0)
; GFX10-CONTRACT-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], v[38:39]
; GFX10-CONTRACT-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17] ; GFX10-CONTRACT-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17]
; GFX10-CONTRACT-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] ; GFX10-CONTRACT-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19]
; GFX10-CONTRACT-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] ; GFX10-CONTRACT-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21]
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0)
; GFX10-CONTRACT-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], v[37:38]
; GFX10-CONTRACT-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23] ; GFX10-CONTRACT-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23]
; GFX10-CONTRACT-NEXT: s_setpc_b64 s[30:31] ; GFX10-CONTRACT-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-DENORM-LABEL: test_f64_add_mul: ; GFX10-DENORM-LABEL: test_f64_add_mul:
; GFX10-DENORM: ; %bb.0: ; %.entry ; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-DENORM-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-DENORM-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-DENORM-NEXT: s_clause 0x8 ; GFX10-DENORM-NEXT: s_clause 0x6
; GFX10-DENORM-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
; GFX10-DENORM-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
; GFX10-DENORM-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:12
; GFX10-DENORM-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16
; GFX10-DENORM-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:20
; GFX10-DENORM-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:24
; GFX10-DENORM-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:28
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(5)
; GFX10-DENORM-NEXT: v_fma_f64 v[16:17], v[16:17], v[24:25], v[31:32]
; GFX10-DENORM-NEXT: s_clause 0x1
; GFX10-DENORM-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; GFX10-DENORM-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-DENORM-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 ; GFX10-DENORM-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:32
; GFX10-DENORM-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 ; GFX10-DENORM-NEXT: s_waitcnt vmcnt(5)
; GFX10-DENORM-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 ; GFX10-DENORM-NEXT: v_fma_f64 v[18:19], v[18:19], v[26:27], v[33:34]
; GFX10-DENORM-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:16 ; GFX10-DENORM-NEXT: s_waitcnt vmcnt(3)
; GFX10-DENORM-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:20 ; GFX10-DENORM-NEXT: v_fma_f64 v[20:21], v[20:21], v[28:29], v[35:36]
; GFX10-DENORM-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:24
; GFX10-DENORM-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:28
; GFX10-DENORM-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:32
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(6)
; GFX10-DENORM-NEXT: v_fma_f64 v[16:17], v[16:17], v[24:25], v[32:33]
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(4)
; GFX10-DENORM-NEXT: v_fma_f64 v[18:19], v[18:19], v[26:27], v[34:35]
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(2)
; GFX10-DENORM-NEXT: v_fma_f64 v[20:21], v[20:21], v[28:29], v[36:37]
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0)
; GFX10-DENORM-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], v[38:39]
; GFX10-DENORM-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17] ; GFX10-DENORM-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17]
; GFX10-DENORM-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] ; GFX10-DENORM-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19]
; GFX10-DENORM-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] ; GFX10-DENORM-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21]
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0)
; GFX10-DENORM-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], v[37:38]
; GFX10-DENORM-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23] ; GFX10-DENORM-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23]
; GFX10-DENORM-NEXT: s_setpc_b64 s[30:31] ; GFX10-DENORM-NEXT: s_setpc_b64 s[30:31]
.entry: .entry:
%x = fmul fast <4 x double> %c, %d %x = fmul fast <4 x double> %c, %d
%y = call fast <4 x double> @llvm.fmuladd.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %x) %y = call fast <4 x double> @llvm.fmuladd.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %x)
%z = fadd fast <4 x double> %y, %e %z = fadd fast <4 x double> %y, %e
ret <4 x double> %z ret <4 x double> %z
} }
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; GFX9-DENORM-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], v[24:25] ; GFX9-DENORM-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], v[24:25]
; GFX9-DENORM-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23] ; GFX9-DENORM-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23]
; GFX9-DENORM-NEXT: s_setpc_b64 s[30:31] ; GFX9-DENORM-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-CONTRACT-LABEL: test_f64_add_mul_rhs: ; GFX10-CONTRACT-LABEL: test_f64_add_mul_rhs:
; GFX10-CONTRACT: ; %bb.0: ; %.entry ; GFX10-CONTRACT: ; %bb.0: ; %.entry
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-CONTRACT-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CONTRACT-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-CONTRACT-NEXT: s_clause 0x8 ; GFX10-CONTRACT-NEXT: s_clause 0x6
; GFX10-CONTRACT-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
; GFX10-CONTRACT-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
; GFX10-CONTRACT-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:12
; GFX10-CONTRACT-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16
; GFX10-CONTRACT-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:20
; GFX10-CONTRACT-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:24
; GFX10-CONTRACT-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:28
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(5)
; GFX10-CONTRACT-NEXT: v_fma_f64 v[16:17], v[16:17], v[24:25], v[31:32]
; GFX10-CONTRACT-NEXT: s_clause 0x1
; GFX10-CONTRACT-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; GFX10-CONTRACT-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-CONTRACT-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 ; GFX10-CONTRACT-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:32
; GFX10-CONTRACT-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 ; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(5)
; GFX10-CONTRACT-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 ; GFX10-CONTRACT-NEXT: v_fma_f64 v[18:19], v[18:19], v[26:27], v[33:34]
; GFX10-CONTRACT-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:16 ; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(3)
; GFX10-CONTRACT-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:20 ; GFX10-CONTRACT-NEXT: v_fma_f64 v[20:21], v[20:21], v[28:29], v[35:36]
; GFX10-CONTRACT-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:24
; GFX10-CONTRACT-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:28
; GFX10-CONTRACT-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:32
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(6)
; GFX10-CONTRACT-NEXT: v_fma_f64 v[16:17], v[16:17], v[24:25], v[32:33]
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(4)
; GFX10-CONTRACT-NEXT: v_fma_f64 v[18:19], v[18:19], v[26:27], v[34:35]
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(2)
; GFX10-CONTRACT-NEXT: v_fma_f64 v[20:21], v[20:21], v[28:29], v[36:37]
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0)
; GFX10-CONTRACT-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], v[38:39]
; GFX10-CONTRACT-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17] ; GFX10-CONTRACT-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17]
; GFX10-CONTRACT-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] ; GFX10-CONTRACT-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19]
; GFX10-CONTRACT-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] ; GFX10-CONTRACT-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21]
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0)
; GFX10-CONTRACT-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], v[37:38]
; GFX10-CONTRACT-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23] ; GFX10-CONTRACT-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23]
; GFX10-CONTRACT-NEXT: s_setpc_b64 s[30:31] ; GFX10-CONTRACT-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-DENORM-LABEL: test_f64_add_mul_rhs: ; GFX10-DENORM-LABEL: test_f64_add_mul_rhs:
; GFX10-DENORM: ; %bb.0: ; %.entry ; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-DENORM-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-DENORM-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-DENORM-NEXT: s_clause 0x8 ; GFX10-DENORM-NEXT: s_clause 0x6
; GFX10-DENORM-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
; GFX10-DENORM-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
; GFX10-DENORM-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:12
; GFX10-DENORM-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16
; GFX10-DENORM-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:20
; GFX10-DENORM-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:24
; GFX10-DENORM-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:28
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(5)
; GFX10-DENORM-NEXT: v_fma_f64 v[16:17], v[16:17], v[24:25], v[31:32]
; GFX10-DENORM-NEXT: s_clause 0x1
; GFX10-DENORM-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; GFX10-DENORM-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-DENORM-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 ; GFX10-DENORM-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:32
; GFX10-DENORM-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 ; GFX10-DENORM-NEXT: s_waitcnt vmcnt(5)
; GFX10-DENORM-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 ; GFX10-DENORM-NEXT: v_fma_f64 v[18:19], v[18:19], v[26:27], v[33:34]
; GFX10-DENORM-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:16 ; GFX10-DENORM-NEXT: s_waitcnt vmcnt(3)
; GFX10-DENORM-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:20 ; GFX10-DENORM-NEXT: v_fma_f64 v[20:21], v[20:21], v[28:29], v[35:36]
; GFX10-DENORM-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:24
; GFX10-DENORM-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:28
; GFX10-DENORM-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:32
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(6)
; GFX10-DENORM-NEXT: v_fma_f64 v[16:17], v[16:17], v[24:25], v[32:33]
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(4)
; GFX10-DENORM-NEXT: v_fma_f64 v[18:19], v[18:19], v[26:27], v[34:35]
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(2)
; GFX10-DENORM-NEXT: v_fma_f64 v[20:21], v[20:21], v[28:29], v[36:37]
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0)
; GFX10-DENORM-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], v[38:39]
; GFX10-DENORM-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17] ; GFX10-DENORM-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17]
; GFX10-DENORM-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] ; GFX10-DENORM-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19]
; GFX10-DENORM-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] ; GFX10-DENORM-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21]
; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0)
; GFX10-DENORM-NEXT: v_fma_f64 v[22:23], v[22:23], v[30:31], v[37:38]
; GFX10-DENORM-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23] ; GFX10-DENORM-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23]
; GFX10-DENORM-NEXT: s_setpc_b64 s[30:31] ; GFX10-DENORM-NEXT: s_setpc_b64 s[30:31]
.entry: .entry:
%x = fmul fast <4 x double> %c, %d %x = fmul fast <4 x double> %c, %d
%y = call fast <4 x double> @llvm.fmuladd.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %x) %y = call fast <4 x double> @llvm.fmuladd.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %x)
%z = fadd fast <4 x double> %e, %y %z = fadd fast <4 x double> %e, %y
ret <4 x double> %z ret <4 x double> %z
} }
declare <4 x double> @llvm.fmuladd.v4f64(<4 x double>, <4 x double>, <4 x double>) #0 declare <4 x double> @llvm.fmuladd.v4f64(<4 x double>, <4 x double>, <4 x double>) #0
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0 declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0
declare <4 x half> @llvm.fmuladd.v4f16(<4 x half>, <4 x half>, <4 x half>) #0 declare <4 x half> @llvm.fmuladd.v4f16(<4 x half>, <4 x half>, <4 x half>) #0
declare double @llvm.fmuladd.f64(double, double, double) #0 declare double @llvm.fmuladd.f64(double, double, double) #0
declare float @llvm.fmuladd.f32(float, float, float) #0 declare float @llvm.fmuladd.f32(float, float, float) #0
declare half @llvm.fmuladd.f16(half, half, half) #0 declare half @llvm.fmuladd.f16(half, half, half) #0
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll

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; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v2, v4 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v2, v4
; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v3, v5 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v3, v5
; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v8, v6 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v8, v6
; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v9, v7 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v9, v7
; GFX9-DENORM-NEXT: ; return to shader part epilog ; GFX9-DENORM-NEXT: ; return to shader part epilog
; ;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul: ; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul:
; GFX10-DENORM: ; %bb.0: ; %entry ; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_xor_b32_e32 v8, 0x80008000, v2
; GFX10-DENORM-NEXT: v_xor_b32_e32 v9, 0x80008000, v3
; GFX10-DENORM-NEXT: v_fma_mix_f32 v5, v0, -v2, -v5 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v5, v0, -v2, -v5 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v2, -v4 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_xor_b32_e32 v2, 0x80008000, v3
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v1, -v3, -v7 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v1, -v3, -v7 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v8, -v4 op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v1, v2, -v6 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v1, v9, -v6 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_mov_b32_e32 v1, v5 ; GFX10-DENORM-NEXT: v_mov_b32_e32 v1, v5
; GFX10-DENORM-NEXT: ; return to shader part epilog ; GFX10-DENORM-NEXT: ; return to shader part epilog
entry: entry:
%a = fmul fast <4 x half> %x, %y %a = fmul fast <4 x half> %x, %y
%b = fneg <4 x half> %a %b = fneg <4 x half> %a
%c = fpext <4 x half> %b to <4 x float> %c = fpext <4 x half> %b to <4 x float>
%d = fsub fast <4 x float> %c, %z %d = fsub fast <4 x float> %c, %z
ret <4 x float> %d ret <4 x float> %d
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; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v2, v4 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v2, v4
; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v3, v5 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v3, v5
; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v8, v6 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v8, v6
; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v9, v7 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v9, v7
; GFX9-DENORM-NEXT: ; return to shader part epilog ; GFX9-DENORM-NEXT: ; return to shader part epilog
; ;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul: ; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %entry ; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_xor_b32_e32 v8, 0x80008000, v2
; GFX10-DENORM-NEXT: v_xor_b32_e32 v9, 0x80008000, v3
; GFX10-DENORM-NEXT: v_fma_mix_f32 v5, v0, -v2, -v5 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v5, v0, -v2, -v5 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v2, -v4 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_xor_b32_e32 v2, 0x80008000, v3
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v1, -v3, -v7 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v1, -v3, -v7 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v8, -v4 op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v1, v2, -v6 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v1, v9, -v6 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_mov_b32_e32 v1, v5 ; GFX10-DENORM-NEXT: v_mov_b32_e32 v1, v5
; GFX10-DENORM-NEXT: ; return to shader part epilog ; GFX10-DENORM-NEXT: ; return to shader part epilog
entry: entry:
%a = fmul fast <4 x half> %x, %y %a = fmul fast <4 x half> %x, %y
%b = fpext <4 x half> %a to <4 x float> %b = fpext <4 x half> %a to <4 x float>
%c = fneg <4 x float> %b %c = fneg <4 x float> %b
%d = fsub fast <4 x float> %c, %z %d = fsub fast <4 x float> %c, %z
ret <4 x float> %d ret <4 x float> %d
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; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v0, v6 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v0, v6
; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v4 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v4
; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v2, v7 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v2, v7
; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v3, v5 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v3, v5
; GFX9-DENORM-NEXT: ; return to shader part epilog ; GFX9-DENORM-NEXT: ; return to shader part epilog
; ;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul2: ; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry ; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_xor_b32_e32 v8, 0x80008000, v6
; GFX10-DENORM-NEXT: v_xor_b32_e32 v9, 0x80008000, v7
; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, -v4, -v6, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, -v4, -v6, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_xor_b32_e32 v6, 0x80008000, v6
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, -v5, -v7, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, -v5, -v7, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v4, v8, v0 op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v4, v6, v0 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, -v5, v9, v2 op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_xor_b32_e32 v4, 0x80008000, v7
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, -v5, v4, v2 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog ; GFX10-DENORM-NEXT: ; return to shader part epilog
entry: entry:
%a = fmul fast <4 x half> %y, %z %a = fmul fast <4 x half> %y, %z
%b = fneg <4 x half> %a %b = fneg <4 x half> %a
%c = fpext <4 x half> %b to <4 x float> %c = fpext <4 x half> %b to <4 x float>
%d = fsub fast <4 x float> %x, %c %d = fsub fast <4 x float> %x, %c
ret <4 x float> %d ret <4 x float> %d
} }
Show All 11 Lines
; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v0, v6 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v0, v6
; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v4 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v4
; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v2, v7 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v2, v7
; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v3, v5 ; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v3, v5
; GFX9-DENORM-NEXT: ; return to shader part epilog ; GFX9-DENORM-NEXT: ; return to shader part epilog
; ;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul2: ; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry ; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_xor_b32_e32 v8, 0x80008000, v6
; GFX10-DENORM-NEXT: v_xor_b32_e32 v9, 0x80008000, v7
; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, -v4, -v6, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, -v4, -v6, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_xor_b32_e32 v6, 0x80008000, v6
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, -v5, -v7, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, -v5, -v7, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v4, v8, v0 op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v4, v6, v0 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, -v5, v9, v2 op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: v_xor_b32_e32 v4, 0x80008000, v7
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, -v5, v4, v2 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog ; GFX10-DENORM-NEXT: ; return to shader part epilog
entry: entry:
%a = fmul fast <4 x half> %y, %z %a = fmul fast <4 x half> %y, %z
%b = fpext <4 x half> %a to <4 x float> %b = fpext <4 x half> %a to <4 x float>
%c = fneg <4 x float> %b %c = fneg <4 x float> %b
%d = fsub fast <4 x float> %x, %c %d = fsub fast <4 x float> %x, %c
ret <4 x float> %d ret <4 x float> %d
} }

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll

Show First 20 Lines • Show All 336 Lines • ▼ Show 20 Lines
; GFX10-LABEL: extractelement_vgpr_v4i128_vgpr_idx: ; GFX10-LABEL: extractelement_vgpr_v4i128_vgpr_idx:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx4 v[8:11], v[0:1], off ; GFX10-NEXT: global_load_dwordx4 v[8:11], v[0:1], off
; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off offset:16 ; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off offset:16
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v2
; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 6, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 7, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v3
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_cndmask_b32_e32 v12, v8, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v12, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v13, v9, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v13, v9, v11, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v14, v8, v10, s4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
; GFX10-NEXT: v_cndmask_b32_e64 v15, v9, v11, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s4
; GFX10-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:32 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v11, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 2, v3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 2, v3
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v10, v12, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v11, v13, v5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
; GFX10-NEXT: v_cndmask_b32_e64 v4, v14, v4, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v4, s4
; GFX10-NEXT: v_cndmask_b32_e64 v5, v15, v5, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v5, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 3, v3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 3, v3
; GFX10-NEXT: v_cndmask_b32_e32 v16, v12, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v16, v10, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v17, v13, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v17, v11, v7, vcc_lo
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:32
; GFX10-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:48 ; GFX10-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:48
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v6, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v6, s4
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v7, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v7, s4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 4, v3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 4, v3
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v9, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v8, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v8, s4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v9, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v9, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v3
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v10, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v10, s4
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v11, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v11, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v3 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v3
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v2
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v12, s4
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v13, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 7, v3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 7, v3
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v12, s5
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v13, s5
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v13, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v14, s6
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v15, s6
; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v14, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v14, s4
; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v15, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v15, s4
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: extractelement_vgpr_v4i128_vgpr_idx: ; GFX11-LABEL: extractelement_vgpr_v4i128_vgpr_idx:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_b128 v[16:19], v[0:1], off ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off offset:16 ; GFX11-NEXT: global_load_b128 v[7:10], v[0:1], off offset:16
; GFX11-NEXT: global_load_b128 v[8:11], v[0:1], off offset:32 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 1, v2
; GFX11-NEXT: global_load_b128 v[12:15], v[0:1], off offset:48 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v2 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT: s_waitcnt vmcnt(3)
; GFX11-NEXT: v_cndmask_b32_e32 v3, v17, v19, vcc_lo
; GFX11-NEXT: v_dual_cndmask_b32 v2, v16, v18 :: v_dual_add_nc_u32 v1, 1, v0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v1
; GFX11-NEXT: s_waitcnt vmcnt(2)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v18, s0
; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v19, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v6 :: v_dual_cndmask_b32 v3, v3, v7
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v4, v16, v4, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v17, v5, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v1
; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v8 :: v_dual_cndmask_b32 v3, v3, v9 ; GFX11-NEXT: v_dual_cndmask_b32 v11, v3, v5 :: v_dual_cndmask_b32 v12, v4, v6
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_add_nc_u32_e32 v16, 1, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 6, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 7, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v16
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v5, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_cndmask_b32_e32 v5, v11, v7, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v6, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v6, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v7, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 4, v1 ; GFX11-NEXT: v_cndmask_b32_e32 v6, v12, v8, vcc_lo
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_cndmask_b32 v3, v3, v11 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v8, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v8, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v9, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v1 ; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v6, v6, v10
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v12 :: v_dual_cndmask_b32 v3, v3, v13 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v9, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v10, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v10, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v11, s0 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 6, v1 ; GFX11-NEXT: global_load_b128 v[8:11], v[0:1], off offset:32
; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v14, vcc_lo ; GFX11-NEXT: global_load_b128 v[12:15], v[0:1], off offset:48
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v12, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 4, v16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v13, s0 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v5, v8 :: v_dual_cndmask_b32 v1, v6, v9
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 7, v1 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v15, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v8, s0
; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, v14, s0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v9, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v16
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v10, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, v15, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v11, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 7, v16
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v12, s1
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v13, s1
; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v4, v4, v13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v14, s2
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v15, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, v14, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v4, v15, s0
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%vector = load <4 x i128>, ptr addrspace(1) %ptr %vector = load <4 x i128>, ptr addrspace(1) %ptr
%element = extractelement <4 x i128> %vector, i32 %idx %element = extractelement <4 x i128> %vector, i32 %idx
ret i128 %element ret i128 %element
} }
define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(ptr addrspace(4) inreg %ptr, i32 %idx) { define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(ptr addrspace(4) inreg %ptr, i32 %idx) {
; GFX9-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX9-LABEL: extractelement_sgpr_v4i128_vgpr_idx:
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; GFX7-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NEXT: v_readfirstlane_b32 s0, v0
; GFX7-NEXT: v_readfirstlane_b32 s1, v1 ; GFX7-NEXT: v_readfirstlane_b32 s1, v1
; GFX7-NEXT: v_readfirstlane_b32 s2, v2 ; GFX7-NEXT: v_readfirstlane_b32 s2, v2
; GFX7-NEXT: v_readfirstlane_b32 s3, v3 ; GFX7-NEXT: v_readfirstlane_b32 s3, v3
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX10-LABEL: extractelement_sgpr_v4i128_vgpr_idx:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx16 s[4:19], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx16 s[8:23], s[2:3], 0x0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 2, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v2
; GFX10-NEXT: s_mov_b32 null, 0
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v2, s6 ; GFX10-NEXT: v_mov_b32_e32 v3, s10
; GFX10-NEXT: v_mov_b32_e32 v3, s7 ; GFX10-NEXT: v_cndmask_b32_e32 v0, s8, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, s4, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s12, s6
; GFX10-NEXT: v_cndmask_b32_e32 v5, s5, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s14, s1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s16, s2
; GFX10-NEXT: v_cndmask_b32_e64 v2, s4, v2, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s18, s3
; GFX10-NEXT: v_cndmask_b32_e64 v3, s5, v3, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s20, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s22, s5
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s9, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s8, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s9, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s11, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 4, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s12, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s13, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s12, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s13, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s15, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s14, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s15, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 6, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s17, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s16, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s17, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 7, v1
; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, s18, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, s19, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s18, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s19, s0
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s11
; GFX10-NEXT: v_cndmask_b32_e32 v1, s9, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s13, s6
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s15, s1
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s17, s2
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s19, s3
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s21, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s23, s5
; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 3, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 4, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 5, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 6, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, s8, v3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 2, v1
; GFX10-NEXT: v_cndmask_b32_e32 v0, s9, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 7, v1
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s12, s8
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s13, s8
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s14, s3
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s15, s3
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s16, s4
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s17, s4
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s18, s5
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s19, s5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s20, s6
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s21, s6
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s22, s7
; GFX10-NEXT: v_cndmask_b32_e64 v3, v0, s23, s7
; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX11-LABEL: extractelement_sgpr_v4i128_vgpr_idx:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b512 s[4:19], s[2:3], 0x0 ; GFX11-NEXT: s_load_b512 s[4:19], s[2:3], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll

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; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX7-NEXT: s_setpc_b64 s[30:31] ; GFX7-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: extractelement_vgpr_v8i16_vgpr_idx: ; GFX10-LABEL: extractelement_vgpr_v8i16_vgpr_idx:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off ; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v7, 1, v2
; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 ; GFX10-NEXT: v_and_b32_e32 v1, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v7
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: extractelement_vgpr_v8i16_vgpr_idx: ; GFX11-LABEL: extractelement_vgpr_v8i16_vgpr_idx:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
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llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll

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; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX7-NEXT: s_setpc_b64 s[30:31] ; GFX7-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: extractelement_vgpr_v16i8_vgpr_idx: ; GFX10-LABEL: extractelement_vgpr_v16i8_vgpr_idx:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off ; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 2, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v7, 2, v2
; GFX10-NEXT: v_and_b32_e32 v2, 3, v2 ; GFX10-NEXT: v_and_b32_e32 v1, 3, v2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v7
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: extractelement_vgpr_v16i8_vgpr_idx: ; GFX11-LABEL: extractelement_vgpr_v16i8_vgpr_idx:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
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llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll

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; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6 ; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6
; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fdiv_v2f16: ; GFX10-LABEL: v_fdiv_v2f16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1
; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v0 ; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v0 ; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX10-NEXT: v_rcp_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v5 ; GFX10-NEXT: v_div_fixup_f16 v1, v2, v1, v0
; GFX10-NEXT: v_rcp_f32_e32 v4, v4 ; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v3
; GFX10-NEXT: v_mul_f32_e32 v3, v6, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_mul_f32_e32 v4, v7, v4 ; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v0
; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4 ; GFX10-NEXT: v_mul_f32_e32 v2, v4, v2
; GFX10-NEXT: v_div_fixup_f16 v0, v3, v1, v0 ; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX10-NEXT: v_div_fixup_f16 v1, v4, v2, v5 ; GFX10-NEXT: v_div_fixup_f16 v0, v2, v3, v0
; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX10-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fdiv_v2f16: ; GFX11-LABEL: v_fdiv_v2f16:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
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; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6 ; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6
; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fdiv_v2f16_ulp25: ; GFX10-LABEL: v_fdiv_v2f16_ulp25:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1
; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v0 ; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v0 ; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX10-NEXT: v_rcp_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v5 ; GFX10-NEXT: v_div_fixup_f16 v1, v2, v1, v0
; GFX10-NEXT: v_rcp_f32_e32 v4, v4 ; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v3
; GFX10-NEXT: v_mul_f32_e32 v3, v6, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_mul_f32_e32 v4, v7, v4 ; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v0
; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4 ; GFX10-NEXT: v_mul_f32_e32 v2, v4, v2
; GFX10-NEXT: v_div_fixup_f16 v0, v3, v1, v0 ; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX10-NEXT: v_div_fixup_f16 v1, v4, v2, v5 ; GFX10-NEXT: v_div_fixup_f16 v0, v2, v3, v0
; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX10-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fdiv_v2f16_ulp25: ; GFX11-LABEL: v_fdiv_v2f16_ulp25:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
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; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6 ; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6
; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fdiv_v2f16_arcp_ulp25: ; GFX10-LABEL: v_fdiv_v2f16_arcp_ulp25:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1
; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v0 ; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v0 ; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX10-NEXT: v_rcp_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v5 ; GFX10-NEXT: v_div_fixup_f16 v1, v2, v1, v0
; GFX10-NEXT: v_rcp_f32_e32 v4, v4 ; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v3
; GFX10-NEXT: v_mul_f32_e32 v3, v6, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_mul_f32_e32 v4, v7, v4 ; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v0
; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4 ; GFX10-NEXT: v_mul_f32_e32 v2, v4, v2
; GFX10-NEXT: v_div_fixup_f16 v0, v3, v1, v0 ; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX10-NEXT: v_div_fixup_f16 v1, v4, v2, v5 ; GFX10-NEXT: v_div_fixup_f16 v0, v2, v3, v0
; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX10-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fdiv_v2f16_arcp_ulp25: ; GFX11-LABEL: v_fdiv_v2f16_arcp_ulp25:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
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llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll

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; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 ; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31] ; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-IEEE-LABEL: v_fdiv_f32: ; GFX10-IEEE-LABEL: v_fdiv_f32:
; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0 ; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-IEEE-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2 ; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0 ; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3 ; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3 ; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4 ; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-FLUSH-LABEL: v_fdiv_f32: ; GFX10-FLUSH-LABEL: v_fdiv_f32:
; GFX10-FLUSH: ; %bb.0: ; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
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; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 ; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-IEEE-LABEL: v_fdiv_f32_ulp25: ; GFX10-IEEE-LABEL: v_fdiv_f32_ulp25:
; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0 ; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-IEEE-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2 ; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0 ; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3 ; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3 ; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4 ; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-FLUSH-LABEL: v_fdiv_f32_ulp25: ; GFX10-FLUSH-LABEL: v_fdiv_f32_ulp25:
; GFX10-FLUSH: ; %bb.0: ; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1| ; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
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; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0 ; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31] ; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-IEEE-LABEL: v_rcp_f32: ; GFX10-IEEE-LABEL: v_rcp_f32:
; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-IEEE-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0 ; GFX10-IEEE-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v1 ; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v1
; GFX10-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0 ; GFX10-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2 ; GFX10-IEEE-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v2 ; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX10-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v3 ; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX10-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-FLUSH-LABEL: v_rcp_f32: ; GFX10-FLUSH-LABEL: v_rcp_f32:
; GFX10-FLUSH: ; %bb.0: ; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0
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; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0 ; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31] ; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-IEEE-LABEL: v_rcp_f32_arcp: ; GFX10-IEEE-LABEL: v_rcp_f32_arcp:
; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-IEEE-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0 ; GFX10-IEEE-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v1 ; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v1
; GFX10-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0 ; GFX10-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2 ; GFX10-IEEE-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v2 ; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX10-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v3 ; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX10-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-FLUSH-LABEL: v_rcp_f32_arcp: ; GFX10-FLUSH-LABEL: v_rcp_f32_arcp:
; GFX10-FLUSH: ; %bb.0: ; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0
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; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 ; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-IEEE-LABEL: v_fdiv_f32_arcp_ulp25: ; GFX10-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0 ; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-IEEE-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2 ; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0 ; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3 ; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3 ; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4 ; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25: ; GFX10-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:
; GFX10-FLUSH: ; %bb.0: ; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1| ; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
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; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1 ; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31] ; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-IEEE-LABEL: v_fdiv_v2f32: ; GFX10-IEEE-LABEL: v_fdiv_v2f32:
; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0 ; GFX10-IEEE-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v4
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v5
; GFX10-IEEE-NEXT: v_div_scale_f32 v6, vcc_lo, v0, v2, v0
; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5
; GFX10-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v8, v5
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
; GFX10-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
; GFX10-IEEE-NEXT: v_div_scale_f32 v5, s4, v3, v3, v1 ; GFX10-IEEE-NEXT: v_div_scale_f32 v5, s4, v3, v3, v1
; GFX10-IEEE-NEXT: v_div_scale_f32 v10, vcc_lo, v0, v2, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v4
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v7, v5
; GFX10-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.0
; GFX10-IEEE-NEXT: v_fma_f32 v9, -v5, v7, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v6, v8, v6
; GFX10-IEEE-NEXT: v_div_scale_f32 v8, s4, v1, v3, v1
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v9, v7
; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v10, v6
; GFX10-IEEE-NEXT: v_mul_f32_e32 v11, v8, v7
; GFX10-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v10
; GFX10-IEEE-NEXT: v_fma_f32 v13, -v5, v11, v8
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v9, v12, v6
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v11, v13, v7
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v10
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v5, v11, v8
; GFX10-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v9
; GFX10-IEEE-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v5, v5, v7, v11
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v5
; GFX10-IEEE-NEXT: v_fma_f32 v7, -v5, v6, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX10-IEEE-NEXT: v_div_scale_f32 v7, vcc_lo, v1, v3, v1
; GFX10-IEEE-NEXT: v_mul_f32_e32 v8, v7, v6
; GFX10-IEEE-NEXT: v_fma_f32 v9, -v5, v8, v7
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v8, v9, v6
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v5, v8, v7
; GFX10-IEEE-NEXT: v_div_fmas_f32 v5, v5, v6, v8
; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-FLUSH-LABEL: v_fdiv_v2f32: ; GFX10-FLUSH-LABEL: v_fdiv_v2f32:
; GFX10-FLUSH: ; %bb.0: ; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v6, vcc_lo, v0, v2, v0 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v6, vcc_lo, v0, v2, v0
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v4 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v4
; GFX10-FLUSH-NEXT: s_denorm_mode 3 ; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0 ; GFX10-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v7, v5 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v7, v5
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5
; GFX10-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6 ; GFX10-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v7, v8, v5 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v7, v8, v5
; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6 ; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6
; GFX10-FLUSH-NEXT: s_denorm_mode 0 ; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v6, s4, v3, v3, v1
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7 ; GFX10-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v6 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v5, vcc_lo, v1, v3, v1
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0 ; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v1, v3, v1 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v3, v3, v1
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 3 ; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v6, v5, 1.0 ; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v4, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v4, v5 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v6, v4
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v5 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4
; GFX10-FLUSH-NEXT: v_fma_f32 v7, -v6, v4, v2 ; GFX10-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v7, v5 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v6, v7, v4
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v6, v4, v2 ; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5
; GFX10-FLUSH-NEXT: s_denorm_mode 0 ; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v5, v4 ; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v6
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1 ; GFX10-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31] ; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-IEEE-LABEL: v_fdiv_v2f32: ; GFX11-IEEE-LABEL: v_fdiv_v2f32:
; GFX11-IEEE: ; %bb.0: ; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-IEEE-NEXT: v_div_scale_f32 v4, null, v2, v2, v0 ; GFX11-IEEE-NEXT: v_div_scale_f32 v4, null, v2, v2, v0
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; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1 ; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-IEEE-LABEL: v_fdiv_v2f32_ulp25: ; GFX10-IEEE-LABEL: v_fdiv_v2f32_ulp25:
; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0 ; GFX10-IEEE-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v4
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v5
; GFX10-IEEE-NEXT: v_div_scale_f32 v6, vcc_lo, v0, v2, v0
; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5
; GFX10-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v8, v5
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
; GFX10-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
; GFX10-IEEE-NEXT: v_div_scale_f32 v5, s4, v3, v3, v1 ; GFX10-IEEE-NEXT: v_div_scale_f32 v5, s4, v3, v3, v1
; GFX10-IEEE-NEXT: v_div_scale_f32 v10, vcc_lo, v0, v2, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v4
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v7, v5
; GFX10-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.0
; GFX10-IEEE-NEXT: v_fma_f32 v9, -v5, v7, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v6, v8, v6
; GFX10-IEEE-NEXT: v_div_scale_f32 v8, s4, v1, v3, v1
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v9, v7
; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v10, v6
; GFX10-IEEE-NEXT: v_mul_f32_e32 v11, v8, v7
; GFX10-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v10
; GFX10-IEEE-NEXT: v_fma_f32 v13, -v5, v11, v8
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v9, v12, v6
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v11, v13, v7
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v10
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v5, v11, v8
; GFX10-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v9
; GFX10-IEEE-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v5, v5, v7, v11
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v5
; GFX10-IEEE-NEXT: v_fma_f32 v7, -v5, v6, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX10-IEEE-NEXT: v_div_scale_f32 v7, vcc_lo, v1, v3, v1
; GFX10-IEEE-NEXT: v_mul_f32_e32 v8, v7, v6
; GFX10-IEEE-NEXT: v_fma_f32 v9, -v5, v8, v7
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v8, v9, v6
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v5, v8, v7
; GFX10-IEEE-NEXT: v_div_fmas_f32 v5, v5, v6, v8
; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-FLUSH-LABEL: v_fdiv_v2f32_ulp25: ; GFX10-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
; GFX10-FLUSH: ; %bb.0: ; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v2| ; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v2|
; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s4 ; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s4
; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v3| ; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v3|
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s4
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v2 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v5
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v4, v0 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v4, v0
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v2
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v5, v1 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v2, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31] ; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-IEEE-LABEL: v_fdiv_v2f32_ulp25: ; GFX11-IEEE-LABEL: v_fdiv_v2f32_ulp25:
; GFX11-IEEE: ; %bb.0: ; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-IEEE-NEXT: v_div_scale_f32 v4, null, v2, v2, v0 ; GFX11-IEEE-NEXT: v_div_scale_f32 v4, null, v2, v2, v0
; GFX11-IEEE-NEXT: v_div_scale_f32 v5, null, v3, v3, v1 ; GFX11-IEEE-NEXT: v_div_scale_f32 v5, null, v3, v3, v1
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; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0 ; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31] ; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-IEEE-LABEL: v_rcp_v2f32: ; GFX10-IEEE-LABEL: v_rcp_v2f32:
; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.0 ; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-IEEE-NEXT: v_div_scale_f32 v3, s4, v1, v1, 1.0 ; GFX10-IEEE-NEXT: v_div_scale_f32 v3, s4, v1, v1, 1.0
; GFX10-IEEE-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v3
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0
; GFX10-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v4
; GFX10-IEEE-NEXT: v_div_scale_f32 v6, s4, 1.0, v1, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v7, v5
; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v8, v4
; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v6, v5
; GFX10-IEEE-NEXT: v_fma_f32 v10, -v2, v7, v8
; GFX10-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v6
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v4
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v9, v11, v5
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v8
; GFX10-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v6
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v7
; GFX10-IEEE-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v3, v3, v5, v9
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v3
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX10-IEEE-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v1, 1.0
; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4
; GFX10-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v6, v7, v4
; GFX10-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5
; GFX10-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-FLUSH-LABEL: v_rcp_v2f32: ; GFX10-FLUSH-LABEL: v_rcp_v2f32:
; GFX10-FLUSH: ; %bb.0: ; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.0 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 3 ; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 ; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 ; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 ; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-FLUSH-NEXT: s_denorm_mode 0 ; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v1, v1, 1.0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 ; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v4 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, s4, v1, v1, 1.0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v1, 1.0
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0 ; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v3
; GFX10-FLUSH-NEXT: s_denorm_mode 3 ; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.0 ; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v3, v2, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v2, v5, v2
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v3 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v2
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v2 ; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v4
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v2
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v2 ; GFX10-FLUSH-NEXT: v_fma_f32 v3, -v3, v5, v4
; GFX10-FLUSH-NEXT: s_denorm_mode 0 ; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 ; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v3, v2, v5
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0 ; GFX10-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31] ; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-IEEE-LABEL: v_rcp_v2f32: ; GFX11-IEEE-LABEL: v_rcp_v2f32:
; GFX11-IEEE: ; %bb.0: ; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v0, v0, 1.0 ; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v0, v0, 1.0
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; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0 ; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31] ; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-IEEE-LABEL: v_rcp_v2f32_arcp: ; GFX10-IEEE-LABEL: v_rcp_v2f32_arcp:
; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.0 ; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-IEEE-NEXT: v_div_scale_f32 v3, s4, v1, v1, 1.0 ; GFX10-IEEE-NEXT: v_div_scale_f32 v3, s4, v1, v1, 1.0
; GFX10-IEEE-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v3
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0
; GFX10-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v4
; GFX10-IEEE-NEXT: v_div_scale_f32 v6, s4, 1.0, v1, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v7, v5
; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v8, v4
; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v6, v5
; GFX10-IEEE-NEXT: v_fma_f32 v10, -v2, v7, v8
; GFX10-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v6
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v4
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v9, v11, v5
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v8
; GFX10-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v6
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v7
; GFX10-IEEE-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v3, v3, v5, v9
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v3
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX10-IEEE-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v1, 1.0
; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4
; GFX10-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v6, v7, v4
; GFX10-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5
; GFX10-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-FLUSH-LABEL: v_rcp_v2f32_arcp: ; GFX10-FLUSH-LABEL: v_rcp_v2f32_arcp:
; GFX10-FLUSH: ; %bb.0: ; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.0 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 3 ; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 ; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 ; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 ; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-FLUSH-NEXT: s_denorm_mode 0 ; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v1, v1, 1.0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 ; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v4 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, s4, v1, v1, 1.0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v1, 1.0
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0 ; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v3
; GFX10-FLUSH-NEXT: s_denorm_mode 3 ; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.0 ; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v3, v2, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v2, v5, v2
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v3 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v2
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v2 ; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v4
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v2
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v2 ; GFX10-FLUSH-NEXT: v_fma_f32 v3, -v3, v5, v4
; GFX10-FLUSH-NEXT: s_denorm_mode 0 ; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 ; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v3, v2, v5
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0 ; GFX10-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31] ; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-IEEE-LABEL: v_rcp_v2f32_arcp: ; GFX11-IEEE-LABEL: v_rcp_v2f32_arcp:
; GFX11-IEEE: ; %bb.0: ; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v0, v0, 1.0 ; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v0, v0, 1.0
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; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1 ; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25: ; GFX10-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0 ; GFX10-IEEE-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v4
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v5
; GFX10-IEEE-NEXT: v_div_scale_f32 v6, vcc_lo, v0, v2, v0
; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5
; GFX10-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v8, v5
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
; GFX10-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
; GFX10-IEEE-NEXT: v_div_scale_f32 v5, s4, v3, v3, v1 ; GFX10-IEEE-NEXT: v_div_scale_f32 v5, s4, v3, v3, v1
; GFX10-IEEE-NEXT: v_div_scale_f32 v10, vcc_lo, v0, v2, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v4
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v7, v5
; GFX10-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.0
; GFX10-IEEE-NEXT: v_fma_f32 v9, -v5, v7, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v6, v8, v6
; GFX10-IEEE-NEXT: v_div_scale_f32 v8, s4, v1, v3, v1
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v9, v7
; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v10, v6
; GFX10-IEEE-NEXT: v_mul_f32_e32 v11, v8, v7
; GFX10-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v10
; GFX10-IEEE-NEXT: v_fma_f32 v13, -v5, v11, v8
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v9, v12, v6
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v11, v13, v7
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v10
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v5, v11, v8
; GFX10-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v9
; GFX10-IEEE-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v5, v5, v7, v11
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v5
; GFX10-IEEE-NEXT: v_fma_f32 v7, -v5, v6, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX10-IEEE-NEXT: v_div_scale_f32 v7, vcc_lo, v1, v3, v1
; GFX10-IEEE-NEXT: v_mul_f32_e32 v8, v7, v6
; GFX10-IEEE-NEXT: v_fma_f32 v9, -v5, v8, v7
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v8, v9, v6
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v5, v8, v7
; GFX10-IEEE-NEXT: v_div_fmas_f32 v5, v5, v6, v8
; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25: ; GFX10-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:
; GFX10-FLUSH: ; %bb.0: ; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v2| ; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v2|
; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s4 ; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s4
; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v3| ; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v3|
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s4
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v2 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v5
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v4, v0 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v4, v0
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v2
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v5, v1 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v2, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31] ; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25: ; GFX11-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
; GFX11-IEEE: ; %bb.0: ; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-IEEE-NEXT: v_div_scale_f32 v4, null, v2, v2, v0 ; GFX11-IEEE-NEXT: v_div_scale_f32 v4, null, v2, v2, v0
; GFX11-IEEE-NEXT: v_div_scale_f32 v5, null, v3, v3, v1 ; GFX11-IEEE-NEXT: v_div_scale_f32 v5, null, v3, v3, v1
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llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll

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; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] ; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fdiv_f64: ; GFX10-LABEL: v_fdiv_f64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_div_scale_f64 v[4:5], s4, v[2:3], v[2:3], v[0:1] ; GFX10-NEXT: v_div_scale_f64 v[4:5], s4, v[2:3], v[2:3], v[0:1]
; GFX10-NEXT: v_div_scale_f64 v[10:11], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] ; GFX10-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 ; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] ; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 ; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] ; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7] ; GFX10-NEXT: v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX10-NEXT: v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11] ; GFX10-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX10-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9] ; GFX10-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX10-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] ; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fdiv_f64: ; GFX11-LABEL: v_fdiv_f64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1] ; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
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; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] ; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fdiv_f64_ulp25: ; GFX10-LABEL: v_fdiv_f64_ulp25:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_div_scale_f64 v[4:5], s4, v[2:3], v[2:3], v[0:1] ; GFX10-NEXT: v_div_scale_f64 v[4:5], s4, v[2:3], v[2:3], v[0:1]
; GFX10-NEXT: v_div_scale_f64 v[10:11], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] ; GFX10-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 ; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] ; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 ; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] ; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7] ; GFX10-NEXT: v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX10-NEXT: v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11] ; GFX10-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX10-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9] ; GFX10-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX10-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] ; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fdiv_f64_ulp25: ; GFX11-LABEL: v_fdiv_f64_ulp25:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1] ; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
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; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 ; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_rcp_f64: ; GFX10-LABEL: v_rcp_f64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_div_scale_f64 v[2:3], s4, v[0:1], v[0:1], 1.0 ; GFX10-NEXT: v_div_scale_f64 v[2:3], s4, v[0:1], v[0:1], 1.0
; GFX10-NEXT: v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] ; GFX10-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 ; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX10-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] ; GFX10-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 ; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX10-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] ; GFX10-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX10-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] ; GFX10-NEXT: v_div_scale_f64 v[6:7], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] ; GFX10-NEXT: v_mul_f64 v[8:9], v[6:7], v[4:5]
; GFX10-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] ; GFX10-NEXT: v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
; GFX10-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 ; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_rcp_f64: ; GFX11-LABEL: v_rcp_f64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0 ; GFX11-NEXT: v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
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; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 ; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_rcp_f64_arcp: ; GFX10-LABEL: v_rcp_f64_arcp:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_div_scale_f64 v[2:3], s4, v[0:1], v[0:1], 1.0 ; GFX10-NEXT: v_div_scale_f64 v[2:3], s4, v[0:1], v[0:1], 1.0
; GFX10-NEXT: v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] ; GFX10-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 ; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX10-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] ; GFX10-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 ; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX10-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] ; GFX10-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX10-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] ; GFX10-NEXT: v_div_scale_f64 v[6:7], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] ; GFX10-NEXT: v_mul_f64 v[8:9], v[6:7], v[4:5]
; GFX10-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] ; GFX10-NEXT: v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
; GFX10-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 ; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_rcp_f64_arcp: ; GFX11-LABEL: v_rcp_f64_arcp:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0 ; GFX11-NEXT: v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 ; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_rcp_f64_ulp25: ; GFX10-LABEL: v_rcp_f64_ulp25:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_div_scale_f64 v[2:3], s4, v[0:1], v[0:1], 1.0 ; GFX10-NEXT: v_div_scale_f64 v[2:3], s4, v[0:1], v[0:1], 1.0
; GFX10-NEXT: v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] ; GFX10-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 ; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX10-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] ; GFX10-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 ; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX10-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] ; GFX10-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX10-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] ; GFX10-NEXT: v_div_scale_f64 v[6:7], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] ; GFX10-NEXT: v_mul_f64 v[8:9], v[6:7], v[4:5]
; GFX10-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] ; GFX10-NEXT: v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
; GFX10-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 ; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_rcp_f64_ulp25: ; GFX11-LABEL: v_rcp_f64_ulp25:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0 ; GFX11-NEXT: v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] ; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fdiv_f64_arcp_ulp25: ; GFX10-LABEL: v_fdiv_f64_arcp_ulp25:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_div_scale_f64 v[4:5], s4, v[2:3], v[2:3], v[0:1] ; GFX10-NEXT: v_div_scale_f64 v[4:5], s4, v[2:3], v[2:3], v[0:1]
; GFX10-NEXT: v_div_scale_f64 v[10:11], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] ; GFX10-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 ; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] ; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 ; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] ; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7] ; GFX10-NEXT: v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX10-NEXT: v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11] ; GFX10-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX10-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9] ; GFX10-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX10-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] ; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fdiv_f64_arcp_ulp25: ; GFX11-LABEL: v_fdiv_f64_arcp_ulp25:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1] ; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] ; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fdiv_v2f64: ; GFX10-LABEL: v_fdiv_v2f64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_div_scale_f64 v[8:9], s4, v[4:5], v[4:5], v[0:1] ; GFX10-NEXT: v_div_scale_f64 v[8:9], s4, v[4:5], v[4:5], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; GFX10-NEXT: v_div_scale_f64 v[12:13], vcc_lo, v[0:1], v[4:5], v[0:1]
; GFX10-NEXT: v_mul_f64 v[14:15], v[12:13], v[10:11]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
; GFX10-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
; GFX10-NEXT: v_div_scale_f64 v[10:11], s4, v[6:7], v[6:7], v[2:3] ; GFX10-NEXT: v_div_scale_f64 v[10:11], s4, v[6:7], v[6:7], v[2:3]
; GFX10-NEXT: v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[4:5], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[12:13], v[8:9]
; GFX10-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
; GFX10-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX10-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; GFX10-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX10-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX10-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; GFX10-NEXT: v_div_scale_f64 v[16:17], s4, v[2:3], v[6:7], v[2:3]
; GFX10-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX10-NEXT: v_mul_f64 v[18:19], v[20:21], v[12:13]
; GFX10-NEXT: v_mul_f64 v[22:23], v[16:17], v[14:15]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[8:9], v[18:19], v[20:21]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[10:11], v[22:23], v[16:17]
; GFX10-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
; GFX10-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23]
; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1] ; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[12:13], v[10:11]
; GFX10-NEXT: v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
; GFX10-NEXT: v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
; GFX10-NEXT: v_div_scale_f64 v[14:15], vcc_lo, v[2:3], v[6:7], v[2:3]
; GFX10-NEXT: v_mul_f64 v[16:17], v[14:15], v[12:13]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
; GFX10-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
; GFX10-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] ; GFX10-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fdiv_v2f64: ; GFX11-LABEL: v_fdiv_v2f64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[0:1] ; GFX11-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[0:1]
; GFX11-NEXT: v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3] ; GFX11-NEXT: v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3]
; GFX11-NEXT: v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[4:5], v[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_rcp_f64_e32 v[12:13], v[8:9] ; GFX11-NEXT: v_rcp_f64_e32 v[12:13], v[8:9]
; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11] ; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 ; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 ; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] ; GFX11-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] ; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 ; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 ; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] ; GFX11-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; GFX11-NEXT: v_div_scale_f64 v[16:17], s0, v[2:3], v[6:7], v[2:3] ; GFX11-NEXT: v_div_scale_f64 v[16:17], vcc_lo, v[0:1], v[4:5], v[0:1]
; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] ; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f64 v[18:19], v[20:21], v[12:13] ; GFX11-NEXT: v_mul_f64 v[18:19], v[16:17], v[12:13]
; GFX11-NEXT: v_mul_f64 v[22:23], v[16:17], v[14:15] ; GFX11-NEXT: v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
; GFX11-NEXT: v_div_scale_f64 v[16:17], s0, v[2:3], v[6:7], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_fma_f64 v[8:9], -v[8:9], v[18:19], v[20:21]
; GFX11-NEXT: v_fma_f64 v[10:11], -v[10:11], v[22:23], v[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19] ; GFX11-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
; GFX11-NEXT: v_mul_f64 v[20:21], v[16:17], v[14:15]
; GFX11-NEXT: s_mov_b32 vcc_lo, s0 ; GFX11-NEXT: s_mov_b32 vcc_lo, s0
; GFX11-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1] ; GFX11-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
; GFX11-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
; GFX11-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] ; GFX11-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv <2 x double> %a, %b %fdiv = fdiv <2 x double> %a, %b
ret <2 x double> %fdiv ret <2 x double> %fdiv
} }
define <2 x double> @v_fdiv_v2f64_afn(<2 x double> %a, <2 x double> %b) { define <2 x double> @v_fdiv_v2f64_afn(<2 x double> %a, <2 x double> %b) {
; GCN-LABEL: v_fdiv_v2f64_afn: ; GCN-LABEL: v_fdiv_v2f64_afn:
Show All 17 Lines
; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[14:15] ; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[14:15]
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fdiv_v2f64_afn: ; GFX10-LABEL: v_fdiv_v2f64_afn:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_rcp_f64_e32 v[8:9], v[4:5] ; GFX10-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[6:7] ; GFX10-NEXT: v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0 ; GFX10-NEXT: v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0 ; GFX10-NEXT: v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[12:13], v[8:9], v[8:9] ; GFX10-NEXT: v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
; GFX10-NEXT: v_fma_f64 v[10:11], v[14:15], v[10:11], v[10:11] ; GFX10-NEXT: v_mul_f64 v[10:11], v[0:1], v[8:9]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0 ; GFX10-NEXT: v_fma_f64 v[0:1], -v[4:5], v[10:11], v[0:1]
; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0 ; GFX10-NEXT: v_rcp_f64_e32 v[4:5], v[6:7]
; GFX10-NEXT: v_fma_f64 v[8:9], v[12:13], v[8:9], v[8:9] ; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[10:11]
; GFX10-NEXT: v_fma_f64 v[10:11], v[14:15], v[10:11], v[10:11] ; GFX10-NEXT: v_fma_f64 v[8:9], -v[6:7], v[4:5], 1.0
; GFX10-NEXT: v_mul_f64 v[12:13], v[0:1], v[8:9] ; GFX10-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
; GFX10-NEXT: v_mul_f64 v[14:15], v[2:3], v[10:11] ; GFX10-NEXT: v_fma_f64 v[8:9], -v[6:7], v[4:5], 1.0
; GFX10-NEXT: v_fma_f64 v[0:1], -v[4:5], v[12:13], v[0:1] ; GFX10-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
; GFX10-NEXT: v_fma_f64 v[2:3], -v[6:7], v[14:15], v[2:3] ; GFX10-NEXT: v_mul_f64 v[8:9], v[2:3], v[4:5]
; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[12:13] ; GFX10-NEXT: v_fma_f64 v[2:3], -v[6:7], v[8:9], v[2:3]
; GFX10-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[14:15] ; GFX10-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[8:9]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fdiv_v2f64_afn: ; GFX11-LABEL: v_fdiv_v2f64_afn:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5] ; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7] ; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] ; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fdiv_v2f64_ulp25: ; GFX10-LABEL: v_fdiv_v2f64_ulp25:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_div_scale_f64 v[8:9], s4, v[4:5], v[4:5], v[0:1] ; GFX10-NEXT: v_div_scale_f64 v[8:9], s4, v[4:5], v[4:5], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; GFX10-NEXT: v_div_scale_f64 v[12:13], vcc_lo, v[0:1], v[4:5], v[0:1]
; GFX10-NEXT: v_mul_f64 v[14:15], v[12:13], v[10:11]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
; GFX10-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
; GFX10-NEXT: v_div_scale_f64 v[10:11], s4, v[6:7], v[6:7], v[2:3] ; GFX10-NEXT: v_div_scale_f64 v[10:11], s4, v[6:7], v[6:7], v[2:3]
; GFX10-NEXT: v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[4:5], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[12:13], v[8:9]
; GFX10-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
; GFX10-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX10-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; GFX10-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX10-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX10-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; GFX10-NEXT: v_div_scale_f64 v[16:17], s4, v[2:3], v[6:7], v[2:3]
; GFX10-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX10-NEXT: v_mul_f64 v[18:19], v[20:21], v[12:13]
; GFX10-NEXT: v_mul_f64 v[22:23], v[16:17], v[14:15]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[8:9], v[18:19], v[20:21]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[10:11], v[22:23], v[16:17]
; GFX10-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
; GFX10-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23]
; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1] ; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[12:13], v[10:11]
; GFX10-NEXT: v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
; GFX10-NEXT: v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
; GFX10-NEXT: v_div_scale_f64 v[14:15], vcc_lo, v[2:3], v[6:7], v[2:3]
; GFX10-NEXT: v_mul_f64 v[16:17], v[14:15], v[12:13]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
; GFX10-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
; GFX10-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] ; GFX10-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fdiv_v2f64_ulp25: ; GFX11-LABEL: v_fdiv_v2f64_ulp25:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[0:1] ; GFX11-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[0:1]
; GFX11-NEXT: v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3] ; GFX11-NEXT: v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3]
; GFX11-NEXT: v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[4:5], v[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_rcp_f64_e32 v[12:13], v[8:9] ; GFX11-NEXT: v_rcp_f64_e32 v[12:13], v[8:9]
; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11] ; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 ; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 ; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] ; GFX11-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] ; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 ; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 ; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] ; GFX11-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; GFX11-NEXT: v_div_scale_f64 v[16:17], s0, v[2:3], v[6:7], v[2:3] ; GFX11-NEXT: v_div_scale_f64 v[16:17], vcc_lo, v[0:1], v[4:5], v[0:1]
; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] ; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f64 v[18:19], v[20:21], v[12:13] ; GFX11-NEXT: v_mul_f64 v[18:19], v[16:17], v[12:13]
; GFX11-NEXT: v_mul_f64 v[22:23], v[16:17], v[14:15] ; GFX11-NEXT: v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
; GFX11-NEXT: v_div_scale_f64 v[16:17], s0, v[2:3], v[6:7], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_fma_f64 v[8:9], -v[8:9], v[18:19], v[20:21]
; GFX11-NEXT: v_fma_f64 v[10:11], -v[10:11], v[22:23], v[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19] ; GFX11-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
; GFX11-NEXT: v_mul_f64 v[20:21], v[16:17], v[14:15]
; GFX11-NEXT: s_mov_b32 vcc_lo, s0 ; GFX11-NEXT: s_mov_b32 vcc_lo, s0
; GFX11-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1] ; GFX11-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
; GFX11-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
; GFX11-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] ; GFX11-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv <2 x double> %a, %b, !fpmath !0 %fdiv = fdiv <2 x double> %a, %b, !fpmath !0
ret <2 x double> %fdiv ret <2 x double> %fdiv
} }
define <2 x double> @v_rcp_v2f64(<2 x double> %x) { define <2 x double> @v_rcp_v2f64(<2 x double> %x) {
; GFX6-LABEL: v_rcp_v2f64: ; GFX6-LABEL: v_rcp_v2f64:
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0 ; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_rcp_v2f64: ; GFX10-LABEL: v_rcp_v2f64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_div_scale_f64 v[4:5], s4, v[0:1], v[0:1], 1.0 ; GFX10-NEXT: v_div_scale_f64 v[4:5], s4, v[0:1], v[0:1], 1.0
; GFX10-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT: v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX10-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX10-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX10-NEXT: v_div_scale_f64 v[6:7], s4, v[2:3], v[2:3], 1.0 ; GFX10-NEXT: v_div_scale_f64 v[6:7], s4, v[2:3], v[2:3], 1.0
; GFX10-NEXT: v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX10-NEXT: v_div_scale_f64 v[12:13], s4, 1.0, v[2:3], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX10-NEXT: v_mul_f64 v[14:15], v[16:17], v[8:9]
; GFX10-NEXT: v_mul_f64 v[18:19], v[12:13], v[10:11]
; GFX10-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[16:17]
; GFX10-NEXT: v_fma_f64 v[6:7], -v[6:7], v[18:19], v[12:13]
; GFX10-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15]
; GFX10-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[18:19]
; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[0:1], 1.0 ; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[0:1], 1.0
; GFX10-NEXT: v_rcp_f64_e32 v[8:9], v[6:7]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
; GFX10-NEXT: v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[2:3], 1.0
; GFX10-NEXT: v_mul_f64 v[12:13], v[10:11], v[8:9]
; GFX10-NEXT: v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
; GFX10-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
; GFX10-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0 ; GFX10-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_rcp_v2f64: ; GFX11-LABEL: v_rcp_v2f64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], 1.0 ; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], 1.0
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0 ; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_rcp_v2f64_arcp: ; GFX10-LABEL: v_rcp_v2f64_arcp:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_div_scale_f64 v[4:5], s4, v[0:1], v[0:1], 1.0 ; GFX10-NEXT: v_div_scale_f64 v[4:5], s4, v[0:1], v[0:1], 1.0
; GFX10-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT: v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX10-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX10-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX10-NEXT: v_div_scale_f64 v[6:7], s4, v[2:3], v[2:3], 1.0 ; GFX10-NEXT: v_div_scale_f64 v[6:7], s4, v[2:3], v[2:3], 1.0
; GFX10-NEXT: v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX10-NEXT: v_div_scale_f64 v[12:13], s4, 1.0, v[2:3], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX10-NEXT: v_mul_f64 v[14:15], v[16:17], v[8:9]
; GFX10-NEXT: v_mul_f64 v[18:19], v[12:13], v[10:11]
; GFX10-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[16:17]
; GFX10-NEXT: v_fma_f64 v[6:7], -v[6:7], v[18:19], v[12:13]
; GFX10-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15]
; GFX10-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[18:19]
; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[0:1], 1.0 ; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[0:1], 1.0
; GFX10-NEXT: v_rcp_f64_e32 v[8:9], v[6:7]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
; GFX10-NEXT: v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[2:3], 1.0
; GFX10-NEXT: v_mul_f64 v[12:13], v[10:11], v[8:9]
; GFX10-NEXT: v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
; GFX10-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
; GFX10-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0 ; GFX10-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_rcp_v2f64_arcp: ; GFX11-LABEL: v_rcp_v2f64_arcp:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], 1.0 ; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], 1.0
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[10:11] ; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[10:11]
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_rcp_v2f64_arcp_afn: ; GFX10-LABEL: v_rcp_v2f64_arcp_afn:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_rcp_f64_e32 v[4:5], v[0:1] ; GFX10-NEXT: v_rcp_f64_e32 v[4:5], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[6:7], v[2:3] ; GFX10-NEXT: v_fma_f64 v[6:7], -v[0:1], v[4:5], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], -v[0:1], v[4:5], 1.0 ; GFX10-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0 ; GFX10-NEXT: v_fma_f64 v[6:7], -v[0:1], v[4:5], 1.0
; GFX10-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5] ; GFX10-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
; GFX10-NEXT: v_fma_f64 v[6:7], v[10:11], v[6:7], v[6:7] ; GFX10-NEXT: v_mul_f64 v[6:7], 1.0, v[4:5]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[0:1], v[4:5], 1.0 ; GFX10-NEXT: v_fma_f64 v[0:1], -v[0:1], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0 ; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[6:7]
; GFX10-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5] ; GFX10-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
; GFX10-NEXT: v_fma_f64 v[6:7], v[10:11], v[6:7], v[6:7] ; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX10-NEXT: v_mul_f64 v[8:9], 1.0, v[4:5] ; GFX10-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
; GFX10-NEXT: v_mul_f64 v[10:11], 1.0, v[6:7] ; GFX10-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX10-NEXT: v_fma_f64 v[0:1], -v[0:1], v[8:9], 1.0 ; GFX10-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
; GFX10-NEXT: v_fma_f64 v[2:3], -v[2:3], v[10:11], 1.0 ; GFX10-NEXT: v_mul_f64 v[6:7], 1.0, v[4:5]
; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[8:9] ; GFX10-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[10:11] ; GFX10-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_rcp_v2f64_arcp_afn: ; GFX11-LABEL: v_rcp_v2f64_arcp_afn:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_rcp_f64_e32 v[4:5], v[0:1] ; GFX11-NEXT: v_rcp_f64_e32 v[4:5], v[0:1]
; GFX11-NEXT: v_rcp_f64_e32 v[6:7], v[2:3] ; GFX11-NEXT: v_rcp_f64_e32 v[6:7], v[2:3]
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0 ; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_rcp_v2f64_ulp25: ; GFX10-LABEL: v_rcp_v2f64_ulp25:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_div_scale_f64 v[4:5], s4, v[0:1], v[0:1], 1.0 ; GFX10-NEXT: v_div_scale_f64 v[4:5], s4, v[0:1], v[0:1], 1.0
; GFX10-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT: v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX10-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX10-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX10-NEXT: v_div_scale_f64 v[6:7], s4, v[2:3], v[2:3], 1.0 ; GFX10-NEXT: v_div_scale_f64 v[6:7], s4, v[2:3], v[2:3], 1.0
; GFX10-NEXT: v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX10-NEXT: v_div_scale_f64 v[12:13], s4, 1.0, v[2:3], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX10-NEXT: v_mul_f64 v[14:15], v[16:17], v[8:9]
; GFX10-NEXT: v_mul_f64 v[18:19], v[12:13], v[10:11]
; GFX10-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[16:17]
; GFX10-NEXT: v_fma_f64 v[6:7], -v[6:7], v[18:19], v[12:13]
; GFX10-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15]
; GFX10-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[18:19]
; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[0:1], 1.0 ; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[0:1], 1.0
; GFX10-NEXT: v_rcp_f64_e32 v[8:9], v[6:7]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
; GFX10-NEXT: v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[2:3], 1.0
; GFX10-NEXT: v_mul_f64 v[12:13], v[10:11], v[8:9]
; GFX10-NEXT: v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
; GFX10-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
; GFX10-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0 ; GFX10-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_rcp_v2f64_ulp25: ; GFX11-LABEL: v_rcp_v2f64_ulp25:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], 1.0 ; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], 1.0
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[14:15] ; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[14:15]
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fdiv_v2f64_afn_ulp25: ; GFX10-LABEL: v_fdiv_v2f64_afn_ulp25:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_rcp_f64_e32 v[8:9], v[4:5] ; GFX10-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[6:7] ; GFX10-NEXT: v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0 ; GFX10-NEXT: v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0 ; GFX10-NEXT: v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[12:13], v[8:9], v[8:9] ; GFX10-NEXT: v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
; GFX10-NEXT: v_fma_f64 v[10:11], v[14:15], v[10:11], v[10:11] ; GFX10-NEXT: v_mul_f64 v[10:11], v[0:1], v[8:9]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0 ; GFX10-NEXT: v_fma_f64 v[0:1], -v[4:5], v[10:11], v[0:1]
; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0 ; GFX10-NEXT: v_rcp_f64_e32 v[4:5], v[6:7]
; GFX10-NEXT: v_fma_f64 v[8:9], v[12:13], v[8:9], v[8:9] ; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[10:11]
; GFX10-NEXT: v_fma_f64 v[10:11], v[14:15], v[10:11], v[10:11] ; GFX10-NEXT: v_fma_f64 v[8:9], -v[6:7], v[4:5], 1.0
; GFX10-NEXT: v_mul_f64 v[12:13], v[0:1], v[8:9] ; GFX10-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
; GFX10-NEXT: v_mul_f64 v[14:15], v[2:3], v[10:11] ; GFX10-NEXT: v_fma_f64 v[8:9], -v[6:7], v[4:5], 1.0
; GFX10-NEXT: v_fma_f64 v[0:1], -v[4:5], v[12:13], v[0:1] ; GFX10-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
; GFX10-NEXT: v_fma_f64 v[2:3], -v[6:7], v[14:15], v[2:3] ; GFX10-NEXT: v_mul_f64 v[8:9], v[2:3], v[4:5]
; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[12:13] ; GFX10-NEXT: v_fma_f64 v[2:3], -v[6:7], v[8:9], v[2:3]
; GFX10-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[14:15] ; GFX10-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[8:9]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fdiv_v2f64_afn_ulp25: ; GFX11-LABEL: v_fdiv_v2f64_afn_ulp25:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5] ; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7] ; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] ; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fdiv_v2f64_arcp_ulp25: ; GFX10-LABEL: v_fdiv_v2f64_arcp_ulp25:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_div_scale_f64 v[8:9], s4, v[4:5], v[4:5], v[0:1] ; GFX10-NEXT: v_div_scale_f64 v[8:9], s4, v[4:5], v[4:5], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; GFX10-NEXT: v_div_scale_f64 v[12:13], vcc_lo, v[0:1], v[4:5], v[0:1]
; GFX10-NEXT: v_mul_f64 v[14:15], v[12:13], v[10:11]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
; GFX10-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
; GFX10-NEXT: v_div_scale_f64 v[10:11], s4, v[6:7], v[6:7], v[2:3] ; GFX10-NEXT: v_div_scale_f64 v[10:11], s4, v[6:7], v[6:7], v[2:3]
; GFX10-NEXT: v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[4:5], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[12:13], v[8:9]
; GFX10-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
; GFX10-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX10-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; GFX10-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX10-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX10-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; GFX10-NEXT: v_div_scale_f64 v[16:17], s4, v[2:3], v[6:7], v[2:3]
; GFX10-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX10-NEXT: v_mul_f64 v[18:19], v[20:21], v[12:13]
; GFX10-NEXT: v_mul_f64 v[22:23], v[16:17], v[14:15]
; GFX10-NEXT: v_fma_f64 v[8:9], -v[8:9], v[18:19], v[20:21]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[10:11], v[22:23], v[16:17]
; GFX10-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
; GFX10-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23]
; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1] ; GFX10-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
; GFX10-NEXT: v_rcp_f64_e32 v[12:13], v[10:11]
; GFX10-NEXT: v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
; GFX10-NEXT: v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
; GFX10-NEXT: v_div_scale_f64 v[14:15], vcc_lo, v[2:3], v[6:7], v[2:3]
; GFX10-NEXT: v_mul_f64 v[16:17], v[14:15], v[12:13]
; GFX10-NEXT: v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
; GFX10-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
; GFX10-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] ; GFX10-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fdiv_v2f64_arcp_ulp25: ; GFX11-LABEL: v_fdiv_v2f64_arcp_ulp25:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[0:1] ; GFX11-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[0:1]
; GFX11-NEXT: v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3] ; GFX11-NEXT: v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3]
; GFX11-NEXT: v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[4:5], v[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_rcp_f64_e32 v[12:13], v[8:9] ; GFX11-NEXT: v_rcp_f64_e32 v[12:13], v[8:9]
; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11] ; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 ; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 ; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] ; GFX11-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] ; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 ; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 ; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] ; GFX11-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; GFX11-NEXT: v_div_scale_f64 v[16:17], s0, v[2:3], v[6:7], v[2:3] ; GFX11-NEXT: v_div_scale_f64 v[16:17], vcc_lo, v[0:1], v[4:5], v[0:1]
; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] ; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f64 v[18:19], v[20:21], v[12:13] ; GFX11-NEXT: v_mul_f64 v[18:19], v[16:17], v[12:13]
; GFX11-NEXT: v_mul_f64 v[22:23], v[16:17], v[14:15] ; GFX11-NEXT: v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
; GFX11-NEXT: v_div_scale_f64 v[16:17], s0, v[2:3], v[6:7], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_fma_f64 v[8:9], -v[8:9], v[18:19], v[20:21]
; GFX11-NEXT: v_fma_f64 v[10:11], -v[10:11], v[22:23], v[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19] ; GFX11-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
; GFX11-NEXT: v_mul_f64 v[20:21], v[16:17], v[14:15]
; GFX11-NEXT: s_mov_b32 vcc_lo, s0 ; GFX11-NEXT: s_mov_b32 vcc_lo, s0
; GFX11-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1] ; GFX11-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
; GFX11-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
; GFX11-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] ; GFX11-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp <2 x double> %a, %b, !fpmath !0 %fdiv = fdiv arcp <2 x double> %a, %b, !fpmath !0
ret <2 x double> %fdiv ret <2 x double> %fdiv
} }
define <2 x double> @v_fdiv_v2f64_arcp_afn_ulp25(<2 x double> %a, <2 x double> %b) { define <2 x double> @v_fdiv_v2f64_arcp_afn_ulp25(<2 x double> %a, <2 x double> %b) {
; GCN-LABEL: v_fdiv_v2f64_arcp_afn_ulp25: ; GCN-LABEL: v_fdiv_v2f64_arcp_afn_ulp25:
Show All 17 Lines
; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[14:15] ; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[14:15]
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fdiv_v2f64_arcp_afn_ulp25: ; GFX10-LABEL: v_fdiv_v2f64_arcp_afn_ulp25:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_rcp_f64_e32 v[8:9], v[4:5] ; GFX10-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[6:7] ; GFX10-NEXT: v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0 ; GFX10-NEXT: v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0 ; GFX10-NEXT: v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
; GFX10-NEXT: v_fma_f64 v[8:9], v[12:13], v[8:9], v[8:9] ; GFX10-NEXT: v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
; GFX10-NEXT: v_fma_f64 v[10:11], v[14:15], v[10:11], v[10:11] ; GFX10-NEXT: v_mul_f64 v[10:11], v[0:1], v[8:9]
; GFX10-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0 ; GFX10-NEXT: v_fma_f64 v[0:1], -v[4:5], v[10:11], v[0:1]
; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0 ; GFX10-NEXT: v_rcp_f64_e32 v[4:5], v[6:7]
; GFX10-NEXT: v_fma_f64 v[8:9], v[12:13], v[8:9], v[8:9] ; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[10:11]
; GFX10-NEXT: v_fma_f64 v[10:11], v[14:15], v[10:11], v[10:11] ; GFX10-NEXT: v_fma_f64 v[8:9], -v[6:7], v[4:5], 1.0
; GFX10-NEXT: v_mul_f64 v[12:13], v[0:1], v[8:9] ; GFX10-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
; GFX10-NEXT: v_mul_f64 v[14:15], v[2:3], v[10:11] ; GFX10-NEXT: v_fma_f64 v[8:9], -v[6:7], v[4:5], 1.0
; GFX10-NEXT: v_fma_f64 v[0:1], -v[4:5], v[12:13], v[0:1] ; GFX10-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
; GFX10-NEXT: v_fma_f64 v[2:3], -v[6:7], v[14:15], v[2:3] ; GFX10-NEXT: v_mul_f64 v[8:9], v[2:3], v[4:5]
; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[12:13] ; GFX10-NEXT: v_fma_f64 v[2:3], -v[6:7], v[8:9], v[2:3]
; GFX10-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[14:15] ; GFX10-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[8:9]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fdiv_v2f64_arcp_afn_ulp25: ; GFX11-LABEL: v_fdiv_v2f64_arcp_afn_ulp25:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5] ; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7] ; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
Show All 27 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll

Show First 20 Lines • Show All 339 Lines • ▼ Show 20 Lines
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc ; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v2, v0, s[4:5] glc dlc ; GFX10-NEXT: global_load_dword v2, v0, s[4:5] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v3, v0, s[6:7] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_max_f32_e64 v1, -v1, -v1 ; GFX10-NEXT: v_max_f32_e64 v1, -v1, -v1
; GFX10-NEXT: v_max_f32_e32 v2, v2, v2 ; GFX10-NEXT: v_max_f32_e32 v2, v2, v2
; GFX10-NEXT: v_max_f32_e32 v3, v3, v3 ; GFX10-NEXT: v_min_f32_e32 v3, v1, v2
; GFX10-NEXT: v_max_f32_e32 v4, v1, v2
; GFX10-NEXT: v_min_f32_e32 v1, v1, v2
; GFX10-NEXT: v_min_f32_e32 v2, v4, v3
; GFX10-NEXT: v_max_f32_e32 v1, v1, v2 ; GFX10-NEXT: v_max_f32_e32 v1, v1, v2
; GFX10-NEXT: global_load_dword v2, v0, s[6:7] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_max_f32_e32 v2, v2, v2
; GFX10-NEXT: v_min_f32_e32 v1, v1, v2
; GFX10-NEXT: v_max_f32_e32 v1, v3, v1
; GFX10-NEXT: global_store_dword v0, v1, s[0:1] ; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_test_no_global_nnans_med3_f32_pat0_srcmod0: ; GFX11-LABEL: v_test_no_global_nnans_med3_f32_pat0_srcmod0:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 ; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc ; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v2, v0, s[4:5] glc dlc ; GFX10-NEXT: global_load_dword v2, v0, s[4:5] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v3, v0, s[6:7] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_max_f32_e32 v1, v1, v1 ; GFX10-NEXT: v_max_f32_e32 v1, v1, v1
; GFX10-NEXT: v_max_f32_e32 v2, v2, v2 ; GFX10-NEXT: v_max_f32_e32 v2, v2, v2
; GFX10-NEXT: v_max_f32_e32 v3, v3, v3 ; GFX10-NEXT: v_min_f32_e32 v3, v1, v2
; GFX10-NEXT: v_max_f32_e32 v4, v1, v2 ; GFX10-NEXT: v_max_f32_e32 v1, v1, v2
; GFX10-NEXT: global_load_dword v2, v0, s[6:7] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_max_f32_e32 v2, v2, v2
; GFX10-NEXT: v_min_f32_e32 v1, v1, v2 ; GFX10-NEXT: v_min_f32_e32 v1, v1, v2
; GFX10-NEXT: v_min_f32_e32 v2, v4, v3 ; GFX10-NEXT: v_max_f32_e32 v1, v3, v1
; GFX10-NEXT: v_max_f32_e32 v2, v1, v2 ; GFX10-NEXT: global_store_dword v[0:1], v3, off
; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v0, v2, s[0:1] ; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_test_safe_med3_f32_pat0_multi_use0: ; GFX11-LABEL: v_test_safe_med3_f32_pat0_multi_use0:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 ; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc
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llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 893 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshl_v2i8: ; GFX10-LABEL: v_fshl_v2i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v2 ; GFX10-NEXT: v_and_b32_e32 v3, 7, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 8, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 8, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 8, v0 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX10-NEXT: v_xor_b32_e32 v7, -1, v2 ; GFX10-NEXT: s_movk_i32 s4, 0xff
; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1 ; GFX10-NEXT: v_lshlrev_b16 v3, v3, v0
; GFX10-NEXT: v_xor_b32_e32 v6, -1, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX10-NEXT: v_and_b32_e32 v4, 0xff, v4 ; GFX10-NEXT: v_and_b32_e32 v5, 7, v4
; GFX10-NEXT: v_and_b32_e32 v3, 7, v3 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: v_and_b32_e32 v2, 7, v2 ; GFX10-NEXT: v_and_b32_e32 v2, 7, v2
; GFX10-NEXT: v_and_b32_e32 v7, 7, v7 ; GFX10-NEXT: v_lshlrev_b16 v0, v5, v0
; GFX10-NEXT: v_and_b32_e32 v6, 7, v6 ; GFX10-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX10-NEXT: v_lshrrev_b16 v4, 1, v4 ; GFX10-NEXT: v_and_b32_e32 v4, 7, v4
; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX10-NEXT: v_lshrrev_b16 v1, 1, v1 ; GFX10-NEXT: v_lshrrev_b16 v1, 1, v1
; GFX10-NEXT: v_lshlrev_b16 v3, v3, v5 ; GFX10-NEXT: v_lshrrev_b16 v5, 1, v5
; GFX10-NEXT: v_lshlrev_b16 v0, v2, v0 ; GFX10-NEXT: v_lshrrev_b16 v1, v2, v1
; GFX10-NEXT: s_movk_i32 s4, 0xff ; GFX10-NEXT: v_lshrrev_b16 v4, v4, v5
; GFX10-NEXT: v_lshrrev_b16 v4, v6, v4 ; GFX10-NEXT: v_or_b32_e32 v1, v3, v1
; GFX10-NEXT: v_lshrrev_b16 v1, v7, v1 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
; GFX10-NEXT: v_or_b32_e32 v2, v3, v4 ; GFX10-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v1, v2, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_v2i8: ; GFX11-LABEL: v_fshl_v2i8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v2
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v1
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 24, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0 ; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshl_v4i8: ; GFX10-LABEL: v_fshl_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 8, v2 ; GFX10-NEXT: v_xor_b32_e32 v3, -1, v2
; GFX10-NEXT: v_and_b32_e32 v10, 7, v2 ; GFX10-NEXT: v_and_b32_e32 v4, 0xff, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v5, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 24, v0 ; GFX10-NEXT: v_and_b32_e32 v3, 7, v3
; GFX10-NEXT: v_lshrrev_b16 v4, 1, v4
; GFX10-NEXT: v_lshrrev_b16 v3, v3, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 8, v2
; GFX10-NEXT: v_and_b32_e32 v6, 7, v4
; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: v_lshlrev_b16 v5, v6, v5
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 8, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v6, 8, v1
; GFX10-NEXT: v_xor_b32_e32 v9, -1, v2 ; GFX10-NEXT: v_and_b32_e32 v4, 7, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX10-NEXT: v_lshlrev_b16 v0, v10, v0
; GFX10-NEXT: v_xor_b32_e32 v10, -1, v8
; GFX10-NEXT: v_and_b32_e32 v8, 7, v8
; GFX10-NEXT: v_mov_b32_e32 v13, 0xff
; GFX10-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX10-NEXT: v_and_b32_e32 v12, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v6, 0xff, v6 ; GFX10-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX10-NEXT: v_lshlrev_b16 v3, v8, v3
; GFX10-NEXT: v_xor_b32_e32 v8, -1, v11
; GFX10-NEXT: v_and_b32_sdwa v1, v1, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_xor_b32_e32 v13, -1, v2
; GFX10-NEXT: v_and_b32_e32 v10, 7, v10
; GFX10-NEXT: v_lshrrev_b16 v6, 1, v6 ; GFX10-NEXT: v_lshrrev_b16 v6, 1, v6
; GFX10-NEXT: v_and_b32_e32 v11, 7, v11 ; GFX10-NEXT: v_lshrrev_b16 v4, v4, v6
; GFX10-NEXT: v_and_b32_e32 v8, 7, v8 ; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX10-NEXT: v_and_b32_e32 v8, 7, v6
; GFX10-NEXT: v_xor_b32_e32 v6, -1, v6
; GFX10-NEXT: v_lshlrev_b16 v7, v8, v7
; GFX10-NEXT: v_mov_b32_e32 v8, 0xff
; GFX10-NEXT: v_and_b32_e32 v6, 7, v6
; GFX10-NEXT: v_and_b32_sdwa v8, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 24, v1
; GFX10-NEXT: v_lshrrev_b16 v8, 1, v8
; GFX10-NEXT: v_lshrrev_b16 v1, 1, v1 ; GFX10-NEXT: v_lshrrev_b16 v1, 1, v1
; GFX10-NEXT: v_lshrrev_b16 v6, v6, v8
; GFX10-NEXT: v_and_b32_e32 v8, 7, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX10-NEXT: v_lshlrev_b16 v8, v8, v0
; GFX10-NEXT: v_and_b32_e32 v9, 7, v2
; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 24, v0
; GFX10-NEXT: v_and_b32_e32 v2, 7, v2 ; GFX10-NEXT: v_and_b32_e32 v2, 7, v2
; GFX10-NEXT: v_and_b32_e32 v13, 7, v13 ; GFX10-NEXT: v_lshlrev_b16 v0, v9, v0
; GFX10-NEXT: v_lshrrev_b16 v7, 1, v7 ; GFX10-NEXT: v_lshrrev_b16 v1, v2, v1
; GFX10-NEXT: v_and_b32_e32 v9, 7, v9 ; GFX10-NEXT: v_or_b32_e32 v2, v8, v3
; GFX10-NEXT: v_lshrrev_b16 v12, 1, v12 ; GFX10-NEXT: v_or_b32_e32 v3, v5, v4
; GFX10-NEXT: v_lshrrev_b16 v6, v10, v6 ; GFX10-NEXT: v_or_b32_e32 v4, v7, v6
; GFX10-NEXT: v_lshlrev_b16 v4, v11, v4 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: v_lshrrev_b16 v1, v8, v1 ; GFX10-NEXT: v_mov_b32_e32 v1, 8
; GFX10-NEXT: v_lshlrev_b16 v2, v2, v5 ; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-NEXT: v_lshrrev_b16 v5, v13, v7 ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_lshrrev_b16 v7, v9, v12 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v4
; GFX10-NEXT: v_or_b32_e32 v3, v3, v6 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX10-NEXT: v_mov_b32_e32 v6, 8 ; GFX10-NEXT: v_and_or_b32 v1, v2, 0xff, v1
; GFX10-NEXT: v_or_b32_e32 v1, v4, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or_b32_e32 v2, v2, v5 ; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0
; GFX10-NEXT: v_or_b32_e32 v0, v0, v7
; GFX10-NEXT: v_lshlrev_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xff, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_v4i8: ; GFX11-LABEL: v_fshl_v4i8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 8, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 8, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v2
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; GFX10-NEXT: v_lshrrev_b32_e64 v3, v3, s2 ; GFX10-NEXT: v_lshrrev_b32_e64 v3, v3, s2
; GFX10-NEXT: s_mov_b32 s0, 8 ; GFX10-NEXT: s_mov_b32 s0, 8
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 ; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-NEXT: v_lshl_or_b32 v1, s1, v1, v3 ; GFX10-NEXT: v_lshl_or_b32 v1, s1, v1, v3
; GFX10-NEXT: s_mov_b32 s0, 16 ; GFX10-NEXT: s_mov_b32 s0, 16
; GFX10-NEXT: v_and_or_b32 v2, v0, 0xff, v2 ; GFX10-NEXT: v_and_or_b32 v2, v0, 0xff, v2
; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v1 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v1
; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_bfe_u32 v4, v1, 8, 8
; GFX10-NEXT: v_bfe_u32 v1, v1, 16, 8
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX10-NEXT: v_lshl_or_b32 v1, v1, 8, v4
; GFX10-NEXT: v_or3_b32 v0, v2, v0, v3 ; GFX10-NEXT: v_or3_b32 v0, v2, v0, v3
; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_bfe_u32 v2, v1, 8, 8
; GFX10-NEXT: v_bfe_u32 v1, v1, 16, 8
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_lshl_or_b32 v1, v1, 8, v2
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_fshl_v2i24: ; GFX11-LABEL: s_fshl_v2i24:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 ; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, 24 ; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
; GFX11-NEXT: s_lshr_b32 s6, s0, 8 ; GFX11-NEXT: s_lshr_b32 s6, s0, 8
; GFX11-NEXT: s_bfe_u32 s9, 8, 0x100000 ; GFX11-NEXT: s_bfe_u32 s9, 8, 0x100000
▲ Show 20 Lines • Show All 293 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_lshl_or_b32 v1, v1, v2, v3 ; GFX9-NEXT: v_lshl_or_b32 v1, v1, v2, v3
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshl_v2i24: ; GFX10-LABEL: v_fshl_v2i24:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4 ; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX10-NEXT: v_bfe_u32 v2, v2, 1, 23 ; GFX10-NEXT: v_bfe_u32 v2, v2, 1, 23
; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX10-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX10-NEXT: v_bfe_u32 v3, v3, 1, 23 ; GFX10-NEXT: v_bfe_u32 v3, v3, 1, 23
; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 ; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7 ; GFX10-NEXT: v_mul_lo_u32 v7, 0xffffffe8, v6
; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v6 ; GFX10-NEXT: v_mul_hi_u32 v7, v6, v7
; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v7
; GFX10-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX10-NEXT: v_mul_hi_u32 v9, v7, v9
; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v8
; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v9
; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6 ; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24 ; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6 ; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6
; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v7
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4 ; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4 ; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
; GFX10-NEXT: v_sub_nc_u32_e32 v6, 23, v4 ; GFX10-NEXT: v_sub_nc_u32_e32 v6, 23, v4
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4 ; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v6 ; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v6
; GFX10-NEXT: v_sub_nc_u32_e32 v7, 23, v5
; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX10-NEXT: v_lshrrev_b32_e32 v2, v6, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX10-NEXT: v_and_b32_e32 v7, 0xffffff, v7
; GFX10-NEXT: v_lshl_or_b32 v0, v0, v4, v2 ; GFX10-NEXT: v_lshl_or_b32 v0, v0, v4, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, v7, v3 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX10-NEXT: v_lshl_or_b32 v1, v1, v5, v3 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX10-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX10-NEXT: v_mul_lo_u32 v4, 0xffffffe8, v2
; GFX10-NEXT: v_mul_hi_u32 v4, v2, v4
; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v4
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v5
; GFX10-NEXT: v_mul_hi_u32 v2, v4, v2
; GFX10-NEXT: v_mul_lo_u32 v2, v2, 24
; GFX10-NEXT: v_sub_nc_u32_e32 v2, v4, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v4, 24, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v4, 24, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v2
; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v3, v4, v3
; GFX10-NEXT: v_lshl_or_b32 v1, v1, v2, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_v2i24: ; GFX11-LABEL: v_fshl_v2i24:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v6, 24 ; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v7, 24 ; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
▲ Show 20 Lines • Show All 509 Lines • ▼ Show 20 Lines
; ;
; GFX10-LABEL: v_fshl_v2i32: ; GFX10-LABEL: v_fshl_v2i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_alignbit_b32 v2, v0, v2, 1 ; GFX10-NEXT: v_alignbit_b32 v2, v0, v2, 1
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v0
; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: v_alignbit_b32 v3, v1, v3, 1
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 1, v1
; GFX10-NEXT: v_xor_b32_e32 v5, -1, v5
; GFX10-NEXT: v_alignbit_b32 v0, v0, v2, v4 ; GFX10-NEXT: v_alignbit_b32 v0, v0, v2, v4
; GFX10-NEXT: v_alignbit_b32 v1, v1, v3, v5 ; GFX10-NEXT: v_alignbit_b32 v2, v1, v3, 1
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 1, v1
; GFX10-NEXT: v_xor_b32_e32 v3, -1, v5
; GFX10-NEXT: v_alignbit_b32 v1, v1, v2, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_v2i32: ; GFX11-LABEL: v_fshl_v2i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_alignbit_b32 v2, v0, v2, 1 ; GFX11-NEXT: v_alignbit_b32 v2, v0, v2, 1
; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v0
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; ;
; GFX10-LABEL: v_fshl_v3i32: ; GFX10-LABEL: v_fshl_v3i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_alignbit_b32 v3, v0, v3, 1 ; GFX10-NEXT: v_alignbit_b32 v3, v0, v3, 1
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v0
; GFX10-NEXT: v_xor_b32_e32 v6, -1, v6 ; GFX10-NEXT: v_xor_b32_e32 v6, -1, v6
; GFX10-NEXT: v_alignbit_b32 v4, v1, v4, 1 ; GFX10-NEXT: v_alignbit_b32 v0, v0, v3, v6
; GFX10-NEXT: v_alignbit_b32 v3, v1, v4, 1
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 1, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 1, v1
; GFX10-NEXT: v_xor_b32_e32 v7, -1, v7 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v7
; GFX10-NEXT: v_alignbit_b32 v5, v2, v5, 1 ; GFX10-NEXT: v_alignbit_b32 v1, v1, v3, v4
; GFX10-NEXT: v_alignbit_b32 v3, v2, v5, 1
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v2
; GFX10-NEXT: v_xor_b32_e32 v8, -1, v8 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v8
; GFX10-NEXT: v_alignbit_b32 v0, v0, v3, v6 ; GFX10-NEXT: v_alignbit_b32 v2, v2, v3, v4
; GFX10-NEXT: v_alignbit_b32 v1, v1, v4, v7
; GFX10-NEXT: v_alignbit_b32 v2, v2, v5, v8
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_v3i32: ; GFX11-LABEL: v_fshl_v3i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_alignbit_b32 v3, v0, v3, 1 ; GFX11-NEXT: v_alignbit_b32 v3, v0, v3, 1
; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v0
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; ;
; GFX10-LABEL: v_fshl_v4i32: ; GFX10-LABEL: v_fshl_v4i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_alignbit_b32 v4, v0, v4, 1 ; GFX10-NEXT: v_alignbit_b32 v4, v0, v4, 1
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v0
; GFX10-NEXT: v_xor_b32_e32 v8, -1, v8 ; GFX10-NEXT: v_xor_b32_e32 v8, -1, v8
; GFX10-NEXT: v_alignbit_b32 v5, v1, v5, 1 ; GFX10-NEXT: v_alignbit_b32 v0, v0, v4, v8
; GFX10-NEXT: v_alignbit_b32 v4, v1, v5, 1
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 1, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 1, v1
; GFX10-NEXT: v_xor_b32_e32 v9, -1, v9 ; GFX10-NEXT: v_xor_b32_e32 v5, -1, v9
; GFX10-NEXT: v_alignbit_b32 v6, v2, v6, 1 ; GFX10-NEXT: v_alignbit_b32 v1, v1, v4, v5
; GFX10-NEXT: v_alignbit_b32 v4, v2, v6, 1
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v2
; GFX10-NEXT: v_xor_b32_e32 v10, -1, v10 ; GFX10-NEXT: v_xor_b32_e32 v5, -1, v10
; GFX10-NEXT: v_alignbit_b32 v7, v3, v7, 1 ; GFX10-NEXT: v_alignbit_b32 v2, v2, v4, v5
; GFX10-NEXT: v_alignbit_b32 v4, v3, v7, 1
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 1, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 1, v3
; GFX10-NEXT: v_xor_b32_e32 v11, -1, v11 ; GFX10-NEXT: v_xor_b32_e32 v5, -1, v11
; GFX10-NEXT: v_alignbit_b32 v0, v0, v4, v8 ; GFX10-NEXT: v_alignbit_b32 v3, v3, v4, v5
; GFX10-NEXT: v_alignbit_b32 v1, v1, v5, v9
; GFX10-NEXT: v_alignbit_b32 v2, v2, v6, v10
; GFX10-NEXT: v_alignbit_b32 v3, v3, v7, v11
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_v4i32: ; GFX11-LABEL: v_fshl_v4i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_alignbit_b32 v4, v0, v4, 1 ; GFX11-NEXT: v_alignbit_b32 v4, v0, v4, 1
; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v0
▲ Show 20 Lines • Show All 1,465 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v4, v2 ; GFX9-NEXT: v_pk_lshrrev_b16 v2, v4, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2 ; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshl_v3i16: ; GFX10-LABEL: v_fshl_v3i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_xor_b32_e32 v6, -1, v4 ; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v4
; GFX10-NEXT: v_xor_b32_e32 v7, -1, v5 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX10-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_and_b32_e32 v5, 0xf000f, v5
; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v6
; GFX10-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
; GFX10-NEXT: v_and_b32_e32 v7, 0xf000f, v7 ; GFX10-NEXT: v_pk_lshlrev_b16 v0, v6, v0
; GFX10-NEXT: v_pk_lshlrev_b16 v0, v4, v0 ; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v5, v1 ; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v5
; GFX10-NEXT: v_pk_lshrrev_b16 v2, v6, v2 ; GFX10-NEXT: v_pk_lshrrev_b16 v2, v4, v2
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v7, v3 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v5
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v6, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v4, v3
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_v3i16: ; GFX11-LABEL: v_fshl_v3i16:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4 ; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
▲ Show 20 Lines • Show All 348 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v4, v2 ; GFX9-NEXT: v_pk_lshrrev_b16 v2, v4, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2 ; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshl_v4i16: ; GFX10-LABEL: v_fshl_v4i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_xor_b32_e32 v6, -1, v4 ; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v4
; GFX10-NEXT: v_xor_b32_e32 v7, -1, v5 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX10-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_and_b32_e32 v5, 0xf000f, v5
; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v6
; GFX10-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
; GFX10-NEXT: v_and_b32_e32 v7, 0xf000f, v7 ; GFX10-NEXT: v_pk_lshlrev_b16 v0, v6, v0
; GFX10-NEXT: v_pk_lshlrev_b16 v0, v4, v0 ; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v5, v1 ; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v5
; GFX10-NEXT: v_pk_lshrrev_b16 v2, v6, v2 ; GFX10-NEXT: v_pk_lshrrev_b16 v2, v4, v2
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v7, v3 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v5
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v6, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v4, v3
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_v4i16: ; GFX11-LABEL: v_fshl_v4i16:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4 ; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshl_i64: ; GFX10-LABEL: v_fshl_i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_xor_b32_e32 v5, -1, v4 ; GFX10-NEXT: v_and_b32_e32 v5, 63, v4
; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3] ; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v5, v[0:1]
; GFX10-NEXT: v_and_b32_e32 v4, 63, v4 ; GFX10-NEXT: v_and_b32_e32 v4, 63, v4
; GFX10-NEXT: v_and_b32_e32 v5, 63, v5 ; GFX10-NEXT: v_lshrrev_b64 v[2:3], v4, v[2:3]
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v5, v[2:3]
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_i64: ; GFX11-LABEL: v_fshl_i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
▲ Show 20 Lines • Show All 492 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_or_b32_e32 v2, v2, v6 ; GFX9-NEXT: v_or_b32_e32 v2, v2, v6
; GFX9-NEXT: v_or_b32_e32 v3, v3, v7 ; GFX9-NEXT: v_or_b32_e32 v3, v3, v7
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshl_v2i64: ; GFX10-LABEL: v_fshl_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_xor_b32_e32 v9, -1, v8 ; GFX10-NEXT: v_and_b32_e32 v9, 63, v8
; GFX10-NEXT: v_xor_b32_e32 v11, -1, v10 ; GFX10-NEXT: v_xor_b32_e32 v8, -1, v8
; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5] ; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]
; GFX10-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
; GFX10-NEXT: v_and_b32_e32 v8, 63, v8 ; GFX10-NEXT: v_and_b32_e32 v8, 63, v8
; GFX10-NEXT: v_and_b32_e32 v9, 63, v9 ; GFX10-NEXT: v_lshrrev_b64 v[4:5], v8, v[4:5]
; GFX10-NEXT: v_and_b32_e32 v10, 63, v10 ; GFX10-NEXT: v_xor_b32_e32 v8, -1, v10
; GFX10-NEXT: v_and_b32_e32 v11, 63, v11
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[4:5], v9, v[4:5]
; GFX10-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]
; GFX10-NEXT: v_lshrrev_b64 v[6:7], v11, v[6:7]
; GFX10-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
; GFX10-NEXT: v_and_b32_e32 v4, 63, v10
; GFX10-NEXT: v_or_b32_e32 v1, v1, v5 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v5
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6 ; GFX10-NEXT: v_lshlrev_b64 v[2:3], v4, v[2:3]
; GFX10-NEXT: v_or_b32_e32 v3, v3, v7 ; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7]
; GFX10-NEXT: v_and_b32_e32 v6, 63, v8
; GFX10-NEXT: v_lshrrev_b64 v[4:5], v6, v[4:5]
; GFX10-NEXT: v_or_b32_e32 v2, v2, v4
; GFX10-NEXT: v_or_b32_e32 v3, v3, v5
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_v2i64: ; GFX11-LABEL: v_fshl_v2i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_xor_b32_e32 v9, -1, v8 ; GFX11-NEXT: v_xor_b32_e32 v9, -1, v8
; GFX11-NEXT: v_xor_b32_e32 v11, -1, v10 ; GFX11-NEXT: v_xor_b32_e32 v11, -1, v10
▲ Show 20 Lines • Show All 404 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_or_b32_e32 v2, v12, v2 ; GFX9-NEXT: v_or_b32_e32 v2, v12, v2
; GFX9-NEXT: v_or_b32_e32 v3, v13, v3 ; GFX9-NEXT: v_or_b32_e32 v3, v13, v3
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshl_i128: ; GFX10-LABEL: v_fshl_i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_and_b32_e32 v18, 0x7f, v8 ; GFX10-NEXT: v_and_b32_e32 v13, 0x7f, v8
; GFX10-NEXT: v_xor_b32_e32 v8, -1, v8 ; GFX10-NEXT: v_xor_b32_e32 v8, -1, v8
; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5] ; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]
; GFX10-NEXT: v_lshlrev_b32_e32 v12, 31, v6 ; GFX10-NEXT: v_sub_nc_u32_e32 v9, 64, v13
; GFX10-NEXT: v_lshlrev_b64 v[11:12], v13, v[2:3]
; GFX10-NEXT: v_and_b32_e32 v15, 0x7f, v8
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v13
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v13
; GFX10-NEXT: v_lshrrev_b64 v[9:10], v9, v[0:1]
; GFX10-NEXT: v_sub_nc_u32_e32 v8, 64, v15
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v15
; GFX10-NEXT: v_or_b32_e32 v14, v9, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 31, v6
; GFX10-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7] ; GFX10-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
; GFX10-NEXT: v_sub_nc_u32_e32 v9, 64, v18 ; GFX10-NEXT: v_or_b32_e32 v12, v10, v12
; GFX10-NEXT: v_and_b32_e32 v19, 0x7f, v8 ; GFX10-NEXT: v_or_b32_e32 v5, v5, v9
; GFX10-NEXT: v_lshlrev_b64 v[10:11], v18, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[8:9], v8, v[6:7]
; GFX10-NEXT: v_or_b32_e32 v5, v5, v12 ; GFX10-NEXT: v_lshrrev_b64 v[10:11], v15, v[4:5]
; GFX10-NEXT: v_subrev_nc_u32_e32 v20, 64, v18 ; GFX10-NEXT: v_or_b32_e32 v10, v10, v8
; GFX10-NEXT: v_lshrrev_b64 v[8:9], v9, v[0:1] ; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 64, v13
; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v19 ; GFX10-NEXT: v_or_b32_e32 v11, v11, v9
; GFX10-NEXT: v_lshlrev_b64 v[12:13], v18, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[8:9], v8, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[14:15], v19, v[4:5] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v13, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v20, v[0:1] ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc_lo
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v10, v8, v10 ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 64, v19 ; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[6:7] ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v2, s4
; GFX10-NEXT: v_or_b32_e32 v11, v9, v11 ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v15
; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v19 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v3, s4
; GFX10-NEXT: v_cndmask_b32_e32 v10, v0, v10, vcc_lo ; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v15
; GFX10-NEXT: v_lshrrev_b64 v[8:9], v8, v[6:7] ; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, v[6:7]
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v19 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s4
; GFX10-NEXT: v_or_b32_e32 v14, v14, v16 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s4
; GFX10-NEXT: v_or_b32_e32 v15, v15, v17 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v2, v4, s5
; GFX10-NEXT: v_cndmask_b32_e32 v11, v1, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v3, v5, s5
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v19, v[6:7] ; GFX10-NEXT: v_lshrrev_b64 v[2:3], v15, v[6:7]
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v18 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v14, s4 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v5
; GFX10-NEXT: v_cndmask_b32_e64 v6, v9, v15, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s4
; GFX10-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s4
; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v13, vcc_lo ; GFX10-NEXT: v_or_b32_e32 v2, v8, v2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, v2, s6 ; GFX10-NEXT: v_or_b32_e32 v3, v9, v3
; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, v3, s6
; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v4, s5
; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, v5, s5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v1, s4
; GFX10-NEXT: v_or_b32_e32 v0, v12, v4
; GFX10-NEXT: v_or_b32_e32 v1, v7, v5
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6
; GFX10-NEXT: v_or_b32_e32 v3, v3, v8
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_i128: ; GFX11-LABEL: v_fshl_i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_and_b32_e32 v18, 0x7f, v8 ; GFX11-NEXT: v_and_b32_e32 v14, 0x7f, v8
; GFX11-NEXT: v_xor_b32_e32 v8, -1, v8 ; GFX11-NEXT: v_xor_b32_e32 v12, -1, v8
; GFX11-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5] ; GFX11-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_sub_nc_u32_e32 v9, 64, v18 ; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v14
; GFX11-NEXT: v_lshlrev_b64 v[10:11], v18, v[2:3] ; GFX11-NEXT: v_lshlrev_b64 v[8:9], v14, v[2:3]
; GFX11-NEXT: v_subrev_nc_u32_e32 v20, 64, v18 ; GFX11-NEXT: v_and_b32_e32 v16, 0x7f, v12
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18 ; GFX11-NEXT: v_lshlrev_b64 v[12:13], v14, v[0:1]
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 31, v6 ; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v14
; GFX11-NEXT: v_and_b32_e32 v19, 0x7f, v8 ; GFX11-NEXT: v_lshrrev_b64 v[10:11], v10, v[0:1]
; GFX11-NEXT: v_lshrrev_b64 v[8:9], v9, v[0:1] ; GFX11-NEXT: v_lshlrev_b32_e32 v15, 31, v6
; GFX11-NEXT: v_subrev_nc_u32_e32 v17, 64, v14
; GFX11-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7] ; GFX11-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v5, v5, v12
; GFX11-NEXT: v_lshlrev_b64 v[12:13], v18, v[0:1]
; GFX11-NEXT: v_lshlrev_b64 v[0:1], v20, v[0:1]
; GFX11-NEXT: v_or_b32_e32 v10, v8, v10
; GFX11-NEXT: v_or_b32_e32 v11, v9, v11
; GFX11-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v16
; GFX11-NEXT: v_cndmask_b32_e32 v10, v0, v10, vcc_lo ; GFX11-NEXT: v_or_b32_e32 v5, v5, v15
; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v19 ; GFX11-NEXT: v_or_b32_e32 v15, v10, v8
; GFX11-NEXT: v_subrev_nc_u32_e32 v8, 64, v19 ; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v16
; GFX11-NEXT: v_lshrrev_b64 v[14:15], v19, v[4:5] ; GFX11-NEXT: v_lshlrev_b64 v[0:1], v17, v[0:1]
; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v19 ; GFX11-NEXT: v_or_b32_e32 v18, v11, v9
; GFX11-NEXT: v_cndmask_b32_e32 v11, v1, v11, vcc_lo ; GFX11-NEXT: v_subrev_nc_u32_e32 v17, 64, v16
; GFX11-NEXT: v_lshlrev_b64 v[16:17], v16, v[6:7] ; GFX11-NEXT: v_lshrrev_b64 v[8:9], v16, v[4:5]
; GFX11-NEXT: v_lshrrev_b64 v[8:9], v8, v[6:7] ; GFX11-NEXT: v_lshlrev_b64 v[10:11], v10, v[6:7]
; GFX11-NEXT: v_lshrrev_b64 v[0:1], v19, v[6:7] ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 0, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 0, v19 ; GFX11-NEXT: v_dual_cndmask_b32 v15, v0, v15 :: v_dual_cndmask_b32 v18, v1, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v18 ; GFX11-NEXT: v_lshrrev_b64 v[0:1], v17, v[6:7]
; GFX11-NEXT: v_cndmask_b32_e32 v7, 0, v13, vcc_lo ; GFX11-NEXT: v_lshrrev_b64 v[6:7], v16, v[6:7]
; GFX11-NEXT: v_or_b32_e32 v14, v14, v16 ; GFX11-NEXT: v_or_b32_e32 v8, v8, v10
; GFX11-NEXT: v_or_b32_e32 v15, v15, v17 ; GFX11-NEXT: v_or_b32_e32 v9, v9, v11
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v14
; GFX11-NEXT: v_cndmask_b32_e64 v2, v10, v2, s2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v3, v11, v3, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v8, s0
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v14, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cndmask_b32_e32 v8, 0, v13, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v6, v9, v15, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v4, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, v5, s1
; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v0, s0
; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v1, s0
; GFX11-NEXT: v_or_b32_e32 v0, v12, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v1, v7, v5
; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v3, v3, v8 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v15, v2, s2
; GFX11-NEXT: v_cndmask_b32_e64 v3, v18, v3, s2
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v4, s1
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v5, s1
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v6, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, v7, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v0, v12, v0
; GFX11-NEXT: v_or_b32_e32 v1, v8, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v2, v2, v4
; GFX11-NEXT: v_or_b32_e32 v3, v3, v5
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt) %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
ret i128 %result ret i128 %result
} }
define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, i128 %amt) { define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, i128 %amt) {
; GFX6-LABEL: v_fshl_i128_ssv: ; GFX6-LABEL: v_fshl_i128_ssv:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
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; GFX9-NEXT: v_or_b32_e32 v0, v8, v0 ; GFX9-NEXT: v_or_b32_e32 v0, v8, v0
; GFX9-NEXT: v_or_b32_e32 v1, v9, v1 ; GFX9-NEXT: v_or_b32_e32 v1, v9, v1
; GFX9-NEXT: v_or_b32_e32 v2, v6, v2 ; GFX9-NEXT: v_or_b32_e32 v2, v6, v2
; GFX9-NEXT: v_or_b32_e32 v3, v10, v3 ; GFX9-NEXT: v_or_b32_e32 v3, v10, v3
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: v_fshl_i128_ssv: ; GFX10-LABEL: v_fshl_i128_ssv:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_b32_e32 v12, 0x7f, v0 ; GFX10-NEXT: v_and_b32_e32 v5, 0x7f, v0
; GFX10-NEXT: v_xor_b32_e32 v0, -1, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX10-NEXT: s_mov_b32 s8, 0 ; GFX10-NEXT: s_mov_b32 s8, 0
; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 1 ; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
; GFX10-NEXT: s_lshl_b32 s9, s6, 31 ; GFX10-NEXT: s_lshl_b32 s9, s6, 31
; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v12 ; GFX10-NEXT: v_sub_nc_u32_e32 v1, 64, v5
; GFX10-NEXT: v_and_b32_e32 v13, 0x7f, v0 ; GFX10-NEXT: v_and_b32_e32 v7, 0x7f, v0
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v12, s[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[3:4], v5, s[2:3]
; GFX10-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9]
; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], 1 ; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, s[0:1] ; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GFX10-NEXT: v_sub_nc_u32_e32 v8, 64, v13 ; GFX10-NEXT: v_lshrrev_b64 v[1:2], v1, s[0:1]
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v12 ; GFX10-NEXT: v_sub_nc_u32_e32 v0, 64, v7
; GFX10-NEXT: v_lshrrev_b64 v[6:7], v13, s[8:9] ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v5
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v12 ; GFX10-NEXT: v_or_b32_e32 v6, v1, v3
; GFX10-NEXT: v_lshlrev_b64 v[4:5], v12, s[0:1] ; GFX10-NEXT: v_or_b32_e32 v4, v2, v4
; GFX10-NEXT: v_or_b32_e32 v2, v2, v0 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, s[6:7]
; GFX10-NEXT: v_subrev_nc_u32_e32 v0, 64, v13 ; GFX10-NEXT: v_lshrrev_b64 v[2:3], v7, s[4:5]
; GFX10-NEXT: v_lshlrev_b64 v[8:9], v8, s[6:7] ; GFX10-NEXT: v_or_b32_e32 v8, v2, v0
; GFX10-NEXT: v_lshlrev_b64 v[10:11], v10, s[0:1] ; GFX10-NEXT: v_or_b32_e32 v9, v3, v1
; GFX10-NEXT: v_or_b32_e32 v3, v3, v1 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v5, s[0:1]
; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 64, v13 ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v5
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v0, s[6:7] ; GFX10-NEXT: v_lshlrev_b64 v[2:3], v2, s[0:1]
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 0, v13 ; GFX10-NEXT: v_cndmask_b32_e32 v10, 0, v0, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v6, v6, v8 ; GFX10-NEXT: v_subrev_nc_u32_e32 v0, 64, v7
; GFX10-NEXT: v_or_b32_e32 v7, v7, v9 ; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 64, v7
; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v2, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 0, v5
; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc_lo
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v13, s[6:7] ; GFX10-NEXT: v_cndmask_b32_e32 v6, v2, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v12 ; GFX10-NEXT: v_lshrrev_b64 v[2:3], v0, s[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v7, s0 ; GFX10-NEXT: v_lshrrev_b64 v[0:1], v7, s[6:7]
; GFX10-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX10-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v8, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s8, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v9, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v8, s2, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, v0, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v10, s3, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s9, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, s5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, s2, s1
; GFX10-NEXT: v_or_b32_e32 v0, v4, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, s3, s1
; GFX10-NEXT: v_or_b32_e32 v0, v10, v0
; GFX10-NEXT: v_or_b32_e32 v1, v5, v1 ; GFX10-NEXT: v_or_b32_e32 v1, v5, v1
; GFX10-NEXT: v_or_b32_e32 v2, v6, v2 ; GFX10-NEXT: v_or_b32_e32 v2, v2, v7
; GFX10-NEXT: v_or_b32_e32 v3, v7, v3 ; GFX10-NEXT: v_or_b32_e32 v3, v3, v8
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: v_fshl_i128_ssv: ; GFX11-LABEL: v_fshl_i128_ssv:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_and_b32_e32 v12, 0x7f, v0 ; GFX11-NEXT: v_and_b32_e32 v12, 0x7f, v0
; GFX11-NEXT: v_xor_b32_e32 v0, -1, v0 ; GFX11-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX11-NEXT: s_mov_b32 s8, 0 ; GFX11-NEXT: s_mov_b32 s8, 0
; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 1 ; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
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; GFX10-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 ; GFX10-NEXT: s_lshl_b64 s[8:9], s[0:1], s8
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s5 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0
; GFX10-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v4
; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 ; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s13, 0 ; GFX10-NEXT: s_cmp_lg_u32 s13, 0
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
; GFX10-NEXT: s_sub_i32 s0, 64, s4 ; GFX10-NEXT: s_sub_i32 s2, 64, s4
; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] ; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[6:7], s2, v[2:3]
; GFX10-NEXT: s_sub_i32 s0, s4, 64 ; GFX10-NEXT: s_sub_i32 s2, s4, 64
; GFX10-NEXT: s_cmp_lt_u32 s4, 64 ; GFX10-NEXT: s_cmp_lt_u32 s4, 64
; GFX10-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3] ; GFX10-NEXT: s_cselect_b32 s3, 1, 0
; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s4, 0 ; GFX10-NEXT: s_cmp_eq_u32 s4, 0
; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX10-NEXT: v_or_b32_e32 v6, v4, v6
; GFX10-NEXT: s_cselect_b32 s5, 1, 0 ; GFX10-NEXT: s_cselect_b32 s5, 1, 0
; GFX10-NEXT: s_and_b32 s0, 1, s1 ; GFX10-NEXT: s_and_b32 s6, 1, s3
; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 ; GFX10-NEXT: v_or_b32_e32 v7, v5, v7
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_lshrrev_b64 v[4:5], s2, v[2:3]
; GFX10-NEXT: s_and_b32 s0, 1, s5 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6
; GFX10-NEXT: s_and_b32 s1, 1, s1 ; GFX10-NEXT: s_and_b32 s2, 1, s5
; GFX10-NEXT: v_lshrrev_b64 v[2:3], s4, v[2:3] ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: s_and_b32 s2, 1, s3
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: v_lshrrev_b64 v[0:1], s4, v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v0, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v0, s8, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v1, s9, v1 ; GFX10-NEXT: v_or_b32_e32 v0, s8, v4
; GFX10-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX10-NEXT: v_or_b32_e32 v1, s9, v5
; GFX10-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX10-NEXT: v_or_b32_e32 v2, s0, v2
; GFX10-NEXT: v_or_b32_e32 v3, s1, v3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: v_fshl_i128_svs: ; GFX11-LABEL: v_fshl_i128_svs:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX11-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX11-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1] ; GFX11-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
; GFX11-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX11-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX11-NEXT: s_and_not1_b64 s[4:5], s[6:7], s[4:5] ; GFX11-NEXT: s_and_not1_b64 s[4:5], s[6:7], s[4:5]
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; GFX9-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX9-NEXT: v_or_b32_e32 v2, s2, v2
; GFX9-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX9-NEXT: v_or_b32_e32 v3, s3, v3
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: v_fshl_i128_vss: ; GFX10-LABEL: v_fshl_i128_vss:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX10-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX10-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX10-NEXT: s_andn2_b64 s[10:11], s[6:7], s[4:5]
; GFX10-NEXT: s_sub_i32 s5, s8, 64 ; GFX10-NEXT: s_sub_i32 s9, 64, s8
; GFX10-NEXT: s_sub_i32 s6, 64, s8
; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3]
; GFX10-NEXT: s_cselect_b32 s9, 1, 0 ; GFX10-NEXT: v_lshrrev_b64 v[4:5], s9, v[0:1]
; GFX10-NEXT: s_sub_i32 s4, s8, 64
; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: s_cselect_b32 s5, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1] ; GFX10-NEXT: v_or_b32_e32 v6, v4, v6
; GFX10-NEXT: s_cselect_b32 s10, 1, 0 ; GFX10-NEXT: s_cselect_b32 s6, 1, 0
; GFX10-NEXT: s_and_b32 s6, 1, s9 ; GFX10-NEXT: s_and_b32 s5, 1, s5
; GFX10-NEXT: v_or_b32_e32 v7, v5, v7
; GFX10-NEXT: v_lshlrev_b64 v[4:5], s8, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[0:1], s4, v[0:1]
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
; GFX10-NEXT: s_and_b32 s4, 1, s6
; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], 1 ; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX10-NEXT: s_lshl_b32 s9, s2, 31 ; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4
; GFX10-NEXT: s_mov_b32 s8, s7 ; GFX10-NEXT: s_lshl_b32 s5, s2, 31
; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX10-NEXT: s_and_b32 s5, 1, s10 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1 ; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: s_sub_i32 s10, s4, 64 ; GFX10-NEXT: s_sub_i32 s11, s10, 64
; GFX10-NEXT: s_sub_i32 s8, 64, s4 ; GFX10-NEXT: s_sub_i32 s6, 64, s10
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v0, v2, s4
; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v1, v3, s4
; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 ; GFX10-NEXT: s_mov_b32 s4, s7
; GFX10-NEXT: s_cmp_lt_u32 s4, 64 ; GFX10-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc_lo
; GFX10-NEXT: s_cselect_b32 s11, 1, 0 ; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX10-NEXT: s_cmp_eq_u32 s4, 0 ; GFX10-NEXT: s_cmp_lt_u32 s10, 64
; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc_lo
; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_cselect_b32 s12, 1, 0
; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s4 ; GFX10-NEXT: s_cmp_eq_u32 s10, 0
; GFX10-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 ; GFX10-NEXT: s_cselect_b32 s13, 1, 0
; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo ; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s10
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo ; GFX10-NEXT: s_lshl_b64 s[6:7], s[2:3], s6
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: s_lshr_b64 s[8:9], s[2:3], s10
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5 ; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GFX10-NEXT: s_lshr_b64 s[4:5], s[2:3], s4 ; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s11
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
; GFX10-NEXT: s_cmp_lg_u32 s11, 0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX10-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo ; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s13, 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0
; GFX10-NEXT: v_or_b32_e32 v0, s0, v6 ; GFX10-NEXT: v_or_b32_e32 v0, s0, v4
; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], 0 ; GFX10-NEXT: s_cselect_b64 s[2:3], s[8:9], 0
; GFX10-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX10-NEXT: v_or_b32_e32 v1, s1, v1
; GFX10-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX10-NEXT: v_or_b32_e32 v2, s2, v2
; GFX10-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX10-NEXT: v_or_b32_e32 v3, s3, v3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: v_fshl_i128_vss: ; GFX11-LABEL: v_fshl_i128_vss:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX11-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshl_i128_65: ; GFX10-LABEL: v_fshl_i128_65:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 31, v5 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 31, v7
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 31, v7 ; GFX10-NEXT: v_lshrrev_b32_e32 v5, 31, v5
; GFX10-NEXT: v_or_b32_e32 v0, v4, v0 ; GFX10-NEXT: v_or_b32_e32 v2, v2, v4
; GFX10-NEXT: v_or_b32_e32 v2, v2, v5 ; GFX10-NEXT: v_or_b32_e32 v0, v5, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_i128_65: ; GFX11-LABEL: v_fshl_i128_65:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7] ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
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; GFX9-NEXT: v_or_b32_e32 v6, v16, v6 ; GFX9-NEXT: v_or_b32_e32 v6, v16, v6
; GFX9-NEXT: v_or_b32_e32 v7, v20, v7 ; GFX9-NEXT: v_or_b32_e32 v7, v20, v7
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshl_v2i128: ; GFX10-LABEL: v_fshl_v2i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_and_b32_e32 v27, 0x7f, v16 ; GFX10-NEXT: v_and_b32_e32 v23, 0x7f, v16
; GFX10-NEXT: v_xor_b32_e32 v16, -1, v16 ; GFX10-NEXT: v_xor_b32_e32 v16, -1, v16
; GFX10-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9] ; GFX10-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9]
; GFX10-NEXT: v_lshlrev_b32_e32 v21, 31, v10 ; GFX10-NEXT: v_and_b32_e32 v27, 0x7f, v20
; GFX10-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11] ; GFX10-NEXT: v_lshrrev_b64 v[12:13], 1, v[12:13]
; GFX10-NEXT: v_sub_nc_u32_e32 v17, 64, v27 ; GFX10-NEXT: v_sub_nc_u32_e32 v17, 64, v23
; GFX10-NEXT: v_and_b32_e32 v28, 0x7f, v16 ; GFX10-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3]
; GFX10-NEXT: v_lshlrev_b64 v[18:19], v27, v[2:3] ; GFX10-NEXT: v_and_b32_e32 v24, 0x7f, v16
; GFX10-NEXT: v_or_b32_e32 v9, v9, v21 ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23
; GFX10-NEXT: v_subrev_nc_u32_e32 v29, 64, v27 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v23
; GFX10-NEXT: v_lshrrev_b64 v[16:17], v17, v[0:1] ; GFX10-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
; GFX10-NEXT: v_sub_nc_u32_e32 v25, 64, v28
; GFX10-NEXT: v_lshlrev_b64 v[21:22], v27, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[23:24], v28, v[8:9]
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v29, v[0:1]
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v27
; GFX10-NEXT: v_or_b32_e32 v18, v16, v18
; GFX10-NEXT: v_subrev_nc_u32_e32 v16, 64, v28
; GFX10-NEXT: v_lshlrev_b64 v[25:26], v25, v[10:11]
; GFX10-NEXT: v_or_b32_e32 v19, v17, v19
; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v28
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v28
; GFX10-NEXT: v_lshrrev_b64 v[16:17], v16, v[10:11]
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v27 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v27
; GFX10-NEXT: v_or_b32_e32 v23, v23, v25 ; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v24
; GFX10-NEXT: v_or_b32_e32 v24, v24, v26 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v24
; GFX10-NEXT: v_cndmask_b32_e32 v19, v1, v19, vcc_lo ; GFX10-NEXT: v_or_b32_e32 v21, v17, v21
; GFX10-NEXT: v_cndmask_b32_e32 v18, v0, v18, vcc_lo ; GFX10-NEXT: v_lshlrev_b32_e32 v17, 31, v10
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v28, v[10:11] ; GFX10-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v23, s4 ; GFX10-NEXT: v_or_b32_e32 v22, v18, v22
; GFX10-NEXT: v_cndmask_b32_e64 v10, v17, v24, s4 ; GFX10-NEXT: v_or_b32_e32 v9, v9, v17
; GFX10-NEXT: v_cndmask_b32_e32 v21, 0, v21, vcc_lo ; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e32 v11, 0, v22, vcc_lo ; GFX10-NEXT: v_lshrrev_b64 v[18:19], v24, v[8:9]
; GFX10-NEXT: v_cndmask_b32_e64 v22, v19, v3, s6 ; GFX10-NEXT: v_or_b32_e32 v25, v18, v16
; GFX10-NEXT: v_cndmask_b32_e64 v3, v16, v8, s5 ; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v27
; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, v2, s6 ; GFX10-NEXT: v_or_b32_e32 v26, v19, v17
; GFX10-NEXT: v_cndmask_b32_e64 v8, v10, v9, s5 ; GFX10-NEXT: v_lshlrev_b64 v[18:19], v27, v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v0, s4 ; GFX10-NEXT: v_lshrrev_b64 v[16:17], v16, v[4:5]
; GFX10-NEXT: v_and_b32_e32 v23, 0x7f, v20 ; GFX10-NEXT: v_or_b32_e32 v28, v16, v18
; GFX10-NEXT: v_or_b32_e32 v0, v21, v3
; GFX10-NEXT: v_xor_b32_e32 v3, -1, v20
; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, v1, s4
; GFX10-NEXT: v_or_b32_e32 v1, v11, v8
; GFX10-NEXT: v_sub_nc_u32_e32 v10, 64, v23
; GFX10-NEXT: v_or_b32_e32 v2, v2, v9
; GFX10-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13]
; GFX10-NEXT: v_lshlrev_b32_e32 v16, 31, v14 ; GFX10-NEXT: v_lshlrev_b32_e32 v16, 31, v14
; GFX10-NEXT: v_and_b32_e32 v25, 0x7f, v3
; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[4:5]
; GFX10-NEXT: v_lshlrev_b64 v[12:13], v23, v[6:7]
; GFX10-NEXT: v_lshrrev_b64 v[14:15], 1, v[14:15] ; GFX10-NEXT: v_lshrrev_b64 v[14:15], 1, v[14:15]
; GFX10-NEXT: v_or_b32_e32 v9, v9, v16 ; GFX10-NEXT: v_or_b32_e32 v29, v17, v19
; GFX10-NEXT: v_sub_nc_u32_e32 v20, 64, v25 ; GFX10-NEXT: v_or_b32_e32 v13, v13, v16
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 64, v23 ; GFX10-NEXT: v_xor_b32_e32 v16, -1, v20
; GFX10-NEXT: v_lshlrev_b64 v[16:17], v23, v[4:5] ; GFX10-NEXT: v_and_b32_e32 v20, 0x7f, v16
; GFX10-NEXT: v_or_b32_e32 v12, v10, v12 ; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v20
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v25 ; GFX10-NEXT: v_lshrrev_b64 v[18:19], v20, v[12:13]
; GFX10-NEXT: v_lshrrev_b64 v[18:19], v25, v[8:9] ; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 0, v20
; GFX10-NEXT: v_lshlrev_b64 v[20:21], v20, v[14:15] ; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[14:15]
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23 ; GFX10-NEXT: v_or_b32_e32 v18, v18, v16
; GFX10-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5] ; GFX10-NEXT: v_subrev_nc_u32_e32 v16, 64, v23
; GFX10-NEXT: v_or_b32_e32 v5, v11, v13 ; GFX10-NEXT: v_or_b32_e32 v19, v19, v17
; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[14:15] ; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[0:1]
; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v25 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v23, v[0:1]
; GFX10-NEXT: v_cndmask_b32_e32 v13, 0, v16, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v21, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v16, v18, v20 ; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v18, v19, v21 ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v12, v3, v12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v2, s4
; GFX10-NEXT: v_lshrrev_b64 v[3:4], v25, v[14:15] ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v24
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v3, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v25 ; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v24
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v23 ; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v18, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v25, s4
; GFX10-NEXT: v_cndmask_b32_e32 v14, 0, v17, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v26, s4
; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, v6, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v2, v8, s5
; GFX10-NEXT: v_cndmask_b32_e64 v7, v5, v7, s6 ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v27
; GFX10-NEXT: v_cndmask_b32_e64 v5, v10, v8, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v3, v9, s5
; GFX10-NEXT: v_cndmask_b32_e64 v8, v11, v9, s5 ; GFX10-NEXT: v_cmp_gt_u32_e64 s5, 64, v27
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v3, s4 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v8
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, v4, s4 ; GFX10-NEXT: v_lshlrev_b64 v[2:3], v2, v[4:5]
; GFX10-NEXT: v_or_b32_e32 v3, v22, v24 ; GFX10-NEXT: v_lshlrev_b64 v[4:5], v27, v[4:5]
; GFX10-NEXT: v_or_b32_e32 v4, v13, v5 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v9
; GFX10-NEXT: v_or_b32_e32 v5, v14, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v28, s5
; GFX10-NEXT: v_or_b32_e32 v6, v6, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v29, s5
; GFX10-NEXT: v_or_b32_e32 v7, v7, v10 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v4, s5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, v5, s5
; GFX10-NEXT: v_cndmask_b32_e64 v21, v2, v6, s6
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v20
; GFX10-NEXT: v_cndmask_b32_e64 v22, v3, v7, s6
; GFX10-NEXT: v_cmp_gt_u32_e64 s6, 64, v20
; GFX10-NEXT: v_lshrrev_b64 v[6:7], v20, v[14:15]
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, v[14:15]
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v6, s6
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, v7, s6
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v18, s6
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v19, s6
; GFX10-NEXT: v_or_b32_e32 v6, v21, v6
; GFX10-NEXT: v_or_b32_e32 v7, v22, v7
; GFX10-NEXT: v_cndmask_b32_e64 v12, v2, v12, s7
; GFX10-NEXT: v_cndmask_b32_e64 v13, v3, v13, s7
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v24, v[10:11]
; GFX10-NEXT: v_or_b32_e32 v4, v4, v12
; GFX10-NEXT: v_or_b32_e32 v5, v5, v13
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s4
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s4
; GFX10-NEXT: v_or_b32_e32 v2, v16, v2
; GFX10-NEXT: v_or_b32_e32 v3, v17, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_v2i128: ; GFX11-LABEL: v_fshl_v2i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9] ; GFX11-NEXT: v_and_b32_e32 v23, 0x7f, v16
; GFX11-NEXT: v_and_b32_e32 v27, 0x7f, v16
; GFX11-NEXT: v_lshlrev_b32_e32 v21, 31, v10
; GFX11-NEXT: v_xor_b32_e32 v16, -1, v16 ; GFX11-NEXT: v_xor_b32_e32 v16, -1, v16
; GFX11-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9]
; GFX11-NEXT: v_and_b32_e32 v27, 0x7f, v20
; GFX11-NEXT: v_lshrrev_b64 v[12:13], 1, v[12:13]
; GFX11-NEXT: v_sub_nc_u32_e32 v17, 64, v23
; GFX11-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3]
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
; GFX11-NEXT: v_or_b32_e32 v21, v17, v21
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v22, v18, v22
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 31, v10
; GFX11-NEXT: v_and_b32_e32 v24, 0x7f, v16
; GFX11-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11] ; GFX11-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_or_b32_e32 v9, v9, v17
; GFX11-NEXT: v_sub_nc_u32_e32 v17, 64, v27 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v9, v9, v21 ; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v24
; GFX11-NEXT: v_lshlrev_b64 v[21:22], v27, v[0:1] ; GFX11-NEXT: v_lshrrev_b64 v[18:19], v24, v[8:9]
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v27 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_and_b32_e32 v28, 0x7f, v16 ; GFX11-NEXT: v_lshlrev_b64 v[16:17], v16, v[10:11]
; GFX11-NEXT: v_lshrrev_b64 v[16:17], v17, v[0:1] ; GFX11-NEXT: v_or_b32_e32 v25, v18, v16
; GFX11-NEXT: v_lshlrev_b64 v[18:19], v27, v[2:3] ; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v27
; GFX11-NEXT: v_subrev_nc_u32_e32 v29, 64, v27 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v21, 0, v21, vcc_lo ; GFX11-NEXT: v_or_b32_e32 v26, v19, v17
; GFX11-NEXT: v_sub_nc_u32_e32 v25, 64, v28 ; GFX11-NEXT: v_lshlrev_b64 v[18:19], v27, v[6:7]
; GFX11-NEXT: v_lshrrev_b64 v[23:24], v28, v[8:9] ; GFX11-NEXT: v_lshrrev_b64 v[16:17], v16, v[4:5]
; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v28 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v18, v16, v18 ; GFX11-NEXT: v_or_b32_e32 v28, v16, v18
; GFX11-NEXT: v_subrev_nc_u32_e32 v16, 64, v28
; GFX11-NEXT: v_lshlrev_b64 v[25:26], v25, v[10:11]
; GFX11-NEXT: v_lshlrev_b64 v[0:1], v29, v[0:1]
; GFX11-NEXT: v_or_b32_e32 v19, v17, v19
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 0, v28
; GFX11-NEXT: v_lshrrev_b64 v[16:17], v16, v[10:11]
; GFX11-NEXT: v_or_b32_e32 v23, v23, v25
; GFX11-NEXT: v_or_b32_e32 v24, v24, v26
; GFX11-NEXT: v_dual_cndmask_b32 v18, v0, v18 :: v_dual_cndmask_b32 v19, v1, v19
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v27
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v23, s0
; GFX11-NEXT: v_lshrrev_b64 v[0:1], v28, v[10:11]
; GFX11-NEXT: v_cndmask_b32_e64 v10, v17, v24, s0
; GFX11-NEXT: v_cndmask_b32_e32 v11, 0, v22, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v22, v19, v3, s2
; GFX11-NEXT: v_cndmask_b32_e64 v3, v16, v8, s1
; GFX11-NEXT: v_cndmask_b32_e64 v2, v18, v2, s2
; GFX11-NEXT: v_cndmask_b32_e64 v8, v10, v9, s1
; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v0, s0
; GFX11-NEXT: v_and_b32_e32 v23, 0x7f, v20
; GFX11-NEXT: v_or_b32_e32 v0, v21, v3
; GFX11-NEXT: v_xor_b32_e32 v3, -1, v20
; GFX11-NEXT: v_cndmask_b32_e64 v24, 0, v1, s0
; GFX11-NEXT: v_or_b32_e32 v1, v11, v8
; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v23
; GFX11-NEXT: v_or_b32_e32 v2, v2, v9
; GFX11-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13]
; GFX11-NEXT: v_lshlrev_b32_e32 v16, 31, v14 ; GFX11-NEXT: v_lshlrev_b32_e32 v16, 31, v14
; GFX11-NEXT: v_and_b32_e32 v25, 0x7f, v3
; GFX11-NEXT: v_lshrrev_b64 v[10:11], v10, v[4:5]
; GFX11-NEXT: v_lshlrev_b64 v[12:13], v23, v[6:7]
; GFX11-NEXT: v_lshrrev_b64 v[14:15], 1, v[14:15] ; GFX11-NEXT: v_lshrrev_b64 v[14:15], 1, v[14:15]
; GFX11-NEXT: v_or_b32_e32 v9, v9, v16 ; GFX11-NEXT: v_or_b32_e32 v29, v17, v19
; GFX11-NEXT: v_sub_nc_u32_e32 v20, 64, v25 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_subrev_nc_u32_e32 v3, 64, v23 ; GFX11-NEXT: v_or_b32_e32 v13, v13, v16
; GFX11-NEXT: v_lshlrev_b64 v[16:17], v23, v[4:5] ; GFX11-NEXT: v_xor_b32_e32 v16, -1, v20
; GFX11-NEXT: v_or_b32_e32 v12, v10, v12 ; GFX11-NEXT: v_and_b32_e32 v20, 0x7f, v16
; GFX11-NEXT: v_subrev_nc_u32_e32 v10, 64, v25 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_lshrrev_b64 v[18:19], v25, v[8:9] ; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v20
; GFX11-NEXT: v_lshlrev_b64 v[20:21], v20, v[14:15] ; GFX11-NEXT: v_lshrrev_b64 v[18:19], v20, v[12:13]
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5] ; GFX11-NEXT: v_lshlrev_b64 v[16:17], v16, v[14:15]
; GFX11-NEXT: v_or_b32_e32 v5, v11, v13 ; GFX11-NEXT: v_or_b32_e32 v18, v18, v16
; GFX11-NEXT: v_lshrrev_b64 v[10:11], v10, v[14:15] ; GFX11-NEXT: v_subrev_nc_u32_e32 v16, 64, v23
; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v25 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v13, 0, v16, vcc_lo ; GFX11-NEXT: v_or_b32_e32 v19, v19, v17
; GFX11-NEXT: v_or_b32_e32 v16, v18, v20 ; GFX11-NEXT: v_lshlrev_b64 v[16:17], v16, v[0:1]
; GFX11-NEXT: v_or_b32_e32 v18, v19, v21 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_cndmask_b32 v12, v3, v12 :: v_dual_cndmask_b32 v5, v4, v5 ; GFX11-NEXT: v_cndmask_b32_e32 v16, v16, v21, vcc_lo
; GFX11-NEXT: v_lshrrev_b64 v[3:4], v25, v[14:15] ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v23
; GFX11-NEXT: v_cndmask_b32_e32 v14, 0, v17, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v16, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 0, v24
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 0, v25 ; GFX11-NEXT: v_lshlrev_b64 v[0:1], v23, v[0:1]
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v23 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v18, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v2, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 64, v24
; GFX11-NEXT: v_cndmask_b32_e64 v6, v12, v6, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v3, s0
; GFX11-NEXT: v_cndmask_b32_e64 v7, v5, v7, s2 ; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v24
; GFX11-NEXT: v_cndmask_b32_e64 v5, v10, v8, s1 ; GFX11-NEXT: v_dual_cndmask_b32 v0, 0, v0 :: v_dual_cndmask_b32 v1, 0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v8, v11, v9, s1 ; GFX11-NEXT: v_lshrrev_b64 v[2:3], v2, v[10:11]
; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v3, s0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v27
; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, v4, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v3, v22, v24 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v25, s0
; GFX11-NEXT: v_or_b32_e32 v4, v13, v5 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v26, s0
; GFX11-NEXT: v_or_b32_e32 v5, v14, v8 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v6, v6, v9 ; GFX11-NEXT: v_cndmask_b32_e64 v8, v2, v8, s1
; GFX11-NEXT: v_or_b32_e32 v7, v7, v10 ; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 64, v27
; GFX11-NEXT: v_cndmask_b32_e64 v9, v3, v9, s1
; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v27
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v0, v0, v8
; GFX11-NEXT: v_lshlrev_b64 v[2:3], v2, v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v1, v1, v9
; GFX11-NEXT: v_cndmask_b32_e64 v22, v2, v28, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v23, v3, v29, s1
; GFX11-NEXT: v_lshrrev_b64 v[2:3], v24, v[10:11]
; GFX11-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
; GFX11-NEXT: v_lshlrev_b64 v[4:5], v27, v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, v3, s0
; GFX11-NEXT: v_subrev_nc_u32_e32 v3, 64, v20
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0
; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v20
; GFX11-NEXT: v_lshrrev_b64 v[8:9], v20, v[14:15]
; GFX11-NEXT: v_cndmask_b32_e64 v21, 0, v4, s1
; GFX11-NEXT: v_lshrrev_b64 v[3:4], v3, v[14:15]
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v20
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, v5, s1
; GFX11-NEXT: v_or_b32_e32 v2, v16, v2
; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v8, s0
; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v9, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v18, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v19, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v6, v6, v8
; GFX11-NEXT: v_or_b32_e32 v7, v7, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v11, v3, v12, s2
; GFX11-NEXT: v_cndmask_b32_e64 v12, v4, v13, s2
; GFX11-NEXT: v_or_b32_e32 v3, v17, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v4, v21, v11
; GFX11-NEXT: v_or_b32_e32 v5, v5, v12
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.fshl.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) %result = call <2 x i128> @llvm.fshl.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
ret <2 x i128> %result ret <2 x i128> %result
} }
declare i7 @llvm.fshl.i7(i7, i7, i7) #0 declare i7 @llvm.fshl.i7(i7, i7, i7) #0
declare i8 @llvm.fshl.i8(i8, i8, i8) #0 declare i8 @llvm.fshl.i8(i8, i8, i8) #0
declare <2 x i8> @llvm.fshl.v2i8(<2 x i8>, <2 x i8>, <2 x i8>) #0 declare <2 x i8> @llvm.fshl.v2i8(<2 x i8>, <2 x i8>, <2 x i8>) #0
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llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll

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; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshr_v2i8: ; GFX10-LABEL: v_fshr_v2i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v2 ; GFX10-NEXT: v_xor_b32_e32 v3, -1, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 8, v0 ; GFX10-NEXT: v_lshlrev_b16 v4, 1, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 8, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v5, 8, v2
; GFX10-NEXT: v_and_b32_e32 v7, 7, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2 ; GFX10-NEXT: v_and_b32_e32 v2, 7, v2
; GFX10-NEXT: v_xor_b32_e32 v6, -1, v3
; GFX10-NEXT: v_and_b32_e32 v3, 7, v3 ; GFX10-NEXT: v_and_b32_e32 v3, 7, v3
; GFX10-NEXT: v_lshlrev_b16 v4, 1, v4 ; GFX10-NEXT: s_movk_i32 s4, 0xff
; GFX10-NEXT: v_and_b32_e32 v5, 0xff, v5 ; GFX10-NEXT: v_and_b32_e32 v6, 7, v5
; GFX10-NEXT: v_xor_b32_e32 v5, -1, v5
; GFX10-NEXT: v_lshlrev_b16 v0, 1, v0 ; GFX10-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX10-NEXT: v_and_b32_e32 v6, 7, v6 ; GFX10-NEXT: v_lshlrev_b16 v3, v3, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 8, v1
; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1 ; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v2, 7, v2 ; GFX10-NEXT: v_and_b32_e32 v5, 7, v5
; GFX10-NEXT: v_lshrrev_b16 v3, v3, v5 ; GFX10-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX10-NEXT: s_movk_i32 s4, 0xff ; GFX10-NEXT: v_lshrrev_b16 v1, v2, v1
; GFX10-NEXT: v_lshlrev_b16 v4, v6, v4 ; GFX10-NEXT: v_lshlrev_b16 v0, v5, v0
; GFX10-NEXT: v_lshrrev_b16 v1, v7, v1 ; GFX10-NEXT: v_lshrrev_b16 v4, v6, v4
; GFX10-NEXT: v_lshlrev_b16 v0, v2, v0 ; GFX10-NEXT: v_or_b32_e32 v1, v3, v1
; GFX10-NEXT: v_or_b32_e32 v2, v4, v3 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX10-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v1, v2, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_v2i8: ; GFX11-LABEL: v_fshr_v2i8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v2
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v0
▲ Show 20 Lines • Show All 454 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 24, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0 ; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshr_v4i8: ; GFX10-LABEL: v_fshr_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 8, v2 ; GFX10-NEXT: v_and_b32_e32 v3, 7, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v0 ; GFX10-NEXT: v_and_b32_e32 v4, 0xff, v1
; GFX10-NEXT: v_xor_b32_e32 v8, -1, v2 ; GFX10-NEXT: v_lshlrev_b16 v5, 1, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v6, 8, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v12, 24, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; GFX10-NEXT: v_xor_b32_e32 v10, -1, v5 ; GFX10-NEXT: v_lshrrev_b16 v3, v3, v4
; GFX10-NEXT: v_lshlrev_b16 v3, 1, v3 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v0 ; GFX10-NEXT: v_and_b32_e32 v7, 7, v6
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 24, v0 ; GFX10-NEXT: v_xor_b32_e32 v6, -1, v6
; GFX10-NEXT: v_lshrrev_b32_e32 v7, 8, v1 ; GFX10-NEXT: v_lshlrev_b16 v9, 1, v9
; GFX10-NEXT: v_and_b32_e32 v10, 7, v10 ; GFX10-NEXT: v_and_b32_e32 v4, 7, v4
; GFX10-NEXT: v_and_b32_e32 v6, 7, v6
; GFX10-NEXT: v_lshlrev_b16 v4, v4, v5
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX10-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX10-NEXT: v_lshrrev_b16 v5, v7, v5
; GFX10-NEXT: v_lshrrev_b32_e32 v7, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 24, v0
; GFX10-NEXT: v_lshlrev_b16 v7, 1, v7
; GFX10-NEXT: v_lshlrev_b16 v0, 1, v0 ; GFX10-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX10-NEXT: v_lshlrev_b16 v6, v6, v7
; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX10-NEXT: v_xor_b32_e32 v8, -1, v7
; GFX10-NEXT: v_and_b32_e32 v7, 7, v7
; GFX10-NEXT: v_and_b32_e32 v8, 7, v8 ; GFX10-NEXT: v_and_b32_e32 v8, 7, v8
; GFX10-NEXT: v_mov_b32_e32 v13, 0xff ; GFX10-NEXT: v_lshlrev_b16 v8, v8, v9
; GFX10-NEXT: v_xor_b32_e32 v14, -1, v12 ; GFX10-NEXT: v_mov_b32_e32 v9, 0xff
; GFX10-NEXT: v_lshlrev_b16 v3, v10, v3 ; GFX10-NEXT: v_and_b32_sdwa v9, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_xor_b32_e32 v10, -1, v11 ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 24, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v9, 24, v1 ; GFX10-NEXT: v_lshrrev_b16 v7, v7, v9
; GFX10-NEXT: v_lshlrev_b16 v0, v8, v0 ; GFX10-NEXT: v_xor_b32_e32 v9, -1, v2
; GFX10-NEXT: v_and_b32_e32 v8, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v5, 7, v5
; GFX10-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX10-NEXT: v_and_b32_e32 v11, 7, v11
; GFX10-NEXT: v_and_b32_e32 v10, 7, v10
; GFX10-NEXT: v_lshlrev_b16 v4, 1, v4
; GFX10-NEXT: v_and_b32_sdwa v1, v1, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_e32 v13, 7, v14
; GFX10-NEXT: v_lshlrev_b16 v6, 1, v6
; GFX10-NEXT: v_and_b32_e32 v12, 7, v12
; GFX10-NEXT: v_and_b32_e32 v2, 7, v2 ; GFX10-NEXT: v_and_b32_e32 v2, 7, v2
; GFX10-NEXT: v_lshrrev_b16 v5, v5, v7 ; GFX10-NEXT: v_and_b32_e32 v9, 7, v9
; GFX10-NEXT: v_lshlrev_b16 v4, v10, v4 ; GFX10-NEXT: v_lshrrev_b16 v1, v2, v1
; GFX10-NEXT: v_lshrrev_b16 v1, v11, v1 ; GFX10-NEXT: v_or_b32_e32 v2, v4, v3
; GFX10-NEXT: v_lshlrev_b16 v6, v13, v6 ; GFX10-NEXT: v_or_b32_e32 v3, v6, v5
; GFX10-NEXT: v_lshrrev_b16 v7, v12, v9 ; GFX10-NEXT: v_or_b32_e32 v4, v8, v7
; GFX10-NEXT: v_lshrrev_b16 v2, v2, v8 ; GFX10-NEXT: v_lshlrev_b16 v0, v9, v0
; GFX10-NEXT: v_or_b32_e32 v3, v3, v5 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v5, 8 ; GFX10-NEXT: v_mov_b32_e32 v1, 8
; GFX10-NEXT: v_or_b32_e32 v1, v4, v1 ; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-NEXT: v_or_b32_e32 v4, v6, v7 ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v4 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v4
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xff, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: v_and_or_b32 v1, v2, 0xff, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_v4i8: ; GFX11-LABEL: v_fshr_v4i8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 8, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 8, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 8, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 8, v2
▲ Show 20 Lines • Show All 877 Lines • ▼ Show 20 Lines
; GFX10-NEXT: v_lshrrev_b32_e64 v1, v1, s3 ; GFX10-NEXT: v_lshrrev_b32_e64 v1, v1, s3
; GFX10-NEXT: v_lshl_or_b32 v0, s0, v3, v0 ; GFX10-NEXT: v_lshl_or_b32 v0, s0, v3, v0
; GFX10-NEXT: s_or_b32 s0, s2, s1 ; GFX10-NEXT: s_or_b32 s0, s2, s1
; GFX10-NEXT: v_lshl_or_b32 v1, s0, v2, v1 ; GFX10-NEXT: v_lshl_or_b32 v1, s0, v2, v1
; GFX10-NEXT: s_mov_b32 s0, 8 ; GFX10-NEXT: s_mov_b32 s0, 8
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 ; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-NEXT: s_mov_b32 s0, 16 ; GFX10-NEXT: s_mov_b32 s0, 16
; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v1 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v1
; GFX10-NEXT: v_bfe_u32 v4, v1, 8, 8
; GFX10-NEXT: v_bfe_u32 v1, v1, 16, 8
; GFX10-NEXT: v_and_or_b32 v2, v0, 0xff, v2 ; GFX10-NEXT: v_and_or_b32 v2, v0, 0xff, v2
; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX10-NEXT: v_lshl_or_b32 v1, v1, 8, v4
; GFX10-NEXT: v_or3_b32 v0, v2, v0, v3 ; GFX10-NEXT: v_or3_b32 v0, v2, v0, v3
; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_bfe_u32 v2, v1, 8, 8
; GFX10-NEXT: v_bfe_u32 v1, v1, 16, 8
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_lshl_or_b32 v1, v1, 8, v2
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_fshr_v2i24: ; GFX11-LABEL: s_fshr_v2i24:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 ; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, 24 ; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
; GFX11-NEXT: s_lshr_b32 s6, s0, 8 ; GFX11-NEXT: s_lshr_b32 s6, s0, 8
; GFX11-NEXT: s_bfe_u32 s9, 8, 0x100000 ; GFX11-NEXT: s_bfe_u32 s9, 8, 0x100000
▲ Show 20 Lines • Show All 301 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_lshl_or_b32 v1, v1, v4, v2 ; GFX9-NEXT: v_lshl_or_b32 v1, v1, v4, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshr_v2i24: ; GFX10-LABEL: v_fshr_v2i24:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4 ; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX10-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 ; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7 ; GFX10-NEXT: v_mul_lo_u32 v7, 0xffffffe8, v6
; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v6 ; GFX10-NEXT: v_mul_hi_u32 v7, v6, v7
; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v7
; GFX10-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX10-NEXT: v_mul_hi_u32 v9, v7, v9
; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v8
; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v9
; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6 ; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24 ; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6 ; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6
; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v7
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4 ; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4 ; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5 ; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v4
; GFX10-NEXT: v_sub_nc_u32_e32 v6, 23, v4 ; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v4
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo ; GFX10-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4 ; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v6 ; GFX10-NEXT: v_lshl_or_b32 v0, v0, v4, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v7, 23, v5 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v2, v4, v2 ; GFX10-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v7 ; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, v5, v3 ; GFX10-NEXT: v_mul_lo_u32 v4, 0xffffffe8, v2
; GFX10-NEXT: v_lshl_or_b32 v0, v0, v6, v2 ; GFX10-NEXT: v_mul_hi_u32 v4, v2, v4
; GFX10-NEXT: v_lshl_or_b32 v1, v1, v4, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v4
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v5
; GFX10-NEXT: v_mul_hi_u32 v2, v4, v2
; GFX10-NEXT: v_mul_lo_u32 v2, v2, 24
; GFX10-NEXT: v_sub_nc_u32_e32 v2, v4, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v4, 24, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v4, 24, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v2, 23, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, v4, v3
; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX10-NEXT: v_lshl_or_b32 v1, v1, v2, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_v2i24: ; GFX11-LABEL: v_fshr_v2i24:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v6, 24 ; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v7, 24 ; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
▲ Show 20 Lines • Show All 1,982 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v2, v3 ; GFX9-NEXT: v_pk_lshrrev_b16 v2, v2, v3
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2 ; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshr_v3i16: ; GFX10-LABEL: v_fshr_v3i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_xor_b32_e32 v6, -1, v4 ; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v4
; GFX10-NEXT: v_xor_b32_e32 v7, -1, v5 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_and_b32_e32 v5, 0xf000f, v5
; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v6
; GFX10-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
; GFX10-NEXT: v_and_b32_e32 v7, 0xf000f, v7 ; GFX10-NEXT: v_pk_lshrrev_b16 v2, v6, v2
; GFX10-NEXT: v_pk_lshrrev_b16 v2, v4, v2 ; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v5, v3 ; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v5
; GFX10-NEXT: v_pk_lshlrev_b16 v0, v6, v0 ; GFX10-NEXT: v_pk_lshlrev_b16 v0, v4, v0
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v7, v1 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v5
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v6, v3
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v4, v1
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_v3i16: ; GFX11-LABEL: v_fshr_v3i16:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4 ; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
▲ Show 20 Lines • Show All 448 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v2, v3 ; GFX9-NEXT: v_pk_lshrrev_b16 v2, v2, v3
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2 ; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshr_v4i16: ; GFX10-LABEL: v_fshr_v4i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_xor_b32_e32 v6, -1, v4 ; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v4
; GFX10-NEXT: v_xor_b32_e32 v7, -1, v5 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_and_b32_e32 v5, 0xf000f, v5
; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v6
; GFX10-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
; GFX10-NEXT: v_and_b32_e32 v7, 0xf000f, v7 ; GFX10-NEXT: v_pk_lshrrev_b16 v2, v6, v2
; GFX10-NEXT: v_pk_lshrrev_b16 v2, v4, v2 ; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v5, v3 ; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v5
; GFX10-NEXT: v_pk_lshlrev_b16 v0, v6, v0 ; GFX10-NEXT: v_pk_lshlrev_b16 v0, v4, v0
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v7, v1 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v5
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v6, v3
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v4, v1
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_v4i16: ; GFX11-LABEL: v_fshr_v4i16:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4 ; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshr_i64: ; GFX10-LABEL: v_fshr_i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_xor_b32_e32 v5, -1, v4 ; GFX10-NEXT: v_and_b32_e32 v5, 63, v4
; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v5, v[2:3]
; GFX10-NEXT: v_and_b32_e32 v4, 63, v4 ; GFX10-NEXT: v_and_b32_e32 v4, 63, v4
; GFX10-NEXT: v_and_b32_e32 v5, 63, v5 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v4, v[2:3]
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v5, v[0:1]
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_i64: ; GFX11-LABEL: v_fshr_i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
▲ Show 20 Lines • Show All 489 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_or_b32_e32 v2, v2, v6 ; GFX9-NEXT: v_or_b32_e32 v2, v2, v6
; GFX9-NEXT: v_or_b32_e32 v3, v3, v7 ; GFX9-NEXT: v_or_b32_e32 v3, v3, v7
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshr_v2i64: ; GFX10-LABEL: v_fshr_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_xor_b32_e32 v9, -1, v8 ; GFX10-NEXT: v_and_b32_e32 v9, 63, v8
; GFX10-NEXT: v_xor_b32_e32 v11, -1, v10 ; GFX10-NEXT: v_xor_b32_e32 v8, -1, v8
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX10-NEXT: v_lshrrev_b64 v[4:5], v9, v[4:5]
; GFX10-NEXT: v_and_b32_e32 v8, 63, v8 ; GFX10-NEXT: v_and_b32_e32 v8, 63, v8
; GFX10-NEXT: v_and_b32_e32 v9, 63, v9 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
; GFX10-NEXT: v_and_b32_e32 v11, 63, v11
; GFX10-NEXT: v_and_b32_e32 v10, 63, v10
; GFX10-NEXT: v_lshrrev_b64 v[4:5], v8, v[4:5]
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[2:3], v11, v[2:3]
; GFX10-NEXT: v_lshrrev_b64 v[6:7], v10, v[6:7]
; GFX10-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
; GFX10-NEXT: v_xor_b32_e32 v4, -1, v10
; GFX10-NEXT: v_or_b32_e32 v1, v1, v5 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v5
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6 ; GFX10-NEXT: v_and_b32_e32 v4, 63, v4
; GFX10-NEXT: v_or_b32_e32 v3, v3, v7 ; GFX10-NEXT: v_lshlrev_b64 v[2:3], v4, v[2:3]
; GFX10-NEXT: v_and_b32_e32 v4, 63, v10
; GFX10-NEXT: v_lshrrev_b64 v[4:5], v4, v[6:7]
; GFX10-NEXT: v_or_b32_e32 v2, v2, v4
; GFX10-NEXT: v_or_b32_e32 v3, v3, v5
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_v2i64: ; GFX11-LABEL: v_fshr_v2i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_xor_b32_e32 v9, -1, v8 ; GFX11-NEXT: v_xor_b32_e32 v9, -1, v8
; GFX11-NEXT: v_xor_b32_e32 v11, -1, v10 ; GFX11-NEXT: v_xor_b32_e32 v11, -1, v10
▲ Show 20 Lines • Show All 403 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_or_b32_e32 v2, v10, v2 ; GFX9-NEXT: v_or_b32_e32 v2, v10, v2
; GFX9-NEXT: v_or_b32_e32 v3, v11, v3 ; GFX9-NEXT: v_or_b32_e32 v3, v11, v3
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshr_i128: ; GFX10-LABEL: v_fshr_i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_xor_b32_e32 v9, -1, v8 ; GFX10-NEXT: v_and_b32_e32 v13, 0x7f, v8
; GFX10-NEXT: v_xor_b32_e32 v8, -1, v8
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX10-NEXT: v_lshrrev_b32_e32 v10, 31, v1 ; GFX10-NEXT: v_sub_nc_u32_e32 v9, 64, v13
; GFX10-NEXT: v_and_b32_e32 v19, 0x7f, v8 ; GFX10-NEXT: v_lshrrev_b64 v[11:12], v13, v[4:5]
; GFX10-NEXT: v_and_b32_e32 v15, 0x7f, v8
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v13
; GFX10-NEXT: v_lshlrev_b64 v[9:10], v9, v[6:7]
; GFX10-NEXT: v_sub_nc_u32_e32 v8, 64, v15
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v15
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v15
; GFX10-NEXT: v_or_b32_e32 v14, v11, v9
; GFX10-NEXT: v_lshrrev_b32_e32 v9, 31, v1
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX10-NEXT: v_and_b32_e32 v18, 0x7f, v9 ; GFX10-NEXT: v_or_b32_e32 v12, v12, v10
; GFX10-NEXT: v_or_b32_e32 v2, v2, v10 ; GFX10-NEXT: v_or_b32_e32 v2, v2, v9
; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v19 ; GFX10-NEXT: v_lshrrev_b64 v[8:9], v8, v[0:1]
; GFX10-NEXT: v_subrev_nc_u32_e32 v21, 64, v19 ; GFX10-NEXT: v_lshlrev_b64 v[10:11], v15, v[2:3]
; GFX10-NEXT: v_sub_nc_u32_e32 v10, 64, v18 ; GFX10-NEXT: v_or_b32_e32 v10, v8, v10
; GFX10-NEXT: v_subrev_nc_u32_e32 v20, 64, v18 ; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 64, v15
; GFX10-NEXT: v_lshlrev_b64 v[8:9], v18, v[2:3] ; GFX10-NEXT: v_or_b32_e32 v11, v9, v11
; GFX10-NEXT: v_lshrrev_b64 v[12:13], v19, v[4:5] ; GFX10-NEXT: v_lshlrev_b64 v[8:9], v8, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[6:7] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v15, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[0:1] ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
; GFX10-NEXT: v_lshlrev_b64 v[14:15], v18, v[0:1] ; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v20, v[0:1] ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18 ; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v19 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v2, s4
; GFX10-NEXT: v_or_b32_e32 v12, v12, v16 ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v13
; GFX10-NEXT: v_or_b32_e32 v10, v10, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v3, s4
; GFX10-NEXT: v_or_b32_e32 v11, v11, v9 ; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v13
; GFX10-NEXT: v_lshrrev_b64 v[8:9], v21, v[6:7] ; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, v[6:7]
; GFX10-NEXT: v_or_b32_e32 v13, v13, v17 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v14, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v19 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v12, s4
; GFX10-NEXT: v_cndmask_b32_e32 v10, v0, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v2, v4, s5
; GFX10-NEXT: v_cndmask_b32_e32 v11, v1, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v3, v5, s5
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v19, v[6:7] ; GFX10-NEXT: v_lshrrev_b64 v[2:3], v13, v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v12, s4 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v18 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v5
; GFX10-NEXT: v_cndmask_b32_e64 v6, v9, v13, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s4
; GFX10-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s4
; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v15, vcc_lo ; GFX10-NEXT: v_or_b32_e32 v2, v8, v2
; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v4, s5 ; GFX10-NEXT: v_or_b32_e32 v3, v9, v3
; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, v2, s6
; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, v3, s6
; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, v5, s5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v1, s4
; GFX10-NEXT: v_or_b32_e32 v0, v14, v4
; GFX10-NEXT: v_or_b32_e32 v1, v7, v5
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6
; GFX10-NEXT: v_or_b32_e32 v3, v3, v8
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_i128: ; GFX11-LABEL: v_fshr_i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_xor_b32_e32 v9, -1, v8 ; GFX11-NEXT: v_xor_b32_e32 v9, -1, v8
; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 31, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v10, 31, v1
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_and_b32_e32 v14, 0x7f, v9
; GFX11-NEXT: v_and_b32_e32 v18, 0x7f, v9
; GFX11-NEXT: v_or_b32_e32 v2, v2, v10 ; GFX11-NEXT: v_or_b32_e32 v2, v2, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b64 v[14:15], v18, v[0:1] ; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v14
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18 ; GFX11-NEXT: v_subrev_nc_u32_e32 v16, 64, v14
; GFX11-NEXT: v_and_b32_e32 v19, 0x7f, v8 ; GFX11-NEXT: v_lshlrev_b64 v[12:13], v14, v[0:1]
; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v18 ; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v14
; GFX11-NEXT: v_subrev_nc_u32_e32 v20, 64, v18 ; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v14
; GFX11-NEXT: v_lshlrev_b64 v[8:9], v18, v[2:3]
; GFX11-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc_lo
; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v19
; GFX11-NEXT: v_lshrrev_b64 v[10:11], v10, v[0:1] ; GFX11-NEXT: v_lshrrev_b64 v[10:11], v10, v[0:1]
; GFX11-NEXT: v_subrev_nc_u32_e32 v21, 64, v19 ; GFX11-NEXT: v_lshlrev_b64 v[0:1], v16, v[0:1]
; GFX11-NEXT: v_lshrrev_b64 v[12:13], v19, v[4:5] ; GFX11-NEXT: v_and_b32_e32 v15, 0x7f, v8
; GFX11-NEXT: v_lshlrev_b64 v[0:1], v20, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[8:9], v14, v[2:3]
; GFX11-NEXT: v_lshlrev_b64 v[16:17], v16, v[6:7] ; GFX11-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo
; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v19
; GFX11-NEXT: v_or_b32_e32 v10, v10, v8
; GFX11-NEXT: v_or_b32_e32 v11, v11, v9
; GFX11-NEXT: v_lshrrev_b64 v[8:9], v21, v[6:7]
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 0, v19
; GFX11-NEXT: v_or_b32_e32 v12, v12, v16
; GFX11-NEXT: v_or_b32_e32 v13, v13, v17
; GFX11-NEXT: v_dual_cndmask_b32 v10, v0, v10 :: v_dual_cndmask_b32 v11, v1, v11
; GFX11-NEXT: v_lshrrev_b64 v[0:1], v19, v[6:7]
; GFX11-NEXT: v_cndmask_b32_e32 v7, 0, v15, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v12, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v18
; GFX11-NEXT: v_cndmask_b32_e64 v6, v9, v13, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v4, s1 ; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v15
; GFX11-NEXT: v_cndmask_b32_e64 v2, v10, v2, s2 ; GFX11-NEXT: v_or_b32_e32 v19, v11, v9
; GFX11-NEXT: v_cndmask_b32_e64 v3, v11, v3, s2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_or_b32_e32 v16, v10, v8
; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, v5, s1 ; GFX11-NEXT: v_lshlrev_b64 v[10:11], v18, v[6:7]
; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v1, s0 ; GFX11-NEXT: v_cndmask_b32_e32 v18, v1, v19, vcc_lo
; GFX11-NEXT: v_or_b32_e32 v0, v14, v4 ; GFX11-NEXT: v_subrev_nc_u32_e32 v17, 64, v15
; GFX11-NEXT: v_or_b32_e32 v1, v7, v5 ; GFX11-NEXT: v_lshrrev_b64 v[8:9], v15, v[4:5]
; GFX11-NEXT: v_cndmask_b32_e32 v16, v0, v16, vcc_lo
; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v15
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 0, v15
; GFX11-NEXT: v_lshrrev_b64 v[0:1], v17, v[6:7]
; GFX11-NEXT: v_lshrrev_b64 v[6:7], v15, v[6:7]
; GFX11-NEXT: v_or_b32_e32 v8, v8, v10
; GFX11-NEXT: v_or_b32_e32 v9, v9, v11
; GFX11-NEXT: v_cndmask_b32_e64 v2, v16, v2, s2
; GFX11-NEXT: v_cndmask_b32_e64 v3, v18, v3, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v2, v2, v6 ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v8, s0
; GFX11-NEXT: v_or_b32_e32 v3, v3, v8 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0
; GFX11-NEXT: v_cndmask_b32_e32 v8, 0, v13, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v4, s1
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v5, s1
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v6, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, v7, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v0, v12, v0
; GFX11-NEXT: v_or_b32_e32 v1, v8, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v2, v2, v4
; GFX11-NEXT: v_or_b32_e32 v3, v3, v5
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt) %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
ret i128 %result ret i128 %result
} }
define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, i128 %amt) { define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, i128 %amt) {
; GFX6-LABEL: v_fshr_i128_ssv: ; GFX6-LABEL: v_fshr_i128_ssv:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
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; GFX9-NEXT: v_or_b32_e32 v0, v8, v0 ; GFX9-NEXT: v_or_b32_e32 v0, v8, v0
; GFX9-NEXT: v_or_b32_e32 v1, v9, v1 ; GFX9-NEXT: v_or_b32_e32 v1, v9, v1
; GFX9-NEXT: v_or_b32_e32 v2, v7, v2 ; GFX9-NEXT: v_or_b32_e32 v2, v7, v2
; GFX9-NEXT: v_or_b32_e32 v3, v10, v3 ; GFX9-NEXT: v_or_b32_e32 v3, v10, v3
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: v_fshr_i128_ssv: ; GFX10-LABEL: v_fshr_i128_ssv:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_xor_b32_e32 v1, -1, v0 ; GFX10-NEXT: v_and_b32_e32 v5, 0x7f, v0
; GFX10-NEXT: v_and_b32_e32 v13, 0x7f, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX10-NEXT: s_mov_b32 s9, 0 ; GFX10-NEXT: s_mov_b32 s9, 0
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: s_lshr_b32 s8, s1, 31 ; GFX10-NEXT: s_lshr_b32 s8, s1, 31
; GFX10-NEXT: v_and_b32_e32 v12, 0x7f, v1 ; GFX10-NEXT: v_sub_nc_u32_e32 v1, 64, v5
; GFX10-NEXT: v_sub_nc_u32_e32 v8, 64, v13 ; GFX10-NEXT: v_and_b32_e32 v7, 0x7f, v0
; GFX10-NEXT: v_lshrrev_b64 v[3:4], v5, s[4:5]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX10-NEXT: s_or_b64 s[8:9], s[2:3], s[8:9] ; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX10-NEXT: v_subrev_nc_u32_e32 v14, 64, v13 ; GFX10-NEXT: v_lshlrev_b64 v[1:2], v1, s[6:7]
; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v12 ; GFX10-NEXT: v_sub_nc_u32_e32 v0, 64, v7
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v12, s[8:9] ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v7
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v12 ; GFX10-NEXT: v_or_b32_e32 v6, v3, v1
; GFX10-NEXT: v_lshrrev_b64 v[4:5], v13, s[4:5] ; GFX10-NEXT: v_or_b32_e32 v4, v4, v2
; GFX10-NEXT: v_lshlrev_b64 v[8:9], v8, s[6:7] ; GFX10-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, s[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[2:3], v7, s[2:3]
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v12 ; GFX10-NEXT: v_or_b32_e32 v8, v0, v2
; GFX10-NEXT: v_lshlrev_b64 v[10:11], v10, s[0:1] ; GFX10-NEXT: v_or_b32_e32 v9, v1, v3
; GFX10-NEXT: v_lshlrev_b64 v[6:7], v12, s[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v7, s[0:1]
; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 64, v13 ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v7
; GFX10-NEXT: v_or_b32_e32 v4, v4, v8 ; GFX10-NEXT: v_lshlrev_b64 v[2:3], v2, s[0:1]
; GFX10-NEXT: v_or_b32_e32 v2, v2, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v10, 0, v0, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v3, v3, v1 ; GFX10-NEXT: v_subrev_nc_u32_e32 v0, 64, v5
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v14, s[6:7] ; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 64, v5
; GFX10-NEXT: v_or_b32_e32 v5, v5, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 0, v7
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 0, v13 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v2, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v9, v3, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v3, vcc_lo ; GFX10-NEXT: v_lshrrev_b64 v[2:3], v0, s[6:7]
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v13, s[6:7] ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v12 ; GFX10-NEXT: v_lshrrev_b64 v[0:1], v5, s[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v5, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
; GFX10-NEXT: v_cndmask_b32_e32 v4, 0, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, v0, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s4, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v5, v8, s8, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, v10, s9, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, s5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s5, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, s2, s1
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v9, s3, s1
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0 ; GFX10-NEXT: v_or_b32_e32 v0, v10, v0
; GFX10-NEXT: v_or_b32_e32 v0, v6, v0
; GFX10-NEXT: v_or_b32_e32 v1, v4, v1 ; GFX10-NEXT: v_or_b32_e32 v1, v4, v1
; GFX10-NEXT: v_or_b32_e32 v2, v5, v2 ; GFX10-NEXT: v_or_b32_e32 v2, v2, v5
; GFX10-NEXT: v_or_b32_e32 v3, v7, v3 ; GFX10-NEXT: v_or_b32_e32 v3, v3, v6
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: v_fshr_i128_ssv: ; GFX11-LABEL: v_fshr_i128_ssv:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_xor_b32_e32 v1, -1, v0 ; GFX11-NEXT: v_xor_b32_e32 v1, -1, v0
; GFX11-NEXT: s_lshr_b32 s8, s1, 31 ; GFX11-NEXT: s_lshr_b32 s8, s1, 31
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 ; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX11-NEXT: s_mov_b32 s9, 0 ; GFX11-NEXT: s_mov_b32 s9, 0
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; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], s4 ; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], s4
; GFX10-NEXT: s_lshl_b64 s[4:5], s[0:1], s4 ; GFX10-NEXT: s_lshl_b64 s[4:5], s[0:1], s4
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], 0 ; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s13, 0 ; GFX10-NEXT: s_cmp_lg_u32 s13, 0
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
; GFX10-NEXT: s_sub_i32 s0, 64, s8 ; GFX10-NEXT: s_sub_i32 s2, 64, s8
; GFX10-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[6:7], s2, v[2:3]
; GFX10-NEXT: s_sub_i32 s0, s8, 64 ; GFX10-NEXT: s_sub_i32 s2, s8, 64
; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3] ; GFX10-NEXT: s_cselect_b32 s3, 1, 0
; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX10-NEXT: v_or_b32_e32 v6, v4, v6
; GFX10-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10-NEXT: s_cselect_b32 s6, 1, 0
; GFX10-NEXT: s_and_b32 s0, 1, s1 ; GFX10-NEXT: s_and_b32 s7, 1, s3
; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 ; GFX10-NEXT: v_or_b32_e32 v7, v5, v7
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_lshrrev_b64 v[4:5], s2, v[2:3]
; GFX10-NEXT: s_and_b32 s0, 1, s6 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s7
; GFX10-NEXT: s_and_b32 s1, 1, s1 ; GFX10-NEXT: s_and_b32 s2, 1, s6
; GFX10-NEXT: v_lshrrev_b64 v[2:3], s8, v[2:3] ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: s_and_b32 s2, 1, s3
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: v_lshrrev_b64 v[0:1], s8, v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v0, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v0, s4, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v1, s5, v1 ; GFX10-NEXT: v_or_b32_e32 v0, s4, v4
; GFX10-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX10-NEXT: v_or_b32_e32 v1, s5, v5
; GFX10-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX10-NEXT: v_or_b32_e32 v2, s0, v2
; GFX10-NEXT: v_or_b32_e32 v3, s1, v3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: v_fshr_i128_svs: ; GFX11-LABEL: v_fshr_i128_svs:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_movk_i32 s6, 0x7f ; GFX11-NEXT: s_movk_i32 s6, 0x7f
; GFX11-NEXT: s_mov_b32 s7, 0 ; GFX11-NEXT: s_mov_b32 s7, 0
; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX11-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX11-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
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; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: v_fshr_i128_vss: ; GFX10-LABEL: v_fshr_i128_vss:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 31, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 31, v1
; GFX10-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX10-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX10-NEXT: s_andn2_b64 s[8:9], s[6:7], s[4:5]
; GFX10-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX10-NEXT: s_and_b64 s[6:7], s[4:5], s[6:7]
; GFX10-NEXT: v_or_b32_e32 v2, v2, v4 ; GFX10-NEXT: v_or_b32_e32 v2, v2, v4
; GFX10-NEXT: s_sub_i32 s6, 64, s4 ; GFX10-NEXT: s_sub_i32 s9, 64, s8
; GFX10-NEXT: s_sub_i32 s5, s4, 64 ; GFX10-NEXT: s_sub_i32 s4, s8, 64
; GFX10-NEXT: s_cmp_lt_u32 s4, 64 ; GFX10-NEXT: v_lshrrev_b64 v[4:5], s9, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] ; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3]
; GFX10-NEXT: s_cselect_b32 s5, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_cselect_b32 s7, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s4, 0 ; GFX10-NEXT: s_and_b32 s5, 1, s5
; GFX10-NEXT: v_lshlrev_b64 v[8:9], s4, v[0:1] ; GFX10-NEXT: v_or_b32_e32 v6, v4, v6
; GFX10-NEXT: s_cselect_b32 s9, 1, 0 ; GFX10-NEXT: v_or_b32_e32 v7, v5, v7
; GFX10-NEXT: v_lshlrev_b64 v[4:5], s8, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[0:1], s4, v[0:1]
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
; GFX10-NEXT: s_and_b32 s4, 1, s7 ; GFX10-NEXT: s_and_b32 s4, 1, s7
; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] ; GFX10-NEXT: s_sub_i32 s10, s6, 64
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 ; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4
; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX10-NEXT: s_sub_i32 s7, 64, s6
; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX10-NEXT: s_and_b32 s4, 1, s9 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX10-NEXT: s_sub_i32 s10, s8, 64 ; GFX10-NEXT: s_cmp_lt_u32 s6, 64
; GFX10-NEXT: s_sub_i32 s6, 64, s8 ; GFX10-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc_lo
; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo
; GFX10-NEXT: s_cselect_b32 s11, 1, 0 ; GFX10-NEXT: s_cselect_b32 s11, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: s_cmp_eq_u32 s6, 0
; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v0, v2, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v1, v3, s4
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_cselect_b32 s12, 1, 0
; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s8 ; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s6
; GFX10-NEXT: s_lshl_b64 s[6:7], s[2:3], s6 ; GFX10-NEXT: s_lshl_b64 s[8:9], s[2:3], s7
; GFX10-NEXT: s_lshr_b64 s[8:9], s[2:3], s8 ; GFX10-NEXT: s_lshr_b64 s[6:7], s[2:3], s6
; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 ; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc_lo
; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3] ; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0
; GFX10-NEXT: v_or_b32_e32 v0, s0, v6 ; GFX10-NEXT: v_or_b32_e32 v0, s0, v4
; GFX10-NEXT: s_cselect_b64 s[2:3], s[8:9], 0 ; GFX10-NEXT: s_cselect_b64 s[2:3], s[6:7], 0
; GFX10-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX10-NEXT: v_or_b32_e32 v1, s1, v1
; GFX10-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX10-NEXT: v_or_b32_e32 v2, s2, v2
; GFX10-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX10-NEXT: v_or_b32_e32 v3, s3, v3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: v_fshr_i128_vss: ; GFX11-LABEL: v_fshr_i128_vss:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] ; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 31, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 31, v1
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; ;
; GFX10-LABEL: v_fshr_i128_65: ; GFX10-LABEL: v_fshr_i128_65:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v8, v2 ; GFX10-NEXT: v_mov_b32_e32 v8, v2
; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7] ; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7]
; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1] ; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1]
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 31, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v6, 31, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 31, v8 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 31, v8
; GFX10-NEXT: v_or_b32_e32 v1, v9, v5 ; GFX10-NEXT: v_or_b32_e32 v1, v6, v5
; GFX10-NEXT: v_or_b32_e32 v3, v0, v3 ; GFX10-NEXT: v_or_b32_e32 v3, v0, v3
; GFX10-NEXT: v_mov_b32_e32 v0, v4 ; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_i128_65: ; GFX11-LABEL: v_fshr_i128_65:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX9-NEXT: v_or_b32_e32 v6, v8, v10 ; GFX9-NEXT: v_or_b32_e32 v6, v8, v10
; GFX9-NEXT: v_or_b32_e32 v7, v9, v11 ; GFX9-NEXT: v_or_b32_e32 v7, v9, v11
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshr_v2i128: ; GFX10-LABEL: v_fshr_v2i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_xor_b32_e32 v17, -1, v16
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX10-NEXT: v_and_b32_e32 v26, 0x7f, v16
; GFX10-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
; GFX10-NEXT: v_and_b32_e32 v25, 0x7f, v17
; GFX10-NEXT: v_lshrrev_b32_e32 v17, 31, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v17, 31, v1
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX10-NEXT: v_subrev_nc_u32_e32 v27, 64, v26 ; GFX10-NEXT: v_and_b32_e32 v24, 0x7f, v16
; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v26 ; GFX10-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
; GFX10-NEXT: v_sub_nc_u32_e32 v18, 64, v25
; GFX10-NEXT: v_or_b32_e32 v2, v2, v17 ; GFX10-NEXT: v_or_b32_e32 v2, v2, v17
; GFX10-NEXT: v_subrev_nc_u32_e32 v19, 64, v25 ; GFX10-NEXT: v_xor_b32_e32 v17, -1, v16
; GFX10-NEXT: v_lshlrev_b64 v[23:24], v25, v[0:1] ; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v24
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v24
; GFX10-NEXT: v_lshrrev_b64 v[17:18], v18, v[0:1] ; GFX10-NEXT: v_and_b32_e32 v23, 0x7f, v17
; GFX10-NEXT: v_lshlrev_b64 v[21:22], v25, v[2:3] ; GFX10-NEXT: v_sub_nc_u32_e32 v17, 64, v23
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v19, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3]
; GFX10-NEXT: v_cndmask_b32_e32 v23, 0, v23, vcc_lo ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23
; GFX10-NEXT: v_cndmask_b32_e32 v24, 0, v24, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v23
; GFX10-NEXT: v_or_b32_e32 v22, v18, v22 ; GFX10-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
; GFX10-NEXT: v_sub_nc_u32_e32 v18, 64, v26
; GFX10-NEXT: v_or_b32_e32 v21, v17, v21 ; GFX10-NEXT: v_or_b32_e32 v21, v17, v21
; GFX10-NEXT: v_lshrrev_b64 v[16:17], v26, v[8:9] ; GFX10-NEXT: v_or_b32_e32 v22, v18, v22
; GFX10-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo ; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[10:11]
; GFX10-NEXT: v_lshlrev_b64 v[18:19], v18, v[10:11] ; GFX10-NEXT: v_lshrrev_b64 v[18:19], v24, v[8:9]
; GFX10-NEXT: v_cndmask_b32_e32 v21, v0, v21, vcc_lo ; GFX10-NEXT: v_or_b32_e32 v25, v18, v16
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v27, v[10:11] ; GFX10-NEXT: v_lshrrev_b32_e32 v16, 31, v5
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v25
; GFX10-NEXT: v_or_b32_e32 v16, v16, v18
; GFX10-NEXT: v_or_b32_e32 v17, v17, v19
; GFX10-NEXT: v_cndmask_b32_e32 v18, v21, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v26
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v16, s4
; GFX10-NEXT: v_xor_b32_e32 v16, -1, v20
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v17, s4
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v26, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX10-NEXT: v_and_b32_e32 v25, 0x7f, v16
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 31, v5
; GFX10-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5] ; GFX10-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo ; GFX10-NEXT: v_or_b32_e32 v26, v19, v17
; GFX10-NEXT: v_or_b32_e32 v0, v23, v0 ; GFX10-NEXT: v_or_b32_e32 v6, v6, v16
; GFX10-NEXT: v_sub_nc_u32_e32 v9, 64, v25 ; GFX10-NEXT: v_xor_b32_e32 v16, -1, v20
; GFX10-NEXT: v_or_b32_e32 v6, v6, v8 ; GFX10-NEXT: v_and_b32_e32 v20, 0x7f, v20
; GFX10-NEXT: v_and_b32_e32 v23, 0x7f, v20 ; GFX10-NEXT: v_and_b32_e32 v27, 0x7f, v16
; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 0, v20
; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v27
; GFX10-NEXT: v_lshlrev_b64 v[18:19], v27, v[6:7]
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v27
; GFX10-NEXT: v_lshrrev_b64 v[16:17], v16, v[4:5]
; GFX10-NEXT: v_or_b32_e32 v28, v16, v18
; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v20
; GFX10-NEXT: v_or_b32_e32 v29, v17, v19
; GFX10-NEXT: v_lshrrev_b64 v[18:19], v20, v[12:13]
; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[14:15]
; GFX10-NEXT: v_or_b32_e32 v18, v18, v16
; GFX10-NEXT: v_subrev_nc_u32_e32 v16, 64, v23
; GFX10-NEXT: v_or_b32_e32 v19, v19, v17
; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v23, v[0:1]
; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v21, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v2, s4
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v24
; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v3, s4
; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v24
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v25, s4
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v26, s4
; GFX10-NEXT: v_cndmask_b32_e64 v8, v2, v8, s5
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v27
; GFX10-NEXT: v_cndmask_b32_e64 v9, v3, v9, s5
; GFX10-NEXT: v_cmp_gt_u32_e64 s5, 64, v27
; GFX10-NEXT: v_or_b32_e32 v0, v0, v8
; GFX10-NEXT: v_lshlrev_b64 v[2:3], v2, v[4:5]
; GFX10-NEXT: v_lshlrev_b64 v[4:5], v27, v[4:5]
; GFX10-NEXT: v_or_b32_e32 v1, v1, v9
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v28, s5
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v29, s5
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v4, s5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, v5, s5
; GFX10-NEXT: v_cndmask_b32_e64 v21, v2, v6, s6
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v20
; GFX10-NEXT: v_cndmask_b32_e64 v22, v3, v7, s6
; GFX10-NEXT: v_cmp_gt_u32_e64 s6, 64, v20
; GFX10-NEXT: v_lshrrev_b64 v[6:7], v20, v[14:15]
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, v[14:15]
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v6, s6
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, v7, s6
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v18, s6
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v19, s6
; GFX10-NEXT: v_or_b32_e32 v6, v21, v6
; GFX10-NEXT: v_or_b32_e32 v7, v22, v7
; GFX10-NEXT: v_cndmask_b32_e64 v12, v2, v12, s7
; GFX10-NEXT: v_cndmask_b32_e64 v13, v3, v13, s7
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v24, v[10:11]
; GFX10-NEXT: v_or_b32_e32 v4, v4, v12
; GFX10-NEXT: v_or_b32_e32 v5, v5, v13
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s4
; GFX10-NEXT: v_cndmask_b32_e64 v26, 0, v3, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s4
; GFX10-NEXT: v_lshrrev_b64 v[8:9], v9, v[4:5] ; GFX10-NEXT: v_or_b32_e32 v2, v16, v2
; GFX10-NEXT: v_lshlrev_b64 v[10:11], v25, v[6:7] ; GFX10-NEXT: v_or_b32_e32 v3, v17, v3
; GFX10-NEXT: v_sub_nc_u32_e32 v20, 64, v23
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 64, v25
; GFX10-NEXT: v_or_b32_e32 v2, v18, v2
; GFX10-NEXT: v_lshlrev_b64 v[16:17], v25, v[4:5]
; GFX10-NEXT: v_lshrrev_b64 v[18:19], v23, v[12:13]
; GFX10-NEXT: v_or_b32_e32 v10, v8, v10
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 64, v23
; GFX10-NEXT: v_lshlrev_b64 v[20:21], v20, v[14:15]
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25
; GFX10-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5]
; GFX10-NEXT: v_or_b32_e32 v5, v9, v11
; GFX10-NEXT: v_lshrrev_b64 v[8:9], v8, v[14:15]
; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v23
; GFX10-NEXT: v_cndmask_b32_e32 v11, 0, v16, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v16, v18, v20
; GFX10-NEXT: v_or_b32_e32 v18, v19, v21
; GFX10-NEXT: v_cndmask_b32_e32 v10, v3, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc_lo
; GFX10-NEXT: v_lshrrev_b64 v[3:4], v23, v[14:15]
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v16, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v23
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v25
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v18, s4
; GFX10-NEXT: v_cndmask_b32_e32 v14, 0, v17, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v1, v24, v1
; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v6, s6
; GFX10-NEXT: v_cndmask_b32_e64 v7, v5, v7, s6
; GFX10-NEXT: v_cndmask_b32_e64 v5, v8, v12, s5
; GFX10-NEXT: v_cndmask_b32_e64 v8, v9, v13, s5
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v3, s4
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, v4, s4
; GFX10-NEXT: v_or_b32_e32 v3, v22, v26
; GFX10-NEXT: v_or_b32_e32 v4, v11, v5
; GFX10-NEXT: v_or_b32_e32 v5, v14, v8
; GFX10-NEXT: v_or_b32_e32 v6, v6, v9
; GFX10-NEXT: v_or_b32_e32 v7, v7, v10
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_v2i128: ; GFX11-LABEL: v_fshr_v2i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_xor_b32_e32 v17, -1, v16 ; GFX11-NEXT: v_xor_b32_e32 v17, -1, v16
; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] ; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX11-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7] ; GFX11-NEXT: v_lshrrev_b32_e32 v18, 31, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_and_b32_e32 v25, 0x7f, v17
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 31, v1
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25 ; GFX11-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_and_b32_e32 v23, 0x7f, v17
; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
; GFX11-NEXT: v_lshlrev_b64 v[23:24], v25, v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_dual_cndmask_b32 v23, 0, v23 :: v_dual_and_b32 v26, 0x7f, v16
; GFX11-NEXT: v_cndmask_b32_e32 v24, 0, v24, vcc_lo
; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v25
; GFX11-NEXT: v_lshlrev_b64 v[21:22], v25, v[2:3]
; GFX11-NEXT: v_subrev_nc_u32_e32 v19, 64, v25
; GFX11-NEXT: v_subrev_nc_u32_e32 v27, 64, v26
; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v26
; GFX11-NEXT: v_lshrrev_b64 v[17:18], v18, v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b64 v[0:1], v19, v[0:1] ; GFX11-NEXT: v_or_b32_e32 v2, v2, v18
; GFX11-NEXT: v_sub_nc_u32_e32 v17, 64, v23
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3]
; GFX11-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v22, v18, v22 ; GFX11-NEXT: v_or_b32_e32 v22, v18, v22
; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v26 ; GFX11-NEXT: v_and_b32_e32 v24, 0x7f, v16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v21, v17, v21 ; GFX11-NEXT: v_or_b32_e32 v21, v17, v21
; GFX11-NEXT: v_lshrrev_b64 v[16:17], v26, v[8:9] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo ; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v24
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_lshrrev_b64 v[18:19], v24, v[8:9]
; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[10:11] ; GFX11-NEXT: v_lshlrev_b64 v[16:17], v16, v[10:11]
; GFX11-NEXT: v_cndmask_b32_e32 v21, v0, v21, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_lshrrev_b64 v[0:1], v27, v[10:11] ; GFX11-NEXT: v_or_b32_e32 v25, v18, v16
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v25 ; GFX11-NEXT: v_lshrrev_b32_e32 v16, 31, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v16, v16, v18
; GFX11-NEXT: v_or_b32_e32 v17, v17, v19
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v16, s0
; GFX11-NEXT: v_xor_b32_e32 v16, -1, v20
; GFX11-NEXT: v_cndmask_b32_e32 v18, v21, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v17, s0
; GFX11-NEXT: v_cndmask_b32_e32 v22, v22, v3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v26
; GFX11-NEXT: v_and_b32_e32 v25, 0x7f, v16
; GFX11-NEXT: v_lshrrev_b64 v[2:3], v26, v[10:11]
; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
; GFX11-NEXT: v_lshrrev_b32_e32 v8, 31, v5
; GFX11-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5] ; GFX11-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
; GFX11-NEXT: v_sub_nc_u32_e32 v9, 64, v25 ; GFX11-NEXT: v_or_b32_e32 v26, v19, v17
; GFX11-NEXT: v_cndmask_b32_e64 v26, 0, v3, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_subrev_nc_u32_e32 v3, 64, v25 ; GFX11-NEXT: v_or_b32_e32 v6, v6, v16
; GFX11-NEXT: v_or_b32_e32 v6, v6, v8 ; GFX11-NEXT: v_xor_b32_e32 v16, -1, v20
; GFX11-NEXT: v_or_b32_e32 v0, v23, v0 ; GFX11-NEXT: v_and_b32_e32 v20, 0x7f, v20
; GFX11-NEXT: v_lshrrev_b64 v[8:9], v9, v[4:5] ; GFX11-NEXT: v_and_b32_e32 v27, 0x7f, v16
; GFX11-NEXT: v_lshlrev_b64 v[16:17], v25, v[4:5] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5] ; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v27
; GFX11-NEXT: v_lshlrev_b64 v[10:11], v25, v[6:7] ; GFX11-NEXT: v_lshlrev_b64 v[18:19], v27, v[6:7]
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25 ; GFX11-NEXT: v_lshrrev_b64 v[16:17], v16, v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v28, v16, v18
; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v20
; GFX11-NEXT: v_or_b32_e32 v29, v17, v19
; GFX11-NEXT: v_lshrrev_b64 v[18:19], v20, v[12:13]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b64 v[16:17], v16, v[14:15]
; GFX11-NEXT: v_or_b32_e32 v18, v18, v16
; GFX11-NEXT: v_subrev_nc_u32_e32 v16, 64, v23
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v19, v19, v17
; GFX11-NEXT: v_lshlrev_b64 v[16:17], v16, v[0:1]
; GFX11-NEXT: v_lshlrev_b64 v[0:1], v23, v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v16, v16, v21, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v23
; GFX11-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 0, v24
; GFX11-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v27
; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v2, s0
; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 64, v24
; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v3, s0
; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v24
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v20
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b64 v[2:3], v2, v[10:11]
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v25, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v26, s0
; GFX11-NEXT: v_cndmask_b32_e64 v8, v2, v8, s1
; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 64, v27
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v9, v3, v9, s1
; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v27
; GFX11-NEXT: v_or_b32_e32 v0, v0, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_lshlrev_b64 v[2:3], v2, v[4:5]
; GFX11-NEXT: v_lshlrev_b64 v[4:5], v27, v[4:5]
; GFX11-NEXT: v_or_b32_e32 v1, v1, v9
; GFX11-NEXT: v_lshrrev_b64 v[8:9], v20, v[14:15]
; GFX11-NEXT: v_cndmask_b32_e64 v22, v2, v28, s1
; GFX11-NEXT: v_cndmask_b32_e64 v23, v3, v29, s1
; GFX11-NEXT: v_lshrrev_b64 v[2:3], v24, v[10:11]
; GFX11-NEXT: v_cndmask_b32_e64 v21, 0, v4, s1
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, v5, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, v3, s0
; GFX11-NEXT: v_subrev_nc_u32_e32 v3, 64, v20
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v25 ; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v20
; GFX11-NEXT: v_or_b32_e32 v1, v24, v1 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v10, v8, v10 ; GFX11-NEXT: v_lshrrev_b64 v[3:4], v3, v[14:15]
; GFX11-NEXT: v_and_b32_e32 v23, 0x7f, v20 ; GFX11-NEXT: v_or_b32_e32 v2, v16, v2
; GFX11-NEXT: v_or_b32_e32 v2, v18, v2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v5, v9, v11 ; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v8, s0
; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v9, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v18, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v19, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_dual_cndmask_b32 v11, 0, v16 :: v_dual_cndmask_b32 v10, v3, v10 ; GFX11-NEXT: v_or_b32_e32 v6, v6, v8
; GFX11-NEXT: v_sub_nc_u32_e32 v20, 64, v23 ; GFX11-NEXT: v_or_b32_e32 v7, v7, v9
; GFX11-NEXT: v_subrev_nc_u32_e32 v8, 64, v23
; GFX11-NEXT: v_lshrrev_b64 v[18:19], v23, v[12:13]
; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 64, v23
; GFX11-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc_lo
; GFX11-NEXT: v_lshlrev_b64 v[20:21], v20, v[14:15]
; GFX11-NEXT: v_lshrrev_b64 v[8:9], v8, v[14:15]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], v23, v[14:15]
; GFX11-NEXT: v_cndmask_b32_e32 v14, 0, v17, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 0, v23
; GFX11-NEXT: v_cndmask_b32_e64 v6, v10, v6, s2
; GFX11-NEXT: v_or_b32_e32 v16, v18, v20
; GFX11-NEXT: v_or_b32_e32 v18, v19, v21
; GFX11-NEXT: v_cndmask_b32_e64 v7, v5, v7, s2
; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, v4, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v16, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v11, v3, v12, s2
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v18, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v12, v4, v13, s2
; GFX11-NEXT: v_or_b32_e32 v3, v17, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v7, v7, v10 ; GFX11-NEXT: v_or_b32_e32 v4, v21, v11
; GFX11-NEXT: v_cndmask_b32_e64 v5, v8, v12, s1 ; GFX11-NEXT: v_or_b32_e32 v5, v5, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v8, v9, v13, s1
; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v3, s0
; GFX11-NEXT: v_or_b32_e32 v3, v22, v26
; GFX11-NEXT: v_or_b32_e32 v4, v11, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v5, v14, v8
; GFX11-NEXT: v_or_b32_e32 v6, v6, v9
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) %result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
ret <2 x i128> %result ret <2 x i128> %result
} }
declare i7 @llvm.fshr.i7(i7, i7, i7) #0 declare i7 @llvm.fshr.i7(i7, i7, i7) #0
declare i8 @llvm.fshr.i8(i8, i8, i8) #0 declare i8 @llvm.fshr.i8(i8, i8, i8) #0
declare <2 x i8> @llvm.fshr.v2i8(<2 x i8>, <2 x i8>, <2 x i8>) #0 declare <2 x i8> @llvm.fshr.v2i8(<2 x i8>, <2 x i8>, <2 x i8>) #0
Show All 29 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll

Show First 20 Lines • Show All 505 Lines • ▼ Show 20 Lines
; GFX7-NEXT: v_mov_b32_e32 v0, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
; GFX7-NEXT: v_mov_b32_e32 v1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
; GFX7-NEXT: v_or_b32_e32 v2, v3, v2 ; GFX7-NEXT: v_or_b32_e32 v2, v3, v2
; GFX7-NEXT: flat_store_dword v[0:1], v2 ; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v2i16_s_v: ; GFX10-LABEL: insertelement_v_v2i16_s_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dword v3, v[0:1], off ; GFX10-NEXT: global_load_dword v0, v[0:1], off
; GFX10-NEXT: v_and_b32_e32 v0, 1, v2 ; GFX10-NEXT: v_and_b32_e32 v1, 1, v2
; GFX10-NEXT: s_and_b32 s0, s2, 0xffff ; GFX10-NEXT: s_and_b32 s0, s2, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX10-NEXT: v_lshlrev_b32_e64 v1, v0, 0xffff ; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e64 v2, v0, s0 ; GFX10-NEXT: v_lshlrev_b32_e64 v1, v1, s0
; GFX10-NEXT: v_xor_b32_e32 v4, -1, v1 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_and_or_b32 v2, v0, v2, v1
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, v2
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v2i16_s_v: ; GFX11-LABEL: insertelement_v_v2i16_s_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b32 v3, v[0:1], off ; GFX11-NEXT: global_load_b32 v3, v[0:1], off
; GFX11-NEXT: v_and_b32_e32 v0, 1, v2 ; GFX11-NEXT: v_and_b32_e32 v0, 1, v2
; GFX11-NEXT: s_and_b32 s0, s2, 0xffff ; GFX11-NEXT: s_and_b32 s0, s2, 0xffff
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; GFX7-NEXT: v_mov_b32_e32 v0, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
; GFX7-NEXT: v_mov_b32_e32 v1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
; GFX7-NEXT: v_or_b32_e32 v2, v3, v2 ; GFX7-NEXT: v_or_b32_e32 v2, v3, v2
; GFX7-NEXT: flat_store_dword v[0:1], v2 ; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v2i16_v_v: ; GFX10-LABEL: insertelement_v_v2i16_v_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dword v4, v[0:1], off ; GFX10-NEXT: global_load_dword v0, v[0:1], off
; GFX10-NEXT: v_and_b32_e32 v0, 1, v3 ; GFX10-NEXT: v_and_b32_e32 v1, 1, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX10-NEXT: v_lshlrev_b32_e64 v1, v0, 0xffff ; GFX10-NEXT: v_lshlrev_b32_e64 v3, v1, 0xffff
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: v_xor_b32_e32 v3, -1, v1 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v3
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_and_or_b32 v2, v0, v2, v1
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_and_or_b32 v2, v4, v3, v2
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v2i16_v_v: ; GFX11-LABEL: insertelement_v_v2i16_v_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b32 v4, v[0:1], off ; GFX11-NEXT: global_load_b32 v4, v[0:1], off
; GFX11-NEXT: v_and_b32_e32 v0, 1, v3 ; GFX11-NEXT: v_and_b32_e32 v0, 1, v3
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v2 ; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v2
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; GFX10-NEXT: s_lshl_b32 s1, s1, 4 ; GFX10-NEXT: s_lshl_b32 s1, s1, 4
; GFX10-NEXT: s_and_b32 s2, s2, 0xffff ; GFX10-NEXT: s_and_b32 s2, s2, 0xffff
; GFX10-NEXT: s_lshl_b32 s3, 0xffff, s1 ; GFX10-NEXT: s_lshl_b32 s3, 0xffff, s1
; GFX10-NEXT: s_lshl_b32 s1, s2, s1 ; GFX10-NEXT: s_lshl_b32 s1, s2, s1
; GFX10-NEXT: s_not_b32 s2, s3 ; GFX10-NEXT: s_not_b32 s2, s3
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s0, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s0, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc_lo
; GFX10-NEXT: v_and_or_b32 v4, v2, s2, s1 ; GFX10-NEXT: v_and_or_b32 v2, v2, s2, s1
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v4i16_s_s: ; GFX11-LABEL: insertelement_v_v4i16_s_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: s_lshr_b32 s0, s3, 1 ; GFX11-NEXT: s_lshr_b32 s0, s3, 1
; GFX11-NEXT: s_and_b32 s1, s3, 1 ; GFX11-NEXT: s_and_b32 s1, s3, 1
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; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v4i16_v_s: ; GFX10-LABEL: insertelement_s_v4i16_v_s:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX10-NEXT: s_lshr_b32 s2, s4, 1 ; GFX10-NEXT: s_lshr_b32 s2, s4, 1
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v0 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX10-NEXT: s_cmp_eq_u32 s2, 1 ; GFX10-NEXT: s_cmp_eq_u32 s2, 1
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_cselect_b32 s3, s1, s0 ; GFX10-NEXT: s_cselect_b32 s3, s1, s0
; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: s_and_b32 s4, s4, 1
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: s_lshl_b32 s4, s4, 4 ; GFX10-NEXT: s_lshl_b32 s4, s4, 4
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_lshl_b32 s5, 0xffff, s4 ; GFX10-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s2, 0
; GFX10-NEXT: s_andn2_b32 s3, s3, s5 ; GFX10-NEXT: s_andn2_b32 s3, s3, s5
; GFX10-NEXT: v_lshl_or_b32 v4, v2, s4, s3 ; GFX10-NEXT: v_lshl_or_b32 v2, v2, s4, s3
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v4i16_v_s: ; GFX11-LABEL: insertelement_s_v4i16_v_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
; GFX11-NEXT: s_lshr_b32 s2, s4, 1 ; GFX11-NEXT: s_lshr_b32 s2, s4, 1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v0 ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v0
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; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX7-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX7-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v4i16_s_v: ; GFX10-LABEL: insertelement_s_v4i16_s_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX10-NEXT: v_and_b32_e32 v1, 1, v0 ; GFX10-NEXT: v_and_b32_e32 v1, 1, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 1, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 1, v0
; GFX10-NEXT: s_and_b32 s2, s4, 0xffff ; GFX10-NEXT: s_and_b32 s2, s4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xffff ; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e64 v3, v1, s2 ; GFX10-NEXT: v_lshlrev_b32_e64 v1, v1, s2
; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s1 ; GFX10-NEXT: v_mov_b32_e32 v0, s1
; GFX10-NEXT: v_cndmask_b32_e32 v5, s0, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX10-NEXT: v_and_or_b32 v2, v0, v2, v1
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v3
; GFX10-NEXT: v_and_or_b32 v5, v5, v2, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v4i16_s_v: ; GFX11-LABEL: insertelement_s_v4i16_s_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
; GFX11-NEXT: v_and_b32_e32 v1, 1, v0 ; GFX11-NEXT: v_and_b32_e32 v1, 1, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 1, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 1, v0
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX7-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX7-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v4i16_v_v: ; GFX10-LABEL: insertelement_s_v4i16_v_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX10-NEXT: v_and_b32_e32 v2, 1, v1 ; GFX10-NEXT: v_and_b32_e32 v2, 1, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 1, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 1, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 4, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 4, v2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GFX10-NEXT: v_lshlrev_b32_e64 v3, v2, 0xffff ; GFX10-NEXT: v_lshlrev_b32_e64 v1, v2, 0xffff
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: v_xor_b32_e32 v3, -1, v3 ; GFX10-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_cndmask_b32_e32 v5, s0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, s0, v2, vcc_lo
; GFX10-NEXT: v_and_or_b32 v2, v2, v1, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v3
; GFX10-NEXT: v_and_or_b32 v5, v5, v3, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v4i16_v_v: ; GFX11-LABEL: insertelement_s_v4i16_v_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
; GFX11-NEXT: v_and_b32_e32 v2, 1, v1 ; GFX11-NEXT: v_and_b32_e32 v2, 1, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 1, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 1, v1
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; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX7-NEXT: flat_store_dwordx2 v[3:4], v[0:1] ; GFX7-NEXT: flat_store_dwordx2 v[3:4], v[0:1]
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v4i16_s_v: ; GFX10-LABEL: insertelement_v_v4i16_s_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: v_and_b32_e32 v3, 1, v2 ; GFX10-NEXT: v_and_b32_e32 v3, 1, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 1, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v2
; GFX10-NEXT: s_and_b32 s0, s2, 0xffff ; GFX10-NEXT: s_and_b32 s0, s2, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 4, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 4, v3
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX10-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff ; GFX10-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e64 v2, v3, s0 ; GFX10-NEXT: v_lshlrev_b32_e64 v3, v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v5 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v2
; GFX10-NEXT: v_xor_b32_e32 v3, -1, v4 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
; GFX10-NEXT: v_and_or_b32 v4, v4, v3, v2 ; GFX10-NEXT: v_and_or_b32 v3, v5, v4, v3
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v4i16_s_v: ; GFX11-LABEL: insertelement_v_v4i16_s_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 1, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 1, v2
; GFX11-NEXT: s_and_b32 s0, s2, 0xffff ; GFX11-NEXT: s_and_b32 s0, s2, 0xffff
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; GFX10-NEXT: s_and_b32 s0, s2, 1 ; GFX10-NEXT: s_and_b32 s0, s2, 1
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s1, 1 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s1, 1
; GFX10-NEXT: s_lshl_b32 s0, s0, 4 ; GFX10-NEXT: s_lshl_b32 s0, s0, 4
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_lshl_b32 s0, 0xffff, s0 ; GFX10-NEXT: s_lshl_b32 s0, 0xffff, s0
; GFX10-NEXT: s_not_b32 s0, s0 ; GFX10-NEXT: s_not_b32 s0, s0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc_lo
; GFX10-NEXT: v_and_or_b32 v4, v3, s0, v2 ; GFX10-NEXT: v_and_or_b32 v2, v3, s0, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s1, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s1, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v4i16_v_s: ; GFX11-LABEL: insertelement_v_v4i16_v_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: s_lshr_b32 s1, s2, 1 ; GFX11-NEXT: s_lshr_b32 s1, s2, 1
; GFX11-NEXT: s_and_b32 s0, s2, 1 ; GFX11-NEXT: s_and_b32 s0, s2, 1
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; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX7-NEXT: flat_store_dwordx2 v[4:5], v[0:1] ; GFX7-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v4i16_v_v: ; GFX10-LABEL: insertelement_v_v4i16_v_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: v_and_b32_e32 v4, 1, v3 ; GFX10-NEXT: v_and_b32_e32 v4, 1, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 1, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 1, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 4, v4 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 4, v4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v3
; GFX10-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: v_xor_b32_e32 v3, -1, v5 ; GFX10-NEXT: v_lshlrev_b32_e64 v4, v4, 0xffff
; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
; GFX10-NEXT: v_and_or_b32 v4, v4, v3, v2 ; GFX10-NEXT: v_and_or_b32 v2, v5, v4, v2
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v4i16_v_v: ; GFX11-LABEL: insertelement_v_v4i16_v_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: v_and_b32_e32 v4, 1, v3 ; GFX11-NEXT: v_and_b32_e32 v4, 1, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 1, v3 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 1, v3
▲ Show 20 Lines • Show All 309 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_and_b32 s2, s2, 0xffff ; GFX10-NEXT: s_and_b32 s2, s2, 0xffff
; GFX10-NEXT: s_lshl_b32 s5, 0xffff, s3 ; GFX10-NEXT: s_lshl_b32 s5, 0xffff, s3
; GFX10-NEXT: s_lshl_b32 s2, s2, s3 ; GFX10-NEXT: s_lshl_b32 s2, s2, s3
; GFX10-NEXT: s_not_b32 s3, s5 ; GFX10-NEXT: s_not_b32 s3, s5
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v2, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v3, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v3, s1
; GFX10-NEXT: v_and_or_b32 v6, v4, s3, s2 ; GFX10-NEXT: v_and_or_b32 v4, v4, s3, s2
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s4, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s4, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s1
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v6, s1
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v8i16_s_s: ; GFX11-LABEL: insertelement_v_v8i16_s_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
; GFX11-NEXT: s_lshr_b32 s4, s3, 1 ; GFX11-NEXT: s_lshr_b32 s4, s3, 1
; GFX11-NEXT: s_and_b32 s1, s3, 1 ; GFX11-NEXT: s_and_b32 s1, s3, 1
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; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v8i16_v_s: ; GFX10-LABEL: insertelement_s_v8i16_v_s:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
; GFX10-NEXT: s_lshr_b32 s5, s4, 1 ; GFX10-NEXT: s_lshr_b32 s5, s4, 1
; GFX10-NEXT: v_and_b32_e32 v4, 0xffff, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-NEXT: s_cmp_eq_u32 s5, 1 ; GFX10-NEXT: s_cmp_eq_u32 s5, 1
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_cselect_b32 s6, s1, s0 ; GFX10-NEXT: s_cselect_b32 s6, s1, s0
; GFX10-NEXT: s_cmp_eq_u32 s5, 2 ; GFX10-NEXT: s_cmp_eq_u32 s5, 2
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: s_cselect_b32 s6, s2, s6 ; GFX10-NEXT: s_cselect_b32 s6, s2, s6
; GFX10-NEXT: s_cmp_eq_u32 s5, 3 ; GFX10-NEXT: s_cmp_eq_u32 s5, 3
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_cselect_b32 s6, s3, s6 ; GFX10-NEXT: s_cselect_b32 s6, s3, s6
; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: s_and_b32 s4, s4, 1
; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: s_lshl_b32 s4, s4, 4 ; GFX10-NEXT: s_lshl_b32 s4, s4, 4
; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: s_lshl_b32 s7, 0xffff, s4 ; GFX10-NEXT: s_lshl_b32 s7, 0xffff, s4
; GFX10-NEXT: s_andn2_b32 s6, s6, s7 ; GFX10-NEXT: s_andn2_b32 s6, s6, s7
; GFX10-NEXT: v_lshl_or_b32 v6, v4, s4, s6 ; GFX10-NEXT: v_lshl_or_b32 v4, v0, s4, s6
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v5, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 1 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s5, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 2 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 3 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 3
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v8i16_v_s: ; GFX11-LABEL: insertelement_s_v8i16_v_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0
; GFX11-NEXT: s_lshr_b32 s5, s4, 1 ; GFX11-NEXT: s_lshr_b32 s5, s4, 1
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v0 ; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v0
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; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v8i16_s_v: ; GFX10-LABEL: insertelement_s_v8i16_s_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 1, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 1, v0
; GFX10-NEXT: v_and_b32_e32 v1, 1, v0 ; GFX10-NEXT: v_and_b32_e32 v1, 1, v0
; GFX10-NEXT: s_and_b32 s1, s4, 0xffff ; GFX10-NEXT: s_and_b32 s1, s4, 0xffff
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v4
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v4
; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xffff ; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e64 v4, v1, s1 ; GFX10-NEXT: v_lshlrev_b32_e64 v1, v1, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v4
; GFX10-NEXT: v_xor_b32_e32 v5, -1, v2 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s9 ; GFX10-NEXT: v_mov_b32_e32 v0, s9
; GFX10-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s10, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v0, s11, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s11, s1
; GFX10-NEXT: v_and_or_b32 v5, v0, v2, v1
; GFX10-NEXT: v_mov_b32_e32 v0, s8 ; GFX10-NEXT: v_mov_b32_e32 v0, s8
; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: v_mov_b32_e32 v2, s10 ; GFX10-NEXT: v_mov_b32_e32 v2, s10
; GFX10-NEXT: v_mov_b32_e32 v3, s11 ; GFX10-NEXT: v_mov_b32_e32 v3, s11
; GFX10-NEXT: v_and_or_b32 v7, v7, v5, v4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v7, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v8i16_s_v: ; GFX11-LABEL: insertelement_s_v8i16_s_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[8:11], s[2:3], 0x0 ; GFX11-NEXT: s_load_b128 s[8:11], s[2:3], 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 1, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 1, v0
; GFX11-NEXT: v_and_b32_e32 v1, 1, v0 ; GFX11-NEXT: v_and_b32_e32 v1, 1, v0
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; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v8i16_v_v: ; GFX10-LABEL: insertelement_s_v8i16_v_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 1, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 1, v1
; GFX10-NEXT: v_and_b32_e32 v2, 1, v1 ; GFX10-NEXT: v_and_b32_e32 v2, 1, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 4, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 4, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v4
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v4
; GFX10-NEXT: s_mov_b32 null, 0 ; GFX10-NEXT: s_mov_b32 null, 0
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v4
; GFX10-NEXT: v_lshlrev_b32_e64 v3, v2, 0xffff ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: v_lshlrev_b32_sdwa v4, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-NEXT: v_lshlrev_b32_e64 v2, v2, 0xffff
; GFX10-NEXT: v_xor_b32_e32 v5, -1, v3 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: v_cndmask_b32_e32 v1, s4, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, s4, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v1, s7, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s7, s1
; GFX10-NEXT: v_and_or_b32 v5, v1, v2, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: v_mov_b32_e32 v2, s6 ; GFX10-NEXT: v_mov_b32_e32 v2, s6
; GFX10-NEXT: v_mov_b32_e32 v3, s7 ; GFX10-NEXT: v_mov_b32_e32 v3, s7
; GFX10-NEXT: v_and_or_b32 v7, v7, v5, v4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v7, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v8i16_v_v: ; GFX11-LABEL: insertelement_s_v8i16_v_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0 ; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 1, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 1, v1
; GFX11-NEXT: v_and_b32_e32 v2, 1, v1 ; GFX11-NEXT: v_and_b32_e32 v2, 1, v1
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; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v2, v5, v7, s[0:1] ; GFX7-NEXT: v_cndmask_b32_e64 v2, v5, v7, s[0:1]
; GFX7-NEXT: v_cndmask_b32_e64 v3, v6, v7, s[2:3] ; GFX7-NEXT: v_cndmask_b32_e64 v3, v6, v7, s[2:3]
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v8i16_s_v: ; GFX10-LABEL: insertelement_v_v8i16_s_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off ; GFX10-NEXT: v_and_b32_e32 v3, 1, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 1, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 1, v2
; GFX10-NEXT: v_and_b32_e32 v0, 1, v2
; GFX10-NEXT: s_and_b32 s1, s2, 0xffff ; GFX10-NEXT: s_and_b32 s1, s2, 0xffff
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v5, 4, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v4
; GFX10-NEXT: v_lshlrev_b32_e64 v7, v0, 0xffff ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v4
; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, s1 ; GFX10-NEXT: v_lshlrev_b32_e64 v7, v5, 0xffff
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v1 ; GFX10-NEXT: v_lshlrev_b32_e64 v5, v5, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v4
; GFX10-NEXT: v_xor_b32_e32 v7, -1, v7 ; GFX10-NEXT: v_xor_b32_e32 v7, -1, v7
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v3, s1
; GFX10-NEXT: v_and_or_b32 v5, v6, v7, v5
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
; GFX10-NEXT: v_and_or_b32 v9, v2, v7, v0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v7, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, v9, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v9, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v6, v9, s1
; GFX10-NEXT: global_store_dwordx4 v[7:8], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v8i16_s_v: ; GFX11-LABEL: insertelement_v_v8i16_s_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 1, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 1, v2
; GFX11-NEXT: v_and_b32_e32 v0, 1, v2 ; GFX11-NEXT: v_and_b32_e32 v0, 1, v2
; GFX11-NEXT: s_and_b32 s1, s2, 0xffff ; GFX11-NEXT: s_and_b32 s1, s2, 0xffff
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; GFX10-NEXT: s_lshr_b32 s3, s2, 1 ; GFX10-NEXT: s_lshr_b32 s3, s2, 1
; GFX10-NEXT: s_and_b32 s1, s2, 1 ; GFX10-NEXT: s_and_b32 s1, s2, 1
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s3, 1 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s3, 1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, 2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, 2
; GFX10-NEXT: s_lshl_b32 s2, s1, 4 ; GFX10-NEXT: s_lshl_b32 s2, s1, 4
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s3, 3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s3, 3
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_lshl_b32 s2, 0xffff, s2 ; GFX10-NEXT: s_lshl_b32 s2, 0xffff, s2
; GFX10-NEXT: v_mov_b32_e32 v7, 0
; GFX10-NEXT: s_not_b32 s2, s2 ; GFX10-NEXT: s_not_b32 s2, s2
; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s1
; GFX10-NEXT: v_and_or_b32 v9, v0, s2, v1 ; GFX10-NEXT: v_and_or_b32 v7, v0, s2, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s3, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s3, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, v9, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v7, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v9, s0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v6, v9, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, v7, s2
; GFX10-NEXT: global_store_dwordx4 v[7:8], v[0:3], off ; GFX10-NEXT: v_cndmask_b32_e64 v3, v6, v7, s1
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v8i16_v_s: ; GFX11-LABEL: insertelement_v_v8i16_v_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
; GFX11-NEXT: s_lshr_b32 s3, s2, 1 ; GFX11-NEXT: s_lshr_b32 s3, s2, 1
; GFX11-NEXT: s_and_b32 s1, s2, 1 ; GFX11-NEXT: s_and_b32 s1, s2, 1
; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s3, 1 ; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s3, 1
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; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, v3, s[0:1] ; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, v3, s[0:1]
; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[2:3] ; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[2:3]
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v8i16_v_v: ; GFX10-LABEL: insertelement_v_v8i16_v_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off ; GFX10-NEXT: v_and_b32_e32 v4, 1, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 1, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v5, 1, v3
; GFX10-NEXT: v_and_b32_e32 v0, 1, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 4, v4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v5
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v5
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v5
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v1 ; GFX10-NEXT: v_lshlrev_b32_sdwa v6, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: v_lshlrev_b32_e64 v8, v0, 0xffff ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-NEXT: v_lshlrev_b32_e64 v4, v4, 0xffff
; GFX10-NEXT: v_xor_b32_e32 v2, -1, v8 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: v_mov_b32_e32 v9, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v7, v0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v3, s1
; GFX10-NEXT: v_and_or_b32 v3, v3, v2, v0 ; GFX10-NEXT: v_and_or_b32 v4, v7, v4, v6
; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v3, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v3, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s1
; GFX10-NEXT: global_store_dwordx4 v[8:9], v[0:3], off ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v8i16_v_v: ; GFX11-LABEL: insertelement_v_v8i16_v_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off ; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 1, v3 ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 1, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
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; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
; GFX10-NEXT: s_and_b32 s0, s5, 1 ; GFX10-NEXT: s_and_b32 s0, s5, 1
; GFX10-NEXT: s_lshr_b32 m0, s5, 1 ; GFX10-NEXT: s_lshr_b32 m0, s5, 1
; GFX10-NEXT: s_lshl_b32 s0, s0, 4 ; GFX10-NEXT: s_lshl_b32 s0, s0, 4
; GFX10-NEXT: s_and_b32 s1, s4, 0xffff ; GFX10-NEXT: s_and_b32 s1, s4, 0xffff
; GFX10-NEXT: s_lshl_b32 s2, 0xffff, s0 ; GFX10-NEXT: s_lshl_b32 s2, 0xffff, s0
; GFX10-NEXT: s_lshl_b32 s0, s1, s0 ; GFX10-NEXT: s_lshl_b32 s0, s1, s0
; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v9, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_mov_b32_e32 v10, 16
; GFX10-NEXT: v_mov_b32_e32 v11, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_movrels_b32 s3, s8 ; GFX10-NEXT: s_movrels_b32 s3, s8
; GFX10-NEXT: s_andn2_b32 s1, s3, s2 ; GFX10-NEXT: s_andn2_b32 s1, s3, s2
; GFX10-NEXT: s_or_b32 s0, s1, s0 ; GFX10-NEXT: s_or_b32 s0, s1, s0
; GFX10-NEXT: s_movreld_b32 s8, s0 ; GFX10-NEXT: s_movreld_b32 s8, s0
; GFX10-NEXT: v_mov_b32_e32 v0, s8 ; GFX10-NEXT: v_mov_b32_e32 v0, s8
; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: v_mov_b32_e32 v2, s10 ; GFX10-NEXT: v_mov_b32_e32 v2, s10
; GFX10-NEXT: v_mov_b32_e32 v3, s11 ; GFX10-NEXT: v_mov_b32_e32 v3, s11
; GFX10-NEXT: v_mov_b32_e32 v4, s12 ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: v_mov_b32_e32 v5, s13 ; GFX10-NEXT: v_mov_b32_e32 v4, 16
; GFX10-NEXT: v_mov_b32_e32 v6, s14 ; GFX10-NEXT: v_mov_b32_e32 v0, s12
; GFX10-NEXT: v_mov_b32_e32 v7, s15 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: global_store_dwordx4 v[8:9], v[0:3], off ; GFX10-NEXT: v_mov_b32_e32 v1, s13
; GFX10-NEXT: global_store_dwordx4 v[10:11], v[4:7], off ; GFX10-NEXT: v_mov_b32_e32 v2, s14
; GFX10-NEXT: v_mov_b32_e32 v3, s15
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v16i16_s_s: ; GFX11-LABEL: insertelement_s_v16i16_s_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0 ; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0
; GFX11-NEXT: s_and_b32 s0, s5, 1 ; GFX11-NEXT: s_and_b32 s0, s5, 1
; GFX11-NEXT: s_lshr_b32 m0, s5, 1 ; GFX11-NEXT: s_lshr_b32 m0, s5, 1
; GFX11-NEXT: s_lshl_b32 s0, s0, 4 ; GFX11-NEXT: s_lshl_b32 s0, s0, 4
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; GFX10-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:16 ; GFX10-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:16
; GFX10-NEXT: s_and_b32 s0, s3, 1 ; GFX10-NEXT: s_and_b32 s0, s3, 1
; GFX10-NEXT: s_lshr_b32 m0, s3, 1 ; GFX10-NEXT: s_lshr_b32 m0, s3, 1
; GFX10-NEXT: s_lshl_b32 s0, s0, 4 ; GFX10-NEXT: s_lshl_b32 s0, s0, 4
; GFX10-NEXT: s_and_b32 s1, s2, 0xffff ; GFX10-NEXT: s_and_b32 s1, s2, 0xffff
; GFX10-NEXT: s_lshl_b32 s2, 0xffff, s0 ; GFX10-NEXT: s_lshl_b32 s2, 0xffff, s0
; GFX10-NEXT: s_lshl_b32 s0, s1, s0 ; GFX10-NEXT: s_lshl_b32 s0, s1, s0
; GFX10-NEXT: s_not_b32 s1, s2 ; GFX10-NEXT: s_not_b32 s1, s2
; GFX10-NEXT: v_mov_b32_e32 v10, 16
; GFX10-NEXT: v_mov_b32_e32 v11, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_movrels_b32_e32 v0, v2 ; GFX10-NEXT: v_movrels_b32_e32 v0, v2
; GFX10-NEXT: v_and_or_b32 v12, v0, s1, s0 ; GFX10-NEXT: v_and_or_b32 v0, v0, s1, s0
; GFX10-NEXT: v_movreld_b32_e32 v2, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_movreld_b32_e32 v2, v12
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[2:5], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX10-NEXT: global_store_dwordx4 v[10:11], v[6:9], off ; GFX10-NEXT: v_mov_b32_e32 v0, 16
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[6:9], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v16i16_s_s: ; GFX11-LABEL: insertelement_v_v16i16_s_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_b128 v[2:5], v[0:1], off ; GFX11-NEXT: global_load_b128 v[2:5], v[0:1], off
; GFX11-NEXT: global_load_b128 v[6:9], v[0:1], off offset:16 ; GFX11-NEXT: global_load_b128 v[6:9], v[0:1], off offset:16
; GFX11-NEXT: s_and_b32 s0, s3, 1 ; GFX11-NEXT: s_and_b32 s0, s3, 1
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; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v16i16_v_s: ; GFX10-LABEL: insertelement_s_v16i16_v_s:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
; GFX10-NEXT: s_and_b32 s0, s4, 1 ; GFX10-NEXT: s_and_b32 s0, s4, 1
; GFX10-NEXT: s_lshr_b32 m0, s4, 1 ; GFX10-NEXT: s_lshr_b32 m0, s4, 1
; GFX10-NEXT: s_lshl_b32 s0, s0, 4 ; GFX10-NEXT: s_lshl_b32 s0, s0, 4
; GFX10-NEXT: v_and_b32_e32 v8, 0xffff, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-NEXT: s_lshl_b32 s1, 0xffff, s0 ; GFX10-NEXT: s_lshl_b32 s1, 0xffff, s0
; GFX10-NEXT: v_mov_b32_e32 v10, 16
; GFX10-NEXT: v_mov_b32_e32 v11, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_movrels_b32 s2, s8 ; GFX10-NEXT: s_movrels_b32 s2, s8
; GFX10-NEXT: v_mov_b32_e32 v0, s8
; GFX10-NEXT: s_andn2_b32 s1, s2, s1 ; GFX10-NEXT: s_andn2_b32 s1, s2, s1
; GFX10-NEXT: v_lshl_or_b32 v8, v0, s0, s1
; GFX10-NEXT: v_mov_b32_e32 v0, s8
; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: v_lshl_or_b32 v12, v8, s0, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s10 ; GFX10-NEXT: v_mov_b32_e32 v2, s10
; GFX10-NEXT: v_mov_b32_e32 v3, s11 ; GFX10-NEXT: v_mov_b32_e32 v3, s11
; GFX10-NEXT: v_mov_b32_e32 v4, s12 ; GFX10-NEXT: v_mov_b32_e32 v4, s12
; GFX10-NEXT: v_mov_b32_e32 v5, s13 ; GFX10-NEXT: v_mov_b32_e32 v5, s13
; GFX10-NEXT: v_mov_b32_e32 v6, s14 ; GFX10-NEXT: v_mov_b32_e32 v6, s14
; GFX10-NEXT: v_mov_b32_e32 v7, s15 ; GFX10-NEXT: v_mov_b32_e32 v7, s15
; GFX10-NEXT: v_movreld_b32_e32 v0, v8
; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: v_mov_b32_e32 v9, 0 ; GFX10-NEXT: v_mov_b32_e32 v9, 0
; GFX10-NEXT: v_movreld_b32_e32 v0, v12
; GFX10-NEXT: global_store_dwordx4 v[8:9], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[8:9], v[0:3], off
; GFX10-NEXT: global_store_dwordx4 v[10:11], v[4:7], off ; GFX10-NEXT: v_mov_b32_e32 v0, 16
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v16i16_v_s: ; GFX11-LABEL: insertelement_s_v16i16_v_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0 ; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0
; GFX11-NEXT: s_and_b32 s0, s4, 1 ; GFX11-NEXT: s_and_b32 s0, s4, 1
; GFX11-NEXT: s_lshr_b32 m0, s4, 1 ; GFX11-NEXT: s_lshr_b32 m0, s4, 1
; GFX11-NEXT: s_lshl_b32 s0, s0, 4 ; GFX11-NEXT: s_lshl_b32 s0, s0, 4
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; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT: s_mov_b64 s[0:1], 16 ; GFX7-NEXT: s_mov_b64 s[0:1], 16
; GFX7-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v16i16_s_v: ; GFX10-LABEL: insertelement_s_v16i16_s_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v12, 1, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 1, v0
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: s_and_b32 s5, s4, 0xffff ; GFX10-NEXT: s_and_b32 s5, s4, 0xffff
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v8
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v8
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v8
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v8
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v8
; GFX10-NEXT: v_lshlrev_b32_e64 v2, v0, 0xffff ; GFX10-NEXT: v_lshlrev_b32_e64 v2, v0, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e64 v8, v0, s5 ; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, s5
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v8
; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: v_xor_b32_e32 v9, -1, v2 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX10-NEXT: v_mov_b32_e32 v9, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s10, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s11, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s11, s1
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s12, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s12, s2
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s13, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s13, s3
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s14, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s14, s4
; GFX10-NEXT: v_cndmask_b32_e64 v10, v1, s15, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s15, s5
; GFX10-NEXT: v_and_or_b32 v10, v1, v2, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s8 ; GFX10-NEXT: v_mov_b32_e32 v0, s8
; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: v_mov_b32_e32 v2, s10 ; GFX10-NEXT: v_mov_b32_e32 v2, s10
; GFX10-NEXT: v_mov_b32_e32 v3, s11 ; GFX10-NEXT: v_mov_b32_e32 v3, s11
; GFX10-NEXT: v_and_or_b32 v13, v10, v9, v8
; GFX10-NEXT: v_mov_b32_e32 v4, s12 ; GFX10-NEXT: v_mov_b32_e32 v4, s12
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v10, s6
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v10, s1
; GFX10-NEXT: v_mov_b32_e32 v5, s13 ; GFX10-NEXT: v_mov_b32_e32 v5, s13
; GFX10-NEXT: v_mov_b32_e32 v6, s14 ; GFX10-NEXT: v_mov_b32_e32 v6, s14
; GFX10-NEXT: v_mov_b32_e32 v7, s15 ; GFX10-NEXT: v_mov_b32_e32 v7, s15
; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v10, s2
; GFX10-NEXT: v_mov_b32_e32 v9, 0
; GFX10-NEXT: v_mov_b32_e32 v10, 16
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v13, s6
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v13, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v13, s1
; GFX10-NEXT: v_mov_b32_e32 v11, 0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v13, s2
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v13, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v13, s5
; GFX10-NEXT: global_store_dwordx4 v[8:9], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[8:9], v[0:3], off
; GFX10-NEXT: global_store_dwordx4 v[10:11], v[4:7], off ; GFX10-NEXT: v_mov_b32_e32 v0, 16
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v10, s3
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v10, s5
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v16i16_s_v: ; GFX11-LABEL: insertelement_s_v16i16_s_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0 ; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v12, 1, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v8, 1, v0
; GFX11-NEXT: s_and_b32 s5, s4, 0xffff ; GFX11-NEXT: s_and_b32 s5, s4, 0xffff
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v8
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e64 v2, v0, 0xffff ; GFX11-NEXT: v_lshlrev_b32_e64 v2, v0, 0xffff
; GFX11-NEXT: v_lshlrev_b32_e64 v8, v0, s5 ; GFX11-NEXT: v_lshlrev_b32_e64 v9, v0, s5
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_mov_b32_e32 v1, s9 ; GFX11-NEXT: v_mov_b32_e32 v1, s9
; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v8
; GFX11-NEXT: v_xor_b32_e32 v9, -1, v2 ; GFX11-NEXT: v_xor_b32_e32 v10, -1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s10, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s10, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s11, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s11, s1
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s12, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s12, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s13, s3 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s13, s3
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s14, s4 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s14, s4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v10, v1, s15, s5 ; GFX11-NEXT: v_cndmask_b32_e64 v11, v1, s15, s5
; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9 ; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
; GFX11-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11 ; GFX11-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
; GFX11-NEXT: v_and_or_b32 v13, v10, v9, v8
; GFX11-NEXT: v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s13 ; GFX11-NEXT: v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s13
; GFX11-NEXT: v_dual_mov_b32 v6, s14 :: v_dual_mov_b32 v7, s15 ; GFX11-NEXT: v_dual_mov_b32 v6, s14 :: v_dual_mov_b32 v7, s15
; GFX11-NEXT: v_mov_b32_e32 v8, 0 ; GFX11-NEXT: v_and_or_b32 v9, v11, v10, v9
; GFX11-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 16 ; GFX11-NEXT: v_mov_b32_e32 v10, 16
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v13, s6
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v13, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v13, s1
; GFX11-NEXT: v_mov_b32_e32 v11, 0 ; GFX11-NEXT: v_mov_b32_e32 v11, 0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v13, s2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3 ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v9, s6
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v13, s4 ; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v13, s5 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v9, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v9, s1
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v9, s2
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v9, s3
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v9, s4
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v9, s5
; GFX11-NEXT: v_mov_b32_e32 v8, 0
; GFX11-NEXT: v_mov_b32_e32 v9, 0
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b128 v[8:9], v[0:3], off ; GFX11-NEXT: global_store_b128 v[8:9], v[0:3], off
; GFX11-NEXT: global_store_b128 v[10:11], v[4:7], off ; GFX11-NEXT: global_store_b128 v[10:11], v[4:7], off
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
%vec = load <16 x i16>, ptr addrspace(4) %ptr %vec = load <16 x i16>, ptr addrspace(4) %ptr
%insert = insertelement <16 x i16> %vec, i16 %val, i32 %idx %insert = insertelement <16 x i16> %vec, i16 %val, i32 %idx
store <16 x i16> %insert, ptr addrspace(1) null store <16 x i16> %insert, ptr addrspace(1) null
▲ Show 20 Lines • Show All 178 Lines • ▼ Show 20 Lines
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT: s_mov_b64 s[0:1], 16 ; GFX7-NEXT: s_mov_b64 s[0:1], 16
; GFX7-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v16i16_v_v: ; GFX10-LABEL: insertelement_s_v16i16_v_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v12, 1, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 1, v1
; GFX10-NEXT: v_and_b32_e32 v1, 1, v1 ; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v8
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v8
; GFX10-NEXT: s_mov_b32 null, 0 ; GFX10-NEXT: s_mov_b32 null, 0
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v8
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v8
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v8
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v8
; GFX10-NEXT: v_lshlrev_b32_e64 v3, v1, 0xffff ; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: v_lshlrev_b32_sdwa v8, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: v_lshlrev_b32_e64 v1, v1, 0xffff
; GFX10-NEXT: v_mov_b32_e32 v9, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v2, s9 ; GFX10-NEXT: v_mov_b32_e32 v2, s9
; GFX10-NEXT: v_xor_b32_e32 v9, -1, v3 ; GFX10-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, s8, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, s8, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s10, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s11, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s11, s1
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s12, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s12, s2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s13, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s13, s3
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s14, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s14, s4
; GFX10-NEXT: v_cndmask_b32_e64 v10, v2, s15, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s15, s5
; GFX10-NEXT: v_and_or_b32 v10, v2, v1, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s8 ; GFX10-NEXT: v_mov_b32_e32 v0, s8
; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: v_mov_b32_e32 v2, s10 ; GFX10-NEXT: v_mov_b32_e32 v2, s10
; GFX10-NEXT: v_mov_b32_e32 v3, s11 ; GFX10-NEXT: v_mov_b32_e32 v3, s11
; GFX10-NEXT: v_and_or_b32 v13, v10, v9, v8
; GFX10-NEXT: v_mov_b32_e32 v4, s12 ; GFX10-NEXT: v_mov_b32_e32 v4, s12
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v10, s6
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v10, s1
; GFX10-NEXT: v_mov_b32_e32 v5, s13 ; GFX10-NEXT: v_mov_b32_e32 v5, s13
; GFX10-NEXT: v_mov_b32_e32 v6, s14 ; GFX10-NEXT: v_mov_b32_e32 v6, s14
; GFX10-NEXT: v_mov_b32_e32 v7, s15 ; GFX10-NEXT: v_mov_b32_e32 v7, s15
; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v10, s2
; GFX10-NEXT: v_mov_b32_e32 v9, 0
; GFX10-NEXT: v_mov_b32_e32 v10, 16
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v13, s6
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v13, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v13, s1
; GFX10-NEXT: v_mov_b32_e32 v11, 0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v13, s2
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v13, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v13, s5
; GFX10-NEXT: global_store_dwordx4 v[8:9], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[8:9], v[0:3], off
; GFX10-NEXT: global_store_dwordx4 v[10:11], v[4:7], off ; GFX10-NEXT: v_mov_b32_e32 v0, 16
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v10, s3
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v10, s5
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v16i16_v_v: ; GFX11-LABEL: insertelement_s_v16i16_v_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0 ; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v12, 1, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v8, 1, v1
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: v_and_b32_e32 v1, 1, v1 ; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v8
; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v8
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 4, v1 ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b32_e64 v3, v1, 0xffff ; GFX11-NEXT: v_lshlrev_b32_e64 v3, v1, 0xffff
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_mov_b32_e32 v2, s9 ; GFX11-NEXT: v_dual_mov_b32 v2, s9 :: v_dual_lshlrev_b32 v9, v1, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v8, v1, v0 ; GFX11-NEXT: v_xor_b32_e32 v10, -1, v3
; GFX11-NEXT: v_xor_b32_e32 v9, -1, v3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v2, s8, v2, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v2, s8, v2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s10, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s10, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s11, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s11, s1
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s12, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s12, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s13, s3 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s13, s3
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s14, s4 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s14, s4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v10, v2, s15, s5 ; GFX11-NEXT: v_cndmask_b32_e64 v11, v2, s15, s5
; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v5, s13 ; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
; GFX11-NEXT: v_dual_mov_b32 v1, s9 :: v_dual_mov_b32 v2, s10 ; GFX11-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
; GFX11-NEXT: v_mov_b32_e32 v7, s15 ; GFX11-NEXT: v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s13
; GFX11-NEXT: v_mov_b32_e32 v3, s11 ; GFX11-NEXT: v_dual_mov_b32 v6, s14 :: v_dual_mov_b32 v7, s15
; GFX11-NEXT: v_and_or_b32 v13, v10, v9, v8 ; GFX11-NEXT: v_and_or_b32 v9, v11, v10, v9
; GFX11-NEXT: v_mov_b32_e32 v4, s12 ; GFX11-NEXT: v_mov_b32_e32 v10, 16
; GFX11-NEXT: v_mov_b32_e32 v6, s14 ; GFX11-NEXT: v_mov_b32_e32 v11, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v9, s6
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v9, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v9, s1
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v9, s2
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v9, s3
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v9, s4
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v9, s5
; GFX11-NEXT: v_mov_b32_e32 v8, 0 ; GFX11-NEXT: v_mov_b32_e32 v8, 0
; GFX11-NEXT: v_mov_b32_e32 v9, 0 ; GFX11-NEXT: v_mov_b32_e32 v9, 0
; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v13 :: v_dual_mov_b32 v10, 16
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v13, s6
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v13, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v13, s1
; GFX11-NEXT: v_mov_b32_e32 v11, 0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v13, s2
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v13, s4
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v13, s5
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b128 v[8:9], v[0:3], off ; GFX11-NEXT: global_store_b128 v[8:9], v[0:3], off
; GFX11-NEXT: global_store_b128 v[10:11], v[4:7], off ; GFX11-NEXT: global_store_b128 v[10:11], v[4:7], off
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
%vec = load <16 x i16>, ptr addrspace(4) %ptr %vec = load <16 x i16>, ptr addrspace(4) %ptr
%insert = insertelement <16 x i16> %vec, i16 %val, i32 %idx %insert = insertelement <16 x i16> %vec, i16 %val, i32 %idx
store <16 x i16> %insert, ptr addrspace(1) null store <16 x i16> %insert, ptr addrspace(1) null
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
; GFX7-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v16i16_s_v: ; GFX10-LABEL: insertelement_v_v16i16_s_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off ; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
; GFX10-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:16 ; GFX10-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:16
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v11, 1, v2
; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 ; GFX10-NEXT: v_and_b32_e32 v1, 1, v2
; GFX10-NEXT: s_and_b32 s5, s2, 0xffff ; GFX10-NEXT: s_and_b32 s5, s2, 0xffff
; GFX10-NEXT: v_mov_b32_e32 v13, 16 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
; GFX10-NEXT: v_mov_b32_e32 v14, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v11
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v11
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 4, v11
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v11
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 4, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 6, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 4, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v11
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 6, v0 ; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xffff
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v0 ; GFX10-NEXT: v_lshlrev_b32_e64 v1, v1, s5
; GFX10-NEXT: v_lshlrev_b32_e64 v11, v2, 0xffff ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v11
; GFX10-NEXT: v_lshlrev_b32_e64 v2, v2, s5 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v0
; GFX10-NEXT: v_xor_b32_e32 v11, -1, v11
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v5, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v6, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s1
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v7, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v7, s3
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v8, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v8, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v9, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v9, s2
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v10, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v10, s5
; GFX10-NEXT: v_and_or_b32 v15, v1, v11, v2 ; GFX10-NEXT: v_and_or_b32 v12, v0, v2, v1
; GFX10-NEXT: v_mov_b32_e32 v11, 0 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v12, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v12, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v12, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, v15, s6 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v15, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, v12, s6
; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v15, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v6, v12, s1
; GFX10-NEXT: v_cndmask_b32_e64 v3, v6, v15, s1 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v7, v15, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v9, v12, s2
; GFX10-NEXT: v_cndmask_b32_e64 v5, v8, v15, s4 ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: v_cndmask_b32_e64 v6, v9, v15, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, 16
; GFX10-NEXT: v_cndmask_b32_e64 v7, v10, v15, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v7, v12, s3
; GFX10-NEXT: global_store_dwordx4 v[11:12], v[0:3], off ; GFX10-NEXT: v_cndmask_b32_e64 v5, v8, v12, s4
; GFX10-NEXT: global_store_dwordx4 v[13:14], v[4:7], off ; GFX10-NEXT: v_cndmask_b32_e64 v7, v10, v12, s5
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v16i16_s_v: ; GFX11-LABEL: insertelement_v_v16i16_s_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
; GFX11-NEXT: global_load_b128 v[7:10], v[0:1], off offset:16 ; GFX11-NEXT: global_load_b128 v[7:10], v[0:1], off offset:16
; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v2
; GFX11-NEXT: s_and_b32 s5, s2, 0xffff ; GFX11-NEXT: s_and_b32 s5, s2, 0xffff
; GFX11-NEXT: v_dual_mov_b32 v13, 16 :: v_dual_and_b32 v2, 1, v2 ; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 4, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 4, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 5, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 5, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 4, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 6, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 6, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 4, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e64 v11, v2, 0xffff ; GFX11-NEXT: v_lshlrev_b32_e64 v11, v2, 0xffff
; GFX11-NEXT: v_lshlrev_b32_e64 v2, v2, s5 ; GFX11-NEXT: v_lshlrev_b32_e64 v2, v2, s5
; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v0
; GFX11-NEXT: v_xor_b32_e32 v11, -1, v11 ; GFX11-NEXT: v_xor_b32_e32 v11, -1, v11
; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v5, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v5, s0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v6, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v6, s1
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v7, s3 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v7, s3
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v8, s4 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v8, s4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s2
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v10, s5 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v10, s5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_and_or_b32 v15, v1, v11, v2 ; GFX11-NEXT: v_and_or_b32 v11, v1, v11, v2
; GFX11-NEXT: v_cndmask_b32_e64 v0, v3, v11, s6
; GFX11-NEXT: v_cndmask_b32_e64 v2, v5, v11, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v6, v11, s1
; GFX11-NEXT: v_cndmask_b32_e64 v5, v8, v11, s4
; GFX11-NEXT: v_cndmask_b32_e64 v6, v9, v11, s2
; GFX11-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_cndmask_b32 v1, v4, v11
; GFX11-NEXT: v_cndmask_b32_e64 v4, v7, v11, s3
; GFX11-NEXT: v_cndmask_b32_e64 v7, v10, v11, s5
; GFX11-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 16
; GFX11-NEXT: v_mov_b32_e32 v11, 0 ; GFX11-NEXT: v_mov_b32_e32 v11, 0
; GFX11-NEXT: v_mov_b32_e32 v12, 0
; GFX11-NEXT: v_dual_mov_b32 v14, 0 :: v_dual_cndmask_b32 v1, v4, v15
; GFX11-NEXT: v_cndmask_b32_e64 v0, v3, v15, s6
; GFX11-NEXT: v_cndmask_b32_e64 v2, v5, v15, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v6, v15, s1
; GFX11-NEXT: v_cndmask_b32_e64 v4, v7, v15, s3
; GFX11-NEXT: v_cndmask_b32_e64 v5, v8, v15, s4
; GFX11-NEXT: v_cndmask_b32_e64 v6, v9, v15, s2
; GFX11-NEXT: v_cndmask_b32_e64 v7, v10, v15, s5
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b128 v[11:12], v[0:3], off ; GFX11-NEXT: global_store_b128 v[8:9], v[0:3], off
; GFX11-NEXT: global_store_b128 v[13:14], v[4:7], off ; GFX11-NEXT: global_store_b128 v[10:11], v[4:7], off
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
%vec = load <16 x i16>, ptr addrspace(1) %ptr %vec = load <16 x i16>, ptr addrspace(1) %ptr
%insert = insertelement <16 x i16> %vec, i16 %val, i32 %idx %insert = insertelement <16 x i16> %vec, i16 %val, i32 %idx
store <16 x i16> %insert, ptr addrspace(1) null store <16 x i16> %insert, ptr addrspace(1) null
ret void ret void
} }
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; GFX10-LABEL: insertelement_v_v16i16_v_s: ; GFX10-LABEL: insertelement_v_v16i16_v_s:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off ; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
; GFX10-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:16 ; GFX10-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:16
; GFX10-NEXT: s_and_b32 s0, s2, 1 ; GFX10-NEXT: s_and_b32 s0, s2, 1
; GFX10-NEXT: s_lshr_b32 m0, s2, 1 ; GFX10-NEXT: s_lshr_b32 m0, s2, 1
; GFX10-NEXT: s_lshl_b32 s0, s0, 4 ; GFX10-NEXT: s_lshl_b32 s0, s0, 4
; GFX10-NEXT: v_mov_b32_e32 v11, 16
; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_lshl_b32 s0, 0xffff, s0 ; GFX10-NEXT: s_lshl_b32 s1, 0xffff, s0
; GFX10-NEXT: v_mov_b32_e32 v12, 0 ; GFX10-NEXT: s_not_b32 s0, s1
; GFX10-NEXT: s_not_b32 s0, s0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_movrels_b32_e32 v1, v3 ; GFX10-NEXT: v_movrels_b32_e32 v1, v3
; GFX10-NEXT: v_and_or_b32 v2, v1, s0, v0 ; GFX10-NEXT: v_and_or_b32 v0, v1, s0, v0
; GFX10-NEXT: v_movreld_b32_e32 v3, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_movreld_b32_e32 v3, v2
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GFX10-NEXT: global_store_dwordx4 v[11:12], v[7:10], off ; GFX10-NEXT: v_mov_b32_e32 v0, 16
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v16i16_v_s: ; GFX11-LABEL: insertelement_v_v16i16_v_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
; GFX11-NEXT: global_load_b128 v[7:10], v[0:1], off offset:16 ; GFX11-NEXT: global_load_b128 v[7:10], v[0:1], off offset:16
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v2 ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v2
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; GFX7-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v16i16_v_v: ; GFX10-LABEL: insertelement_v_v16i16_v_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off ; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off
; GFX10-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:16 ; GFX10-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:16
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v12, 1, v3
; GFX10-NEXT: v_and_b32_e32 v3, 1, v3 ; GFX10-NEXT: v_and_b32_e32 v1, 1, v3
; GFX10-NEXT: v_mov_b32_e32 v14, 16 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
; GFX10-NEXT: v_mov_b32_e32 v15, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v12
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v12
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v12
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v12
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v12
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 4, v3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v12
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v12
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v0 ; GFX10-NEXT: v_lshlrev_b32_e64 v1, v1, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e64 v12, v3, 0xffff ; GFX10-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: v_xor_b32_e32 v3, -1, v12
; GFX10-NEXT: v_mov_b32_e32 v12, 0
; GFX10-NEXT: v_mov_b32_e32 v13, 0
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v7, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v7, s1
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v8, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v8, s2
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v9, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v9, s3
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v10, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v10, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v11, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v11, s5
; GFX10-NEXT: v_and_or_b32 v16, v1, v3, v2 ; GFX10-NEXT: v_and_or_b32 v13, v0, v1, v2
; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v16, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v13, s6
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v16, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v16, s0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v16, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v13, s0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v16, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v13, s1
; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v16, s3 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v16, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v13, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v16, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v13, s5
; GFX10-NEXT: global_store_dwordx4 v[12:13], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: global_store_dwordx4 v[14:15], v[4:7], off ; GFX10-NEXT: v_mov_b32_e32 v0, 16
; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v13, s2
; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v13, s3
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v16i16_v_v: ; GFX11-LABEL: insertelement_v_v16i16_v_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off ; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off
; GFX11-NEXT: global_load_b128 v[8:11], v[0:1], off offset:16 ; GFX11-NEXT: global_load_b128 v[8:11], v[0:1], off offset:16
; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v3 ; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v3
; GFX11-NEXT: v_dual_mov_b32 v14, 16 :: v_dual_and_b32 v3, 1, v3 ; GFX11-NEXT: v_and_b32_e32 v3, 1, v3
; GFX11-NEXT: v_dual_mov_b32 v15, 0 :: v_dual_and_b32 v2, 0xffff, v2 ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 4, v3 ; GFX11-NEXT: v_lshlrev_b32_e32 v3, 4, v3
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e64 v12, v3, 0xffff
; GFX11-NEXT: v_lshlrev_b32_e32 v2, v3, v2 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, v3, v2
; GFX11-NEXT: v_xor_b32_e32 v3, -1, v12 ; GFX11-NEXT: v_lshlrev_b32_e64 v3, v3, 0xffff
; GFX11-NEXT: v_mov_b32_e32 v12, 0 ; GFX11-NEXT: v_xor_b32_e32 v3, -1, v3
; GFX11-NEXT: v_mov_b32_e32 v13, 0
; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v7, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v7, s1
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v8, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v8, s2
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s3 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v10, s4 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v10, s4
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v11, s5 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v11, s5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_and_or_b32 v16, v1, v3, v2 ; GFX11-NEXT: v_and_or_b32 v12, v1, v3, v2
; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v16, s6 ; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v12, s6
; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v16, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v12, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, v16, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v12, s2
; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, v16, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, v12, s3
; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v16, s2 ; GFX11-NEXT: v_mov_b32_e32 v8, 0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, v16, s3 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, v12, s0
; GFX11-NEXT: v_cndmask_b32_e64 v6, v10, v16, s4 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, v12, s1
; GFX11-NEXT: v_cndmask_b32_e64 v7, v11, v16, s5 ; GFX11-NEXT: v_cndmask_b32_e64 v6, v10, v12, s4
; GFX11-NEXT: v_cndmask_b32_e64 v7, v11, v12, s5
; GFX11-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 16
; GFX11-NEXT: v_mov_b32_e32 v11, 0
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b128 v[12:13], v[0:3], off ; GFX11-NEXT: global_store_b128 v[8:9], v[0:3], off
; GFX11-NEXT: global_store_b128 v[14:15], v[4:7], off ; GFX11-NEXT: global_store_b128 v[10:11], v[4:7], off
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
%vec = load <16 x i16>, ptr addrspace(1) %ptr %vec = load <16 x i16>, ptr addrspace(1) %ptr
%insert = insertelement <16 x i16> %vec, i16 %val, i32 %idx %insert = insertelement <16 x i16> %vec, i16 %val, i32 %idx
store <16 x i16> %insert, ptr addrspace(1) null store <16 x i16> %insert, ptr addrspace(1) null
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll

Show First 20 Lines • Show All 991 Lines • ▼ Show 20 Lines
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_and_b32_e32 v0, v0, v1 ; GFX7-NEXT: v_and_b32_e32 v0, v0, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v4i8_s_v: ; GFX10-LABEL: insertelement_v_v4i8_s_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dword v3, v[0:1], off ; GFX10-NEXT: global_load_dword v0, v[0:1], off
; GFX10-NEXT: v_and_b32_e32 v0, 3, v2 ; GFX10-NEXT: v_and_b32_e32 v1, 3, v2
; GFX10-NEXT: s_and_b32 s0, s2, 0xff ; GFX10-NEXT: s_and_b32 s0, s2, 0xff
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v1
; GFX10-NEXT: v_lshlrev_b32_e64 v1, v0, 0xff ; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xff
; GFX10-NEXT: v_lshlrev_b32_e64 v2, v0, s0 ; GFX10-NEXT: v_lshlrev_b32_e64 v1, v1, s0
; GFX10-NEXT: v_xor_b32_e32 v4, -1, v1 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_and_or_b32 v2, v0, v2, v1
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, v2
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v4i8_s_v: ; GFX11-LABEL: insertelement_v_v4i8_s_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b32 v3, v[0:1], off ; GFX11-NEXT: global_load_b32 v3, v[0:1], off
; GFX11-NEXT: v_and_b32_e32 v0, 3, v2 ; GFX11-NEXT: v_and_b32_e32 v0, 3, v2
; GFX11-NEXT: s_and_b32 s0, s2, 0xff ; GFX11-NEXT: s_and_b32 s0, s2, 0xff
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; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_and_b32_e32 v0, v0, v1 ; GFX7-NEXT: v_and_b32_e32 v0, v0, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v4i8_v_v: ; GFX10-LABEL: insertelement_v_v4i8_v_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dword v4, v[0:1], off ; GFX10-NEXT: global_load_dword v0, v[0:1], off
; GFX10-NEXT: v_and_b32_e32 v0, 3, v3 ; GFX10-NEXT: v_and_b32_e32 v1, 3, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v1
; GFX10-NEXT: v_lshlrev_b32_e64 v1, v0, 0xff ; GFX10-NEXT: v_lshlrev_b32_e64 v3, v1, 0xff
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_xor_b32_e32 v3, -1, v1 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v3
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_and_or_b32 v2, v0, v2, v1
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_and_or_b32 v2, v4, v3, v2
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v4i8_v_v: ; GFX11-LABEL: insertelement_v_v4i8_v_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b32 v4, v[0:1], off ; GFX11-NEXT: global_load_b32 v4, v[0:1], off
; GFX11-NEXT: v_and_b32_e32 v0, 3, v3 ; GFX11-NEXT: v_and_b32_e32 v0, 3, v3
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v2 ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v2
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; GFX10-NEXT: s_lshl_b32 s1, s1, 3 ; GFX10-NEXT: s_lshl_b32 s1, s1, 3
; GFX10-NEXT: s_and_b32 s2, s2, 0xff ; GFX10-NEXT: s_and_b32 s2, s2, 0xff
; GFX10-NEXT: s_lshl_b32 s3, 0xff, s1 ; GFX10-NEXT: s_lshl_b32 s3, 0xff, s1
; GFX10-NEXT: s_lshl_b32 s1, s2, s1 ; GFX10-NEXT: s_lshl_b32 s1, s2, s1
; GFX10-NEXT: s_not_b32 s2, s3 ; GFX10-NEXT: s_not_b32 s2, s3
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s0, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s0, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc_lo
; GFX10-NEXT: v_and_or_b32 v4, v2, s2, s1 ; GFX10-NEXT: v_and_or_b32 v2, v2, s2, s1
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v8i8_s_s: ; GFX11-LABEL: insertelement_v_v8i8_s_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: s_lshr_b32 s0, s3, 2 ; GFX11-NEXT: s_lshr_b32 s0, s3, 2
; GFX11-NEXT: s_and_b32 s1, s3, 3 ; GFX11-NEXT: s_and_b32 s1, s3, 3
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; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v8i8_v_s: ; GFX10-LABEL: insertelement_s_v8i8_v_s:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX10-NEXT: s_lshr_b32 s2, s4, 2 ; GFX10-NEXT: s_lshr_b32 s2, s4, 2
; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v0 ; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX10-NEXT: s_cmp_eq_u32 s2, 1 ; GFX10-NEXT: s_cmp_eq_u32 s2, 1
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_cselect_b32 s3, s1, s0 ; GFX10-NEXT: s_cselect_b32 s3, s1, s0
; GFX10-NEXT: s_and_b32 s4, s4, 3 ; GFX10-NEXT: s_and_b32 s4, s4, 3
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: s_lshl_b32 s4, s4, 3 ; GFX10-NEXT: s_lshl_b32 s4, s4, 3
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_lshl_b32 s5, 0xff, s4 ; GFX10-NEXT: s_lshl_b32 s5, 0xff, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s2, 0
; GFX10-NEXT: s_andn2_b32 s3, s3, s5 ; GFX10-NEXT: s_andn2_b32 s3, s3, s5
; GFX10-NEXT: v_lshl_or_b32 v4, v2, s4, s3 ; GFX10-NEXT: v_lshl_or_b32 v2, v2, s4, s3
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v8i8_v_s: ; GFX11-LABEL: insertelement_s_v8i8_v_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
; GFX11-NEXT: s_lshr_b32 s2, s4, 2 ; GFX11-NEXT: s_lshr_b32 s2, s4, 2
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v0 ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v0
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; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v8i8_s_v: ; GFX10-LABEL: insertelement_s_v8i8_s_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX10-NEXT: v_and_b32_e32 v1, 3, v0 ; GFX10-NEXT: v_and_b32_e32 v1, 3, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 2, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 2, v0
; GFX10-NEXT: s_and_b32 s2, s4, 0xff ; GFX10-NEXT: s_and_b32 s2, s4, 0xff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xff ; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xff
; GFX10-NEXT: v_lshlrev_b32_e64 v3, v1, s2 ; GFX10-NEXT: v_lshlrev_b32_e64 v1, v1, s2
; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s1 ; GFX10-NEXT: v_mov_b32_e32 v0, s1
; GFX10-NEXT: v_cndmask_b32_e32 v5, s0, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX10-NEXT: v_and_or_b32 v2, v0, v2, v1
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v3
; GFX10-NEXT: v_and_or_b32 v5, v5, v2, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v8i8_s_v: ; GFX11-LABEL: insertelement_s_v8i8_s_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
; GFX11-NEXT: v_and_b32_e32 v1, 3, v0 ; GFX11-NEXT: v_and_b32_e32 v1, 3, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 2, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 2, v0
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; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v8i8_v_v: ; GFX10-LABEL: insertelement_s_v8i8_v_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX10-NEXT: v_and_b32_e32 v2, 3, v1 ; GFX10-NEXT: v_and_b32_e32 v2, 3, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 2, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 2, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GFX10-NEXT: v_lshlrev_b32_e64 v3, v2, 0xff ; GFX10-NEXT: v_lshlrev_b32_e64 v1, v2, 0xff
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_xor_b32_e32 v3, -1, v3 ; GFX10-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_cndmask_b32_e32 v5, s0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, s0, v2, vcc_lo
; GFX10-NEXT: v_and_or_b32 v2, v2, v1, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v3
; GFX10-NEXT: v_and_or_b32 v5, v5, v3, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v8i8_v_v: ; GFX11-LABEL: insertelement_s_v8i8_v_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
; GFX11-NEXT: v_and_b32_e32 v2, 3, v1 ; GFX11-NEXT: v_and_b32_e32 v2, 3, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 2, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 2, v1
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; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v8i8_s_v: ; GFX10-LABEL: insertelement_v_v8i8_s_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: v_and_b32_e32 v3, 3, v2 ; GFX10-NEXT: v_and_b32_e32 v3, 3, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 2, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 2, v2
; GFX10-NEXT: s_and_b32 s0, s2, 0xff ; GFX10-NEXT: s_and_b32 s0, s2, 0xff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 3, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 3, v3
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX10-NEXT: v_lshlrev_b32_e64 v4, v3, 0xff ; GFX10-NEXT: v_lshlrev_b32_e64 v4, v3, 0xff
; GFX10-NEXT: v_lshlrev_b32_e64 v2, v3, s0 ; GFX10-NEXT: v_lshlrev_b32_e64 v3, v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v5 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v2
; GFX10-NEXT: v_xor_b32_e32 v3, -1, v4 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
; GFX10-NEXT: v_and_or_b32 v4, v4, v3, v2 ; GFX10-NEXT: v_and_or_b32 v3, v5, v4, v3
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v8i8_s_v: ; GFX11-LABEL: insertelement_v_v8i8_s_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 2, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 2, v2
; GFX11-NEXT: s_and_b32 s0, s2, 0xff ; GFX11-NEXT: s_and_b32 s0, s2, 0xff
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; GFX10-NEXT: s_and_b32 s0, s2, 3 ; GFX10-NEXT: s_and_b32 s0, s2, 3
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s1, 1 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s1, 1
; GFX10-NEXT: s_lshl_b32 s0, s0, 3 ; GFX10-NEXT: s_lshl_b32 s0, s0, 3
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: s_lshl_b32 s0, 0xff, s0 ; GFX10-NEXT: s_lshl_b32 s0, 0xff, s0
; GFX10-NEXT: s_not_b32 s0, s0 ; GFX10-NEXT: s_not_b32 s0, s0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc_lo
; GFX10-NEXT: v_and_or_b32 v4, v3, s0, v2 ; GFX10-NEXT: v_and_or_b32 v2, v3, s0, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s1, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s1, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v8i8_v_s: ; GFX11-LABEL: insertelement_v_v8i8_v_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: s_lshr_b32 s1, s2, 2 ; GFX11-NEXT: s_lshr_b32 s1, s2, 2
; GFX11-NEXT: s_and_b32 s0, s2, 3 ; GFX11-NEXT: s_and_b32 s0, s2, 3
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; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v8i8_v_v: ; GFX10-LABEL: insertelement_v_v8i8_v_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: v_and_b32_e32 v4, 3, v3 ; GFX10-NEXT: v_and_b32_e32 v4, 3, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 2, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 2, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v4 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v3
; GFX10-NEXT: v_lshlrev_b32_e64 v5, v4, 0xff
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_xor_b32_e32 v3, -1, v5 ; GFX10-NEXT: v_lshlrev_b32_e64 v4, v4, 0xff
; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
; GFX10-NEXT: v_and_or_b32 v4, v4, v3, v2 ; GFX10-NEXT: v_and_or_b32 v2, v5, v4, v2
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v8i8_v_v: ; GFX11-LABEL: insertelement_v_v8i8_v_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: v_and_b32_e32 v4, 3, v3 ; GFX11-NEXT: v_and_b32_e32 v4, 3, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 2, v3 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 2, v3
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; GFX10-NEXT: s_and_b32 s2, s2, 0xff ; GFX10-NEXT: s_and_b32 s2, s2, 0xff
; GFX10-NEXT: s_lshl_b32 s5, 0xff, s3 ; GFX10-NEXT: s_lshl_b32 s5, 0xff, s3
; GFX10-NEXT: s_lshl_b32 s2, s2, s3 ; GFX10-NEXT: s_lshl_b32 s2, s2, s3
; GFX10-NEXT: s_not_b32 s3, s5 ; GFX10-NEXT: s_not_b32 s3, s5
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v2, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v3, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v3, s1
; GFX10-NEXT: v_and_or_b32 v6, v4, s3, s2 ; GFX10-NEXT: v_and_or_b32 v4, v4, s3, s2
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s4, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s4, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s1
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v6, s1
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v16i8_s_s: ; GFX11-LABEL: insertelement_v_v16i8_s_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
; GFX11-NEXT: s_lshr_b32 s4, s3, 2 ; GFX11-NEXT: s_lshr_b32 s4, s3, 2
; GFX11-NEXT: s_and_b32 s1, s3, 3 ; GFX11-NEXT: s_and_b32 s1, s3, 3
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; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v16i8_v_s: ; GFX10-LABEL: insertelement_s_v16i8_v_s:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
; GFX10-NEXT: s_lshr_b32 s5, s4, 2 ; GFX10-NEXT: s_lshr_b32 s5, s4, 2
; GFX10-NEXT: v_and_b32_e32 v4, 0xff, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-NEXT: s_cmp_eq_u32 s5, 1 ; GFX10-NEXT: s_cmp_eq_u32 s5, 1
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_cselect_b32 s6, s1, s0 ; GFX10-NEXT: s_cselect_b32 s6, s1, s0
; GFX10-NEXT: s_cmp_eq_u32 s5, 2 ; GFX10-NEXT: s_cmp_eq_u32 s5, 2
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: s_cselect_b32 s6, s2, s6 ; GFX10-NEXT: s_cselect_b32 s6, s2, s6
; GFX10-NEXT: s_cmp_eq_u32 s5, 3 ; GFX10-NEXT: s_cmp_eq_u32 s5, 3
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_cselect_b32 s6, s3, s6 ; GFX10-NEXT: s_cselect_b32 s6, s3, s6
; GFX10-NEXT: s_and_b32 s4, s4, 3 ; GFX10-NEXT: s_and_b32 s4, s4, 3
; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: s_lshl_b32 s4, s4, 3 ; GFX10-NEXT: s_lshl_b32 s4, s4, 3
; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: s_lshl_b32 s7, 0xff, s4 ; GFX10-NEXT: s_lshl_b32 s7, 0xff, s4
; GFX10-NEXT: s_andn2_b32 s6, s6, s7 ; GFX10-NEXT: s_andn2_b32 s6, s6, s7
; GFX10-NEXT: v_lshl_or_b32 v6, v4, s4, s6 ; GFX10-NEXT: v_lshl_or_b32 v4, v0, s4, s6
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v5, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 1 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s5, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 2 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 3 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 3
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v16i8_v_s: ; GFX11-LABEL: insertelement_s_v16i8_v_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0
; GFX11-NEXT: s_lshr_b32 s5, s4, 2 ; GFX11-NEXT: s_lshr_b32 s5, s4, 2
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v0 ; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v0
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; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v16i8_s_v: ; GFX10-LABEL: insertelement_s_v16i8_s_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 2, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 2, v0
; GFX10-NEXT: v_and_b32_e32 v1, 3, v0 ; GFX10-NEXT: v_and_b32_e32 v1, 3, v0
; GFX10-NEXT: s_and_b32 s1, s4, 0xff ; GFX10-NEXT: s_and_b32 s1, s4, 0xff
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v4
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v4
; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xff ; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xff
; GFX10-NEXT: v_lshlrev_b32_e64 v4, v1, s1 ; GFX10-NEXT: v_lshlrev_b32_e64 v1, v1, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v4
; GFX10-NEXT: v_xor_b32_e32 v5, -1, v2 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s9 ; GFX10-NEXT: v_mov_b32_e32 v0, s9
; GFX10-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s10, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v0, s11, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s11, s1
; GFX10-NEXT: v_and_or_b32 v5, v0, v2, v1
; GFX10-NEXT: v_mov_b32_e32 v0, s8 ; GFX10-NEXT: v_mov_b32_e32 v0, s8
; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: v_mov_b32_e32 v2, s10 ; GFX10-NEXT: v_mov_b32_e32 v2, s10
; GFX10-NEXT: v_mov_b32_e32 v3, s11 ; GFX10-NEXT: v_mov_b32_e32 v3, s11
; GFX10-NEXT: v_and_or_b32 v7, v7, v5, v4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v7, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v16i8_s_v: ; GFX11-LABEL: insertelement_s_v16i8_s_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[8:11], s[2:3], 0x0 ; GFX11-NEXT: s_load_b128 s[8:11], s[2:3], 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 2, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 2, v0
; GFX11-NEXT: v_and_b32_e32 v1, 3, v0 ; GFX11-NEXT: v_and_b32_e32 v1, 3, v0
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; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_s_v16i8_v_v: ; GFX10-LABEL: insertelement_s_v16i8_v_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 2, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 2, v1
; GFX10-NEXT: v_and_b32_e32 v2, 3, v1 ; GFX10-NEXT: v_and_b32_e32 v2, 3, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v4
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v4
; GFX10-NEXT: s_mov_b32 null, 0 ; GFX10-NEXT: s_mov_b32 null, 0
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v4
; GFX10-NEXT: v_lshlrev_b32_e64 v3, v2, 0xff ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_lshlrev_b32_sdwa v4, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_e64 v2, v2, 0xff
; GFX10-NEXT: v_xor_b32_e32 v5, -1, v3 ; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: v_cndmask_b32_e32 v1, s4, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, s4, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v1, s7, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s7, s1
; GFX10-NEXT: v_and_or_b32 v5, v1, v2, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: v_mov_b32_e32 v2, s6 ; GFX10-NEXT: v_mov_b32_e32 v2, s6
; GFX10-NEXT: v_mov_b32_e32 v3, s7 ; GFX10-NEXT: v_mov_b32_e32 v3, s7
; GFX10-NEXT: v_and_or_b32 v7, v7, v5, v4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v7, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_s_v16i8_v_v: ; GFX11-LABEL: insertelement_s_v16i8_v_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0 ; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 2, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 2, v1
; GFX11-NEXT: v_and_b32_e32 v2, 3, v1 ; GFX11-NEXT: v_and_b32_e32 v2, 3, v1
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v2, v5, v7, s[0:1] ; GFX7-NEXT: v_cndmask_b32_e64 v2, v5, v7, s[0:1]
; GFX7-NEXT: v_cndmask_b32_e64 v3, v6, v7, s[2:3] ; GFX7-NEXT: v_cndmask_b32_e64 v3, v6, v7, s[2:3]
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v16i8_s_v: ; GFX10-LABEL: insertelement_v_v16i8_s_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off ; GFX10-NEXT: v_and_b32_e32 v3, 3, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 2, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 2, v2
; GFX10-NEXT: v_and_b32_e32 v0, 3, v2
; GFX10-NEXT: s_and_b32 s1, s2, 0xff ; GFX10-NEXT: s_and_b32 s1, s2, 0xff
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v5, 3, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v4
; GFX10-NEXT: v_lshlrev_b32_e64 v7, v0, 0xff ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v4
; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, s1 ; GFX10-NEXT: v_lshlrev_b32_e64 v7, v5, 0xff
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v1 ; GFX10-NEXT: v_lshlrev_b32_e64 v5, v5, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v4
; GFX10-NEXT: v_xor_b32_e32 v7, -1, v7 ; GFX10-NEXT: v_xor_b32_e32 v7, -1, v7
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v3, s1
; GFX10-NEXT: v_and_or_b32 v5, v6, v7, v5
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
; GFX10-NEXT: v_and_or_b32 v9, v2, v7, v0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v7, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, v9, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v9, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v6, v9, s1
; GFX10-NEXT: global_store_dwordx4 v[7:8], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v16i8_s_v: ; GFX11-LABEL: insertelement_v_v16i8_s_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 2, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 2, v2
; GFX11-NEXT: v_and_b32_e32 v0, 3, v2 ; GFX11-NEXT: v_and_b32_e32 v0, 3, v2
; GFX11-NEXT: s_and_b32 s1, s2, 0xff ; GFX11-NEXT: s_and_b32 s1, s2, 0xff
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_lshr_b32 s3, s2, 2 ; GFX10-NEXT: s_lshr_b32 s3, s2, 2
; GFX10-NEXT: s_and_b32 s1, s2, 3 ; GFX10-NEXT: s_and_b32 s1, s2, 3
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s3, 1 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s3, 1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, 2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, 2
; GFX10-NEXT: s_lshl_b32 s2, s1, 3 ; GFX10-NEXT: s_lshl_b32 s2, s1, 3
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s3, 3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s3, 3
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: s_lshl_b32 s2, 0xff, s2 ; GFX10-NEXT: s_lshl_b32 s2, 0xff, s2
; GFX10-NEXT: v_mov_b32_e32 v7, 0
; GFX10-NEXT: s_not_b32 s2, s2 ; GFX10-NEXT: s_not_b32 s2, s2
; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s1
; GFX10-NEXT: v_and_or_b32 v9, v0, s2, v1 ; GFX10-NEXT: v_and_or_b32 v7, v0, s2, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s3, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s3, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, v9, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v7, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v9, s0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v6, v9, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, v7, s2
; GFX10-NEXT: global_store_dwordx4 v[7:8], v[0:3], off ; GFX10-NEXT: v_cndmask_b32_e64 v3, v6, v7, s1
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v16i8_v_s: ; GFX11-LABEL: insertelement_v_v16i8_v_s:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
; GFX11-NEXT: s_lshr_b32 s3, s2, 2 ; GFX11-NEXT: s_lshr_b32 s3, s2, 2
; GFX11-NEXT: s_and_b32 s1, s2, 3 ; GFX11-NEXT: s_and_b32 s1, s2, 3
; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s3, 1 ; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s3, 1
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, v3, s[0:1] ; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, v3, s[0:1]
; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[2:3] ; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[2:3]
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 ; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX10-LABEL: insertelement_v_v16i8_v_v: ; GFX10-LABEL: insertelement_v_v16i8_v_v:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off ; GFX10-NEXT: v_and_b32_e32 v4, 3, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 2, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v5, 2, v3
; GFX10-NEXT: v_and_b32_e32 v0, 3, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v5
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v5
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v5
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v1 ; GFX10-NEXT: v_lshlrev_b32_sdwa v6, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_lshlrev_b32_e64 v8, v0, 0xff ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_e64 v4, v4, 0xff
; GFX10-NEXT: v_xor_b32_e32 v2, -1, v8 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: v_mov_b32_e32 v9, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v7, v0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v3, s1
; GFX10-NEXT: v_and_or_b32 v3, v3, v2, v0 ; GFX10-NEXT: v_and_or_b32 v4, v7, v4, v6
; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v3, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v3, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s1
; GFX10-NEXT: global_store_dwordx4 v[8:9], v[0:3], off ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: insertelement_v_v16i8_v_v: ; GFX11-LABEL: insertelement_v_v16i8_v_v:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off ; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 2, v3 ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 2, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
Show All 30 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_insert_v64i32_37: ; GFX10-LABEL: v_insert_v64i32_37:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-NEXT: v_lshlrev_b32_e32 v64, 8, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v64, 8, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0xf ; GFX10-NEXT: s_clause 0xf
; GFX10-NEXT: global_load_dwordx4 v[0:3], v64, s[0:1] ; GFX10-NEXT: global_load_dwordx4 v[0:3], v64, s[0:1] offset:128
; GFX10-NEXT: global_load_dwordx4 v[8:11], v64, s[0:1] offset:16
; GFX10-NEXT: global_load_dwordx4 v[12:15], v64, s[0:1] offset:32
; GFX10-NEXT: global_load_dwordx4 v[16:19], v64, s[0:1] offset:48
; GFX10-NEXT: global_load_dwordx4 v[20:23], v64, s[0:1] offset:64
; GFX10-NEXT: global_load_dwordx4 v[24:27], v64, s[0:1] offset:80
; GFX10-NEXT: global_load_dwordx4 v[28:31], v64, s[0:1] offset:96
; GFX10-NEXT: global_load_dwordx4 v[32:35], v64, s[0:1] offset:112
; GFX10-NEXT: global_load_dwordx4 v[36:39], v64, s[0:1] offset:160
; GFX10-NEXT: global_load_dwordx4 v[40:43], v64, s[0:1] offset:176
; GFX10-NEXT: global_load_dwordx4 v[44:47], v64, s[0:1] offset:192
; GFX10-NEXT: global_load_dwordx4 v[48:51], v64, s[0:1] offset:208
; GFX10-NEXT: global_load_dwordx4 v[52:55], v64, s[0:1] offset:224
; GFX10-NEXT: global_load_dwordx4 v[56:59], v64, s[0:1] offset:240
; GFX10-NEXT: global_load_dwordx4 v[60:63], v64, s[0:1] offset:128
; GFX10-NEXT: global_load_dwordx4 v[4:7], v64, s[0:1] offset:144 ; GFX10-NEXT: global_load_dwordx4 v[4:7], v64, s[0:1] offset:144
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_load_dwordx4 v[8:11], v64, s[0:1]
; GFX10-NEXT: global_load_dwordx4 v[12:15], v64, s[0:1] offset:16
; GFX10-NEXT: global_load_dwordx4 v[16:19], v64, s[0:1] offset:32
; GFX10-NEXT: global_load_dwordx4 v[20:23], v64, s[0:1] offset:48
; GFX10-NEXT: global_load_dwordx4 v[24:27], v64, s[0:1] offset:64
; GFX10-NEXT: global_load_dwordx4 v[28:31], v64, s[0:1] offset:80
; GFX10-NEXT: global_load_dwordx4 v[32:35], v64, s[0:1] offset:96
; GFX10-NEXT: global_load_dwordx4 v[36:39], v64, s[0:1] offset:112
; GFX10-NEXT: global_load_dwordx4 v[40:43], v64, s[0:1] offset:160
; GFX10-NEXT: global_load_dwordx4 v[44:47], v64, s[0:1] offset:176
; GFX10-NEXT: global_load_dwordx4 v[48:51], v64, s[0:1] offset:192
; GFX10-NEXT: global_load_dwordx4 v[52:55], v64, s[0:1] offset:208
; GFX10-NEXT: global_load_dwordx4 v[56:59], v64, s[0:1] offset:224
; GFX10-NEXT: global_load_dwordx4 v[60:63], v64, s[0:1] offset:240
; GFX10-NEXT: s_waitcnt vmcnt(14)
; GFX10-NEXT: v_mov_b32_e32 v5, 0x3e7 ; GFX10-NEXT: v_mov_b32_e32 v5, 0x3e7
; GFX10-NEXT: global_store_dwordx4 v64, v[0:3], s[2:3]
; GFX10-NEXT: global_store_dwordx4 v64, v[8:11], s[2:3] offset:16
; GFX10-NEXT: global_store_dwordx4 v64, v[12:15], s[2:3] offset:32
; GFX10-NEXT: global_store_dwordx4 v64, v[16:19], s[2:3] offset:48
; GFX10-NEXT: global_store_dwordx4 v64, v[20:23], s[2:3] offset:64
; GFX10-NEXT: global_store_dwordx4 v64, v[24:27], s[2:3] offset:80
; GFX10-NEXT: global_store_dwordx4 v64, v[28:31], s[2:3] offset:96
; GFX10-NEXT: global_store_dwordx4 v64, v[32:35], s[2:3] offset:112
; GFX10-NEXT: global_store_dwordx4 v64, v[60:63], s[2:3] offset:128
; GFX10-NEXT: global_store_dwordx4 v64, v[4:7], s[2:3] offset:144 ; GFX10-NEXT: global_store_dwordx4 v64, v[4:7], s[2:3] offset:144
; GFX10-NEXT: global_store_dwordx4 v64, v[36:39], s[2:3] offset:160 ; GFX10-NEXT: s_waitcnt vmcnt(13)
; GFX10-NEXT: global_store_dwordx4 v64, v[40:43], s[2:3] offset:176 ; GFX10-NEXT: global_store_dwordx4 v64, v[8:11], s[2:3]
; GFX10-NEXT: global_store_dwordx4 v64, v[44:47], s[2:3] offset:192 ; GFX10-NEXT: s_waitcnt vmcnt(12)
; GFX10-NEXT: global_store_dwordx4 v64, v[48:51], s[2:3] offset:208 ; GFX10-NEXT: global_store_dwordx4 v64, v[12:15], s[2:3] offset:16
; GFX10-NEXT: global_store_dwordx4 v64, v[52:55], s[2:3] offset:224 ; GFX10-NEXT: s_waitcnt vmcnt(11)
; GFX10-NEXT: global_store_dwordx4 v64, v[56:59], s[2:3] offset:240 ; GFX10-NEXT: global_store_dwordx4 v64, v[16:19], s[2:3] offset:32
; GFX10-NEXT: s_waitcnt vmcnt(10)
; GFX10-NEXT: global_store_dwordx4 v64, v[20:23], s[2:3] offset:48
; GFX10-NEXT: s_waitcnt vmcnt(9)
; GFX10-NEXT: global_store_dwordx4 v64, v[24:27], s[2:3] offset:64
; GFX10-NEXT: s_waitcnt vmcnt(8)
; GFX10-NEXT: global_store_dwordx4 v64, v[28:31], s[2:3] offset:80
; GFX10-NEXT: s_waitcnt vmcnt(7)
; GFX10-NEXT: global_store_dwordx4 v64, v[32:35], s[2:3] offset:96
; GFX10-NEXT: s_waitcnt vmcnt(6)
; GFX10-NEXT: global_store_dwordx4 v64, v[36:39], s[2:3] offset:112
; GFX10-NEXT: global_store_dwordx4 v64, v[0:3], s[2:3] offset:128
; GFX10-NEXT: s_waitcnt vmcnt(5)
; GFX10-NEXT: global_store_dwordx4 v64, v[40:43], s[2:3] offset:160
; GFX10-NEXT: s_waitcnt vmcnt(4)
; GFX10-NEXT: global_store_dwordx4 v64, v[44:47], s[2:3] offset:176
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: global_store_dwordx4 v64, v[48:51], s[2:3] offset:192
; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: global_store_dwordx4 v64, v[52:55], s[2:3] offset:208
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: global_store_dwordx4 v64, v[56:59], s[2:3] offset:224
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v64, v[60:63], s[2:3] offset:240
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_insert_v64i32_37: ; GFX11-LABEL: v_insert_v64i32_37:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX11-NEXT: v_lshlrev_b32_e32 v64, 8, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v64, 8, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0xf
; GFX11-NEXT: global_load_b128 v[0:3], v64, s[0:1]
; GFX11-NEXT: global_load_b128 v[8:11], v64, s[0:1] offset:16
; GFX11-NEXT: global_load_b128 v[12:15], v64, s[0:1] offset:32
; GFX11-NEXT: global_load_b128 v[16:19], v64, s[0:1] offset:48
; GFX11-NEXT: global_load_b128 v[20:23], v64, s[0:1] offset:64
; GFX11-NEXT: global_load_b128 v[24:27], v64, s[0:1] offset:80
; GFX11-NEXT: global_load_b128 v[28:31], v64, s[0:1] offset:96
; GFX11-NEXT: global_load_b128 v[32:35], v64, s[0:1] offset:112
; GFX11-NEXT: global_load_b128 v[36:39], v64, s[0:1] offset:128
; GFX11-NEXT: global_load_b128 v[4:7], v64, s[0:1] offset:144 ; GFX11-NEXT: global_load_b128 v[4:7], v64, s[0:1] offset:144
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_mov_b32_e32 v5, 0x3e7
; GFX11-NEXT: s_clause 0xe
; GFX11-NEXT: global_load_b128 v[0:3], v64, s[0:1] offset:128
; GFX11-NEXT: global_load_b128 v[8:11], v64, s[0:1]
; GFX11-NEXT: global_load_b128 v[12:15], v64, s[0:1] offset:16
; GFX11-NEXT: global_load_b128 v[16:19], v64, s[0:1] offset:32
; GFX11-NEXT: global_load_b128 v[20:23], v64, s[0:1] offset:48
; GFX11-NEXT: global_load_b128 v[24:27], v64, s[0:1] offset:64
; GFX11-NEXT: global_load_b128 v[28:31], v64, s[0:1] offset:80
; GFX11-NEXT: global_load_b128 v[32:35], v64, s[0:1] offset:96
; GFX11-NEXT: global_load_b128 v[36:39], v64, s[0:1] offset:112
; GFX11-NEXT: global_load_b128 v[40:43], v64, s[0:1] offset:160 ; GFX11-NEXT: global_load_b128 v[40:43], v64, s[0:1] offset:160
; GFX11-NEXT: global_load_b128 v[44:47], v64, s[0:1] offset:176 ; GFX11-NEXT: global_load_b128 v[44:47], v64, s[0:1] offset:176
; GFX11-NEXT: global_load_b128 v[48:51], v64, s[0:1] offset:192 ; GFX11-NEXT: global_load_b128 v[48:51], v64, s[0:1] offset:192
; GFX11-NEXT: global_load_b128 v[52:55], v64, s[0:1] offset:208 ; GFX11-NEXT: global_load_b128 v[52:55], v64, s[0:1] offset:208
; GFX11-NEXT: global_load_b128 v[56:59], v64, s[0:1] offset:224 ; GFX11-NEXT: global_load_b128 v[56:59], v64, s[0:1] offset:224
; GFX11-NEXT: global_load_b128 v[60:63], v64, s[0:1] offset:240 ; GFX11-NEXT: global_load_b128 v[60:63], v64, s[0:1] offset:240
; GFX11-NEXT: s_waitcnt vmcnt(6)
; GFX11-NEXT: v_mov_b32_e32 v5, 0x3e7
; GFX11-NEXT: s_clause 0x9
; GFX11-NEXT: global_store_b128 v64, v[0:3], s[2:3]
; GFX11-NEXT: global_store_b128 v64, v[8:11], s[2:3] offset:16
; GFX11-NEXT: global_store_b128 v64, v[12:15], s[2:3] offset:32
; GFX11-NEXT: global_store_b128 v64, v[16:19], s[2:3] offset:48
; GFX11-NEXT: global_store_b128 v64, v[20:23], s[2:3] offset:64
; GFX11-NEXT: global_store_b128 v64, v[24:27], s[2:3] offset:80
; GFX11-NEXT: global_store_b128 v64, v[28:31], s[2:3] offset:96
; GFX11-NEXT: global_store_b128 v64, v[32:35], s[2:3] offset:112
; GFX11-NEXT: global_store_b128 v64, v[36:39], s[2:3] offset:128
; GFX11-NEXT: global_store_b128 v64, v[4:7], s[2:3] offset:144 ; GFX11-NEXT: global_store_b128 v64, v[4:7], s[2:3] offset:144
; GFX11-NEXT: s_waitcnt vmcnt(14)
; GFX11-NEXT: global_store_b128 v64, v[0:3], s[2:3] offset:128
; GFX11-NEXT: s_waitcnt vmcnt(13)
; GFX11-NEXT: global_store_b128 v64, v[8:11], s[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(12)
; GFX11-NEXT: global_store_b128 v64, v[12:15], s[2:3] offset:16
; GFX11-NEXT: s_waitcnt vmcnt(11)
; GFX11-NEXT: global_store_b128 v64, v[16:19], s[2:3] offset:32
; GFX11-NEXT: s_waitcnt vmcnt(10)
; GFX11-NEXT: global_store_b128 v64, v[20:23], s[2:3] offset:48
; GFX11-NEXT: s_waitcnt vmcnt(9)
; GFX11-NEXT: global_store_b128 v64, v[24:27], s[2:3] offset:64
; GFX11-NEXT: s_waitcnt vmcnt(8)
; GFX11-NEXT: global_store_b128 v64, v[28:31], s[2:3] offset:80
; GFX11-NEXT: s_waitcnt vmcnt(7)
; GFX11-NEXT: global_store_b128 v64, v[32:35], s[2:3] offset:96
; GFX11-NEXT: s_waitcnt vmcnt(6)
; GFX11-NEXT: global_store_b128 v64, v[36:39], s[2:3] offset:112
; GFX11-NEXT: s_waitcnt vmcnt(5) ; GFX11-NEXT: s_waitcnt vmcnt(5)
; GFX11-NEXT: global_store_b128 v64, v[40:43], s[2:3] offset:160 ; GFX11-NEXT: global_store_b128 v64, v[40:43], s[2:3] offset:160
; GFX11-NEXT: s_waitcnt vmcnt(4) ; GFX11-NEXT: s_waitcnt vmcnt(4)
; GFX11-NEXT: global_store_b128 v64, v[44:47], s[2:3] offset:176 ; GFX11-NEXT: global_store_b128 v64, v[44:47], s[2:3] offset:176
; GFX11-NEXT: s_waitcnt vmcnt(3) ; GFX11-NEXT: s_waitcnt vmcnt(3)
; GFX11-NEXT: global_store_b128 v64, v[48:51], s[2:3] offset:192 ; GFX11-NEXT: global_store_b128 v64, v[48:51], s[2:3] offset:192
; GFX11-NEXT: s_waitcnt vmcnt(2) ; GFX11-NEXT: s_waitcnt vmcnt(2)
; GFX11-NEXT: global_store_b128 v64, v[52:55], s[2:3] offset:208 ; GFX11-NEXT: global_store_b128 v64, v[52:55], s[2:3] offset:208
Show All 19 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

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Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; GPRIDX-NEXT: v_mov_b32_e32 v1, v9 ; GPRIDX-NEXT: v_mov_b32_e32 v1, v9
; GPRIDX-NEXT: s_setpc_b64 s[30:31] ; GPRIDX-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: dyn_insertelement_v8f32_const_s_v_v: ; GFX10-LABEL: dyn_insertelement_v8f32_const_s_v_v:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s11, 0x41000000 ; GFX10-NEXT: s_mov_b32 s11, 0x41000000
; GFX10-NEXT: s_mov_b32 s4, 1.0
; GFX10-NEXT: s_mov_b32 s10, 0x40e00000 ; GFX10-NEXT: s_mov_b32 s10, 0x40e00000
; GFX10-NEXT: s_mov_b32 s9, 0x40c00000 ; GFX10-NEXT: s_mov_b32 s9, 0x40c00000
; GFX10-NEXT: s_mov_b32 s8, 0x40a00000 ; GFX10-NEXT: s_mov_b32 s8, 0x40a00000
; GFX10-NEXT: s_mov_b32 s7, 4.0 ; GFX10-NEXT: s_mov_b32 s7, 4.0
; GFX10-NEXT: s_mov_b32 s6, 0x40400000 ; GFX10-NEXT: s_mov_b32 s6, 0x40400000
; GFX10-NEXT: s_mov_b32 s5, 2.0 ; GFX10-NEXT: s_mov_b32 s5, 2.0
; GFX10-NEXT: s_mov_b32 s4, 1.0
; GFX10-NEXT: v_mov_b32_e32 v15, s11 ; GFX10-NEXT: v_mov_b32_e32 v15, s11
; GFX10-NEXT: v_mov_b32_e32 v8, s4 ; GFX10-NEXT: v_mov_b32_e32 v14, s10
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_mov_b32_e32 v13, s9
; GFX10-NEXT: v_mov_b32_e32 v9, s5
; GFX10-NEXT: v_mov_b32_e32 v10, s6
; GFX10-NEXT: v_mov_b32_e32 v11, s7
; GFX10-NEXT: v_mov_b32_e32 v12, s8 ; GFX10-NEXT: v_mov_b32_e32 v12, s8
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v11, s7
; GFX10-NEXT: v_mov_b32_e32 v10, s6
; GFX10-NEXT: v_mov_b32_e32 v9, s5
; GFX10-NEXT: v_mov_b32_e32 v8, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 0, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX10-NEXT: v_mov_b32_e32 v13, s9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 2, v1
; GFX10-NEXT: v_mov_b32_e32 v14, s10 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 3, v1
; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 4, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 5, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 6, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 7, v1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v0, s10
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, v0, s4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, v0, s5
; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v12, v0, s6
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v13, v0, s7
; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, v14, v0, s8
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v15, v0, s9
; GFX10-NEXT: v_mov_b32_e32 v1, v9
; GFX10-NEXT: v_cndmask_b32_e32 v7, v15, v0, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, v8 ; GFX10-NEXT: v_mov_b32_e32 v0, v8
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: dyn_insertelement_v8f32_const_s_v_v: ; GFX11-LABEL: dyn_insertelement_v8f32_const_s_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_mov_b32 s7, 0x41000000 ; GFX11-NEXT: s_mov_b32 s7, 0x41000000
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v15, s7 ; GFX10-NEXT: v_mov_b32_e32 v8, s7
; GFX10-NEXT: v_mov_b32_e32 v8, s0 ; GFX10-NEXT: v_mov_b32_e32 v7, s6
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_mov_b32_e32 v6, s5
; GFX10-NEXT: v_mov_b32_e32 v9, s1 ; GFX10-NEXT: v_mov_b32_e32 v5, s4
; GFX10-NEXT: v_mov_b32_e32 v10, s2 ; GFX10-NEXT: v_mov_b32_e32 v4, s3
; GFX10-NEXT: v_mov_b32_e32 v11, s3 ; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: v_mov_b32_e32 v12, s4 ; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s10, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX10-NEXT: v_mov_b32_e32 v13, s5 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v14, s6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, s10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, s10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, s10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s10, s6
; GFX10-NEXT: v_cndmask_b32_e64 v4, v12, s10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s10, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, s10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v5, v13, s10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, s10, s1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s10, s2
; GFX10-NEXT: v_cndmask_b32_e64 v6, v14, s10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, s10, s3
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, s10, s4
; GFX10-NEXT: v_mov_b32_e32 v0, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v8, s10, s5
; GFX10-NEXT: v_cndmask_b32_e64 v7, v15, s10, vcc_lo
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v8f32_s_s_v: ; GFX11-LABEL: dyn_insertelement_v8f32_s_s_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s3, s5 ; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s5, s7 ; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: s_mov_b32 s7, s9
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; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v15, s7 ; GFX10-NEXT: v_mov_b32_e32 v15, s7
; GFX10-NEXT: v_mov_b32_e32 v8, s0 ; GFX10-NEXT: v_mov_b32_e32 v14, s6
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_mov_b32_e32 v13, s5
; GFX10-NEXT: v_mov_b32_e32 v9, s1
; GFX10-NEXT: v_mov_b32_e32 v10, s2
; GFX10-NEXT: v_mov_b32_e32 v11, s3
; GFX10-NEXT: v_mov_b32_e32 v12, s4 ; GFX10-NEXT: v_mov_b32_e32 v12, s4
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v11, s3
; GFX10-NEXT: v_mov_b32_e32 v10, s2
; GFX10-NEXT: v_mov_b32_e32 v9, s1
; GFX10-NEXT: v_mov_b32_e32 v8, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX10-NEXT: v_mov_b32_e32 v13, s5 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX10-NEXT: v_mov_b32_e32 v14, s6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v1
; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v0, s6
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, v0, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, v0, s1
; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v12, v0, s2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v13, v0, s3
; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, v14, v0, s4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v15, v0, s5
; GFX10-NEXT: v_mov_b32_e32 v1, v9
; GFX10-NEXT: v_cndmask_b32_e32 v7, v15, v0, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, v8 ; GFX10-NEXT: v_mov_b32_e32 v0, v8
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v8f32_s_v_v: ; GFX11-LABEL: dyn_insertelement_v8f32_s_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s3, s5 ; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s5, s7 ; GFX11-NEXT: s_mov_b32 s5, s7
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; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v8 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v8
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v8 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v8
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v8 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v8
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_s_v: ; GFX10-LABEL: dyn_insertelement_v8f32_v_s_v:
; GFX10PLUS: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v8
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v8
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 4, v8
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v8
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 6, v8
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 7, v8
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 0, v8
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, s0
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s2, s1
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v5, v5, s2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s2, s3
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, s7
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s2, s4
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s2, s5
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v7, v7, s2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s2, s6
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: dyn_insertelement_v8f32_v_s_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v8
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s2, vcc_lo
; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx %insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_s(<8 x float> %vec, float %val, i32 inreg %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_s(<8 x float> %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
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; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v9
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v9
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v9
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_v_v: ; GFX10-LABEL: dyn_insertelement_v8f32_v_v_v:
; GFX10PLUS: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v8, s0
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v8, s1
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v8, s2
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v8, s6
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v8, s3
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v8, s4
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v8, s5
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: dyn_insertelement_v8f32_v_v_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9
; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9
; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx %insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x i64> @dyn_insertelement_v8i64_s_s_s(<8 x i64> inreg %vec, i64 inreg %val, i32 inreg %idx) { define amdgpu_ps <8 x i64> @dyn_insertelement_v8i64_s_s_s(<8 x i64> inreg %vec, i64 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8i64_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v8i64_s_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
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; GFX10-NEXT: v_mov_b32_e32 v11, s12 ; GFX10-NEXT: v_mov_b32_e32 v11, s12
; GFX10-NEXT: v_mov_b32_e32 v12, s13 ; GFX10-NEXT: v_mov_b32_e32 v12, s13
; GFX10-NEXT: v_mov_b32_e32 v13, s14 ; GFX10-NEXT: v_mov_b32_e32 v13, s14
; GFX10-NEXT: v_mov_b32_e32 v14, s15 ; GFX10-NEXT: v_mov_b32_e32 v14, s15
; GFX10-NEXT: v_mov_b32_e32 v15, s16 ; GFX10-NEXT: v_mov_b32_e32 v15, s16
; GFX10-NEXT: v_mov_b32_e32 v16, s17 ; GFX10-NEXT: v_mov_b32_e32 v16, s17
; GFX10-NEXT: v_mov_b32_e32 v17, s18 ; GFX10-NEXT: v_mov_b32_e32 v17, s18
; GFX10-NEXT: v_mov_b32_e32 v18, s19 ; GFX10-NEXT: v_mov_b32_e32 v18, s19
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 0, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 2, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 3, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 3, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 2, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 4, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 4, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 5, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 5, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 6, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 6, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 7, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 7, v2
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v0, s10
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s4 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v1, s10
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s4 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v0, s10 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s5
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v1, s10 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v0, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v0, s6
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v0, s7 ; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v0, s7
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v1, s6
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v1, s7 ; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v1, s7
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v0, s8 ; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v0, s8
; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v0, s9 ; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v0, s9
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v1, s8 ; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v1, s8
Show All 9 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: dyn_insertelement_v8f64_const_s_v_v: ; GFX11-LABEL: dyn_insertelement_v8f64_const_s_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_mov_b32 s14, 0 ; GFX11-NEXT: s_mov_b32 s14, 0
; GFX11-NEXT: s_mov_b32 s15, 0x40200000 ; GFX11-NEXT: s_mov_b32 s15, 0x40200000
; GFX11-NEXT: s_mov_b64 s[0:1], 1.0
; GFX11-NEXT: s_mov_b32 s13, 0x401c0000 ; GFX11-NEXT: s_mov_b32 s13, 0x401c0000
; GFX11-NEXT: s_mov_b32 s12, s14 ; GFX11-NEXT: s_mov_b32 s12, s14
; GFX11-NEXT: s_mov_b32 s11, 0x40180000 ; GFX11-NEXT: s_mov_b32 s11, 0x40180000
; GFX11-NEXT: s_mov_b32 s10, s14 ; GFX11-NEXT: s_mov_b32 s10, s14
; GFX11-NEXT: s_mov_b32 s9, 0x40140000 ; GFX11-NEXT: s_mov_b32 s9, 0x40140000
; GFX11-NEXT: s_mov_b32 s8, s14 ; GFX11-NEXT: s_mov_b32 s8, s14
; GFX11-NEXT: s_mov_b64 s[6:7], 4.0 ; GFX11-NEXT: s_mov_b64 s[6:7], 4.0
; GFX11-NEXT: s_mov_b32 s5, 0x40080000 ; GFX11-NEXT: s_mov_b32 s5, 0x40080000
; GFX11-NEXT: s_mov_b32 s4, s14 ; GFX11-NEXT: s_mov_b32 s4, s14
; GFX11-NEXT: s_mov_b64 s[2:3], 2.0 ; GFX11-NEXT: s_mov_b64 s[2:3], 2.0
; GFX11-NEXT: s_mov_b64 s[0:1], 1.0
; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14 ; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12 ; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10 ; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8 ; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6 ; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4 ; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2 ; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2 ; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v2
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v2
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v2
; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v0 :: v_dual_cndmask_b32 v8, v8, v1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v2
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v2
; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v0, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v0, s6
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0 ; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v0 :: v_dual_cndmask_b32 v6, v6, v1
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v1, s6
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v0, s0
; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v0 :: v_dual_cndmask_b32 v12, v12, v1 ; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v0, s1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v18, v18, v1, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s1
; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v0, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v0, s2
; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v1, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v0, s3
; GFX11-NEXT: v_dual_cndmask_b32 v15, v15, v0 :: v_dual_cndmask_b32 v16, v16, v1 ; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v1, s2
; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v1, s3
; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, v0, s4
; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5
; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v1, s4
; GFX11-NEXT: v_cndmask_b32_e64 v18, v18, v1, s5
; GFX11-NEXT: global_store_b128 v[0:1], v[3:6], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[3:6], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[7:10], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[7:10], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[11:14], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[11:14], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[15:18], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[15:18], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s12, s14 ; GFX10-NEXT: s_mov_b32 s12, s14
; GFX10-NEXT: s_mov_b32 s14, s16 ; GFX10-NEXT: s_mov_b32 s14, s16
; GFX10-NEXT: v_mov_b32_e32 v16, s15 ; GFX10-NEXT: v_mov_b32_e32 v16, s15
; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_mov_b32_e32 v15, s14 ; GFX10-NEXT: v_mov_b32_e32 v15, s14
; GFX10-NEXT: v_mov_b32_e32 v14, s13 ; GFX10-NEXT: v_mov_b32_e32 v14, s13
; GFX10-NEXT: v_mov_b32_e32 v13, s12 ; GFX10-NEXT: v_mov_b32_e32 v13, s12
; GFX10-NEXT: v_mov_b32_e32 v12, s11 ; GFX10-NEXT: v_mov_b32_e32 v12, s11
; GFX10-NEXT: v_mov_b32_e32 v11, s10 ; GFX10-NEXT: v_mov_b32_e32 v11, s10
; GFX10-NEXT: v_mov_b32_e32 v10, s9 ; GFX10-NEXT: v_mov_b32_e32 v10, s9
; GFX10-NEXT: v_mov_b32_e32 v9, s8 ; GFX10-NEXT: v_mov_b32_e32 v9, s8
; GFX10-NEXT: v_mov_b32_e32 v8, s7 ; GFX10-NEXT: v_mov_b32_e32 v8, s7
; GFX10-NEXT: v_mov_b32_e32 v7, s6 ; GFX10-NEXT: v_mov_b32_e32 v7, s6
; GFX10-NEXT: v_mov_b32_e32 v6, s5 ; GFX10-NEXT: v_mov_b32_e32 v6, s5
; GFX10-NEXT: v_mov_b32_e32 v5, s4 ; GFX10-NEXT: v_mov_b32_e32 v5, s4
; GFX10-NEXT: v_mov_b32_e32 v4, s3 ; GFX10-NEXT: v_mov_b32_e32 v4, s3
; GFX10-NEXT: v_mov_b32_e32 v3, s2 ; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v0 ; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s18, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s19, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 0, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 2, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s18, s0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s19, s0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 4, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 5, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 6, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 6, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 7, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 7, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s18, s3
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s18, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s19, s3
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s19, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, s18, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s18, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, s19, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s19, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s18, s0
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, s18, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, s19, s0
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, s19, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, s18, s1
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, s18, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v8, s19, s1
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, s19, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v9, s18, s2
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, s18, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v10, s19, s2
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, s19, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v11, s18, s4
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, s18, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v11, v12, s19, s4
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, s19, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v12, v13, s18, s5
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[1:4], off ; GFX10-NEXT: v_cndmask_b32_e64 v13, v14, s19, s5
; GFX10-NEXT: v_cndmask_b32_e64 v14, v15, s18, s6
; GFX10-NEXT: v_cndmask_b32_e64 v15, v16, s19, s6
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[5:8], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[9:12], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[13:16], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: dyn_insertelement_v8f64_s_s_v: ; GFX11-LABEL: dyn_insertelement_v8f64_s_s_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s3, s5 ; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s5, s7 ; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: s_mov_b32 s9, s11 ; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: s_mov_b32 s11, s13 ; GFX11-NEXT: s_mov_b32 s11, s13
; GFX11-NEXT: s_mov_b32 s13, s15 ; GFX11-NEXT: s_mov_b32 s13, s15
; GFX11-NEXT: s_mov_b32 s15, s17 ; GFX11-NEXT: s_mov_b32 s15, s17
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: s_mov_b32 s4, s6
; GFX11-NEXT: s_mov_b32 s6, s8 ; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s8, s10 ; GFX11-NEXT: s_mov_b32 s8, s10
; GFX11-NEXT: s_mov_b32 s10, s12 ; GFX11-NEXT: s_mov_b32 s10, s12
; GFX11-NEXT: s_mov_b32 s12, s14 ; GFX11-NEXT: s_mov_b32 s12, s14
; GFX11-NEXT: s_mov_b32 s14, s16 ; GFX11-NEXT: s_mov_b32 s14, s16
; GFX11-NEXT: v_dual_mov_b32 v16, s15 :: v_dual_mov_b32 v15, s14 ; GFX11-NEXT: v_dual_mov_b32 v16, s15 :: v_dual_mov_b32 v15, s14
; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_dual_mov_b32 v14, s13 :: v_dual_mov_b32 v13, s12 ; GFX11-NEXT: v_dual_mov_b32 v14, s13 :: v_dual_mov_b32 v13, s12
; GFX11-NEXT: v_dual_mov_b32 v12, s11 :: v_dual_mov_b32 v11, s10 ; GFX11-NEXT: v_dual_mov_b32 v12, s11 :: v_dual_mov_b32 v11, s10
; GFX11-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v9, s8 ; GFX11-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v9, s8
; GFX11-NEXT: v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v7, s6 ; GFX11-NEXT: v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v7, s6
; GFX11-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 ; GFX11-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4
; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2 ; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v0 ; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s18, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s19, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 0, v0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s18, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s19, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 5, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 6, v0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s18, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 7, v0
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s19, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s18, s3
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s19, s3
; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s18, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, s18, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s18, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v4, s19, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s19, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v5, s18, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, s19, s0
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, s18, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v6, v7, s18, s1
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s19, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v7, v8, s19, s1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v8, v9, s18, s2
; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, s19, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v9, v10, s19, s2
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s18, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v10, v11, s18, s4
; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, s19, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v11, v12, s19, s4
; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, s18, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v12, v13, s18, s5
; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, s19, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v13, v14, s19, s5
; GFX11-NEXT: global_store_b128 v[0:1], v[1:4], off dlc ; GFX11-NEXT: v_cndmask_b32_e64 v14, v15, s18, s6
; GFX11-NEXT: v_cndmask_b32_e64 v15, v16, s19, s6
; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[5:8], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[9:12], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[13:16], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
entry: entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx %insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1> %vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3> %vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5> %vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
▲ Show 20 Lines • Show All 313 Lines • ▼ Show 20 Lines
; GFX10-NEXT: v_mov_b32_e32 v10, s7 ; GFX10-NEXT: v_mov_b32_e32 v10, s7
; GFX10-NEXT: v_mov_b32_e32 v9, s6 ; GFX10-NEXT: v_mov_b32_e32 v9, s6
; GFX10-NEXT: v_mov_b32_e32 v8, s5 ; GFX10-NEXT: v_mov_b32_e32 v8, s5
; GFX10-NEXT: v_mov_b32_e32 v7, s4 ; GFX10-NEXT: v_mov_b32_e32 v7, s4
; GFX10-NEXT: v_mov_b32_e32 v6, s3 ; GFX10-NEXT: v_mov_b32_e32 v6, s3
; GFX10-NEXT: v_mov_b32_e32 v5, s2 ; GFX10-NEXT: v_mov_b32_e32 v5, s2
; GFX10-NEXT: v_mov_b32_e32 v4, s1 ; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: v_mov_b32_e32 v3, s0 ; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 2, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v2
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v0, s6
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v1, s6
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v0, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v0, s0
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s1
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v0, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v0, s2
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v0, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v0, s3
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v1, s2
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v1, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v1, s3
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v0, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v1, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v1, s4
Show All 22 Lines
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: s_mov_b32 s4, s6
; GFX11-NEXT: s_mov_b32 s6, s8 ; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s8, s10 ; GFX11-NEXT: s_mov_b32 s8, s10
; GFX11-NEXT: s_mov_b32 s10, s12 ; GFX11-NEXT: s_mov_b32 s10, s12
; GFX11-NEXT: s_mov_b32 s12, s14 ; GFX11-NEXT: s_mov_b32 s12, s14
; GFX11-NEXT: s_mov_b32 s14, s16 ; GFX11-NEXT: s_mov_b32 s14, s16
; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14 ; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12 ; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10 ; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8 ; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6 ; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4 ; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2 ; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2 ; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v2
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v2
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v2
; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v0 :: v_dual_cndmask_b32 v8, v8, v1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v2
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v2
; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v0, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v0, s6
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0 ; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v0 :: v_dual_cndmask_b32 v6, v6, v1
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v1, s6
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v0, s0
; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v0 :: v_dual_cndmask_b32 v12, v12, v1 ; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v0, s1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v18, v18, v1, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s1
; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v0, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v0, s2
; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v1, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v0, s3
; GFX11-NEXT: v_dual_cndmask_b32 v15, v15, v0 :: v_dual_cndmask_b32 v16, v16, v1 ; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v1, s2
; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v1, s3
; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, v0, s4
; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5
; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v1, s4
; GFX11-NEXT: v_cndmask_b32_e64 v18, v18, v1, s5
; GFX11-NEXT: global_store_b128 v[0:1], v[3:6], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[3:6], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[7:10], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[7:10], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[11:14], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[11:14], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[15:18], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[15:18], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
▲ Show 20 Lines • Show All 701 Lines • ▼ Show 20 Lines
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v9
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v9
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v9
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_v_v_add_1: ; GFX10-LABEL: dyn_insertelement_v8f32_v_v_v_add_1:
; GFX10PLUS: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: v_add_nc_u32_e32 v9, 1, v9 ; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v8, s0
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v8, s1
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v8, s2
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v8, s6
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v8, s3
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v8, s4
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v8, s5
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: dyn_insertelement_v8f32_v_v_v_add_1:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_add_nc_u32_e32 v9, 1, v9
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9
; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9
; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%idx.add = add i32 %idx, 1 %idx.add = add i32 %idx, 1
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add %insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v_add_7(<8 x float> %vec, float %val, i32 %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v_add_7(<8 x float> %vec, float %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_v_add_7: ; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_v_add_7:
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; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v9
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v9
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v9
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_v_v_add_7: ; GFX10-LABEL: dyn_insertelement_v8f32_v_v_v_add_7:
; GFX10PLUS: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: v_add_nc_u32_e32 v9, 7, v9 ; GFX10-NEXT: v_add_nc_u32_e32 v9, 7, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v8, s0
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v8, s1
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v8, s2
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v8, s6
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v8, s3
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v8, s4
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v8, s5
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: dyn_insertelement_v8f32_v_v_v_add_7:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_add_nc_u32_e32 v9, 7, v9
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9
; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9
; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%idx.add = add i32 %idx, 7 %idx.add = add i32 %idx, 7
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add %insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %vec, double inreg %val, i32 inreg %idx) { define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %vec, double inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_s_s_s_add_1: ; GPRIDX-LABEL: dyn_insertelement_v8f64_s_s_s_add_1:
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; GFX10-NEXT: s_mov_b32 s13, s15 ; GFX10-NEXT: s_mov_b32 s13, s15
; GFX10-NEXT: s_mov_b32 s14, s16 ; GFX10-NEXT: s_mov_b32 s14, s16
; GFX10-NEXT: s_mov_b32 s15, s17 ; GFX10-NEXT: s_mov_b32 s15, s17
; GFX10-NEXT: s_movreld_b64 s[2:3], s[18:19] ; GFX10-NEXT: s_movreld_b64 s[2:3], s[18:19]
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: v_mov_b32_e32 v4, s4
; GFX10-NEXT: v_mov_b32_e32 v5, s5
; GFX10-NEXT: v_mov_b32_e32 v6, s6
; GFX10-NEXT: v_mov_b32_e32 v7, s7
; GFX10-NEXT: v_mov_b32_e32 v8, s8
; GFX10-NEXT: v_mov_b32_e32 v9, s9
; GFX10-NEXT: v_mov_b32_e32 v10, s10
; GFX10-NEXT: v_mov_b32_e32 v11, s11
; GFX10-NEXT: v_mov_b32_e32 v12, s12
; GFX10-NEXT: v_mov_b32_e32 v13, s13
; GFX10-NEXT: v_mov_b32_e32 v14, s14
; GFX10-NEXT: v_mov_b32_e32 v15, s15
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: v_mov_b32_e32 v2, s6
; GFX10-NEXT: v_mov_b32_e32 v3, s7
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GFX10-NEXT: v_mov_b32_e32 v0, s8
; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: v_mov_b32_e32 v2, s10
; GFX10-NEXT: v_mov_b32_e32 v3, s11
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GFX10-NEXT: v_mov_b32_e32 v0, s12
; GFX10-NEXT: v_mov_b32_e32 v1, s13
; GFX10-NEXT: v_mov_b32_e32 v2, s14
; GFX10-NEXT: v_mov_b32_e32 v3, s15
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: dyn_insertelement_v8f64_s_s_s_add_1: ; GFX11-LABEL: dyn_insertelement_v8f64_s_s_s_add_1:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: s_mov_b32 s2, s4
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; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v18, s8 ; GFX10-NEXT: v_mov_b32_e32 v17, s8
; GFX10-NEXT: v_mov_b32_e32 v10, s0 ; GFX10-NEXT: v_mov_b32_e32 v16, s7
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_mov_b32_e32 v15, s6
; GFX10-NEXT: v_mov_b32_e32 v11, s1 ; GFX10-NEXT: v_mov_b32_e32 v14, s5
; GFX10-NEXT: v_mov_b32_e32 v12, s2 ; GFX10-NEXT: v_mov_b32_e32 v13, s4
; GFX10-NEXT: v_mov_b32_e32 v13, s3 ; GFX10-NEXT: v_mov_b32_e32 v12, s3
; GFX10-NEXT: v_mov_b32_e32 v14, s4 ; GFX10-NEXT: v_mov_b32_e32 v11, s2
; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v0, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v10, s1
; GFX10-NEXT: v_mov_b32_e32 v9, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 0, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX10-NEXT: v_mov_b32_e32 v15, s5 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX10-NEXT: v_mov_b32_e32 v16, s6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v1
; GFX10-NEXT: v_mov_b32_e32 v17, s7 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v1
; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v12, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 8, v1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v13, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s7
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v10, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v11, v0, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v12, v0, s1
; GFX10-NEXT: v_cndmask_b32_e32 v5, v15, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v13, v0, s2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v14, v0, s3
; GFX10-NEXT: v_cndmask_b32_e32 v6, v16, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, v15, v0, s4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v16, v0, s5
; GFX10-NEXT: v_cndmask_b32_e32 v7, v17, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v8, v17, v0, s6
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v1 ; GFX10-NEXT: v_mov_b32_e32 v0, v9
; GFX10-NEXT: v_mov_b32_e32 v1, v9
; GFX10-NEXT: v_cndmask_b32_e32 v8, v18, v0, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, v10
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v9f32_s_v_v: ; GFX11-LABEL: dyn_insertelement_v9f32_s_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: s_mov_b32 s4, s6
; GFX11-NEXT: s_mov_b32 s6, s8 ; GFX11-NEXT: s_mov_b32 s6, s8
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; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v10 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v10
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v10 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v10
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 8, v10 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 8, v10
; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: dyn_insertelement_v9f32_v_v_v: ; GFX10-LABEL: dyn_insertelement_v9f32_v_v_v:
; GFX10PLUS: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v10 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v10
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v10
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v10
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v10 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v10
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v10
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v10 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v10
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 8, v10
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v10 ; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 0, v10
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v10 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v9, s0
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v9, s1
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v10 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v9, s2
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v9, s7
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v10 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v9, s3
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v9, s4
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v10 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v9, s5
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v9, s6
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: dyn_insertelement_v9f32_v_v_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v10
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v10
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v10
; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v10
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v10
; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v10
; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v10
; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v10
; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <9 x float> %vec, float %val, i32 %idx %insert = insertelement <9 x float> %vec, float %val, i32 %idx
ret <9 x float> %insert ret <9 x float> %insert
} }
define amdgpu_ps <10 x float> @dyn_insertelement_v10f32_s_v_s(<10 x float> inreg %vec, float %val, i32 inreg %idx) { define amdgpu_ps <10 x float> @dyn_insertelement_v10f32_s_v_s(<10 x float> inreg %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v10f32_s_v_s: ; GPRIDX-LABEL: dyn_insertelement_v10f32_s_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: v_mov_b32_e32 v19, s9 ; GFX10-NEXT: v_mov_b32_e32 v19, s9
; GFX10-NEXT: v_mov_b32_e32 v10, s0 ; GFX10-NEXT: v_mov_b32_e32 v18, s8
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_mov_b32_e32 v17, s7
; GFX10-NEXT: v_mov_b32_e32 v11, s1 ; GFX10-NEXT: v_mov_b32_e32 v16, s6
; GFX10-NEXT: v_mov_b32_e32 v12, s2 ; GFX10-NEXT: v_mov_b32_e32 v15, s5
; GFX10-NEXT: v_mov_b32_e32 v13, s3
; GFX10-NEXT: v_mov_b32_e32 v14, s4 ; GFX10-NEXT: v_mov_b32_e32 v14, s4
; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v0, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v13, s3
; GFX10-NEXT: v_mov_b32_e32 v12, s2
; GFX10-NEXT: v_mov_b32_e32 v11, s1
; GFX10-NEXT: v_mov_b32_e32 v10, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 0, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX10-NEXT: v_mov_b32_e32 v15, s5 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX10-NEXT: v_mov_b32_e32 v16, s6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v1
; GFX10-NEXT: v_mov_b32_e32 v17, s7 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v1
; GFX10-NEXT: v_mov_b32_e32 v18, s8 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v1
; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v12, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 8, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 9, v1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v13, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v0, s8
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v11, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v12, v0, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v13, v0, s1
; GFX10-NEXT: v_cndmask_b32_e32 v5, v15, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v14, v0, s2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v15, v0, s3
; GFX10-NEXT: v_cndmask_b32_e32 v6, v16, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, v16, v0, s4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v17, v0, s5
; GFX10-NEXT: v_cndmask_b32_e32 v7, v17, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v8, v18, v0, s6
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v19, v0, s7
; GFX10-NEXT: v_cndmask_b32_e32 v8, v18, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v1
; GFX10-NEXT: v_mov_b32_e32 v1, v11
; GFX10-NEXT: v_cndmask_b32_e32 v9, v19, v0, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, v10 ; GFX10-NEXT: v_mov_b32_e32 v0, v10
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v10f32_s_v_v: ; GFX11-LABEL: dyn_insertelement_v10f32_s_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s3, s5 ; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s5, s7 ; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: s_mov_b32 s9, s11 ; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: s_mov_b32 s4, s6
; GFX11-NEXT: s_mov_b32 s6, s8 ; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s8, s10 ; GFX11-NEXT: s_mov_b32 s8, s10
; GFX11-NEXT: v_dual_mov_b32 v19, s9 :: v_dual_mov_b32 v18, s8 ; GFX11-NEXT: v_dual_mov_b32 v19, s9 :: v_dual_mov_b32 v18, s8
; GFX11-NEXT: v_dual_mov_b32 v11, s1 :: v_dual_mov_b32 v10, s0 ; GFX11-NEXT: v_dual_mov_b32 v11, s1 :: v_dual_mov_b32 v10, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-NEXT: v_dual_mov_b32 v13, s3 :: v_dual_mov_b32 v12, s2 ; GFX11-NEXT: v_dual_mov_b32 v13, s3 :: v_dual_mov_b32 v12, s2
; GFX11-NEXT: v_dual_mov_b32 v15, s5 :: v_dual_mov_b32 v14, s4 ; GFX11-NEXT: v_dual_mov_b32 v15, s5 :: v_dual_mov_b32 v14, s4
; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11-NEXT: v_dual_mov_b32 v17, s7 :: v_dual_mov_b32 v16, s6 ; GFX11-NEXT: v_dual_mov_b32 v17, s7 :: v_dual_mov_b32 v16, s6
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 8, v1
; GFX11-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
; GFX11-NEXT: v_cndmask_b32_e64 v8, v18, v0, s0
; GFX11-NEXT: v_cndmask_b32_e32 v2, v12, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v2, v12, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
; GFX11-NEXT: v_cndmask_b32_e32 v3, v13, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v3, v13, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
; GFX11-NEXT: v_cndmask_b32_e32 v4, v14, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v4, v14, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
; GFX11-NEXT: v_cndmask_b32_e32 v5, v15, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v5, v15, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
; GFX11-NEXT: v_cndmask_b32_e32 v6, v16, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v6, v16, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
; GFX11-NEXT: v_cndmask_b32_e32 v7, v17, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v7, v17, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v1
; GFX11-NEXT: v_cndmask_b32_e32 v8, v18, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v1
; GFX11-NEXT: v_mov_b32_e32 v1, v11 ; GFX11-NEXT: v_mov_b32_e32 v1, v11
; GFX11-NEXT: v_dual_cndmask_b32 v9, v19, v0 :: v_dual_mov_b32 v0, v10 ; GFX11-NEXT: v_dual_cndmask_b32 v9, v19, v0 :: v_dual_mov_b32 v0, v10
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <10 x float> %vec, float %val, i32 %idx %insert = insertelement <10 x float> %vec, float %val, i32 %idx
ret <10 x float> %insert ret <10 x float> %insert
} }
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; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v11 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v11
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 8, v11 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 8, v11
; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 9, v11 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 9, v11
; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: dyn_insertelement_v10f32_v_v_v: ; GFX10-LABEL: dyn_insertelement_v10f32_v_v_v:
; GFX10PLUS: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v11 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v11
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v11
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v11
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v11 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v11
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v11
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v11 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v11
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 8, v11
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v11 ; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 9, v11
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 0, v11
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v11 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc_lo
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v11 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v10, s1
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v10, s2
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v11 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v10, s8
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v10, s3
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v11 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s4
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v10, s5
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v11 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s6
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v10, s7
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: dyn_insertelement_v10f32_v_v_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v11
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v11
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v11
; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v11
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v11
; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v11
; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v11
; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v11
; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v11
; GFX11-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc_lo
; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <10 x float> %vec, float %val, i32 %idx %insert = insertelement <10 x float> %vec, float %val, i32 %idx
ret <10 x float> %insert ret <10 x float> %insert
} }
define amdgpu_ps <11 x float> @dyn_insertelement_v11f32_s_v_s(<11 x float> inreg %vec, float %val, i32 inreg %idx) { define amdgpu_ps <11 x float> @dyn_insertelement_v11f32_s_v_s(<11 x float> inreg %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v11f32_s_v_s: ; GPRIDX-LABEL: dyn_insertelement_v11f32_s_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
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; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: v_mov_b32_e32 v22, s10 ; GFX10-NEXT: v_mov_b32_e32 v21, s10
; GFX10-NEXT: v_mov_b32_e32 v12, s0 ; GFX10-NEXT: v_mov_b32_e32 v20, s9
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_mov_b32_e32 v19, s8
; GFX10-NEXT: v_mov_b32_e32 v13, s1 ; GFX10-NEXT: v_mov_b32_e32 v18, s7
; GFX10-NEXT: v_mov_b32_e32 v14, s2 ; GFX10-NEXT: v_mov_b32_e32 v17, s6
; GFX10-NEXT: v_mov_b32_e32 v15, s3 ; GFX10-NEXT: v_mov_b32_e32 v16, s5
; GFX10-NEXT: v_mov_b32_e32 v16, s4 ; GFX10-NEXT: v_mov_b32_e32 v15, s4
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v14, s3
; GFX10-NEXT: v_mov_b32_e32 v13, s2
; GFX10-NEXT: v_mov_b32_e32 v12, s1
; GFX10-NEXT: v_mov_b32_e32 v11, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 0, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX10-NEXT: v_mov_b32_e32 v17, s5 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX10-NEXT: v_mov_b32_e32 v18, s6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v1
; GFX10-NEXT: v_mov_b32_e32 v19, s7 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v1
; GFX10-NEXT: v_mov_b32_e32 v20, s8 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v1
; GFX10-NEXT: v_cndmask_b32_e32 v11, v13, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v1
; GFX10-NEXT: v_mov_b32_e32 v21, s9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 8, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v14, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 9, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 10, v1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v15, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v0, s9
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v12, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v16, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v13, v0, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v14, v0, s1
; GFX10-NEXT: v_cndmask_b32_e32 v5, v17, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v15, v0, s2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v16, v0, s3
; GFX10-NEXT: v_cndmask_b32_e32 v6, v18, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, v17, v0, s4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v18, v0, s5
; GFX10-NEXT: v_cndmask_b32_e32 v7, v19, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v8, v19, v0, s6
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v20, v0, s7
; GFX10-NEXT: v_cndmask_b32_e32 v8, v20, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v10, v21, v0, s8
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v1 ; GFX10-NEXT: v_mov_b32_e32 v0, v11
; GFX10-NEXT: v_cndmask_b32_e32 v9, v21, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v1
; GFX10-NEXT: v_mov_b32_e32 v1, v11
; GFX10-NEXT: v_cndmask_b32_e32 v10, v22, v0, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, v12
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v11f32_s_v_v: ; GFX11-LABEL: dyn_insertelement_v11f32_s_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: s_mov_b32 s4, s6
; GFX11-NEXT: s_mov_b32 s6, s8 ; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s8, s10 ; GFX11-NEXT: s_mov_b32 s8, s10
; GFX11-NEXT: s_mov_b32 s10, s12 ; GFX11-NEXT: s_mov_b32 s10, s12
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s3, s5 ; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s5, s7 ; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: s_mov_b32 s9, s11 ; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v21, s9 ; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v21, s9
; GFX11-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v13, s1 ; GFX11-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v13, s1
; GFX11-NEXT: v_mov_b32_e32 v12, s0 ; GFX11-NEXT: v_mov_b32_e32 v12, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-NEXT: v_dual_mov_b32 v16, s4 :: v_dual_mov_b32 v15, s3 ; GFX11-NEXT: v_dual_mov_b32 v16, s4 :: v_dual_mov_b32 v15, s3
; GFX11-NEXT: v_dual_mov_b32 v18, s6 :: v_dual_mov_b32 v17, s5 ; GFX11-NEXT: v_dual_mov_b32 v18, s6 :: v_dual_mov_b32 v17, s5
; GFX11-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11-NEXT: v_dual_mov_b32 v20, s8 :: v_dual_mov_b32 v19, s7 ; GFX11-NEXT: v_dual_mov_b32 v20, s8 :: v_dual_mov_b32 v19, s7
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 9, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 10, v1
; GFX11-NEXT: v_cndmask_b32_e32 v11, v13, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v11, v13, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 7, v1
; GFX11-NEXT: v_cndmask_b32_e64 v9, v21, v0, s0
; GFX11-NEXT: v_cndmask_b32_e64 v10, v22, v0, s1
; GFX11-NEXT: v_cndmask_b32_e32 v2, v14, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v2, v14, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
; GFX11-NEXT: v_cndmask_b32_e64 v7, v19, v0, s2
; GFX11-NEXT: v_cndmask_b32_e32 v3, v15, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v3, v15, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
; GFX11-NEXT: v_cndmask_b32_e32 v4, v16, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v4, v16, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
; GFX11-NEXT: v_cndmask_b32_e32 v5, v17, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v5, v17, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
; GFX11-NEXT: v_cndmask_b32_e32 v6, v18, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v6, v18, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
; GFX11-NEXT: v_cndmask_b32_e32 v7, v19, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v1
; GFX11-NEXT: v_cndmask_b32_e32 v8, v20, v0, vcc_lo ; GFX11-NEXT: v_dual_mov_b32 v1, v11 :: v_dual_cndmask_b32 v8, v20, v0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v1
; GFX11-NEXT: v_cndmask_b32_e32 v9, v21, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v1
; GFX11-NEXT: v_dual_mov_b32 v1, v11 :: v_dual_cndmask_b32 v10, v22, v0
; GFX11-NEXT: v_mov_b32_e32 v0, v12 ; GFX11-NEXT: v_mov_b32_e32 v0, v12
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <11 x float> %vec, float %val, i32 %idx %insert = insertelement <11 x float> %vec, float %val, i32 %idx
ret <11 x float> %insert ret <11 x float> %insert
} }
define amdgpu_ps <11 x float> @dyn_insertelement_v11f32_v_v_s(<11 x float> %vec, float %val, i32 inreg %idx) { define amdgpu_ps <11 x float> @dyn_insertelement_v11f32_v_v_s(<11 x float> %vec, float %val, i32 inreg %idx) {
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; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 8, v12 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 8, v12
; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 9, v12 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 9, v12
; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 10, v12 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 10, v12
; GPRIDX-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: dyn_insertelement_v11f32_v_v_v: ; GFX10-LABEL: dyn_insertelement_v11f32_v_v_v:
; GFX10PLUS: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v11, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v12
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v12
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v12
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v12
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v12
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v12
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 8, v12
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 9, v12
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 10, v12
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 0, v12
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v12 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v11, s0
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s1
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v12 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v11, s2
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v11, s9
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v12 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v11, s3
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v11, s4
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v12 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s5
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v11, s6
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v12 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v11, s7
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v11, s8
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: dyn_insertelement_v11f32_v_v_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v11, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12
; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v12
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v12
; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v12
; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v12
; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v12
; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v12
; GFX11-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v12
; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo
; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <11 x float> %vec, float %val, i32 %idx %insert = insertelement <11 x float> %vec, float %val, i32 %idx
ret <11 x float> %insert ret <11 x float> %insert
} }
define amdgpu_ps <12 x float> @dyn_insertelement_v12f32_s_v_s(<12 x float> inreg %vec, float %val, i32 inreg %idx) { define amdgpu_ps <12 x float> @dyn_insertelement_v12f32_s_v_s(<12 x float> inreg %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v12f32_s_v_s: ; GPRIDX-LABEL: dyn_insertelement_v12f32_s_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
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; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: v_mov_b32_e32 v23, s11 ; GFX10-NEXT: v_mov_b32_e32 v23, s11
; GFX10-NEXT: v_mov_b32_e32 v12, s0 ; GFX10-NEXT: v_mov_b32_e32 v22, s10
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_mov_b32_e32 v21, s9
; GFX10-NEXT: v_mov_b32_e32 v13, s1 ; GFX10-NEXT: v_mov_b32_e32 v20, s8
; GFX10-NEXT: v_mov_b32_e32 v14, s2 ; GFX10-NEXT: v_mov_b32_e32 v19, s7
; GFX10-NEXT: v_mov_b32_e32 v15, s3 ; GFX10-NEXT: v_mov_b32_e32 v18, s6
; GFX10-NEXT: v_mov_b32_e32 v17, s5
; GFX10-NEXT: v_mov_b32_e32 v16, s4 ; GFX10-NEXT: v_mov_b32_e32 v16, s4
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v15, s3
; GFX10-NEXT: v_mov_b32_e32 v14, s2
; GFX10-NEXT: v_mov_b32_e32 v13, s1
; GFX10-NEXT: v_mov_b32_e32 v12, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 0, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX10-NEXT: v_mov_b32_e32 v17, s5 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX10-NEXT: v_mov_b32_e32 v18, s6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v1
; GFX10-NEXT: v_mov_b32_e32 v19, s7 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v1
; GFX10-NEXT: v_mov_b32_e32 v20, s8 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v1
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v1
; GFX10-NEXT: v_mov_b32_e32 v21, s9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 8, v1
; GFX10-NEXT: v_mov_b32_e32 v22, s10 ; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 9, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v14, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 10, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 11, v1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v15, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v0, s10
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v13, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v16, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v14, v0, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v15, v0, s1
; GFX10-NEXT: v_cndmask_b32_e32 v5, v17, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v16, v0, s2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v17, v0, s3
; GFX10-NEXT: v_cndmask_b32_e32 v6, v18, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, v18, v0, s4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v19, v0, s5
; GFX10-NEXT: v_cndmask_b32_e32 v7, v19, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v8, v20, v0, s6
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v21, v0, s7
; GFX10-NEXT: v_cndmask_b32_e32 v8, v20, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v10, v22, v0, s8
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v11, v23, v0, s9
; GFX10-NEXT: v_cndmask_b32_e32 v9, v21, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v1
; GFX10-NEXT: v_cndmask_b32_e32 v10, v22, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 11, v1
; GFX10-NEXT: v_mov_b32_e32 v1, v13
; GFX10-NEXT: v_cndmask_b32_e32 v11, v23, v0, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, v12 ; GFX10-NEXT: v_mov_b32_e32 v0, v12
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v12f32_s_v_v: ; GFX11-LABEL: dyn_insertelement_v12f32_s_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s3, s5 ; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s5, s7 ; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: s_mov_b32 s9, s11 ; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: s_mov_b32 s11, s13 ; GFX11-NEXT: s_mov_b32 s11, s13
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: s_mov_b32 s4, s6
; GFX11-NEXT: s_mov_b32 s6, s8 ; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s8, s10 ; GFX11-NEXT: s_mov_b32 s8, s10
; GFX11-NEXT: s_mov_b32 s10, s12 ; GFX11-NEXT: s_mov_b32 s10, s12
; GFX11-NEXT: v_dual_mov_b32 v23, s11 :: v_dual_mov_b32 v22, s10 ; GFX11-NEXT: v_dual_mov_b32 v23, s11 :: v_dual_mov_b32 v22, s10
; GFX11-NEXT: v_dual_mov_b32 v13, s1 :: v_dual_mov_b32 v12, s0 ; GFX11-NEXT: v_dual_mov_b32 v13, s1 :: v_dual_mov_b32 v12, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-NEXT: v_dual_mov_b32 v15, s3 :: v_dual_mov_b32 v14, s2 ; GFX11-NEXT: v_dual_mov_b32 v15, s3 :: v_dual_mov_b32 v14, s2
; GFX11-NEXT: v_dual_mov_b32 v17, s5 :: v_dual_mov_b32 v16, s4 ; GFX11-NEXT: v_dual_mov_b32 v17, s5 :: v_dual_mov_b32 v16, s4
; GFX11-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11-NEXT: v_dual_mov_b32 v19, s7 :: v_dual_mov_b32 v18, s6
; GFX11-NEXT: v_dual_mov_b32 v21, s9 :: v_dual_mov_b32 v20, s8 ; GFX11-NEXT: v_dual_mov_b32 v21, s9 :: v_dual_mov_b32 v20, s8
; GFX11-NEXT: v_dual_mov_b32 v19, s7 :: v_dual_mov_b32 v18, s6
; GFX11-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 8, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 9, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 10, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 11, v1
; GFX11-NEXT: v_cndmask_b32_e32 v2, v14, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v2, v14, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v1
; GFX11-NEXT: v_cndmask_b32_e64 v8, v20, v0, s0
; GFX11-NEXT: v_cndmask_b32_e64 v9, v21, v0, s1
; GFX11-NEXT: v_cndmask_b32_e64 v10, v22, v0, s2
; GFX11-NEXT: v_cndmask_b32_e32 v3, v15, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v3, v15, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
; GFX11-NEXT: v_cndmask_b32_e64 v6, v18, v0, s4
; GFX11-NEXT: v_cndmask_b32_e64 v11, v23, v0, s3
; GFX11-NEXT: v_cndmask_b32_e32 v4, v16, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v4, v16, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
; GFX11-NEXT: v_cndmask_b32_e32 v5, v17, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v5, v17, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
; GFX11-NEXT: v_cndmask_b32_e32 v6, v18, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
; GFX11-NEXT: v_cndmask_b32_e32 v7, v19, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v1
; GFX11-NEXT: v_cndmask_b32_e32 v8, v20, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v1
; GFX11-NEXT: v_cndmask_b32_e32 v9, v21, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v1
; GFX11-NEXT: v_cndmask_b32_e32 v10, v22, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 11, v1
; GFX11-NEXT: v_mov_b32_e32 v1, v13 ; GFX11-NEXT: v_mov_b32_e32 v1, v13
; GFX11-NEXT: v_dual_cndmask_b32 v11, v23, v0 :: v_dual_mov_b32 v0, v12 ; GFX11-NEXT: v_dual_cndmask_b32 v7, v19, v0 :: v_dual_mov_b32 v0, v12
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <12 x float> %vec, float %val, i32 %idx %insert = insertelement <12 x float> %vec, float %val, i32 %idx
ret <12 x float> %insert ret <12 x float> %insert
} }
define amdgpu_ps <12 x float> @dyn_insertelement_v12f32_v_v_s(<12 x float> %vec, float %val, i32 inreg %idx) { define amdgpu_ps <12 x float> @dyn_insertelement_v12f32_v_v_s(<12 x float> %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v12f32_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v12f32_v_v_s:
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; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 9, v13 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 9, v13
; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 10, v13 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 10, v13
; GPRIDX-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 11, v13 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 11, v13
; GPRIDX-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: dyn_insertelement_v12f32_v_v_v: ; GFX10-LABEL: dyn_insertelement_v12f32_v_v_v:
; GFX10PLUS: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v13 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v13
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v13
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v13
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v13 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v13
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v13
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v13 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v13
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 8, v13
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v13 ; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 9, v13
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 10, v13
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v13 ; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 11, v13
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 0, v13
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v13 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc_lo
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v12, s0
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v13 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v12, s1
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v12, s2
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v13 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v12, s10
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v12, s3
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v13 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v12, s4
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v12, s5
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v13 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v12, s6
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v12, s7
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 11, v13 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v12, s8
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v12, s9
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: dyn_insertelement_v12f32_v_v_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v13
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v13
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v13
; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v13
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v13
; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v13
; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v13
; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v13
; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v13
; GFX11-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v13
; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 11, v13
; GFX11-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc_lo
; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <12 x float> %vec, float %val, i32 %idx %insert = insertelement <12 x float> %vec, float %val, i32 %idx
ret <12 x float> %insert ret <12 x float> %insert
} }
define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_s_s(<16 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) { define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_s_s(<16 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v16i32_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v16i32_s_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
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; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_mov_b32_e32 v13, s6 ; GFX10-NEXT: v_mov_b32_e32 v13, s6
; GFX10-NEXT: v_mov_b32_e32 v7, s0 ; GFX10-NEXT: v_mov_b32_e32 v12, s5
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 0
; GFX10-NEXT: v_mov_b32_e32 v8, s1
; GFX10-NEXT: v_mov_b32_e32 v9, s2
; GFX10-NEXT: v_mov_b32_e32 v10, s3
; GFX10-NEXT: v_mov_b32_e32 v11, s4 ; GFX10-NEXT: v_mov_b32_e32 v11, s4
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v10, s3
; GFX10-NEXT: v_mov_b32_e32 v9, s2
; GFX10-NEXT: v_mov_b32_e32 v8, s1
; GFX10-NEXT: v_mov_b32_e32 v7, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, s9, 0
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 1 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 1
; GFX10-NEXT: v_mov_b32_e32 v12, s5 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, 2
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s9, 3
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s9, 4
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, s9, 5
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, s9, 6
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v0, s5
; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v9, v0, s0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v9, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v10, v0, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 3 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v11, v0, s2
; GFX10-NEXT: v_cndmask_b32_e32 v3, v10, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v12, v0, s3
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 4 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v13, v0, s4
; GFX10-NEXT: v_cndmask_b32_e32 v4, v11, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 5
; GFX10-NEXT: v_cndmask_b32_e32 v5, v12, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 6
; GFX10-NEXT: v_cndmask_b32_e32 v6, v13, v0, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, v7 ; GFX10-NEXT: v_mov_b32_e32 v0, v7
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v7f32_s_v_s: ; GFX11-LABEL: dyn_insertelement_v7f32_s_v_s:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: s_mov_b32 s4, s6
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; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_mov_b32_e32 v14, s6 ; GFX10-NEXT: v_mov_b32_e32 v13, s6
; GFX10-NEXT: v_mov_b32_e32 v8, s0 ; GFX10-NEXT: v_mov_b32_e32 v12, s5
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_mov_b32_e32 v11, s4
; GFX10-NEXT: v_mov_b32_e32 v9, s1 ; GFX10-NEXT: v_mov_b32_e32 v10, s3
; GFX10-NEXT: v_mov_b32_e32 v10, s2 ; GFX10-NEXT: v_mov_b32_e32 v9, s2
; GFX10-NEXT: v_mov_b32_e32 v11, s3 ; GFX10-NEXT: v_mov_b32_e32 v8, s1
; GFX10-NEXT: v_mov_b32_e32 v12, s4 ; GFX10-NEXT: v_mov_b32_e32 v7, s0
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX10-NEXT: v_mov_b32_e32 v13, s5 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX10-NEXT: v_cndmask_b32_e32 v7, v9, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v0, s5
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v9, v0, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v10, v0, s1
; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v11, v0, s2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v12, v0, s3
; GFX10-NEXT: v_mov_b32_e32 v1, v7 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v13, v0, s4
; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v0, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v0, v7
; GFX10-NEXT: v_mov_b32_e32 v0, v8
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v7f32_s_v_v: ; GFX11-LABEL: dyn_insertelement_v7f32_s_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: s_mov_b32 s4, s6
; GFX11-NEXT: s_mov_b32 s6, s8 ; GFX11-NEXT: s_mov_b32 s6, s8
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; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v8 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v8
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v8 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v8
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v8 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v8
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: dyn_insertelement_v7f32_v_v_v: ; GFX10-LABEL: dyn_insertelement_v7f32_v_v_v:
; GFX10PLUS: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v8
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v8
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v8
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8 ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v8
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v8
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v8
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v7, s0
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v7, s2
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v7, s5
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v7, s3
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v7, s4
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: dyn_insertelement_v7f32_v_v_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8
; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8
; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8
; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx %insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert ret <7 x float> %insert
} }
define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_s_s(<7 x double> inreg %vec, double inreg %val, i32 inreg %idx) { define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_s_s(<7 x double> inreg %vec, double inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7f64_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v7f64_s_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
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; GFX10-NEXT: v_mov_b32_e32 v10, s7 ; GFX10-NEXT: v_mov_b32_e32 v10, s7
; GFX10-NEXT: v_mov_b32_e32 v9, s6 ; GFX10-NEXT: v_mov_b32_e32 v9, s6
; GFX10-NEXT: v_mov_b32_e32 v8, s5 ; GFX10-NEXT: v_mov_b32_e32 v8, s5
; GFX10-NEXT: v_mov_b32_e32 v7, s4 ; GFX10-NEXT: v_mov_b32_e32 v7, s4
; GFX10-NEXT: v_mov_b32_e32 v6, s3 ; GFX10-NEXT: v_mov_b32_e32 v6, s3
; GFX10-NEXT: v_mov_b32_e32 v5, s2 ; GFX10-NEXT: v_mov_b32_e32 v5, s2
; GFX10-NEXT: v_mov_b32_e32 v4, s1 ; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: v_mov_b32_e32 v3, s0 ; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 6, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v2
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v2
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v2
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v2
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v1, s0
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s1
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v1, s2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, v0, s5
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v7, v0, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v9, v0, s1
; GFX10-NEXT: v_readfirstlane_b32 s2, v5 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v11, v0, s2
; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v11, v13, v0, s3
; GFX10-NEXT: v_cndmask_b32_e32 v2, v12, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v15, v0, s4
; GFX10-NEXT: v_readfirstlane_b32 s3, v6 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v12, v13, v0, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v13, v14, v1, s3
; GFX10-NEXT: v_cndmask_b32_e64 v13, v14, v1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v16, v1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v0, v15, v0, s1 ; GFX10-NEXT: v_readfirstlane_b32 s0, v2
; GFX10-NEXT: v_cndmask_b32_e64 v1, v16, v1, s1 ; GFX10-NEXT: v_readfirstlane_b32 s2, v3
; GFX10-NEXT: v_readfirstlane_b32 s0, v3
; GFX10-NEXT: v_readfirstlane_b32 s1, v4 ; GFX10-NEXT: v_readfirstlane_b32 s1, v4
; GFX10-NEXT: v_readfirstlane_b32 s4, v7 ; GFX10-NEXT: v_readfirstlane_b32 s3, v6
; GFX10-NEXT: v_readfirstlane_b32 s4, v5
; GFX10-NEXT: v_readfirstlane_b32 s5, v8 ; GFX10-NEXT: v_readfirstlane_b32 s5, v8
; GFX10-NEXT: v_readfirstlane_b32 s6, v9 ; GFX10-NEXT: v_readfirstlane_b32 s6, v7
; GFX10-NEXT: v_readfirstlane_b32 s7, v10 ; GFX10-NEXT: v_readfirstlane_b32 s7, v10
; GFX10-NEXT: v_readfirstlane_b32 s8, v11 ; GFX10-NEXT: v_readfirstlane_b32 s8, v9
; GFX10-NEXT: v_readfirstlane_b32 s9, v2 ; GFX10-NEXT: v_readfirstlane_b32 s9, v12
; GFX10-NEXT: v_readfirstlane_b32 s10, v12 ; GFX10-NEXT: v_readfirstlane_b32 s10, v11
; GFX10-NEXT: v_readfirstlane_b32 s11, v13 ; GFX10-NEXT: v_readfirstlane_b32 s11, v13
; GFX10-NEXT: v_readfirstlane_b32 s12, v0 ; GFX10-NEXT: v_readfirstlane_b32 s12, v0
; GFX10-NEXT: v_readfirstlane_b32 s13, v1 ; GFX10-NEXT: v_readfirstlane_b32 s13, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v7f64_s_v_v: ; GFX11-LABEL: dyn_insertelement_v7f64_s_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: s_mov_b32 s0, s2
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; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12 ; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10 ; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8 ; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6 ; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4 ; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2 ; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0 ; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 6, v2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 1, v2
; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1 ; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s1
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v5, v0, s5
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v5, v7, v0, s0
; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v0 :: v_dual_cndmask_b32 v8, v8, v1 ; GFX11-NEXT: v_cndmask_b32_e64 v7, v9, v0, s1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v9, v11, v0, s2
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v11, v13, v0, s3
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v0, v15, v0, s4
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s5
; GFX11-NEXT: v_readfirstlane_b32 s2, v5 ; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v1, s2
; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v0 :: v_dual_cndmask_b32 v2, v12, v1 ; GFX11-NEXT: v_cndmask_b32_e64 v13, v14, v1, s3
; GFX11-NEXT: v_readfirstlane_b32 s3, v6 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v16, v1, s4
; GFX11-NEXT: v_cndmask_b32_e64 v12, v13, v0, s0
; GFX11-NEXT: v_cndmask_b32_e64 v13, v14, v1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v15, v0, s1
; GFX11-NEXT: v_cndmask_b32_e64 v1, v16, v1, s1
; GFX11-NEXT: v_readfirstlane_b32 s0, v3 ; GFX11-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-NEXT: v_readfirstlane_b32 s1, v4 ; GFX11-NEXT: v_readfirstlane_b32 s1, v4
; GFX11-NEXT: v_readfirstlane_b32 s4, v7 ; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v6
; GFX11-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-NEXT: v_readfirstlane_b32 s5, v8 ; GFX11-NEXT: v_readfirstlane_b32 s5, v8
; GFX11-NEXT: v_readfirstlane_b32 s6, v9 ; GFX11-NEXT: v_readfirstlane_b32 s6, v7
; GFX11-NEXT: v_readfirstlane_b32 s7, v10 ; GFX11-NEXT: v_readfirstlane_b32 s7, v10
; GFX11-NEXT: v_readfirstlane_b32 s8, v11 ; GFX11-NEXT: v_readfirstlane_b32 s8, v9
; GFX11-NEXT: v_readfirstlane_b32 s9, v2 ; GFX11-NEXT: v_readfirstlane_b32 s9, v12
; GFX11-NEXT: v_readfirstlane_b32 s10, v12 ; GFX11-NEXT: v_readfirstlane_b32 s10, v11
; GFX11-NEXT: v_readfirstlane_b32 s11, v13 ; GFX11-NEXT: v_readfirstlane_b32 s11, v13
; GFX11-NEXT: v_readfirstlane_b32 s12, v0 ; GFX11-NEXT: v_readfirstlane_b32 s12, v0
; GFX11-NEXT: v_readfirstlane_b32 s13, v1 ; GFX11-NEXT: v_readfirstlane_b32 s13, v1
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx %insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert ret <7 x double> %insert
} }
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; GFX10-NEXT: v_readfirstlane_b32 s11, v11 ; GFX10-NEXT: v_readfirstlane_b32 s11, v11
; GFX10-NEXT: v_readfirstlane_b32 s12, v12 ; GFX10-NEXT: v_readfirstlane_b32 s12, v12
; GFX10-NEXT: v_readfirstlane_b32 s13, v13 ; GFX10-NEXT: v_readfirstlane_b32 s13, v13
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v7f64_v_v_v: ; GFX11-LABEL: dyn_insertelement_v7f64_v_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v16 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 6, v16 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 2, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 3, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 4, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 5, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 6, v16
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v14 :: v_dual_cndmask_b32 v1, v1, v15 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v14 :: v_dual_cndmask_b32 v1, v1, v15
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v14, s0
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v14, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v14, s1
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v15, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v14, s2
; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v14, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v14, s3
; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v15, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v14, s4
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v14 :: v_dual_cndmask_b32 v3, v3, v15 ; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v14, s5
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v15, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v15, s1
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v15, s2
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v15, s3
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v15, s4
; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v15, s5
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2 ; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3 ; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v14 :: v_dual_cndmask_b32 v5, v5, v15
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
; GFX11-NEXT: v_readfirstlane_b32 s10, v10
; GFX11-NEXT: v_readfirstlane_b32 s11, v11
; GFX11-NEXT: v_readfirstlane_b32 s4, v4 ; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5 ; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v14 :: v_dual_cndmask_b32 v7, v7, v15
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
; GFX11-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-NEXT: v_readfirstlane_b32 s13, v13
; GFX11-NEXT: v_readfirstlane_b32 s6, v6 ; GFX11-NEXT: v_readfirstlane_b32 s6, v6
; GFX11-NEXT: v_readfirstlane_b32 s7, v7 ; GFX11-NEXT: v_readfirstlane_b32 s7, v7
; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_cndmask_b32 v9, v9, v15
; GFX11-NEXT: v_readfirstlane_b32 s8, v8 ; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9 ; GFX11-NEXT: v_readfirstlane_b32 s9, v9
; GFX11-NEXT: v_readfirstlane_b32 s10, v10
; GFX11-NEXT: v_readfirstlane_b32 s11, v11
; GFX11-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-NEXT: v_readfirstlane_b32 s13, v13
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx %insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert ret <7 x double> %insert
} }
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_s_s(<5 x double> inreg %vec, double inreg %val, i32 inreg %idx) { define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_s_s(<5 x double> inreg %vec, double inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5f64_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v5f64_s_s_s:
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; GFX10-NEXT: v_mov_b32_e32 v9, s7 ; GFX10-NEXT: v_mov_b32_e32 v9, s7
; GFX10-NEXT: v_mov_b32_e32 v8, s6 ; GFX10-NEXT: v_mov_b32_e32 v8, s6
; GFX10-NEXT: v_mov_b32_e32 v7, s5 ; GFX10-NEXT: v_mov_b32_e32 v7, s5
; GFX10-NEXT: v_mov_b32_e32 v6, s4 ; GFX10-NEXT: v_mov_b32_e32 v6, s4
; GFX10-NEXT: v_mov_b32_e32 v5, s3 ; GFX10-NEXT: v_mov_b32_e32 v5, s3
; GFX10-NEXT: v_mov_b32_e32 v4, s2 ; GFX10-NEXT: v_mov_b32_e32 v4, s2
; GFX10-NEXT: v_mov_b32_e32 v3, s1 ; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0 ; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s12, 1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s12, 2
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s12, 4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s12, 3
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s12, 4
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, s12, 0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v0, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 2 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v0, s0
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v0, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s12, 3 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s2, v4 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v0, s3
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v10, v0, s2
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v1, s3
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v0, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v0, v10, v0, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v11, v1, s2
; GFX10-NEXT: v_cndmask_b32_e64 v1, v11, v1, s1
; GFX10-NEXT: v_readfirstlane_b32 s0, v2 ; GFX10-NEXT: v_readfirstlane_b32 s0, v2
; GFX10-NEXT: v_readfirstlane_b32 s1, v3 ; GFX10-NEXT: v_readfirstlane_b32 s1, v3
; GFX10-NEXT: v_readfirstlane_b32 s2, v4
; GFX10-NEXT: v_readfirstlane_b32 s3, v5 ; GFX10-NEXT: v_readfirstlane_b32 s3, v5
; GFX10-NEXT: v_readfirstlane_b32 s4, v6 ; GFX10-NEXT: v_readfirstlane_b32 s4, v6
; GFX10-NEXT: v_readfirstlane_b32 s5, v7 ; GFX10-NEXT: v_readfirstlane_b32 s5, v7
; GFX10-NEXT: v_readfirstlane_b32 s6, v8 ; GFX10-NEXT: v_readfirstlane_b32 s6, v8
; GFX10-NEXT: v_readfirstlane_b32 s7, v9 ; GFX10-NEXT: v_readfirstlane_b32 s7, v9
; GFX10-NEXT: v_readfirstlane_b32 s8, v0 ; GFX10-NEXT: v_readfirstlane_b32 s8, v0
; GFX10-NEXT: v_readfirstlane_b32 s9, v1 ; GFX10-NEXT: v_readfirstlane_b32 s9, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
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; GFX10-NEXT: v_mov_b32_e32 v10, s7 ; GFX10-NEXT: v_mov_b32_e32 v10, s7
; GFX10-NEXT: v_mov_b32_e32 v9, s6 ; GFX10-NEXT: v_mov_b32_e32 v9, s6
; GFX10-NEXT: v_mov_b32_e32 v8, s5 ; GFX10-NEXT: v_mov_b32_e32 v8, s5
; GFX10-NEXT: v_mov_b32_e32 v7, s4 ; GFX10-NEXT: v_mov_b32_e32 v7, s4
; GFX10-NEXT: v_mov_b32_e32 v6, s3 ; GFX10-NEXT: v_mov_b32_e32 v6, s3
; GFX10-NEXT: v_mov_b32_e32 v5, s2 ; GFX10-NEXT: v_mov_b32_e32 v5, s2
; GFX10-NEXT: v_mov_b32_e32 v4, s1 ; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: v_mov_b32_e32 v3, s0 ; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 4, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v2
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v2
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 0, v2
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, v0, s3
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v0, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s2, v5 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v7, v0, s0
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v7, v9, v0, s1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v8, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v11, v0, s2
; GFX10-NEXT: v_cndmask_b32_e64 v8, v9, v0, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v1, s3
; GFX10-NEXT: v_cndmask_b32_e64 v9, v10, v1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v10, v1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v0, v11, v0, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v12, v1, s2
; GFX10-NEXT: v_cndmask_b32_e64 v1, v12, v1, s1 ; GFX10-NEXT: v_readfirstlane_b32 s0, v2
; GFX10-NEXT: v_readfirstlane_b32 s0, v3 ; GFX10-NEXT: v_readfirstlane_b32 s2, v3
; GFX10-NEXT: v_readfirstlane_b32 s1, v4 ; GFX10-NEXT: v_readfirstlane_b32 s1, v4
; GFX10-NEXT: v_readfirstlane_b32 s3, v6 ; GFX10-NEXT: v_readfirstlane_b32 s3, v6
; GFX10-NEXT: v_readfirstlane_b32 s4, v7 ; GFX10-NEXT: v_readfirstlane_b32 s4, v5
; GFX10-NEXT: v_readfirstlane_b32 s5, v2 ; GFX10-NEXT: v_readfirstlane_b32 s5, v8
; GFX10-NEXT: v_readfirstlane_b32 s6, v8 ; GFX10-NEXT: v_readfirstlane_b32 s6, v7
; GFX10-NEXT: v_readfirstlane_b32 s7, v9 ; GFX10-NEXT: v_readfirstlane_b32 s7, v9
; GFX10-NEXT: v_readfirstlane_b32 s8, v0 ; GFX10-NEXT: v_readfirstlane_b32 s8, v0
; GFX10-NEXT: v_readfirstlane_b32 s9, v1 ; GFX10-NEXT: v_readfirstlane_b32 s9, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v5f64_s_v_v: ; GFX11-LABEL: dyn_insertelement_v5f64_s_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: s_mov_b32 s1, s3
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; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7 ; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7
; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8 ; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9 ; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: dyn_insertelement_v5f64_v_v_s: ; GFX10-LABEL: dyn_insertelement_v5f64_v_v_s:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s2, 4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s2, 1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s2, 2
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, s2, 3
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s2, 4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v10, s1
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s3
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v11, s1
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v11, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s3
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v11, s2
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
; GFX10-NEXT: v_readfirstlane_b32 s8, v8
; GFX10-NEXT: v_readfirstlane_b32 s9, v9
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3
; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: v_readfirstlane_b32 s5, v5 ; GFX10-NEXT: v_readfirstlane_b32 s5, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s6, v6 ; GFX10-NEXT: v_readfirstlane_b32 s6, v6
; GFX10-NEXT: v_readfirstlane_b32 s7, v7 ; GFX10-NEXT: v_readfirstlane_b32 s7, v7
; GFX10-NEXT: v_readfirstlane_b32 s8, v8
; GFX10-NEXT: v_readfirstlane_b32 s9, v9
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v5f64_v_v_s: ; GFX11-LABEL: dyn_insertelement_v5f64_v_v_s:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0 ; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s2, 2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s2, 1
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, s2, 4 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, s2, 2
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, s2, 3
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, s2, 4
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11
; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v10, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v10, s1
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v11, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v10, s3
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v10, s2
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v11, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_cndmask_b32 v3, v3, v11 ; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v11, s1
; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3 ; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v11, s3
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v11, s2
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2 ; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3 ; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v10 :: v_dual_cndmask_b32 v7, v7, v11
; GFX11-NEXT: v_readfirstlane_b32 s4, v4 ; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5 ; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s6, v6 ; GFX11-NEXT: v_readfirstlane_b32 s6, v6
; GFX11-NEXT: v_readfirstlane_b32 s7, v7 ; GFX11-NEXT: v_readfirstlane_b32 s7, v7
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9 ; GFX11-NEXT: v_readfirstlane_b32 s9, v9
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx %insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert ret <5 x double> %insert
} }
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_v(<5 x double> %vec, double %val, i32 %idx) { define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_v(<5 x double> %vec, double %val, i32 %idx) {
Show All 24 Lines
; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7 ; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7
; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8 ; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9 ; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: dyn_insertelement_v5f64_v_v_v: ; GFX10-LABEL: dyn_insertelement_v5f64_v_v_v:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 4, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v12
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 2, v12
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 3, v12
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 4, v12
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v10, s1
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s2
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s3
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v11, s1
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v11, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s2
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v11, s3
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
; GFX10-NEXT: v_readfirstlane_b32 s8, v8
; GFX10-NEXT: v_readfirstlane_b32 s9, v9
; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12
; GFX10-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: v_readfirstlane_b32 s5, v5 ; GFX10-NEXT: v_readfirstlane_b32 s5, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s6, v6 ; GFX10-NEXT: v_readfirstlane_b32 s6, v6
; GFX10-NEXT: v_readfirstlane_b32 s7, v7 ; GFX10-NEXT: v_readfirstlane_b32 s7, v7
; GFX10-NEXT: v_readfirstlane_b32 s8, v8
; GFX10-NEXT: v_readfirstlane_b32 s9, v9
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v5f64_v_v_v: ; GFX11-LABEL: dyn_insertelement_v5f64_v_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v12
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 4, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 2, v12
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 3, v12
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 4, v12
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v10, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v10, s1
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v11, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v10, s2
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v10, s3
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v11, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_cndmask_b32 v3, v3, v11 ; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v11, s1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12 ; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v11, s2
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v11, s3
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2 ; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3 ; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v10 :: v_dual_cndmask_b32 v7, v7, v11
; GFX11-NEXT: v_readfirstlane_b32 s4, v4 ; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5 ; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s6, v6 ; GFX11-NEXT: v_readfirstlane_b32 s6, v6
; GFX11-NEXT: v_readfirstlane_b32 s7, v7 ; GFX11-NEXT: v_readfirstlane_b32 s7, v7
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9 ; GFX11-NEXT: v_readfirstlane_b32 s9, v9
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx %insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert ret <5 x double> %insert
} }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll

Show First 20 Lines • Show All 991 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX9-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: flat_atomic_inc_ret_i64_offset_addr64: ; GFX10-LABEL: flat_atomic_inc_ret_i64_offset_addr64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX10-NEXT: v_mov_b32_e32 v2, 42
; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s3 ; GFX10-NEXT: v_mov_b32_e32 v1, s3
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, v4 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, 42 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 40
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 40 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; GFX10-NEXT: v_mov_b32_e32 v3, s1 ; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0 ; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX10-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; ;
; GFX10-LABEL: flat_atomic_inc_noret_i64_offset_addr64: ; GFX10-LABEL: flat_atomic_inc_noret_i64_offset_addr64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, 42 ; GFX10-NEXT: v_mov_b32_e32 v2, 42
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 40 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 40
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1] ; GFX10-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: flat_atomic_inc_noret_i64_offset_addr64: ; GFX11-LABEL: flat_atomic_inc_noret_i64_offset_addr64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX11-NEXT: v_mov_b32_e32 v2, 42 ; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll

Show First 20 Lines • Show All 343 Lines • ▼ Show 20 Lines
; GFX6-NEXT: s_wqm_b64 exec, exec ; GFX6-NEXT: s_wqm_b64 exec, exec
; GFX6-NEXT: s_and_b64 exec, exec, s[14:15] ; GFX6-NEXT: s_and_b64 exec, exec, s[14:15]
; GFX6-NEXT: image_gather4_c_b_cl_o v[0:3], v[0:5], s[0:7], s[8:11] dmask:0x1 ; GFX6-NEXT: image_gather4_c_b_cl_o v[0:3], v[0:5], s[0:7], s[8:11] dmask:0x1
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: gather4_c_b_cl_o_2d: ; GFX10-LABEL: gather4_c_b_cl_o_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: s_mov_b32 s1, exec_lo ; GFX10-NEXT: s_mov_b32 s14, exec_lo
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s1
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s14
; GFX10-NEXT: image_gather4_c_b_cl_o v[0:3], v[0:5], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX10-NEXT: image_gather4_c_b_cl_o v[0:3], v[0:5], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
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llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; GCN-NEXT: ; return to shader part epilog
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1 %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2 %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
%r = bitcast <4 x i32> %v to <4 x float> %r = bitcast <4 x i32> %v to <4 x float>
ret <4 x float> %r ret <4 x float> %r
} }
define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> inreg %tdescr) { define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> inreg %tdescr) {
; GFX10-LABEL: image_bvh_intersect_ray_a16: ; GFX1030-LABEL: image_bvh_intersect_ray_a16:
; GFX10: ; %bb.0: ; GFX1030: ; %bb.0:
; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v5 ; GFX1030-NEXT: v_lshrrev_b32_e32 v9, 16, v5
; GFX10-NEXT: v_and_b32_e32 v10, 0xffff, v7 ; GFX1030-NEXT: v_and_b32_e32 v10, 0xffff, v7
; GFX10-NEXT: v_and_b32_e32 v8, 0xffff, v8 ; GFX1030-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v9 ; GFX1030-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v10 ; GFX1030-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX10-NEXT: v_alignbit_b32 v7, v8, v7, 16 ; GFX1030-NEXT: v_alignbit_b32 v7, v8, v7, 16
; GFX10-NEXT: v_and_or_b32 v5, v5, 0xffff, v9 ; GFX1030-NEXT: v_and_or_b32 v5, v5, 0xffff, v9
; GFX10-NEXT: v_and_or_b32 v6, v6, 0xffff, v10 ; GFX1030-NEXT: v_and_or_b32 v6, v6, 0xffff, v10
; GFX10-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16 ; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX1030-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX1030-NEXT: ; return to shader part epilog
;
; GFX1013-LABEL: image_bvh_intersect_ray_a16:
; GFX1013: ; %bb.0:
; GFX1013-NEXT: v_lshrrev_b32_e32 v9, 16, v5
; GFX1013-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX1013-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX1013-NEXT: v_and_or_b32 v5, v5, 0xffff, v9
; GFX1013-NEXT: v_and_b32_e32 v9, 0xffff, v7
; GFX1013-NEXT: v_alignbit_b32 v7, v8, v7, 16
; GFX1013-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX1013-NEXT: v_and_or_b32 v6, v6, 0xffff, v9
; GFX1013-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16
; GFX1013-NEXT: s_waitcnt vmcnt(0)
; GFX1013-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: image_bvh_intersect_ray_a16: ; GFX11-LABEL: image_bvh_intersect_ray_a16:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_perm_b32 v9, v5, v7, 0x5040100 ; GFX11-NEXT: v_perm_b32 v9, v5, v7, 0x5040100
; GFX11-NEXT: v_perm_b32 v10, v5, v7, 0x7060302 ; GFX11-NEXT: v_perm_b32 v10, v5, v7, 0x7060302
; GFX11-NEXT: v_perm_b32 v11, v6, v8, 0x5040100 ; GFX11-NEXT: v_perm_b32 v11, v6, v8, 0x5040100
; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v0, v1, v[2:4], v[9:11]], s[0:3] a16 ; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v0, v1, v[2:4], v[9:11]], s[0:3] a16
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
Show All 31 Lines; GCN-NEXT: ; return to shader part epilog
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1 %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2 %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr) %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
%r = bitcast <4 x i32> %v to <4 x float> %r = bitcast <4 x i32> %v to <4 x float>
ret <4 x float> %r ret <4 x float> %r
} }
define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> inreg %tdescr) { define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> inreg %tdescr) {
; GFX10-LABEL: image_bvh64_intersect_ray_a16: ; GFX1030-LABEL: image_bvh64_intersect_ray_a16:
; GFX10: ; %bb.0: ; GFX1030: ; %bb.0:
; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v6 ; GFX1030-NEXT: v_lshrrev_b32_e32 v10, 16, v6
; GFX10-NEXT: v_and_b32_e32 v11, 0xffff, v8 ; GFX1030-NEXT: v_and_b32_e32 v11, 0xffff, v8
; GFX10-NEXT: v_and_b32_e32 v9, 0xffff, v9 ; GFX1030-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v10 ; GFX1030-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v11 ; GFX1030-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX10-NEXT: v_alignbit_b32 v8, v9, v8, 16 ; GFX1030-NEXT: v_alignbit_b32 v8, v9, v8, 16
; GFX10-NEXT: v_and_or_b32 v6, v6, 0xffff, v10 ; GFX1030-NEXT: v_and_or_b32 v6, v6, 0xffff, v10
; GFX10-NEXT: v_and_or_b32 v7, v7, 0xffff, v11 ; GFX1030-NEXT: v_and_or_b32 v7, v7, 0xffff, v11
; GFX10-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16 ; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX1030-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX1030-NEXT: ; return to shader part epilog
;
; GFX1013-LABEL: image_bvh64_intersect_ray_a16:
; GFX1013: ; %bb.0:
; GFX1013-NEXT: v_lshrrev_b32_e32 v10, 16, v6
; GFX1013-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX1013-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX1013-NEXT: v_and_or_b32 v6, v6, 0xffff, v10
; GFX1013-NEXT: v_and_b32_e32 v10, 0xffff, v8
; GFX1013-NEXT: v_alignbit_b32 v8, v9, v8, 16
; GFX1013-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX1013-NEXT: v_and_or_b32 v7, v7, 0xffff, v10
; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16
; GFX1013-NEXT: s_waitcnt vmcnt(0)
; GFX1013-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: image_bvh64_intersect_ray_a16: ; GFX11-LABEL: image_bvh64_intersect_ray_a16:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_perm_b32 v10, v6, v8, 0x5040100 ; GFX11-NEXT: v_perm_b32 v10, v6, v8, 0x5040100
; GFX11-NEXT: v_perm_b32 v11, v6, v8, 0x7060302 ; GFX11-NEXT: v_perm_b32 v11, v6, v8, 0x7060302
; GFX11-NEXT: v_perm_b32 v12, v7, v9, 0x5040100 ; GFX11-NEXT: v_perm_b32 v12, v7, v9, 0x5040100
; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[0:1], v2, v[3:5], v[10:12]], s[0:3] a16 ; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[0:1], v2, v[3:5], v[10:12]], s[0:3] a16
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; GFX1013-NEXT: v_readfirstlane_b32 s6, v13 ; GFX1013-NEXT: v_readfirstlane_b32 s6, v13
; GFX1013-NEXT: v_readfirstlane_b32 s7, v14 ; GFX1013-NEXT: v_readfirstlane_b32 s7, v14
; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12] ; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14] ; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14]
; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0 ; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0 ; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh_intersect_ray v[15:18], v[0:10], s[4:7] ; GFX1013-NEXT: image_bvh_intersect_ray v[15:18], v[0:10], s[4:7]
; GFX1013-NEXT: ; implicit-def: $vgpr11 ; GFX1013-NEXT: ; implicit-def: $vgpr11
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
; GFX1013-NEXT: ; implicit-def: $vgpr11_vgpr12_vgpr13_vgpr14 ; GFX1013-NEXT: ; implicit-def: $vgpr11_vgpr12_vgpr13_vgpr14
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1013-NEXT: s_cbranch_execnz .LBB6_1 ; GFX1013-NEXT: s_cbranch_execnz .LBB6_1
; GFX1013-NEXT: ; %bb.2: ; GFX1013-NEXT: ; %bb.2:
; GFX1013-NEXT: s_mov_b32 exec_lo, s1 ; GFX1013-NEXT: s_mov_b32 exec_lo, s1
; GFX1013-NEXT: s_waitcnt vmcnt(0) ; GFX1013-NEXT: s_waitcnt vmcnt(0)
; GFX1013-NEXT: v_mov_b32_e32 v0, v15 ; GFX1013-NEXT: v_mov_b32_e32 v0, v15
; GFX1013-NEXT: v_mov_b32_e32 v1, v16 ; GFX1013-NEXT: v_mov_b32_e32 v1, v16
Show All 36 Lines; GFX11-NEXT: ; return to shader part epilog
%r = bitcast <4 x i32> %v to <4 x float> %r = bitcast <4 x i32> %v to <4 x float>
ret <4 x float> %r ret <4 x float> %r
} }
define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) { define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) {
; GFX1030-LABEL: image_bvh_intersect_ray_a16_vgpr_descr: ; GFX1030-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX1030: ; %bb.0: ; GFX1030: ; %bb.0:
; GFX1030-NEXT: v_mov_b32_e32 v13, v0 ; GFX1030-NEXT: v_mov_b32_e32 v13, v0
; GFX1030-NEXT: v_mov_b32_e32 v14, v1
; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v5 ; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v5
; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v7 ; GFX1030-NEXT: v_mov_b32_e32 v14, v1
; GFX1030-NEXT: v_mov_b32_e32 v15, v2 ; GFX1030-NEXT: v_mov_b32_e32 v15, v2
; GFX1030-NEXT: v_and_b32_e32 v2, 0xffff, v8
; GFX1030-NEXT: v_mov_b32_e32 v16, v3 ; GFX1030-NEXT: v_mov_b32_e32 v16, v3
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX1030-NEXT: v_mov_b32_e32 v17, v4 ; GFX1030-NEXT: v_mov_b32_e32 v17, v4
; GFX1030-NEXT: v_alignbit_b32 v20, v2, v7, 16 ; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1030-NEXT: s_mov_b32 s1, exec_lo ; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: v_and_or_b32 v18, v5, 0xffff, v0 ; GFX1030-NEXT: v_and_or_b32 v18, v5, 0xffff, v0
; GFX1030-NEXT: v_and_or_b32 v19, v6, 0xffff, v1 ; GFX1030-NEXT: v_and_b32_e32 v0, 0xffff, v7
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1030-NEXT: v_and_or_b32 v19, v6, 0xffff, v0
; GFX1030-NEXT: v_and_b32_e32 v0, 0xffff, v8
; GFX1030-NEXT: v_alignbit_b32 v20, v0, v7, 16
; GFX1030-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 ; GFX1030-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
; GFX1030-NEXT: v_readfirstlane_b32 s4, v9 ; GFX1030-NEXT: v_readfirstlane_b32 s4, v9
; GFX1030-NEXT: v_readfirstlane_b32 s5, v10 ; GFX1030-NEXT: v_readfirstlane_b32 s5, v10
; GFX1030-NEXT: v_readfirstlane_b32 s6, v11 ; GFX1030-NEXT: v_readfirstlane_b32 s6, v11
; GFX1030-NEXT: v_readfirstlane_b32 s7, v12 ; GFX1030-NEXT: v_readfirstlane_b32 s7, v12
; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10] ; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12] ; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12]
; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0 ; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0
Show All 14 Lines
; GFX1030-NEXT: ; %bb.2: ; GFX1030-NEXT: ; %bb.2:
; GFX1030-NEXT: s_mov_b32 exec_lo, s1 ; GFX1030-NEXT: s_mov_b32 exec_lo, s1
; GFX1030-NEXT: s_waitcnt vmcnt(0) ; GFX1030-NEXT: s_waitcnt vmcnt(0)
; GFX1030-NEXT: ; return to shader part epilog ; GFX1030-NEXT: ; return to shader part epilog
; ;
; GFX1013-LABEL: image_bvh_intersect_ray_a16_vgpr_descr: ; GFX1013-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX1013: ; %bb.0: ; GFX1013: ; %bb.0:
; GFX1013-NEXT: v_lshrrev_b32_e32 v13, 16, v5 ; GFX1013-NEXT: v_lshrrev_b32_e32 v13, 16, v5
; GFX1013-NEXT: v_and_b32_e32 v14, 0xffff, v7
; GFX1013-NEXT: v_and_b32_e32 v8, 0xffff, v8 ; GFX1013-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX1013-NEXT: s_mov_b32 s1, exec_lo ; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: v_lshlrev_b32_e32 v13, 16, v13 ; GFX1013-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX1013-NEXT: v_alignbit_b32 v7, v8, v7, 16
; GFX1013-NEXT: v_and_or_b32 v5, v5, 0xffff, v13 ; GFX1013-NEXT: v_and_or_b32 v5, v5, 0xffff, v13
; GFX1013-NEXT: v_and_or_b32 v6, v6, 0xffff, v14 ; GFX1013-NEXT: v_and_b32_e32 v13, 0xffff, v7
; GFX1013-NEXT: v_alignbit_b32 v7, v8, v7, 16
; GFX1013-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX1013-NEXT: v_and_or_b32 v6, v6, 0xffff, v13
; GFX1013-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 ; GFX1013-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
; GFX1013-NEXT: v_readfirstlane_b32 s4, v9 ; GFX1013-NEXT: v_readfirstlane_b32 s4, v9
; GFX1013-NEXT: v_readfirstlane_b32 s5, v10 ; GFX1013-NEXT: v_readfirstlane_b32 s5, v10
; GFX1013-NEXT: v_readfirstlane_b32 s6, v11 ; GFX1013-NEXT: v_readfirstlane_b32 s6, v11
; GFX1013-NEXT: v_readfirstlane_b32 s7, v12 ; GFX1013-NEXT: v_readfirstlane_b32 s7, v12
; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10] ; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12] ; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[11:12]
; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0 ; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0 ; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh_intersect_ray v[13:16], v[0:7], s[4:7] a16 ; GFX1013-NEXT: image_bvh_intersect_ray v[13:16], v[0:7], s[4:7] a16
; GFX1013-NEXT: ; implicit-def: $vgpr9 ; GFX1013-NEXT: ; implicit-def: $vgpr9
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX1013-NEXT: ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12 ; GFX1013-NEXT: ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1013-NEXT: s_cbranch_execnz .LBB7_1 ; GFX1013-NEXT: s_cbranch_execnz .LBB7_1
; GFX1013-NEXT: ; %bb.2: ; GFX1013-NEXT: ; %bb.2:
; GFX1013-NEXT: s_mov_b32 exec_lo, s1 ; GFX1013-NEXT: s_mov_b32 exec_lo, s1
; GFX1013-NEXT: s_waitcnt vmcnt(0) ; GFX1013-NEXT: s_waitcnt vmcnt(0)
; GFX1013-NEXT: v_mov_b32_e32 v0, v13 ; GFX1013-NEXT: v_mov_b32_e32 v0, v13
; GFX1013-NEXT: v_mov_b32_e32 v1, v14 ; GFX1013-NEXT: v_mov_b32_e32 v1, v14
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; GFX1013-NEXT: v_readfirstlane_b32 s6, v14 ; GFX1013-NEXT: v_readfirstlane_b32 s6, v14
; GFX1013-NEXT: v_readfirstlane_b32 s7, v15 ; GFX1013-NEXT: v_readfirstlane_b32 s7, v15
; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[12:13] ; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[12:13]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[14:15] ; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[14:15]
; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0 ; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0 ; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh64_intersect_ray v[16:19], v[0:11], s[4:7] ; GFX1013-NEXT: image_bvh64_intersect_ray v[16:19], v[0:11], s[4:7]
; GFX1013-NEXT: ; implicit-def: $vgpr12 ; GFX1013-NEXT: ; implicit-def: $vgpr12
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
; GFX1013-NEXT: ; implicit-def: $vgpr12_vgpr13_vgpr14_vgpr15 ; GFX1013-NEXT: ; implicit-def: $vgpr12_vgpr13_vgpr14_vgpr15
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1013-NEXT: s_cbranch_execnz .LBB8_1 ; GFX1013-NEXT: s_cbranch_execnz .LBB8_1
; GFX1013-NEXT: ; %bb.2: ; GFX1013-NEXT: ; %bb.2:
; GFX1013-NEXT: s_mov_b32 exec_lo, s1 ; GFX1013-NEXT: s_mov_b32 exec_lo, s1
; GFX1013-NEXT: s_waitcnt vmcnt(0) ; GFX1013-NEXT: s_waitcnt vmcnt(0)
; GFX1013-NEXT: v_mov_b32_e32 v0, v16 ; GFX1013-NEXT: v_mov_b32_e32 v0, v16
; GFX1013-NEXT: v_mov_b32_e32 v1, v17 ; GFX1013-NEXT: v_mov_b32_e32 v1, v17
Show All 36 Lines; GFX11-NEXT: ; return to shader part epilog
%r = bitcast <4 x i32> %v to <4 x float> %r = bitcast <4 x i32> %v to <4 x float>
ret <4 x float> %r ret <4 x float> %r
} }
define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16_vgpr_descr(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) { define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16_vgpr_descr(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) {
; GFX1030-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr: ; GFX1030-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr:
; GFX1030: ; %bb.0: ; GFX1030: ; %bb.0:
; GFX1030-NEXT: v_mov_b32_e32 v14, v0 ; GFX1030-NEXT: v_mov_b32_e32 v14, v0
; GFX1030-NEXT: v_mov_b32_e32 v15, v1
; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v6 ; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v6
; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v8 ; GFX1030-NEXT: v_mov_b32_e32 v15, v1
; GFX1030-NEXT: v_mov_b32_e32 v16, v2 ; GFX1030-NEXT: v_mov_b32_e32 v16, v2
; GFX1030-NEXT: v_and_b32_e32 v2, 0xffff, v9
; GFX1030-NEXT: v_mov_b32_e32 v17, v3 ; GFX1030-NEXT: v_mov_b32_e32 v17, v3
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX1030-NEXT: v_mov_b32_e32 v18, v4 ; GFX1030-NEXT: v_mov_b32_e32 v18, v4
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1030-NEXT: v_mov_b32_e32 v19, v5 ; GFX1030-NEXT: v_mov_b32_e32 v19, v5
; GFX1030-NEXT: v_alignbit_b32 v22, v2, v8, 16
; GFX1030-NEXT: v_and_or_b32 v20, v6, 0xffff, v0
; GFX1030-NEXT: v_and_or_b32 v21, v7, 0xffff, v1
; GFX1030-NEXT: s_mov_b32 s1, exec_lo ; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: v_and_or_b32 v20, v6, 0xffff, v0
; GFX1030-NEXT: v_and_b32_e32 v0, 0xffff, v8
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1030-NEXT: v_and_or_b32 v21, v7, 0xffff, v0
; GFX1030-NEXT: v_and_b32_e32 v0, 0xffff, v9
; GFX1030-NEXT: v_alignbit_b32 v22, v0, v8, 16
; GFX1030-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 ; GFX1030-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GFX1030-NEXT: v_readfirstlane_b32 s4, v10 ; GFX1030-NEXT: v_readfirstlane_b32 s4, v10
; GFX1030-NEXT: v_readfirstlane_b32 s5, v11 ; GFX1030-NEXT: v_readfirstlane_b32 s5, v11
; GFX1030-NEXT: v_readfirstlane_b32 s6, v12 ; GFX1030-NEXT: v_readfirstlane_b32 s6, v12
; GFX1030-NEXT: v_readfirstlane_b32 s7, v13 ; GFX1030-NEXT: v_readfirstlane_b32 s7, v13
; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[10:11] ; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[10:11]
; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[12:13] ; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[12:13]
; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0 ; GFX1030-NEXT: s_and_b32 s0, vcc_lo, s0
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; GFX1030-NEXT: ; %bb.2: ; GFX1030-NEXT: ; %bb.2:
; GFX1030-NEXT: s_mov_b32 exec_lo, s1 ; GFX1030-NEXT: s_mov_b32 exec_lo, s1
; GFX1030-NEXT: s_waitcnt vmcnt(0) ; GFX1030-NEXT: s_waitcnt vmcnt(0)
; GFX1030-NEXT: ; return to shader part epilog ; GFX1030-NEXT: ; return to shader part epilog
; ;
; GFX1013-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr: ; GFX1013-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr:
; GFX1013: ; %bb.0: ; GFX1013: ; %bb.0:
; GFX1013-NEXT: v_lshrrev_b32_e32 v14, 16, v6 ; GFX1013-NEXT: v_lshrrev_b32_e32 v14, 16, v6
; GFX1013-NEXT: v_and_b32_e32 v15, 0xffff, v8
; GFX1013-NEXT: v_and_b32_e32 v9, 0xffff, v9 ; GFX1013-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX1013-NEXT: s_mov_b32 s1, exec_lo ; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14 ; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX1013-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX1013-NEXT: v_alignbit_b32 v8, v9, v8, 16
; GFX1013-NEXT: v_and_or_b32 v6, v6, 0xffff, v14 ; GFX1013-NEXT: v_and_or_b32 v6, v6, 0xffff, v14
; GFX1013-NEXT: v_and_or_b32 v7, v7, 0xffff, v15 ; GFX1013-NEXT: v_and_b32_e32 v14, 0xffff, v8
; GFX1013-NEXT: v_alignbit_b32 v8, v9, v8, 16
; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX1013-NEXT: v_and_or_b32 v7, v7, 0xffff, v14
; GFX1013-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 ; GFX1013-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GFX1013-NEXT: v_readfirstlane_b32 s4, v10 ; GFX1013-NEXT: v_readfirstlane_b32 s4, v10
; GFX1013-NEXT: v_readfirstlane_b32 s5, v11 ; GFX1013-NEXT: v_readfirstlane_b32 s5, v11
; GFX1013-NEXT: v_readfirstlane_b32 s6, v12 ; GFX1013-NEXT: v_readfirstlane_b32 s6, v12
; GFX1013-NEXT: v_readfirstlane_b32 s7, v13 ; GFX1013-NEXT: v_readfirstlane_b32 s7, v13
; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[10:11] ; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[10:11]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[12:13] ; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[12:13]
; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0 ; GFX1013-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0 ; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh64_intersect_ray v[14:17], v[0:8], s[4:7] a16 ; GFX1013-NEXT: image_bvh64_intersect_ray v[14:17], v[0:8], s[4:7] a16
; GFX1013-NEXT: ; implicit-def: $vgpr10 ; GFX1013-NEXT: ; implicit-def: $vgpr10
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
; GFX1013-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13 ; GFX1013-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1013-NEXT: s_cbranch_execnz .LBB9_1 ; GFX1013-NEXT: s_cbranch_execnz .LBB9_1
; GFX1013-NEXT: ; %bb.2: ; GFX1013-NEXT: ; %bb.2:
; GFX1013-NEXT: s_mov_b32 exec_lo, s1 ; GFX1013-NEXT: s_mov_b32 exec_lo, s1
; GFX1013-NEXT: s_waitcnt vmcnt(0) ; GFX1013-NEXT: s_waitcnt vmcnt(0)
; GFX1013-NEXT: v_mov_b32_e32 v0, v14 ; GFX1013-NEXT: v_mov_b32_e32 v0, v14
; GFX1013-NEXT: v_mov_b32_e32 v1, v15 ; GFX1013-NEXT: v_mov_b32_e32 v1, v15
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7] ; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7]
; GFX1030-NEXT: s_waitcnt vmcnt(0) ; GFX1030-NEXT: s_waitcnt vmcnt(0)
; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3] ; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
; GFX1030-NEXT: s_endpgm ; GFX1030-NEXT: s_endpgm
; ;
; GFX1013-LABEL: image_bvh_intersect_ray_nsa_reassign: ; GFX1013-LABEL: image_bvh_intersect_ray_nsa_reassign:
; GFX1013: ; %bb.0: ; GFX1013: ; %bb.0:
; GFX1013-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX1013-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX1013-NEXT: v_lshlrev_b32_e32 v6, 2, v0 ; GFX1013-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; GFX1013-NEXT: v_mov_b32_e32 v6, 4.0
; GFX1013-NEXT: v_mov_b32_e32 v7, 0x40a00000 ; GFX1013-NEXT: v_mov_b32_e32 v7, 0x40a00000
; GFX1013-NEXT: v_mov_b32_e32 v8, 0x40c00000 ; GFX1013-NEXT: v_mov_b32_e32 v8, 0x40c00000
; GFX1013-NEXT: v_mov_b32_e32 v9, 0x40e00000 ; GFX1013-NEXT: v_mov_b32_e32 v9, 0x40e00000
; GFX1013-NEXT: v_mov_b32_e32 v10, 0x41000000 ; GFX1013-NEXT: v_mov_b32_e32 v10, 0x41000000
; GFX1013-NEXT: s_waitcnt lgkmcnt(0) ; GFX1013-NEXT: s_waitcnt lgkmcnt(0)
; GFX1013-NEXT: v_mov_b32_e32 v0, s0 ; GFX1013-NEXT: v_mov_b32_e32 v0, s0
; GFX1013-NEXT: v_mov_b32_e32 v1, s1 ; GFX1013-NEXT: v_mov_b32_e32 v1, s1
; GFX1013-NEXT: v_mov_b32_e32 v2, s2 ; GFX1013-NEXT: v_add_co_u32 v2, vcc_lo, v0, v4
; GFX1013-NEXT: v_mov_b32_e32 v3, s3 ; GFX1013-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
; GFX1013-NEXT: v_add_co_u32 v4, vcc_lo, v0, v6 ; GFX1013-NEXT: v_mov_b32_e32 v0, s2
; GFX1013-NEXT: v_mov_b32_e32 v1, s3
; GFX1013-NEXT: v_add_co_u32 v4, vcc_lo, v0, v4
; GFX1013-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo ; GFX1013-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX1013-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6 ; GFX1013-NEXT: flat_load_dword v0, v[2:3]
; GFX1013-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo ; GFX1013-NEXT: flat_load_dword v1, v[4:5]
; GFX1013-NEXT: v_mov_b32_e32 v6, 4.0
; GFX1013-NEXT: flat_load_dword v0, v[4:5]
; GFX1013-NEXT: flat_load_dword v1, v[2:3]
; GFX1013-NEXT: v_mov_b32_e32 v2, 0 ; GFX1013-NEXT: v_mov_b32_e32 v2, 0
; GFX1013-NEXT: v_mov_b32_e32 v3, 1.0 ; GFX1013-NEXT: v_mov_b32_e32 v3, 1.0
; GFX1013-NEXT: v_mov_b32_e32 v4, 2.0 ; GFX1013-NEXT: v_mov_b32_e32 v4, 2.0
; GFX1013-NEXT: v_mov_b32_e32 v5, 0x40400000 ; GFX1013-NEXT: v_mov_b32_e32 v5, 0x40400000
; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1013-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7] ; GFX1013-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7]
; GFX1013-NEXT: s_waitcnt vmcnt(0) ; GFX1013-NEXT: s_waitcnt vmcnt(0)
; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3] ; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[4:7] a16 ; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[4:7] a16
; GFX1030-NEXT: s_waitcnt vmcnt(0) ; GFX1030-NEXT: s_waitcnt vmcnt(0)
; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3] ; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
; GFX1030-NEXT: s_endpgm ; GFX1030-NEXT: s_endpgm
; ;
; GFX1013-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: ; GFX1013-LABEL: image_bvh_intersect_ray_a16_nsa_reassign:
; GFX1013: ; %bb.0: ; GFX1013: ; %bb.0:
; GFX1013-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX1013-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX1013-NEXT: v_lshlrev_b32_e32 v6, 2, v0 ; GFX1013-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; GFX1013-NEXT: s_movk_i32 s9, 0x4600 ; GFX1013-NEXT: s_movk_i32 s9, 0x4600
; GFX1013-NEXT: s_movk_i32 s8, 0x4700 ; GFX1013-NEXT: s_movk_i32 s8, 0x4700
; GFX1013-NEXT: s_bfe_u32 s8, s8, 0x100000 ; GFX1013-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX1013-NEXT: s_waitcnt lgkmcnt(0) ; GFX1013-NEXT: s_waitcnt lgkmcnt(0)
; GFX1013-NEXT: v_mov_b32_e32 v0, s0 ; GFX1013-NEXT: v_mov_b32_e32 v0, s0
; GFX1013-NEXT: v_mov_b32_e32 v1, s1 ; GFX1013-NEXT: v_mov_b32_e32 v1, s1
; GFX1013-NEXT: v_mov_b32_e32 v2, s2
; GFX1013-NEXT: v_mov_b32_e32 v3, s3
; GFX1013-NEXT: s_movk_i32 s1, 0x4400 ; GFX1013-NEXT: s_movk_i32 s1, 0x4400
; GFX1013-NEXT: v_add_co_u32 v4, vcc_lo, v0, v6 ; GFX1013-NEXT: s_movk_i32 s0, 0x4500
; GFX1013-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX1013-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6
; GFX1013-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
; GFX1013-NEXT: s_movk_i32 s2, 0x4200
; GFX1013-NEXT: flat_load_dword v0, v[4:5]
; GFX1013-NEXT: flat_load_dword v1, v[2:3]
; GFX1013-NEXT: s_bfe_u32 s1, s1, 0x100000 ; GFX1013-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX1013-NEXT: v_add_co_u32 v2, vcc_lo, v0, v4
; GFX1013-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
; GFX1013-NEXT: v_mov_b32_e32 v0, s2
; GFX1013-NEXT: v_mov_b32_e32 v1, s3
; GFX1013-NEXT: s_movk_i32 s2, 0x4200
; GFX1013-NEXT: s_movk_i32 s3, 0x4800 ; GFX1013-NEXT: s_movk_i32 s3, 0x4800
; GFX1013-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX1013-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX1013-NEXT: v_add_co_u32 v4, vcc_lo, v0, v4
; GFX1013-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX1013-NEXT: flat_load_dword v0, v[2:3]
; GFX1013-NEXT: flat_load_dword v1, v[4:5]
; GFX1013-NEXT: s_lshl_b32 s1, s1, 16 ; GFX1013-NEXT: s_lshl_b32 s1, s1, 16
; GFX1013-NEXT: s_movk_i32 s0, 0x4500 ; GFX1013-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX1013-NEXT: s_or_b32 s1, s2, s1 ; GFX1013-NEXT: s_or_b32 s1, s2, s1
; GFX1013-NEXT: s_bfe_u32 s2, s9, 0x100000 ; GFX1013-NEXT: s_bfe_u32 s2, s9, 0x100000
; GFX1013-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX1013-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX1013-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX1013-NEXT: s_lshl_b32 s2, s2, 16 ; GFX1013-NEXT: s_lshl_b32 s2, s2, 16
; GFX1013-NEXT: s_lshl_b32 s3, s3, 16 ; GFX1013-NEXT: s_lshl_b32 s3, s3, 16
; GFX1013-NEXT: s_or_b32 s0, s0, s2 ; GFX1013-NEXT: s_or_b32 s0, s0, s2
; GFX1013-NEXT: s_or_b32 s2, s8, s3 ; GFX1013-NEXT: s_or_b32 s2, s8, s3
; GFX1013-NEXT: v_mov_b32_e32 v2, 0 ; GFX1013-NEXT: v_mov_b32_e32 v2, 0
; GFX1013-NEXT: v_mov_b32_e32 v3, 1.0 ; GFX1013-NEXT: v_mov_b32_e32 v3, 1.0
; GFX1013-NEXT: v_mov_b32_e32 v4, 2.0 ; GFX1013-NEXT: v_mov_b32_e32 v4, 2.0
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Lines
; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16 ; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16
; GFX1030-NEXT: s_waitcnt vmcnt(0) ; GFX1030-NEXT: s_waitcnt vmcnt(0)
; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3] ; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
; GFX1030-NEXT: s_endpgm ; GFX1030-NEXT: s_endpgm
; ;
; GFX1013-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: ; GFX1013-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
; GFX1013: ; %bb.0: ; GFX1013: ; %bb.0:
; GFX1013-NEXT: s_clause 0x1 ; GFX1013-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX1013-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX1013-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX1013-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX1013-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX1013-NEXT: s_movk_i32 s1, 0x4400 ; GFX1013-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
; GFX1013-NEXT: s_movk_i32 s9, 0x4600 ; GFX1013-NEXT: s_movk_i32 s7, 0x4400
; GFX1013-NEXT: s_bfe_u32 s1, s1, 0x100000 ; GFX1013-NEXT: s_movk_i32 s8, 0x4200
; GFX1013-NEXT: s_movk_i32 s0, 0x4500 ; GFX1013-NEXT: s_movk_i32 s9, 0x4800
; GFX1013-NEXT: s_lshl_b32 s1, s1, 16 ; GFX1013-NEXT: s_movk_i32 s11, 0x4600
; GFX1013-NEXT: s_movk_i32 s8, 0x4700 ; GFX1013-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX1013-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX1013-NEXT: s_movk_i32 s6, 0x4500
; GFX1013-NEXT: s_movk_i32 s10, 0x4700
; GFX1013-NEXT: s_bfe_u32 s8, s8, 0x100000 ; GFX1013-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX1013-NEXT: s_bfe_u32 s11, s11, 0x100000
; GFX1013-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX1013-NEXT: v_mov_b32_e32 v3, 0 ; GFX1013-NEXT: v_mov_b32_e32 v3, 0
; GFX1013-NEXT: v_mov_b32_e32 v4, 1.0 ; GFX1013-NEXT: v_mov_b32_e32 v4, 1.0
; GFX1013-NEXT: v_mov_b32_e32 v5, 2.0 ; GFX1013-NEXT: v_mov_b32_e32 v5, 2.0
; GFX1013-NEXT: s_waitcnt lgkmcnt(0) ; GFX1013-NEXT: s_waitcnt lgkmcnt(0)
; GFX1013-NEXT: v_mov_b32_e32 v0, s2 ; GFX1013-NEXT: v_mov_b32_e32 v0, s4
; GFX1013-NEXT: v_mov_b32_e32 v1, s3 ; GFX1013-NEXT: v_mov_b32_e32 v1, s5
; GFX1013-NEXT: s_movk_i32 s2, 0x4200 ; GFX1013-NEXT: s_lshl_b32 s4, s7, 16
; GFX1013-NEXT: s_movk_i32 s3, 0x4800 ; GFX1013-NEXT: s_bfe_u32 s7, s9, 0x100000
; GFX1013-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX1013-NEXT: s_lshl_b32 s5, s11, 16
; GFX1013-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 ; GFX1013-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX1013-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX1013-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX1013-NEXT: s_or_b32 s1, s2, s1 ; GFX1013-NEXT: s_or_b32 s4, s8, s4
; GFX1013-NEXT: s_bfe_u32 s2, s9, 0x100000 ; GFX1013-NEXT: s_bfe_u32 s8, s10, 0x100000
; GFX1013-NEXT: s_bfe_u32 s3, s3, 0x100000 ; GFX1013-NEXT: s_lshl_b32 s7, s7, 16
; GFX1013-NEXT: flat_load_dword v2, v[0:1] ; GFX1013-NEXT: flat_load_dword v2, v[0:1]
; GFX1013-NEXT: s_lshl_b32 s2, s2, 16 ; GFX1013-NEXT: s_or_b32 s5, s6, s5
; GFX1013-NEXT: s_lshl_b32 s3, s3, 16 ; GFX1013-NEXT: s_or_b32 s6, s8, s7
; GFX1013-NEXT: s_or_b32 s0, s0, s2
; GFX1013-NEXT: s_or_b32 s2, s8, s3
; GFX1013-NEXT: v_mov_b32_e32 v0, 0xb36211c6 ; GFX1013-NEXT: v_mov_b32_e32 v0, 0xb36211c6
; GFX1013-NEXT: v_mov_b32_e32 v1, 0x102 ; GFX1013-NEXT: v_mov_b32_e32 v1, 0x102
; GFX1013-NEXT: v_mov_b32_e32 v6, s1 ; GFX1013-NEXT: v_mov_b32_e32 v6, s4
; GFX1013-NEXT: v_mov_b32_e32 v7, s0 ; GFX1013-NEXT: v_mov_b32_e32 v7, s5
; GFX1013-NEXT: v_mov_b32_e32 v8, s2 ; GFX1013-NEXT: v_mov_b32_e32 v8, s6
; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[4:7] a16 ; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16
; GFX1013-NEXT: s_waitcnt vmcnt(0) ; GFX1013-NEXT: s_waitcnt vmcnt(0)
; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3] ; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
; GFX1013-NEXT: s_endpgm ; GFX1013-NEXT: s_endpgm
; ;
; GFX11-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: ; GFX11-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x24 ; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x24
Show All 36 Lines; GFX11-NEXT: s_endpgm
%ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2 %ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
%ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0 %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1 %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
%ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2 %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr) %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
store <4 x i32> %v, ptr undef store <4 x i32> %v, ptr undef
ret void ret void
} }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX10: {{.*}}

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xff, v1 ; GFX10-NEXT: v_and_or_b32 v0, v0, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v2 ; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v3 ; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v3
; GFX10-NEXT: v_lshlrev_b32_sdwa v3, s4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v7
; GFX10-NEXT: v_and_b32_e32 v5, 0xff, v6
; GFX10-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX10-NEXT: v_and_or_b32 v3, v4, 0xff, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 24, v6
; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX10-NEXT: v_or3_b32 v1, v3, v4, v5 ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX10-NEXT: v_and_or_b32 v1, v4, 0xff, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: v_or3_b32 v1, v1, v2, v3
; GFX10-NEXT: v_dot4_i32_i8 v0, v0, v1, v8 ; GFX10-NEXT: v_dot4_i32_i8 v0, v0, v1, v8
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%a.cast = bitcast <4 x i8> %a to i32 %a.cast = bitcast <4 x i8> %a to i32
%b.cast = bitcast <4 x i8> %b to i32 %b.cast = bitcast <4 x i8> %b to i32
%r = call i32 @llvm.amdgcn.sdot4(i32 %a.cast, i32 %b.cast, i32 %c, i1 false) %r = call i32 @llvm.amdgcn.sdot4(i32 %a.cast, i32 %b.cast, i32 %c, i1 false)
ret i32 %r ret i32 %r
} }
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xff, v1 ; GFX10-NEXT: v_and_or_b32 v0, v0, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v2 ; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v3 ; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v3
; GFX10-NEXT: v_lshlrev_b32_sdwa v3, s4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v7
; GFX10-NEXT: v_and_b32_e32 v5, 0xff, v6
; GFX10-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX10-NEXT: v_and_or_b32 v3, v4, 0xff, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 24, v6
; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX10-NEXT: v_or3_b32 v1, v3, v4, v5 ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX10-NEXT: v_and_or_b32 v1, v4, 0xff, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: v_or3_b32 v1, v1, v2, v3
; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v8 ; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v8
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_udot4_cast_v4i8: ; GFX11-LABEL: v_udot4_cast_v4i8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1 ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
; GFX7-NEXT: s_setpc_b64 s[30:31] ; GFX7-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: load_lds_v4i32_align1: ; GFX10-LABEL: load_lds_v4i32_align1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_read_u8 v1, v0 ; GFX10-NEXT: ds_read_u8 v1, v0
; GFX10-NEXT: ds_read_u8 v2, v0 offset:1 ; GFX10-NEXT: ds_read_u8 v2, v0 offset:1
; GFX10-NEXT: ds_read_u8 v3, v0 offset:2 ; GFX10-NEXT: ds_read_u8 v3, v0 offset:3
; GFX10-NEXT: ds_read_u8 v4, v0 offset:3 ; GFX10-NEXT: ds_read_u8 v4, v0 offset:2
; GFX10-NEXT: ds_read_u8 v5, v0 offset:4 ; GFX10-NEXT: ds_read_u8 v5, v0 offset:4
; GFX10-NEXT: ds_read_u8 v6, v0 offset:5 ; GFX10-NEXT: ds_read_u8 v6, v0 offset:5
; GFX10-NEXT: ds_read_u8 v7, v0 offset:6 ; GFX10-NEXT: ds_read_u8 v7, v0 offset:7
; GFX10-NEXT: ds_read_u8 v8, v0 offset:7 ; GFX10-NEXT: ds_read_u8 v8, v0 offset:6
; GFX10-NEXT: ds_read_u8 v9, v0 offset:8
; GFX10-NEXT: ds_read_u8 v10, v0 offset:9
; GFX10-NEXT: ds_read_u8 v11, v0 offset:10
; GFX10-NEXT: ds_read_u8 v12, v0 offset:11
; GFX10-NEXT: ds_read_u8 v13, v0 offset:12
; GFX10-NEXT: ds_read_u8 v14, v0 offset:13
; GFX10-NEXT: ds_read_u8 v15, v0 offset:15
; GFX10-NEXT: ds_read_u8 v0, v0 offset:14
; GFX10-NEXT: s_waitcnt lgkmcnt(14)
; GFX10-NEXT: v_lshl_or_b32 v1, v2, 8, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(13)
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_waitcnt lgkmcnt(12)
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v4
; GFX10-NEXT: s_waitcnt lgkmcnt(10)
; GFX10-NEXT: v_lshl_or_b32 v4, v6, 8, v5
; GFX10-NEXT: s_waitcnt lgkmcnt(9)
; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v7
; GFX10-NEXT: s_waitcnt lgkmcnt(8)
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 24, v8
; GFX10-NEXT: s_waitcnt lgkmcnt(6) ; GFX10-NEXT: s_waitcnt lgkmcnt(6)
; GFX10-NEXT: v_lshl_or_b32 v7, v10, 8, v9 ; GFX10-NEXT: v_lshl_or_b32 v1, v2, 8, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(5) ; GFX10-NEXT: s_waitcnt lgkmcnt(5)
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v11 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX10-NEXT: s_waitcnt lgkmcnt(4) ; GFX10-NEXT: s_waitcnt lgkmcnt(4)
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 24, v12 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX10-NEXT: v_or3_b32 v4, v2, v3, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(2) ; GFX10-NEXT: s_waitcnt lgkmcnt(2)
; GFX10-NEXT: v_lshl_or_b32 v10, v14, 8, v13 ; GFX10-NEXT: v_lshl_or_b32 v1, v6, 8, v5
; GFX10-NEXT: s_waitcnt lgkmcnt(1) ; GFX10-NEXT: s_waitcnt lgkmcnt(1)
; GFX10-NEXT: v_lshlrev_b32_e32 v11, 24, v15 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v7
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v8
; GFX10-NEXT: v_or3_b32 v1, v2, v3, v1
; GFX10-NEXT: ds_read_u8 v2, v0 offset:8
; GFX10-NEXT: ds_read_u8 v3, v0 offset:9
; GFX10-NEXT: ds_read_u8 v5, v0 offset:11
; GFX10-NEXT: ds_read_u8 v6, v0 offset:10
; GFX10-NEXT: ds_read_u8 v7, v0 offset:12
; GFX10-NEXT: ds_read_u8 v8, v0 offset:13
; GFX10-NEXT: ds_read_u8 v9, v0 offset:15
; GFX10-NEXT: ds_read_u8 v0, v0 offset:14
; GFX10-NEXT: s_waitcnt lgkmcnt(6)
; GFX10-NEXT: v_lshl_or_b32 v2, v3, 8, v2
; GFX10-NEXT: s_waitcnt lgkmcnt(5)
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v5
; GFX10-NEXT: s_waitcnt lgkmcnt(4)
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_or3_b32 v0, v2, v3, v1 ; GFX10-NEXT: v_or3_b32 v2, v3, v5, v2
; GFX10-NEXT: v_or3_b32 v1, v5, v6, v4 ; GFX10-NEXT: v_lshl_or_b32 v3, v8, 8, v7
; GFX10-NEXT: v_or3_b32 v2, v8, v9, v7 ; GFX10-NEXT: v_lshlrev_b32_e32 v5, 24, v9
; GFX10-NEXT: v_or3_b32 v3, v11, v12, v10 ; GFX10-NEXT: v_or3_b32 v3, v5, v0, v3
; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: load_lds_v4i32_align1: ; GFX11-LABEL: load_lds_v4i32_align1:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: ds_load_u8 v1, v0 ; GFX11-NEXT: ds_load_u8 v1, v0
; GFX11-NEXT: ds_load_u8 v2, v0 offset:1 ; GFX11-NEXT: ds_load_u8 v2, v0 offset:1
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llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; GFX7-NEXT: s_setpc_b64 s[30:31] ; GFX7-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: load_lds_v3i32_align1: ; GFX10-LABEL: load_lds_v3i32_align1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_read_u8 v1, v0 ; GFX10-NEXT: ds_read_u8 v1, v0
; GFX10-NEXT: ds_read_u8 v2, v0 offset:1 ; GFX10-NEXT: ds_read_u8 v2, v0 offset:1
; GFX10-NEXT: ds_read_u8 v3, v0 offset:2 ; GFX10-NEXT: ds_read_u8 v3, v0 offset:3
; GFX10-NEXT: ds_read_u8 v4, v0 offset:3 ; GFX10-NEXT: ds_read_u8 v4, v0 offset:2
; GFX10-NEXT: ds_read_u8 v5, v0 offset:4 ; GFX10-NEXT: ds_read_u8 v5, v0 offset:4
; GFX10-NEXT: ds_read_u8 v6, v0 offset:5 ; GFX10-NEXT: ds_read_u8 v6, v0 offset:5
; GFX10-NEXT: ds_read_u8 v7, v0 offset:6 ; GFX10-NEXT: ds_read_u8 v7, v0 offset:7
; GFX10-NEXT: ds_read_u8 v8, v0 offset:7 ; GFX10-NEXT: ds_read_u8 v8, v0 offset:6
; GFX10-NEXT: ds_read_u8 v9, v0 offset:8
; GFX10-NEXT: ds_read_u8 v10, v0 offset:9
; GFX10-NEXT: ds_read_u8 v11, v0 offset:11
; GFX10-NEXT: ds_read_u8 v0, v0 offset:10
; GFX10-NEXT: s_waitcnt lgkmcnt(10)
; GFX10-NEXT: v_lshl_or_b32 v1, v2, 8, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(9)
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_waitcnt lgkmcnt(8)
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v4
; GFX10-NEXT: s_waitcnt lgkmcnt(6) ; GFX10-NEXT: s_waitcnt lgkmcnt(6)
; GFX10-NEXT: v_lshl_or_b32 v4, v6, 8, v5 ; GFX10-NEXT: v_lshl_or_b32 v1, v2, 8, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(5) ; GFX10-NEXT: s_waitcnt lgkmcnt(5)
; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX10-NEXT: s_waitcnt lgkmcnt(4) ; GFX10-NEXT: s_waitcnt lgkmcnt(4)
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 24, v8 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v8
; GFX10-NEXT: v_or3_b32 v3, v2, v3, v1
; GFX10-NEXT: v_lshl_or_b32 v1, v6, 8, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v7
; GFX10-NEXT: v_or3_b32 v1, v2, v4, v1
; GFX10-NEXT: ds_read_u8 v2, v0 offset:8
; GFX10-NEXT: ds_read_u8 v4, v0 offset:9
; GFX10-NEXT: ds_read_u8 v5, v0 offset:11
; GFX10-NEXT: ds_read_u8 v0, v0 offset:10
; GFX10-NEXT: s_waitcnt lgkmcnt(2) ; GFX10-NEXT: s_waitcnt lgkmcnt(2)
; GFX10-NEXT: v_lshl_or_b32 v7, v10, 8, v9 ; GFX10-NEXT: v_lshl_or_b32 v2, v4, 8, v2
; GFX10-NEXT: s_waitcnt lgkmcnt(1) ; GFX10-NEXT: s_waitcnt lgkmcnt(1)
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 24, v11 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 24, v5
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_or3_b32 v0, v2, v3, v1 ; GFX10-NEXT: v_or3_b32 v2, v4, v0, v2
; GFX10-NEXT: v_or3_b32 v1, v5, v6, v4 ; GFX10-NEXT: v_mov_b32_e32 v0, v3
; GFX10-NEXT: v_or3_b32 v2, v8, v9, v7
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: load_lds_v3i32_align1: ; GFX11-LABEL: load_lds_v3i32_align1:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: ds_load_u8 v1, v0 ; GFX11-NEXT: ds_load_u8 v1, v0
; GFX11-NEXT: ds_load_u8 v2, v0 offset:1 ; GFX11-NEXT: ds_load_u8 v2, v0 offset:1
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llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll

Show First 20 Lines • Show All 476 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v15, v16, v15 ; GCN-NEXT: v_lshrrev_b32_e32 v15, v16, v15
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_lshr_v16i32: ; GFX10-LABEL: v_lshr_v16i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_lshrrev_b32_e32 v0, v16, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, v16, v0
; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GFX10-NEXT: v_lshrrev_b32_e32 v1, v17, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v1, v17, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v2, v18, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, v18, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, v19, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, v19, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v4, v20, v4 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, v20, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v5, v21, v5 ; GFX10-NEXT: v_lshrrev_b32_e32 v5, v21, v5
; GFX10-NEXT: v_lshrrev_b32_e32 v6, v22, v6 ; GFX10-NEXT: v_lshrrev_b32_e32 v6, v22, v6
; GFX10-NEXT: v_lshrrev_b32_e32 v7, v23, v7 ; GFX10-NEXT: v_lshrrev_b32_e32 v7, v23, v7
; GFX10-NEXT: v_lshrrev_b32_e32 v8, v24, v8 ; GFX10-NEXT: v_lshrrev_b32_e32 v8, v24, v8
; GFX10-NEXT: v_lshrrev_b32_e32 v9, v25, v9 ; GFX10-NEXT: v_lshrrev_b32_e32 v9, v25, v9
; GFX10-NEXT: v_lshrrev_b32_e32 v10, v26, v10 ; GFX10-NEXT: v_lshrrev_b32_e32 v10, v26, v10
; GFX10-NEXT: v_lshrrev_b32_e32 v11, v27, v11 ; GFX10-NEXT: v_lshrrev_b32_e32 v11, v27, v11
; GFX10-NEXT: v_lshrrev_b32_e32 v12, v28, v12 ; GFX10-NEXT: v_lshrrev_b32_e32 v12, v28, v12
; GFX10-NEXT: v_lshrrev_b32_e32 v13, v29, v13 ; GFX10-NEXT: v_lshrrev_b32_e32 v13, v29, v13
; GFX10-NEXT: v_lshrrev_b32_e32 v14, v30, v14 ; GFX10-NEXT: v_lshrrev_b32_e32 v14, v30, v14
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v15, v31, v15 ; GFX10-NEXT: v_lshrrev_b32_e32 v15, v16, v15
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_lshr_v16i32: ; GFX11-LABEL: v_lshr_v16i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_lshrrev_b32_e32 v0, v16, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v0, v16, v0
; GFX11-NEXT: scratch_load_b32 v16, off, s32
; GFX11-NEXT: v_lshrrev_b32_e32 v1, v17, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v1, v17, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v2, v18, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v2, v18, v2
; GFX11-NEXT: v_lshrrev_b32_e32 v3, v19, v3 ; GFX11-NEXT: v_lshrrev_b32_e32 v3, v19, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v4, v20, v4 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, v20, v4
; GFX11-NEXT: v_lshrrev_b32_e32 v5, v21, v5 ; GFX11-NEXT: v_lshrrev_b32_e32 v5, v21, v5
; GFX11-NEXT: v_lshrrev_b32_e32 v6, v22, v6 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, v22, v6
; GFX11-NEXT: v_lshrrev_b32_e32 v7, v23, v7 ; GFX11-NEXT: v_lshrrev_b32_e32 v7, v23, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v8, v24, v8 ; GFX11-NEXT: v_lshrrev_b32_e32 v8, v24, v8
; GFX11-NEXT: v_lshrrev_b32_e32 v9, v25, v9 ; GFX11-NEXT: v_lshrrev_b32_e32 v9, v25, v9
; GFX11-NEXT: v_lshrrev_b32_e32 v10, v26, v10 ; GFX11-NEXT: v_lshrrev_b32_e32 v10, v26, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v11, v27, v11 ; GFX11-NEXT: v_lshrrev_b32_e32 v11, v27, v11
; GFX11-NEXT: v_lshrrev_b32_e32 v12, v28, v12 ; GFX11-NEXT: v_lshrrev_b32_e32 v12, v28, v12
; GFX11-NEXT: v_lshrrev_b32_e32 v13, v29, v13 ; GFX11-NEXT: v_lshrrev_b32_e32 v13, v29, v13
; GFX11-NEXT: v_lshrrev_b32_e32 v14, v30, v14 ; GFX11-NEXT: v_lshrrev_b32_e32 v14, v30, v14
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshrrev_b32_e32 v15, v31, v15 ; GFX11-NEXT: v_lshrrev_b32_e32 v15, v16, v15
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = lshr <16 x i32> %value, %amount %result = lshr <16 x i32> %value, %amount
ret <16 x i32> %result ret <16 x i32> %result
} }
define amdgpu_ps <16 x i32> @s_lshr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) { define amdgpu_ps <16 x i32> @s_lshr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) {
; GCN-LABEL: s_lshr_v16i32: ; GCN-LABEL: s_lshr_v16i32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
▲ Show 20 Lines • Show All 1,128 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_lshr_i65: ; GFX10-LABEL: v_lshr_i65:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_and_b32_e32 v4, 1, v2 ; GFX10-NEXT: v_and_b32_e32 v4, 1, v2
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v3 ; GFX10-NEXT: v_lshrrev_b64 v[8:9], v3, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3 ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v3
; GFX10-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5] ; GFX10-NEXT: v_lshlrev_b64 v[6:7], v2, v[4:5]
; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[4:5] ; GFX10-NEXT: v_or_b32_e32 v2, v8, v6
; GFX10-NEXT: v_lshrrev_b64 v[4:5], v3, v[4:5] ; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 64, v3
; GFX10-NEXT: v_or_b32_e32 v2, v6, v8 ; GFX10-NEXT: v_or_b32_e32 v8, v9, v7
; GFX10-NEXT: v_or_b32_e32 v6, v7, v9 ; GFX10-NEXT: v_lshrrev_b64 v[6:7], v6, v[4:5]
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4 ; GFX10-NEXT: v_lshrrev_b64 v[2:3], v3, v[4:5]
; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v6, v1, s4
; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_lshr_i65: ; GFX11-LABEL: v_lshr_i65:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v4, 1, v2 ; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v4, 1, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v3 ; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v3
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llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx1010 -global-isel=1 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -global-isel=1 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GFX10 %s
; RUN: llc -march=amdgcn -mcpu=gfx1100 -global-isel=1 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GFX11 %s ; RUN: llc -march=amdgcn -mcpu=gfx1100 -global-isel=1 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GFX11 %s
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
; A 64-bit multiplication where no arguments were zero extended. ; A 64-bit multiplication where no arguments were zero extended.
define amdgpu_kernel void @v_mul_i64_zext_00(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind { define amdgpu_kernel void @v_mul_i64_zext_00(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {
; GFX10-LABEL: v_mul_i64_zext_00: ; GFX10-LABEL: v_mul_i64_zext_00:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c
; GFX10-NEXT: v_lshlrev_b32_e32 v6, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx2 v[0:1], v6, s[0:1] ; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v6, s[2:3] ; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mad_u64_u32 v[4:5], s0, v0, v2, 0 ; GFX10-NEXT: v_mul_lo_u32 v3, v0, v3
; GFX10-NEXT: v_mul_lo_u32 v0, v0, v3 ; GFX10-NEXT: v_mul_lo_u32 v5, v1, v2
; GFX10-NEXT: v_mul_lo_u32 v1, v1, v2 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v0, v2, 0
; GFX10-NEXT: v_add3_u32 v5, v5, v0, v1 ; GFX10-NEXT: v_add3_u32 v1, v1, v3, v5
; GFX10-NEXT: global_store_dwordx2 v6, v[4:5], s[2:3] ; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_mul_i64_zext_00: ; GFX11-LABEL: v_mul_i64_zext_00:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x2c ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x2c
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 3, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v6, 3, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
Show All 27 Lines
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 2, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[6:7] ; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[6:7]
; GFX10-NEXT: global_load_dword v4, v3, s[2:3] ; GFX10-NEXT: global_load_dword v4, v3, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, v0, v4, 0 ; GFX10-NEXT: v_mul_lo_u32 v2, v1, v4
; GFX10-NEXT: v_mul_lo_u32 v0, v1, v4 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v0, v4, 0
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: global_store_dwordx2 v0, v[2:3], s[4:5] ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_mul_i64_zext_01: ; GFX11-LABEL: v_mul_i64_zext_01:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 3, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 3, v0
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; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 3, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dword v4, v2, s[6:7] ; GFX10-NEXT: global_load_dword v4, v2, s[6:7]
; GFX10-NEXT: global_load_dwordx2 v[0:1], v3, s[2:3] ; GFX10-NEXT: global_load_dwordx2 v[0:1], v3, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, v4, v0, 0 ; GFX10-NEXT: v_mul_lo_u32 v2, v4, v1
; GFX10-NEXT: v_mul_lo_u32 v0, v4, v1 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v4, v0, 0
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: global_store_dwordx2 v0, v[2:3], s[4:5] ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_mul_i64_zext_10: ; GFX11-LABEL: v_mul_i64_zext_10:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v0
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; GFX10-LABEL: v_mul_i64_and_a_hi: ; GFX10-LABEL: v_mul_i64_and_a_hi:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dword v4, v2, s[6:7] ; GFX10-NEXT: global_load_dword v3, v2, s[6:7]
; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] ; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, v4, v0, 0 ; GFX10-NEXT: v_mul_lo_u32 v2, v3, v1
; GFX10-NEXT: v_mul_lo_u32 v0, v4, v1 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v3, v0, 0
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: global_store_dwordx2 v0, v[2:3], s[4:5] ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_mul_i64_and_a_hi: ; GFX11-LABEL: v_mul_i64_and_a_hi:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0
Show All 20 Lines %tid = call i32 @llvm.amdgcn.workitem.id.x()
ret void ret void
} }
; 64-bit multiplication where lower bytes of first argument were masked. ; 64-bit multiplication where lower bytes of first argument were masked.
define amdgpu_kernel void @v_mul_i64_and_a_lo(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { define amdgpu_kernel void @v_mul_i64_and_a_lo(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
; GFX10-LABEL: v_mul_i64_and_a_lo: ; GFX10-LABEL: v_mul_i64_and_a_lo:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3] ; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7] ; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_mad_u64_u32 v[4:5], s0, 0, v0, 0
; GFX10-NEXT: v_mul_lo_u32 v1, 0, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mul_lo_u32 v0, v3, v0 ; GFX10-NEXT: v_mul_lo_u32 v4, v1, v2
; GFX10-NEXT: v_add3_u32 v5, v5, v1, v0 ; GFX10-NEXT: v_mul_lo_u32 v3, 0, v3
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, 0, v2, 0
; GFX10-NEXT: global_store_dwordx2 v0, v[4:5], s[4:5] ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_add3_u32 v1, v1, v3, v4
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_mul_i64_and_a_lo: ; GFX11-LABEL: v_mul_i64_and_a_lo:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x34 ; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x34
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0
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; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7] ; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3] ; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_mad_u64_u32 v[4:5], s0, v0, 0, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mul_lo_u32 v0, v0, v3 ; GFX10-NEXT: v_mul_lo_u32 v2, v0, v3
; GFX10-NEXT: v_mul_lo_u32 v1, v1, 0 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, 0
; GFX10-NEXT: v_add3_u32 v5, v5, v0, v1 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v0, 0, 0
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_add3_u32 v1, v1, v2, v3
; GFX10-NEXT: global_store_dwordx2 v0, v[4:5], s[4:5] ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_mul_i64_and_b_lo: ; GFX11-LABEL: v_mul_i64_and_b_lo:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0
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; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7] ; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3] ; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_and_b32_e32 v4, 0xfff00000, v0 ; GFX10-NEXT: v_and_b32_e32 v1, 0xf00f, v1
; GFX10-NEXT: v_and_b32_e32 v5, 0xf00f, v1 ; GFX10-NEXT: v_and_b32_e32 v0, 0xfff00000, v0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v4, v2, 0 ; GFX10-NEXT: v_mul_lo_u32 v4, v1, v2
; GFX10-NEXT: v_mul_lo_u32 v3, v4, v3 ; GFX10-NEXT: v_mul_lo_u32 v3, v0, v3
; GFX10-NEXT: v_mul_lo_u32 v2, v5, v2 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v0, v2, 0
; GFX10-NEXT: v_add3_u32 v1, v1, v3, v2
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_add3_u32 v1, v1, v3, v4
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_mul_i64_partially_masked_src0: ; GFX11-LABEL: v_mul_i64_partially_masked_src0:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
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; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx2 v[2:3], v0, s[6:7] ; GFX10-NEXT: global_load_dwordx2 v[2:3], v0, s[6:7]
; GFX10-NEXT: global_load_dwordx2 v[4:5], v0, s[2:3] ; GFX10-NEXT: global_load_dwordx2 v[4:5], v0, s[2:3]
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_cmp_ge_u64_e32 vcc_lo, 0, v[2:3] ; GFX10-NEXT: v_cmp_ge_u64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mul_lo_u32 v5, v2, v5 ; GFX10-NEXT: v_mul_lo_u32 v3, v2, v5
; GFX10-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GFX10-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX10-NEXT: s_xor_b32 s0, exec_lo, s0 ; GFX10-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX10-NEXT: ; %bb.1: ; %else ; GFX10-NEXT: ; %bb.1: ; %else
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s1, v2, v4, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s1, v2, v4, 0
; GFX10-NEXT: v_mul_lo_u32 v2, 0, v4 ; GFX10-NEXT: v_mul_lo_u32 v2, 0, v4
; GFX10-NEXT: v_add3_u32 v1, v1, v5, v2 ; GFX10-NEXT: v_add3_u32 v1, v1, v3, v2
; GFX10-NEXT: ; implicit-def: $vgpr2_vgpr3 ; GFX10-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr5 ; GFX10-NEXT: ; implicit-def: $vgpr3
; GFX10-NEXT: ; %bb.2: ; %Flow ; GFX10-NEXT: ; %bb.2: ; %Flow
; GFX10-NEXT: s_andn2_saveexec_b32 s0, s0 ; GFX10-NEXT: s_andn2_saveexec_b32 s0, s0
; GFX10-NEXT: ; %bb.3: ; %if ; GFX10-NEXT: ; %bb.3: ; %if
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s1, v2, 0, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s1, v2, 0, 0
; GFX10-NEXT: v_mul_lo_u32 v2, 0, 0 ; GFX10-NEXT: v_mul_lo_u32 v2, 0, 0
; GFX10-NEXT: v_add3_u32 v1, v1, v5, v2 ; GFX10-NEXT: v_add3_u32 v1, v1, v3, v2
; GFX10-NEXT: ; %bb.4: ; %endif ; GFX10-NEXT: ; %bb.4: ; %endif
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: mul64_and_in_branch_2: ; GFX11-LABEL: mul64_and_in_branch_2:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
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llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll

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; GCN-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, v3, v[1:2] ; GCN-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, v3, v[1:2]
; GCN-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v2, v[3:4] ; GCN-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v2, v[3:4]
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_i64: ; GFX10-LABEL: v_mul_i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v4, v0 ; GFX10-NEXT: v_mul_lo_u32 v3, v0, v3
; GFX10-NEXT: v_mov_b32_e32 v5, v1 ; GFX10-NEXT: v_mul_lo_u32 v4, v1, v2
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v2, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v0, v2, 0
; GFX10-NEXT: v_mul_lo_u32 v3, v4, v3 ; GFX10-NEXT: v_add3_u32 v1, v1, v3, v4
; GFX10-NEXT: v_mul_lo_u32 v2, v5, v2
; GFX10-NEXT: v_add3_u32 v1, v1, v3, v2
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_i64: ; GFX11-LABEL: v_mul_i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v1 ; GFX11-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v1
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v2, 0 ; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v2, 0
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; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_i96: ; GFX10-LABEL: v_mul_i96:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v6, v0 ; GFX10-NEXT: v_mov_b32_e32 v6, v0
; GFX10-NEXT: v_mov_b32_e32 v7, v1 ; GFX10-NEXT: v_mov_b32_e32 v7, v1
; GFX10-NEXT: v_mul_lo_u32 v2, v2, v3 ; GFX10-NEXT: v_mul_lo_u32 v1, v2, v3
; GFX10-NEXT: v_mul_lo_u32 v5, v6, v5 ; GFX10-NEXT: v_mul_lo_u32 v0, v6, v5
; GFX10-NEXT: v_mul_lo_u32 v8, v7, v4 ; GFX10-NEXT: v_mul_lo_u32 v2, v7, v4
; GFX10-NEXT: v_add3_u32 v2, v0, v2, v1
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v6, v3, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v6, v3, 0
; GFX10-NEXT: v_add3_u32 v2, v5, v8, v2
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v6, v4, v[1:2] ; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v6, v4, v[1:2]
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v7, v3, v[1:2] ; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v7, v3, v[1:2]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_i96: ; GFX11-LABEL: v_mul_i96:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v8, v0 ; GFX10-NEXT: v_mov_b32_e32 v8, v0
; GFX10-NEXT: v_mov_b32_e32 v9, v1 ; GFX10-NEXT: v_mov_b32_e32 v9, v1
; GFX10-NEXT: v_mov_b32_e32 v10, v2 ; GFX10-NEXT: v_mov_b32_e32 v10, v2
; GFX10-NEXT: v_mul_lo_u32 v3, v3, v4 ; GFX10-NEXT: v_mul_lo_u32 v3, v3, v4
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v8, v6, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v8, v6, 0
; GFX10-NEXT: v_mul_lo_u32 v7, v8, v7 ; GFX10-NEXT: v_mul_lo_u32 v7, v8, v7
; GFX10-NEXT: v_mul_lo_u32 v6, v9, v6 ; GFX10-NEXT: v_mul_lo_u32 v6, v9, v6
; GFX10-NEXT: v_mad_u64_u32 v[11:12], s4, v9, v5, v[0:1] ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v9, v5, v[0:1]
; GFX10-NEXT: v_mad_u64_u32 v[11:12], s4, v10, v4, v[0:1]
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v8, v4, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v8, v4, 0
; GFX10-NEXT: v_mad_u64_u32 v[11:12], s4, v10, v4, v[11:12]
; GFX10-NEXT: v_mov_b32_e32 v2, v11 ; GFX10-NEXT: v_mov_b32_e32 v2, v11
; GFX10-NEXT: v_mad_u64_u32 v[1:2], vcc_lo, v8, v5, v[1:2] ; GFX10-NEXT: v_mad_u64_u32 v[1:2], vcc_lo, v8, v5, v[1:2]
; GFX10-NEXT: v_mul_lo_u32 v5, v10, v5 ; GFX10-NEXT: v_mul_lo_u32 v5, v10, v5
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v9, v4, v[1:2] ; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v9, v4, v[1:2]
; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, v12, v7, s4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, v12, v7, s4
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v7, v6, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v7, v6, vcc_lo
; GFX10-NEXT: v_add3_u32 v3, v4, v5, v3 ; GFX10-NEXT: v_add3_u32 v3, v4, v5, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
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; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_i256: ; GFX10-LABEL: v_mul_i256:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v16, v0 ; GFX10-NEXT: v_mov_b32_e32 v16, v0
; GFX10-NEXT: v_mov_b32_e32 v17, v1 ; GFX10-NEXT: v_mov_b32_e32 v17, v1
; GFX10-NEXT: v_mul_lo_u32 v27, v6, v9 ; GFX10-NEXT: v_mul_lo_u32 v25, v6, v9
; GFX10-NEXT: v_mul_lo_u32 v28, v5, v10 ; GFX10-NEXT: v_mul_lo_u32 v26, v5, v10
; GFX10-NEXT: v_mul_lo_u32 v7, v7, v8 ; GFX10-NEXT: v_mul_lo_u32 v7, v7, v8
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v16, v14, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v16, v14, 0
; GFX10-NEXT: v_mad_u64_u32 v[18:19], s4, v16, v12, 0 ; GFX10-NEXT: v_mad_u64_u32 v[18:19], s4, v16, v12, 0
; GFX10-NEXT: v_mul_lo_u32 v30, v17, v14
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v17, v13, v[0:1] ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v17, v13, v[0:1]
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v2, v12, v[0:1] ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v2, v12, v[0:1]
; GFX10-NEXT: v_mad_u64_u32 v[18:19], s4, v17, v11, v[18:19] ; GFX10-NEXT: v_mad_u64_u32 v[18:19], s4, v17, v11, v[18:19]
; GFX10-NEXT: v_cndmask_b32_e64 v20, 0, 1, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v20, 0, 1, s4
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s5, v3, v11, v[0:1] ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s5, v3, v11, v[0:1]
; GFX10-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v2, v10, v[18:19] ; GFX10-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v2, v10, v[18:19]
; GFX10-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, 0, v20, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
; GFX10-NEXT: v_mad_u64_u32 v[20:21], s4, v16, v10, 0
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v10, v[0:1] ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v10, v[0:1]
; GFX10-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v3, v9, v[18:19] ; GFX10-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v3, v9, v[18:19]
; GFX10-NEXT: v_add_co_ci_u32_e32 v24, vcc_lo, 0, v22, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, 0, v20, vcc_lo
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v5, v9, v[0:1] ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v5, v9, v[0:1]
; GFX10-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v4, v8, v[18:19] ; GFX10-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v4, v8, v[18:19]
; GFX10-NEXT: v_add_co_ci_u32_e32 v26, vcc_lo, 0, v24, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v24, vcc_lo, 0, v22, vcc_lo
; GFX10-NEXT: v_mad_u64_u32 v[22:23], s4, v6, v8, v[0:1] ; GFX10-NEXT: v_mad_u64_u32 v[20:21], s4, v6, v8, v[0:1]
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v17, v9, v[20:21] ; GFX10-NEXT: v_mov_b32_e32 v0, v19
; GFX10-NEXT: v_cndmask_b32_e64 v25, 0, 1, s4 ; GFX10-NEXT: v_mov_b32_e32 v23, v18
; GFX10-NEXT: v_mov_b32_e32 v20, v22 ; GFX10-NEXT: v_mul_lo_u32 v18, v4, v11
; GFX10-NEXT: v_mad_u64_u32 v[21:22], vcc_lo, v2, v8, v[0:1] ; GFX10-NEXT: v_mov_b32_e32 v1, v20
; GFX10-NEXT: v_add_co_ci_u32_e32 v29, vcc_lo, 0, v25, vcc_lo ; GFX10-NEXT: v_mad_u64_u32 v[19:20], s4, v16, v10, 0
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v16, v13, v[19:20] ; GFX10-NEXT: v_mad_u64_u32 v[0:1], vcc_lo, v16, v13, v[0:1]
; GFX10-NEXT: v_mov_b32_e32 v20, v18 ; GFX10-NEXT: v_mad_u64_u32 v[19:20], s4, v17, v9, v[19:20]
; GFX10-NEXT: v_mov_b32_e32 v19, v22 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s4
; GFX10-NEXT: v_mul_lo_u32 v22, v16, v15 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s5, v17, v12, v[0:1]
; GFX10-NEXT: v_mad_u64_u32 v[24:25], vcc_lo, v17, v12, v[0:1] ; GFX10-NEXT: v_mad_u64_u32 v[19:20], s4, v2, v8, v[19:20]
; GFX10-NEXT: v_mad_u64_u32 v[14:15], s6, v16, v11, v[19:20] ; GFX10-NEXT: v_add_co_ci_u32_e64 v27, s4, 0, v6, s4
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s5, v16, v8, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v2, v11, v[0:1]
; GFX10-NEXT: v_mul_lo_u32 v20, v4, v11 ; GFX10-NEXT: v_mov_b32_e32 v22, v20
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6 ; GFX10-NEXT: v_mul_lo_u32 v20, v3, v12
; GFX10-NEXT: v_mad_u64_u32 v[18:19], s5, v2, v11, v[24:25] ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s6, v3, v10, v[0:1]
; GFX10-NEXT: v_mul_lo_u32 v25, v3, v12 ; GFX10-NEXT: v_mad_u64_u32 v[22:23], s7, v16, v11, v[22:23]
; GFX10-NEXT: v_mad_u64_u32 v[11:12], s6, v17, v10, v[14:15] ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s7
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s6, 0, v6, s6 ; GFX10-NEXT: v_mad_u64_u32 v[10:11], s7, v17, v10, v[22:23]
; GFX10-NEXT: v_mul_lo_u32 v24, v2, v13 ; GFX10-NEXT: v_mul_lo_u32 v22, v2, v13
; GFX10-NEXT: v_mad_u64_u32 v[18:19], s7, v3, v10, v[18:19] ; GFX10-NEXT: v_mad_u64_u32 v[12:13], s8, v4, v9, v[0:1]
; GFX10-NEXT: v_mov_b32_e32 v13, v1 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s9, v16, v8, 0
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s6, v2, v9, v[11:12] ; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s7, 0, v6, s7
; GFX10-NEXT: v_mov_b32_e32 v14, v21 ; GFX10-NEXT: v_mad_u64_u32 v[10:11], s7, v2, v9, v[10:11]
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s6, 0, v6, s6 ; GFX10-NEXT: v_mov_b32_e32 v2, v19
; GFX10-NEXT: v_mad_u64_u32 v[10:11], s6, v4, v9, v[18:19] ; GFX10-NEXT: v_mad_u64_u32 v[5:6], s9, v5, v8, v[12:13]
; GFX10-NEXT: v_mad_u64_u32 v[12:13], s8, v16, v9, v[13:14] ; GFX10-NEXT: v_add_co_ci_u32_e64 v12, s7, 0, v4, s7
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s8 ; GFX10-NEXT: v_mad_u64_u32 v[1:2], s10, v16, v9, v[1:2]
; GFX10-NEXT: v_mad_u64_u32 v[3:4], s8, v3, v8, v[1:2] ; GFX10-NEXT: v_mad_u64_u32 v[3:4], s7, v3, v8, v[10:11]
; GFX10-NEXT: v_add_co_ci_u32_e64 v14, s8, 0, v6, s8 ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s10
; GFX10-NEXT: v_mad_u64_u32 v[5:6], s8, v5, v8, v[10:11] ; GFX10-NEXT: v_add_co_ci_u32_e64 v10, s7, 0, v12, s7
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s9, v17, v8, v[12:13] ; GFX10-NEXT: v_mul_lo_u32 v9, v17, v14
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s9, v9, v3, s9 ; GFX10-NEXT: v_mad_u64_u32 v[1:2], s7, v17, v8, v[1:2]
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s9, v29, v4, s9 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s7, v11, v3, s7
; GFX10-NEXT: v_add_co_ci_u32_e64 v5, s9, v14, v5, s9 ; GFX10-NEXT: v_mul_lo_u32 v11, v16, v15
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s9, v26, v6, s9 ; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s7, v27, v4, s7
; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s9, v23, v22, s9 ; GFX10-NEXT: v_add_co_ci_u32_e64 v5, s7, v10, v5, s7
; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s8, v9, v30, s8 ; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s7, v24, v6, s7
; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s6, v9, v24, s6 ; GFX10-NEXT: v_add_co_ci_u32_e64 v10, s7, v21, v11, s7
; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s6, v9, v25, s7 ; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s7, v10, v9, s9
; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s5, v9, v20, s5 ; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s7, v9, v22, s8
; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v9, v28, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s6, v9, v20, s6
; GFX10-NEXT: v_add_co_ci_u32_e64 v8, vcc_lo, v9, v27, s4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s4, v9, v18, s4
; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s4, v9, v26, s5
; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, v9, v25, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v7, v8, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v7, v8, v7
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_i256: ; GFX11-LABEL: v_mul_i256:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v17, v1 ; GFX11-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v17, v1
; GFX11-NEXT: v_mul_lo_u32 v25, v6, v9
; GFX11-NEXT: v_mul_lo_u32 v26, v5, v10
; GFX11-NEXT: v_mul_lo_u32 v7, v7, v8 ; GFX11-NEXT: v_mul_lo_u32 v7, v7, v8
; GFX11-NEXT: v_mul_lo_u32 v27, v6, v9
; GFX11-NEXT: v_mul_lo_u32 v28, v5, v10
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v16, v14, 0 ; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v16, v14, 0
; GFX11-NEXT: v_mad_u64_u32 v[18:19], null, v16, v12, 0 ; GFX11-NEXT: v_mad_u64_u32 v[18:19], null, v16, v12, 0
; GFX11-NEXT: v_mul_lo_u32 v30, v17, v14
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v17, v13, v[0:1] ; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v17, v13, v[0:1]
; GFX11-NEXT: v_mad_u64_u32 v[18:19], s0, v17, v11, v[18:19] ; GFX11-NEXT: v_mad_u64_u32 v[18:19], s0, v17, v11, v[18:19]
; GFX11-NEXT: v_cndmask_b32_e64 v20, 0, 1, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v20, 0, 1, s0
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v12, v[0:1] ; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v12, v[0:1]
; GFX11-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v2, v10, v[18:19] ; GFX11-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v2, v10, v[18:19]
; GFX11-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, 0, v20, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
; GFX11-NEXT: v_mad_u64_u32 v[20:21], null, v16, v10, 0
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v3, v11, v[0:1] ; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v3, v11, v[0:1]
; GFX11-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v3, v9, v[18:19] ; GFX11-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v3, v9, v[18:19]
; GFX11-NEXT: v_add_co_ci_u32_e32 v24, vcc_lo, 0, v22, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, 0, v20, vcc_lo
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v10, v[0:1] ; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v10, v[0:1]
; GFX11-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v4, v8, v[18:19] ; GFX11-NEXT: v_mad_u64_u32 v[18:19], vcc_lo, v4, v8, v[18:19]
; GFX11-NEXT: v_add_co_ci_u32_e32 v26, vcc_lo, 0, v24, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v24, vcc_lo, 0, v22, vcc_lo
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v5, v9, v[0:1] ; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v5, v9, v[0:1]
; GFX11-NEXT: v_mad_u64_u32 v[22:23], null, v6, v8, v[0:1] ; GFX11-NEXT: v_mad_u64_u32 v[20:21], null, v6, v8, v[0:1]
; GFX11-NEXT: v_mad_u64_u32 v[0:1], s0, v17, v9, v[20:21] ; GFX11-NEXT: v_dual_mov_b32 v0, v19 :: v_dual_mov_b32 v1, v20
; GFX11-NEXT: v_cndmask_b32_e64 v25, 0, 1, s0 ; GFX11-NEXT: v_mad_u64_u32 v[19:20], null, v16, v10, 0
; GFX11-NEXT: v_mov_b32_e32 v20, v22 ; GFX11-NEXT: v_mad_u64_u32 v[0:1], vcc_lo, v16, v13, v[0:1]
; GFX11-NEXT: v_mad_u64_u32 v[21:22], vcc_lo, v2, v8, v[0:1] ; GFX11-NEXT: v_mad_u64_u32 v[19:20], s0, v17, v9, v[19:20]
; GFX11-NEXT: v_add_co_ci_u32_e32 v29, vcc_lo, 0, v25, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX11-NEXT: v_mad_u64_u32 v[0:1], s0, v16, v13, v[19:20] ; GFX11-NEXT: v_mad_u64_u32 v[0:1], s1, v17, v12, v[0:1]
; GFX11-NEXT: v_mov_b32_e32 v20, v18 ; GFX11-NEXT: v_mad_u64_u32 v[19:20], s0, v2, v8, v[19:20]
; GFX11-NEXT: v_mov_b32_e32 v19, v22 ; GFX11-NEXT: v_mov_b32_e32 v23, v18
; GFX11-NEXT: v_mul_lo_u32 v22, v16, v15 ; GFX11-NEXT: v_add_co_ci_u32_e64 v27, s0, 0, v6, s0
; GFX11-NEXT: v_mad_u64_u32 v[24:25], vcc_lo, v17, v12, v[0:1] ; GFX11-NEXT: v_mad_u64_u32 v[0:1], s0, v2, v11, v[0:1]
; GFX11-NEXT: v_mad_u64_u32 v[14:15], s2, v16, v11, v[19:20] ; GFX11-NEXT: v_mul_lo_u32 v18, v4, v11
; GFX11-NEXT: v_mov_b32_e32 v22, v20
; GFX11-NEXT: v_mul_lo_u32 v20, v3, v12
; GFX11-NEXT: v_mad_u64_u32 v[22:23], s3, v16, v11, v[22:23]
; GFX11-NEXT: v_mad_u64_u32 v[0:1], s2, v3, v10, v[0:1]
; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 1, s3
; GFX11-NEXT: v_mad_u64_u32 v[10:11], s3, v17, v10, v[22:23]
; GFX11-NEXT: v_mul_lo_u32 v22, v2, v13
; GFX11-NEXT: v_mad_u64_u32 v[12:13], s4, v4, v9, v[0:1]
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v16, v8, 0 ; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v16, v8, 0
; GFX11-NEXT: v_mul_lo_u32 v20, v4, v11 ; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s3, 0, v6, s3
; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 1, s2 ; GFX11-NEXT: v_mad_u64_u32 v[10:11], s3, v2, v9, v[10:11]
; GFX11-NEXT: v_mad_u64_u32 v[18:19], s1, v2, v11, v[24:25] ; GFX11-NEXT: v_mov_b32_e32 v2, v19
; GFX11-NEXT: v_mul_lo_u32 v25, v3, v12 ; GFX11-NEXT: v_mad_u64_u32 v[5:6], s5, v5, v8, v[12:13]
; GFX11-NEXT: v_mad_u64_u32 v[11:12], s2, v17, v10, v[14:15] ; GFX11-NEXT: v_add_co_ci_u32_e64 v12, s3, 0, v4, s3
; GFX11-NEXT: v_mov_b32_e32 v14, v21 ; GFX11-NEXT: v_mad_u64_u32 v[1:2], s6, v16, v9, v[1:2]
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s2, 0, v6, s2 ; GFX11-NEXT: v_mad_u64_u32 v[3:4], s3, v3, v8, v[10:11]
; GFX11-NEXT: v_mad_u64_u32 v[18:19], s3, v3, v10, v[18:19] ; GFX11-NEXT: v_cndmask_b32_e64 v11, 0, 1, s6
; GFX11-NEXT: v_mul_lo_u32 v24, v2, v13 ; GFX11-NEXT: v_add_co_ci_u32_e64 v10, s3, 0, v12, s3
; GFX11-NEXT: v_mov_b32_e32 v13, v1 ; GFX11-NEXT: v_mul_lo_u32 v9, v17, v14
; GFX11-NEXT: v_mad_u64_u32 v[1:2], s2, v2, v9, v[11:12] ; GFX11-NEXT: v_mad_u64_u32 v[1:2], s3, v17, v8, v[1:2]
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s2, 0, v6, s2 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s3, v11, v3, s3
; GFX11-NEXT: v_mad_u64_u32 v[10:11], s2, v4, v9, v[18:19] ; GFX11-NEXT: v_mul_lo_u32 v11, v16, v15
; GFX11-NEXT: v_mad_u64_u32 v[12:13], s4, v16, v9, v[13:14] ; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s3, v27, v4, s3
; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, 1, s4 ; GFX11-NEXT: v_add_co_ci_u32_e64 v5, s3, v10, v5, s3
; GFX11-NEXT: v_mad_u64_u32 v[3:4], s4, v3, v8, v[1:2] ; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s3, v24, v6, s3
; GFX11-NEXT: v_add_co_ci_u32_e64 v14, s4, 0, v6, s4 ; GFX11-NEXT: v_add_co_ci_u32_e64 v10, s3, v21, v11, s3
; GFX11-NEXT: v_mad_u64_u32 v[5:6], s4, v5, v8, v[10:11] ; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s3, v10, v9, s5
; GFX11-NEXT: v_mad_u64_u32 v[1:2], s5, v17, v8, v[12:13] ; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s3, v9, v22, s4
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s5, v9, v3, s5 ; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s2, v9, v20, s2
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s5, v29, v4, s5 ; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s0, v9, v18, s0
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, s5, v14, v5, s5 ; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s0, v9, v26, s1
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s5, v26, v6, s5 ; GFX11-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, v9, v25, vcc_lo
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s5, v23, v22, s5
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s4, v9, v30, s4
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s2, v9, v24, s2
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s2, v9, v25, s3
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, s1, v9, v20, s1
; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v9, v28, vcc_lo
; GFX11-NEXT: v_add_co_ci_u32_e64 v8, vcc_lo, v9, v27, s0
; GFX11-NEXT: v_add_nc_u32_e32 v7, v8, v7 ; GFX11-NEXT: v_add_nc_u32_e32 v7, v8, v7
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = mul i256 %num, %den %result = mul i256 %num, %den
ret i256 %result ret i256 %result
} }

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

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; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_saddsat_v4i8: ; GFX10-LABEL: v_saddsat_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 24, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 24, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 8, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 24, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 24, v1
; GFX10-NEXT: v_perm_b32 v2, v2, v0, 0x5040100 ; GFX10-NEXT: v_perm_b32 v2, v2, v0, 0x5040100
; GFX10-NEXT: v_alignbit_b32 v0, v3, v0, 16 ; GFX10-NEXT: v_alignbit_b32 v0, v3, v0, 16
; GFX10-NEXT: v_perm_b32 v3, v4, v1, 0x5040100 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX10-NEXT: v_alignbit_b32 v1, v5, v1, 16
; GFX10-NEXT: v_mov_b32_e32 v4, 24
; GFX10-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_perm_b32 v3, v3, v1, 0x5040100
; GFX10-NEXT: v_alignbit_b32 v1, v4, v1, 16
; GFX10-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_add_i16 v2, v2, v3 clamp ; GFX10-NEXT: v_pk_add_i16 v2, v2, v3 clamp
; GFX10-NEXT: v_mov_b32_e32 v3, 8
; GFX10-NEXT: v_pk_add_i16 v0, v0, v1 clamp ; GFX10-NEXT: v_pk_add_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_mov_b32_e32 v1, 8 ; GFX10-NEXT: v_pk_ashrrev_i16 v1, 8, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_ashrrev_i16 v2, 8, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v0 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v0
; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; GFX10-NEXT: v_and_or_b32 v1, v1, 0xff, v2
; GFX10-NEXT: v_and_or_b32 v1, v2, 0xff, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, 24
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_or3_b32 v0, v1, v3, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_saddsat_v4i8: ; GFX11-LABEL: v_saddsat_v4i8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
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; GFX9-NEXT: v_add_i32 v4, s4, v4 clamp ; GFX9-NEXT: v_add_i32 v4, s4, v4 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v4 ; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: s_saddsat_v5i32: ; GFX10-LABEL: s_saddsat_v5i32:
; GFX10PLUS: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10PLUS-NEXT: v_add_nc_i32 v0, s0, s5 clamp ; GFX10-NEXT: v_add_nc_i32 v0, s0, s5 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v1, s1, s6 clamp ; GFX10-NEXT: v_add_nc_i32 v1, s1, s6 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v2, s2, s7 clamp ; GFX10-NEXT: v_add_nc_i32 v2, s2, s7 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v3, s3, s8 clamp ; GFX10-NEXT: v_add_nc_i32 v3, s3, s8 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v4, s4, s9 clamp ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_add_nc_i32 v0, s4, s9 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_saddsat_v5i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_add_nc_i32 v0, s0, s5 clamp
; GFX11-NEXT: v_add_nc_i32 v1, s1, s6 clamp
; GFX11-NEXT: v_add_nc_i32 v2, s2, s7 clamp
; GFX11-NEXT: v_add_nc_i32 v3, s3, s8 clamp
; GFX11-NEXT: v_add_nc_i32 v4, s4, s9 clamp
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) %result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result ret <5 x i32> %result
} }
define <16 x i32> @v_saddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) { define <16 x i32> @v_saddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v16i32: ; GFX6-LABEL: v_saddsat_v16i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_i32 v15, v15, v16 clamp ; GFX9-NEXT: v_add_i32 v15, v15, v16 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_saddsat_v16i32: ; GFX10-LABEL: v_saddsat_v16i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_add_nc_i32 v0, v0, v16 clamp ; GFX10-NEXT: v_add_nc_i32 v0, v0, v16 clamp
; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GFX10-NEXT: v_add_nc_i32 v1, v1, v17 clamp ; GFX10-NEXT: v_add_nc_i32 v1, v1, v17 clamp
; GFX10-NEXT: v_add_nc_i32 v2, v2, v18 clamp ; GFX10-NEXT: v_add_nc_i32 v2, v2, v18 clamp
; GFX10-NEXT: v_add_nc_i32 v3, v3, v19 clamp ; GFX10-NEXT: v_add_nc_i32 v3, v3, v19 clamp
; GFX10-NEXT: v_add_nc_i32 v4, v4, v20 clamp ; GFX10-NEXT: v_add_nc_i32 v4, v4, v20 clamp
; GFX10-NEXT: v_add_nc_i32 v5, v5, v21 clamp ; GFX10-NEXT: v_add_nc_i32 v5, v5, v21 clamp
; GFX10-NEXT: v_add_nc_i32 v6, v6, v22 clamp ; GFX10-NEXT: v_add_nc_i32 v6, v6, v22 clamp
; GFX10-NEXT: v_add_nc_i32 v7, v7, v23 clamp ; GFX10-NEXT: v_add_nc_i32 v7, v7, v23 clamp
; GFX10-NEXT: v_add_nc_i32 v8, v8, v24 clamp ; GFX10-NEXT: v_add_nc_i32 v8, v8, v24 clamp
; GFX10-NEXT: v_add_nc_i32 v9, v9, v25 clamp ; GFX10-NEXT: v_add_nc_i32 v9, v9, v25 clamp
; GFX10-NEXT: v_add_nc_i32 v10, v10, v26 clamp ; GFX10-NEXT: v_add_nc_i32 v10, v10, v26 clamp
; GFX10-NEXT: v_add_nc_i32 v11, v11, v27 clamp ; GFX10-NEXT: v_add_nc_i32 v11, v11, v27 clamp
; GFX10-NEXT: v_add_nc_i32 v12, v12, v28 clamp ; GFX10-NEXT: v_add_nc_i32 v12, v12, v28 clamp
; GFX10-NEXT: v_add_nc_i32 v13, v13, v29 clamp ; GFX10-NEXT: v_add_nc_i32 v13, v13, v29 clamp
; GFX10-NEXT: v_add_nc_i32 v14, v14, v30 clamp ; GFX10-NEXT: v_add_nc_i32 v14, v14, v30 clamp
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_nc_i32 v15, v15, v31 clamp ; GFX10-NEXT: v_add_nc_i32 v15, v15, v16 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_saddsat_v16i32: ; GFX11-LABEL: v_saddsat_v16i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_add_nc_i32 v0, v0, v16 clamp ; GFX11-NEXT: v_add_nc_i32 v0, v0, v16 clamp
; GFX11-NEXT: scratch_load_b32 v16, off, s32
; GFX11-NEXT: v_add_nc_i32 v1, v1, v17 clamp ; GFX11-NEXT: v_add_nc_i32 v1, v1, v17 clamp
; GFX11-NEXT: v_add_nc_i32 v2, v2, v18 clamp ; GFX11-NEXT: v_add_nc_i32 v2, v2, v18 clamp
; GFX11-NEXT: v_add_nc_i32 v3, v3, v19 clamp ; GFX11-NEXT: v_add_nc_i32 v3, v3, v19 clamp
; GFX11-NEXT: v_add_nc_i32 v4, v4, v20 clamp ; GFX11-NEXT: v_add_nc_i32 v4, v4, v20 clamp
; GFX11-NEXT: v_add_nc_i32 v5, v5, v21 clamp ; GFX11-NEXT: v_add_nc_i32 v5, v5, v21 clamp
; GFX11-NEXT: v_add_nc_i32 v6, v6, v22 clamp ; GFX11-NEXT: v_add_nc_i32 v6, v6, v22 clamp
; GFX11-NEXT: v_add_nc_i32 v7, v7, v23 clamp ; GFX11-NEXT: v_add_nc_i32 v7, v7, v23 clamp
; GFX11-NEXT: v_add_nc_i32 v8, v8, v24 clamp ; GFX11-NEXT: v_add_nc_i32 v8, v8, v24 clamp
; GFX11-NEXT: v_add_nc_i32 v9, v9, v25 clamp ; GFX11-NEXT: v_add_nc_i32 v9, v9, v25 clamp
; GFX11-NEXT: v_add_nc_i32 v10, v10, v26 clamp ; GFX11-NEXT: v_add_nc_i32 v10, v10, v26 clamp
; GFX11-NEXT: v_add_nc_i32 v11, v11, v27 clamp ; GFX11-NEXT: v_add_nc_i32 v11, v11, v27 clamp
; GFX11-NEXT: v_add_nc_i32 v12, v12, v28 clamp ; GFX11-NEXT: v_add_nc_i32 v12, v12, v28 clamp
; GFX11-NEXT: v_add_nc_i32 v13, v13, v29 clamp ; GFX11-NEXT: v_add_nc_i32 v13, v13, v29 clamp
; GFX11-NEXT: v_add_nc_i32 v14, v14, v30 clamp ; GFX11-NEXT: v_add_nc_i32 v14, v14, v30 clamp
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_add_nc_i32 v15, v15, v31 clamp ; GFX11-NEXT: v_add_nc_i32 v15, v15, v16 clamp
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define amdgpu_ps <16 x i32> @s_saddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) { define amdgpu_ps <16 x i32> @s_saddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v16i32: ; GFX6-LABEL: s_saddsat_v16i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
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; GFX9-NEXT: v_readfirstlane_b32 s10, v10 ; GFX9-NEXT: v_readfirstlane_b32 s10, v10
; GFX9-NEXT: v_readfirstlane_b32 s11, v11 ; GFX9-NEXT: v_readfirstlane_b32 s11, v11
; GFX9-NEXT: v_readfirstlane_b32 s12, v12 ; GFX9-NEXT: v_readfirstlane_b32 s12, v12
; GFX9-NEXT: v_readfirstlane_b32 s13, v13 ; GFX9-NEXT: v_readfirstlane_b32 s13, v13
; GFX9-NEXT: v_readfirstlane_b32 s14, v14 ; GFX9-NEXT: v_readfirstlane_b32 s14, v14
; GFX9-NEXT: v_readfirstlane_b32 s15, v15 ; GFX9-NEXT: v_readfirstlane_b32 s15, v15
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: s_saddsat_v16i32: ; GFX10-LABEL: s_saddsat_v16i32:
; GFX10PLUS: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10PLUS-NEXT: v_add_nc_i32 v0, s0, s16 clamp ; GFX10-NEXT: v_add_nc_i32 v0, s0, s16 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v1, s1, s17 clamp ; GFX10-NEXT: v_add_nc_i32 v1, s1, s17 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v2, s2, s18 clamp ; GFX10-NEXT: v_add_nc_i32 v2, s2, s18 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v3, s3, s19 clamp ; GFX10-NEXT: v_add_nc_i32 v3, s3, s19 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v4, s4, s20 clamp ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10PLUS-NEXT: v_add_nc_i32 v5, s5, s21 clamp ; GFX10-NEXT: v_add_nc_i32 v0, s4, s20 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v6, s6, s22 clamp ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10PLUS-NEXT: v_add_nc_i32 v7, s7, s23 clamp ; GFX10-NEXT: v_add_nc_i32 v1, s5, s21 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v8, s8, s24 clamp ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10PLUS-NEXT: v_add_nc_i32 v9, s9, s25 clamp ; GFX10-NEXT: v_add_nc_i32 v2, s6, s22 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v10, s10, s26 clamp ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10PLUS-NEXT: v_add_nc_i32 v11, s11, s27 clamp ; GFX10-NEXT: v_add_nc_i32 v3, s7, s23 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v12, s12, s28 clamp ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10PLUS-NEXT: v_add_nc_i32 v13, s13, s29 clamp ; GFX10-NEXT: v_add_nc_i32 v0, s8, s24 clamp
; GFX10PLUS-NEXT: v_add_nc_i32 v14, s14, s30 clamp ; GFX10-NEXT: v_readfirstlane_b32 s5, v1
; GFX10PLUS-NEXT: v_add_nc_i32 v15, s15, s31 clamp ; GFX10-NEXT: v_add_nc_i32 v1, s9, s25 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s6, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_add_nc_i32 v2, s10, s26 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s7, v3
; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_add_nc_i32 v3, s11, s27 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s8, v0
; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5 ; GFX10-NEXT: v_add_nc_i32 v0, s12, s28 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6 ; GFX10-NEXT: v_readfirstlane_b32 s9, v1
; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7 ; GFX10-NEXT: v_add_nc_i32 v1, s13, s29 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v8 ; GFX10-NEXT: v_readfirstlane_b32 s10, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v9 ; GFX10-NEXT: v_add_nc_i32 v2, s14, s30 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s10, v10 ; GFX10-NEXT: v_readfirstlane_b32 s11, v3
; GFX10PLUS-NEXT: v_readfirstlane_b32 s11, v11 ; GFX10-NEXT: v_add_nc_i32 v3, s15, s31 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v12 ; GFX10-NEXT: v_readfirstlane_b32 s12, v0
; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v13 ; GFX10-NEXT: v_readfirstlane_b32 s13, v1
; GFX10PLUS-NEXT: v_readfirstlane_b32 s14, v14 ; GFX10-NEXT: v_readfirstlane_b32 s14, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s15, v15 ; GFX10-NEXT: v_readfirstlane_b32 s15, v3
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_saddsat_v16i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_add_nc_i32 v0, s0, s16 clamp
; GFX11-NEXT: v_add_nc_i32 v1, s1, s17 clamp
; GFX11-NEXT: v_add_nc_i32 v2, s2, s18 clamp
; GFX11-NEXT: v_add_nc_i32 v3, s3, s19 clamp
; GFX11-NEXT: v_add_nc_i32 v4, s4, s20 clamp
; GFX11-NEXT: v_add_nc_i32 v5, s5, s21 clamp
; GFX11-NEXT: v_add_nc_i32 v6, s6, s22 clamp
; GFX11-NEXT: v_add_nc_i32 v7, s7, s23 clamp
; GFX11-NEXT: v_add_nc_i32 v8, s8, s24 clamp
; GFX11-NEXT: v_add_nc_i32 v9, s9, s25 clamp
; GFX11-NEXT: v_add_nc_i32 v10, s10, s26 clamp
; GFX11-NEXT: v_add_nc_i32 v11, s11, s27 clamp
; GFX11-NEXT: v_add_nc_i32 v12, s12, s28 clamp
; GFX11-NEXT: v_add_nc_i32 v13, s13, s29 clamp
; GFX11-NEXT: v_add_nc_i32 v14, s14, s30 clamp
; GFX11-NEXT: v_add_nc_i32 v15, s15, s31 clamp
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_readfirstlane_b32 s6, v6
; GFX11-NEXT: v_readfirstlane_b32 s7, v7
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9
; GFX11-NEXT: v_readfirstlane_b32 s10, v10
; GFX11-NEXT: v_readfirstlane_b32 s11, v11
; GFX11-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-NEXT: v_readfirstlane_b32 s13, v13
; GFX11-NEXT: v_readfirstlane_b32 s14, v14
; GFX11-NEXT: v_readfirstlane_b32 s15, v15
; GFX11-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) { define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) {
; GFX6-LABEL: v_saddsat_i16: ; GFX6-LABEL: v_saddsat_i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3]
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3] ; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[4:5], v[0:1] ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[4:5], v[0:1]
; GFX10-NEXT: v_add_co_u32 v1, s5, 0x80000000, v6 ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX10-NEXT: v_add_co_u32 v1, s5, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s4 ; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_saddsat_i48: ; GFX11-LABEL: v_saddsat_i48:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: saddsat_i48_sv: ; GFX10-LABEL: saddsat_i48_sv:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, s0, v0 ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, s0, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[0:1]
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3] ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX10-NEXT: v_cmp_gt_i64_e64 s0, 0, v[0:1] ; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], v[2:3]
; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v4 ; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: saddsat_i48_sv: ; GFX11-LABEL: saddsat_i48_sv:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
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; ;
; GFX10-LABEL: saddsat_i48_vs: ; GFX10-LABEL: saddsat_i48_vs:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, s0 ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, s0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[0:1], 0 ; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[0:1], 0
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1] ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v4 ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: saddsat_i48_vs: ; GFX11-LABEL: saddsat_i48_vs:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
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; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_saddsat_i64: ; GFX10-LABEL: v_saddsat_i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[2:3] ; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[4:5], v[0:1]
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1] ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX10-NEXT: v_add_co_u32 v1, s5, 0x80000000, v6 ; GFX10-NEXT: v_add_co_u32 v1, s5, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_saddsat_i64: ; GFX11-LABEL: v_saddsat_i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2 ; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
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; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: saddsat_i64_sv: ; GFX10-LABEL: saddsat_i64_sv:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, s0, v0 ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, s0, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[0:1]
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3] ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX10-NEXT: v_cmp_gt_i64_e64 s0, 0, v[0:1] ; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], v[2:3]
; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v4 ; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: saddsat_i64_sv: ; GFX11-LABEL: saddsat_i64_sv:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, s0, v0 ; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, s0, v0
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v3
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; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: saddsat_i64_vs: ; GFX10-LABEL: saddsat_i64_vs:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, s0 ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, s0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[0:1], 0 ; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[0:1], 0
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1] ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v4 ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: saddsat_i64_vs: ; GFX11-LABEL: saddsat_i64_vs:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v0, s0 ; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v0, s0
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[0:1], 0 ; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[0:1], 0
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; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_saddsat_v2i64: ; GFX10-LABEL: v_saddsat_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v0, v4 ; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v0, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32 v10, vcc_lo, v2, v6
; GFX10-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v3, v7, vcc_lo
; GFX10-NEXT: v_ashrrev_i32_e32 v12, 31, v9
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]
; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[4:5] ; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[4:5]
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v11 ; GFX10-NEXT: v_add_co_u32 v4, s5, v2, v6
; GFX10-NEXT: v_add_co_ci_u32_e64 v5, s5, v3, v7, s5
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]
; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v9
; GFX10-NEXT: v_cmp_gt_i64_e64 s6, 0, v[6:7] ; GFX10-NEXT: v_cmp_gt_i64_e64 s6, 0, v[6:7]
; GFX10-NEXT: v_add_co_u32 v1, s5, 0x80000000, v12 ; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[4:5], v[2:3]
; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[10:11], v[2:3] ; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX10-NEXT: v_add_co_u32 v3, s7, 0x80000000, v4
; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v12, vcc_lo ; GFX10-NEXT: v_add_co_u32 v1, s4, 0x80000000, v0
; GFX10-NEXT: v_add_co_u32 v3, s4, 0x80000000, v2
; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
; GFX10-NEXT: s_xor_b32 vcc_lo, s6, s5 ; GFX10-NEXT: s_xor_b32 vcc_lo, s6, s5
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_saddsat_v2i64: ; GFX11-LABEL: v_saddsat_v2i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v0, v4 ; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v0, v4
; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo
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; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: saddsat_i128_sv: ; GFX10-LABEL: saddsat_i128_sv:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3] ; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_gt_u64_e64 s0, s[0:1], v[0:1]
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[4:5] ; GFX10-NEXT: v_cmp_gt_i64_e64 s4, s[2:3], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX10-NEXT: v_cmp_eq_u64_e64 s0, s[2:3], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v6, 0, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v2, v3, v2
; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v5 ; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v2, v2, v6
; GFX10-NEXT: v_add_co_u32 v6, s0, 0x80000000, v3
; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 ; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
; GFX10-NEXT: v_add_co_u32 v6, s0, 0x80000000, v3
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: saddsat_i128_sv: ; GFX11-LABEL: saddsat_i128_sv:
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; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: saddsat_i128_vs: ; GFX10-LABEL: saddsat_i128_vs:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, s0 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, s0
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1] ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, v[4:5], v[0:1]
; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0 ; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0
; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[2:3], 0 ; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[2:3], 0
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX10-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: s_and_b32 s0, 1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3] ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v7 ; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, 0, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0
; GFX10-NEXT: v_add_co_u32 v3, s0, 0x80000000, v2 ; GFX10-NEXT: v_add_co_u32 v3, s0, 0x80000000, v2
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
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; GFX10-LABEL: v_saddsat_v2i128: ; GFX10-LABEL: v_saddsat_v2i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v0, v8 ; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v0, v8
; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v9, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v9, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v16, vcc_lo, v2, v10, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v16, vcc_lo, v2, v10, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v17, vcc_lo, v3, v11, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v17, vcc_lo, v3, v11, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[0:1]
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[16:17], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[10:11] ; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[8:9], v[0:1]
; GFX10-NEXT: v_add_co_u32 v12, vcc_lo, v4, v12 ; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[16:17], v[2:3]
; GFX10-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, v5, v13, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v18, vcc_lo, v6, v14, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v19, vcc_lo, v7, v15, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[12:13], v[4:5] ; GFX10-NEXT: v_cmp_eq_u64_e64 s4, v[16:17], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s5
; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v17
; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v18, 0, vcc_lo
; GFX10-NEXT: v_add_co_u32 v3, s4, 0x80000000, v2
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[6:7]
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc_lo
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v4, v12
; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, v6, v14, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v7, v15, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[14:15] ; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[14:15]
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[8:9], v[4:5]
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[6:7] ; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[10:11], v[6:7]
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v19 ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15] ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v17 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
; GFX10-NEXT: v_add_co_u32 v7, s5, 0x80000000, v6 ; GFX10-NEXT: v_cmp_eq_u64_e64 s4, v[10:11], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s5
; GFX10-NEXT: v_add_co_u32 v4, s4, 0x80000000, v3 ; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v11
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, v4, s4
; GFX10-NEXT: v_xor_b32_e32 v1, v2, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v12, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v3, vcc_lo ; GFX10-NEXT: v_add_co_u32 v7, s4, 0x80000000, v6
; GFX10-NEXT: v_cndmask_b32_e32 v2, v16, v3, vcc_lo ; GFX10-NEXT: v_xor_b32_e32 v4, v5, v4
; GFX10-NEXT: v_and_b32_e32 v5, 1, v1 ; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX10-NEXT: v_cndmask_b32_e32 v3, v17, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, v5 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v12, v6, s4 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v13, v6, s4 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v18, v6, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v19, v7, s4
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_saddsat_v2i128: ; GFX11-LABEL: v_saddsat_v2i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v0, v8 ; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v0, v8
; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v9, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v9, vcc_lo
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; ;
; GFX10-LABEL: s_saddsat_v2i128: ; GFX10-LABEL: s_saddsat_v2i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_add_u32 s8, s0, s8 ; GFX10-NEXT: s_add_u32 s8, s0, s8
; GFX10-NEXT: s_addc_u32 s9, s1, s9 ; GFX10-NEXT: s_addc_u32 s9, s1, s9
; GFX10-NEXT: s_addc_u32 s16, s2, s10 ; GFX10-NEXT: s_addc_u32 s16, s2, s10
; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1] ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
; GFX10-NEXT: s_addc_u32 s17, s3, s11 ; GFX10-NEXT: s_addc_u32 s17, s3, s11
; GFX10-NEXT: v_mov_b32_e32 v3, s8
; GFX10-NEXT: s_cmp_eq_u64 s[16:17], s[2:3] ; GFX10-NEXT: s_cmp_eq_u64 s[16:17], s[2:3]
; GFX10-NEXT: s_cselect_b32 s18, 1, 0 ; GFX10-NEXT: s_cselect_b32 s18, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[16:17], s[2:3] ; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[16:17], s[2:3]
; GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[10:11], 0 ; GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[10:11], 0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: s_and_b32 s0, 1, s18 ; GFX10-NEXT: s_and_b32 s0, 1, s18
; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0 ; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
; GFX10-NEXT: s_cselect_b32 s1, 1, 0 ; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: s_ashr_i32 s2, s17, 31
; GFX10-NEXT: s_and_b32 s1, 1, s1 ; GFX10-NEXT: s_and_b32 s1, 1, s1
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX10-NEXT: s_add_u32 s1, s2, 0x80000000
; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, 0, s0
; GFX10-NEXT: s_ashr_i32 s0, s17, 31
; GFX10-NEXT: v_mov_b32_e32 v2, s9
; GFX10-NEXT: s_add_u32 s1, s0, 0x80000000
; GFX10-NEXT: s_add_u32 s10, s4, s12 ; GFX10-NEXT: s_add_u32 s10, s4, s12
; GFX10-NEXT: s_addc_u32 s11, s5, s13 ; GFX10-NEXT: s_addc_u32 s11, s5, s13
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e64 s3, s[10:11], s[4:5]
; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, 0, s0
; GFX10-NEXT: s_addc_u32 s12, s6, s14 ; GFX10-NEXT: s_addc_u32 s12, s6, s14
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[10:11], s[4:5]
; GFX10-NEXT: s_addc_u32 s13, s7, s15 ; GFX10-NEXT: s_addc_u32 s13, s7, s15
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: s_cmp_eq_u64 s[12:13], s[6:7] ; GFX10-NEXT: s_cmp_eq_u64 s[12:13], s[6:7]
; GFX10-NEXT: v_mov_b32_e32 v1, s8 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: s_cselect_b32 s8, 1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s3
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4 ; GFX10-NEXT: v_cmp_lt_i64_e64 s3, s[12:13], s[6:7]
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[12:13], s[6:7] ; GFX10-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-NEXT: v_cmp_lt_i64_e64 s6, s[14:15], 0 ; GFX10-NEXT: s_and_b32 s0, 1, s0
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: s_mov_b32 s3, s0
; GFX10-NEXT: s_mov_b32 s2, s0
; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
; GFX10-NEXT: s_and_b32 s4, 1, s8
; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0 ; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: s_cselect_b32 s5, 1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s3
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 ; GFX10-NEXT: v_cmp_lt_i64_e64 s3, s[14:15], 0
; GFX10-NEXT: s_and_b32 s5, 1, s5 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: v_mov_b32_e32 v7, s13 ; GFX10-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s5 ; GFX10-NEXT: s_ashr_i32 s4, s13, 31
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo ; GFX10-NEXT: s_and_b32 s0, 1, s0
; GFX10-NEXT: s_add_u32 s5, s4, 0x80000000
; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s3
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s16 ; GFX10-NEXT: s_mov_b32 s3, s2
; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, 0, s4 ; GFX10-NEXT: s_mov_b32 s7, s4
; GFX10-NEXT: v_mov_b32_e32 v5, s17 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, s2, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v3, v4, v3 ; GFX10-NEXT: v_mov_b32_e32 v3, s9
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX10-NEXT: v_xor_b32_e32 v1, v2, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s1, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v2, s16
; GFX10-NEXT: v_mov_b32_e32 v5, s10 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: s_ashr_i32 s0, s13, 31 ; GFX10-NEXT: v_mov_b32_e32 v0, s17
; GFX10-NEXT: v_and_b32_e32 v3, 1, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
; GFX10-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
; GFX10-NEXT: s_mov_b32 s3, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
; GFX10-NEXT: s_mov_b32 s2, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s1, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_readfirstlane_b32 s1, v3
; GFX10-NEXT: v_mov_b32_e32 v3, s12 ; GFX10-NEXT: v_mov_b32_e32 v3, s10
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s0, vcc_lo ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s3, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v2, s11
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s1, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v1, s12
; GFX10-NEXT: v_readfirstlane_b32 s0, v1 ; GFX10-NEXT: v_readfirstlane_b32 s3, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v2 ; GFX10-NEXT: v_mov_b32_e32 v0, s13
; GFX10-NEXT: v_readfirstlane_b32 s2, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s4, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s3, v4 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s4, v5 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s5, v6 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s5, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s6, v3 ; GFX10-NEXT: v_readfirstlane_b32 s4, v3
; GFX10-NEXT: v_readfirstlane_b32 s7, v7 ; GFX10-NEXT: v_readfirstlane_b32 s5, v2
; GFX10-NEXT: v_readfirstlane_b32 s6, v1
; GFX10-NEXT: v_readfirstlane_b32 s7, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_saddsat_v2i128: ; GFX11-LABEL: s_saddsat_v2i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_add_u32 s8, s0, s8 ; GFX11-NEXT: s_add_u32 s8, s0, s8
; GFX11-NEXT: s_addc_u32 s9, s1, s9 ; GFX11-NEXT: s_addc_u32 s9, s1, s9
; GFX11-NEXT: s_addc_u32 s16, s2, s10 ; GFX11-NEXT: s_addc_u32 s16, s2, s10
; GFX11-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1] ; GFX11-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
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llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll

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; GFX10-NEXT: s_ashr_i32 s12, s11, 31 ; GFX10-NEXT: s_ashr_i32 s12, s11, 31
; GFX10-NEXT: s_add_u32 s0, s8, s2 ; GFX10-NEXT: s_add_u32 s0, s8, s2
; GFX10-NEXT: s_addc_u32 s1, s9, s2 ; GFX10-NEXT: s_addc_u32 s1, s9, s2
; GFX10-NEXT: s_add_u32 s8, s10, s12 ; GFX10-NEXT: s_add_u32 s8, s10, s12
; GFX10-NEXT: s_mov_b32 s13, s12 ; GFX10-NEXT: s_mov_b32 s13, s12
; GFX10-NEXT: s_addc_u32 s9, s11, s12 ; GFX10-NEXT: s_addc_u32 s9, s11, s12
; GFX10-NEXT: s_mov_b32 s3, s2 ; GFX10-NEXT: s_mov_b32 s3, s2
; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13] ; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3] ; GFX10-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3]
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX10-NEXT: s_sub_u32 s10, 0, s8 ; GFX10-NEXT: s_sub_u32 s0, 0, s8
; GFX10-NEXT: s_subb_u32 s11, 0, s9 ; GFX10-NEXT: s_subb_u32 s1, 0, s9
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX10-NEXT: v_trunc_f32_e32 v1, v1 ; GFX10-NEXT: v_trunc_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX10-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX10-NEXT: v_add_f32_e32 v0, v2, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v0
; GFX10-NEXT: v_mul_lo_u32 v4, s10, v2 ; GFX10-NEXT: v_mul_lo_u32 v4, s0, v2
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s14, s10, v3, 0 ; GFX10-NEXT: v_mul_lo_u32 v5, s1, v3
; GFX10-NEXT: v_mul_lo_u32 v5, s11, v3 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s14, s0, v3, 0
; GFX10-NEXT: v_mul_hi_u32 v6, v2, v0
; GFX10-NEXT: v_add3_u32 v1, v1, v4, v5 ; GFX10-NEXT: v_add3_u32 v1, v1, v4, v5
; GFX10-NEXT: v_mul_lo_u32 v4, v2, v0 ; GFX10-NEXT: v_mul_lo_u32 v4, v2, v0
; GFX10-NEXT: v_mul_hi_u32 v0, v3, v0
; GFX10-NEXT: v_mul_lo_u32 v5, v3, v1 ; GFX10-NEXT: v_mul_lo_u32 v5, v3, v1
; GFX10-NEXT: v_mul_lo_u32 v7, v2, v1
; GFX10-NEXT: v_mul_hi_u32 v8, v3, v1
; GFX10-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX10-NEXT: v_add_co_u32 v4, s14, v4, v5 ; GFX10-NEXT: v_add_co_u32 v4, s14, v4, v5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s14 ; GFX10-NEXT: v_mul_hi_u32 v5, v3, v0
; GFX10-NEXT: v_add_co_u32 v6, s14, v7, v6
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s14
; GFX10-NEXT: v_add_co_u32 v0, s14, v4, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s14
; GFX10-NEXT: v_add_co_u32 v4, s14, v6, v8
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s14 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s14
; GFX10-NEXT: v_add_nc_u32_e32 v0, v5, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, v2, v0
; GFX10-NEXT: v_add_nc_u32_e32 v5, v7, v6 ; GFX10-NEXT: v_add_co_u32 v4, s14, v4, v5
; GFX10-NEXT: v_add_co_u32 v0, s14, v4, v0 ; GFX10-NEXT: v_mul_lo_u32 v5, v2, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s14
; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v4
; GFX10-NEXT: v_add_co_u32 v0, s14, v5, v0
; GFX10-NEXT: v_mul_hi_u32 v5, v3, v1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s14
; GFX10-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX10-NEXT: v_add_co_u32 v0, s14, v0, v5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s14
; GFX10-NEXT: v_add_co_u32 v0, s14, v0, v4
; GFX10-NEXT: v_add_nc_u32_e32 v5, v6, v5
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s14 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s14
; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v3, v0 ; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v3, v0
; GFX10-NEXT: v_add3_u32 v1, v5, v4, v1 ; GFX10-NEXT: v_add3_u32 v1, v5, v4, v1
; GFX10-NEXT: v_mul_lo_u32 v4, s11, v3 ; GFX10-NEXT: v_mul_lo_u32 v4, s1, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v1, vcc_lo
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s14, s10, v3, 0 ; GFX10-NEXT: v_mul_lo_u32 v5, s0, v2
; GFX10-NEXT: v_mul_lo_u32 v5, s10, v2 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s0, v3, 0
; GFX10-NEXT: v_mul_hi_u32 v6, v2, v0
; GFX10-NEXT: v_add3_u32 v1, v1, v5, v4 ; GFX10-NEXT: v_add3_u32 v1, v1, v5, v4
; GFX10-NEXT: v_mul_lo_u32 v4, v2, v0 ; GFX10-NEXT: v_mul_lo_u32 v4, v2, v0
; GFX10-NEXT: v_mul_hi_u32 v0, v3, v0
; GFX10-NEXT: v_mul_lo_u32 v5, v3, v1 ; GFX10-NEXT: v_mul_lo_u32 v5, v3, v1
; GFX10-NEXT: v_mul_lo_u32 v7, v2, v1 ; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_mul_hi_u32 v8, v3, v1 ; GFX10-NEXT: v_mul_hi_u32 v5, v3, v0
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v0, v2, v0
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_mul_lo_u32 v5, v2, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v4
; GFX10-NEXT: v_add_co_u32 v0, s0, v5, v0
; GFX10-NEXT: v_mul_hi_u32 v5, v3, v1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v1, v2, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX10-NEXT: v_add_co_u32 v4, s10, v4, v5 ; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s10 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v6, s10, v7, v6 ; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v4
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s10 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v6, v5
; GFX10-NEXT: v_add_co_u32 v0, s10, v4, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s10
; GFX10-NEXT: v_add_co_u32 v4, s10, v6, v8
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s10
; GFX10-NEXT: v_add_nc_u32_e32 v0, v5, v0
; GFX10-NEXT: v_add_nc_u32_e32 v5, v7, v6
; GFX10-NEXT: v_add_co_u32 v0, s10, v4, v0
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s10
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v3, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v3, v0
; GFX10-NEXT: v_add3_u32 v1, v5, v4, v1 ; GFX10-NEXT: v_add3_u32 v1, v5, v4, v1
; GFX10-NEXT: v_mul_hi_u32 v4, s1, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v2, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v2, v1, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v2, s1, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s11, v0
; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX10-NEXT: v_mul_lo_u32 v3, s10, v1
; GFX10-NEXT: v_mul_lo_u32 v3, s0, v1 ; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v3
; GFX10-NEXT: v_mul_lo_u32 v5, s1, v1 ; GFX10-NEXT: v_mul_hi_u32 v3, s10, v0
; GFX10-NEXT: v_mul_hi_u32 v6, s0, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX10-NEXT: v_mul_hi_u32 v0, s11, v0
; GFX10-NEXT: v_add_co_u32 v2, s10, v2, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v3
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s10 ; GFX10-NEXT: v_mul_lo_u32 v3, s11, v1
; GFX10-NEXT: v_add_co_u32 v4, s10, v5, v4 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s10 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v4, v2
; GFX10-NEXT: v_add_co_u32 v0, s10, v2, v0 ; GFX10-NEXT: v_add_co_u32 v0, s0, v3, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s10 ; GFX10-NEXT: v_mul_hi_u32 v3, s10, v1
; GFX10-NEXT: v_add_co_u32 v2, s10, v4, v6 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s10 ; GFX10-NEXT: v_mul_hi_u32 v1, s11, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v3, v0 ; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v3
; GFX10-NEXT: v_add_nc_u32_e32 v3, v5, v4 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v2, s10, v2, v0 ; GFX10-NEXT: v_add_co_u32 v2, s0, v0, v2
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s10 ; GFX10-NEXT: v_add_nc_u32_e32 v3, v4, v3
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX10-NEXT: v_mul_lo_u32 v4, s9, v2 ; GFX10-NEXT: v_mul_lo_u32 v4, s9, v2
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v2, 1
; GFX10-NEXT: v_add3_u32 v3, v3, v0, v1 ; GFX10-NEXT: v_add3_u32 v3, v3, v0, v1
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s10, s8, v2, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s8, v2, 0
; GFX10-NEXT: v_mul_lo_u32 v5, s8, v3 ; GFX10-NEXT: v_mul_lo_u32 v5, s8, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: v_add3_u32 v1, v1, v5, v4 ; GFX10-NEXT: v_add3_u32 v1, v1, v5, v4
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v6, 1 ; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, s10, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v7, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e64 v5, s0, s11, v1, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v8, s1, v1 ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s8, v4
; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, s0, v0 ; GFX10-NEXT: v_sub_nc_u32_e32 v1, s11, v1
; GFX10-NEXT: v_sub_co_ci_u32_e64 v1, s0, s1, v1, vcc_lo ; GFX10-NEXT: s_xor_b64 s[10:11], s[2:3], s[12:13]
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v5
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s8, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, -1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, -1, s0
; GFX10-NEXT: v_sub_co_u32 v10, vcc_lo, v0, s8 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v5
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v11, s0, 0, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, v0, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v1 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s9, v1, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo ; GFX10-NEXT: v_sub_co_u32 v7, vcc_lo, v4, s8
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s9, v11 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v8, s0, 0, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, s0 ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s8, v7
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v10 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v8
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, -1, s1
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v11 ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, -1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, -1, s0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v8
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v9, v12, v9, s0 ; GFX10-NEXT: v_add_co_u32 v1, s0, v2, 1
; GFX10-NEXT: v_cndmask_b32_e32 v12, v14, v13, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e64 v10, s0, 0, v3, s0
; GFX10-NEXT: v_sub_co_u32 v13, vcc_lo, v10, s8 ; GFX10-NEXT: v_add_co_u32 v11, s0, v1, 1
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e64 v12, s0, 0, v10, s0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v9
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v12 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v11, s0
; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v12, s0
; GFX10-NEXT: s_xor_b64 s[8:9], s[2:3], s[12:13] ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0
; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v13, s0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v8, s0 ; GFX10-NEXT: v_xor_b32_e32 v0, s10, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v4, s1 ; GFX10-NEXT: v_xor_b32_e32 v1, s11, v1
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1 ; GFX10-NEXT: v_sub_co_u32 v0, s1, v0, s10
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s1 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v1, s1, s11, v1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v7, s1 ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, s9, v6, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v2, s8, v2 ; GFX10-NEXT: v_sub_co_u32 v1, vcc_lo, v7, s8
; GFX10-NEXT: v_xor_b32_e32 v3, s9, v3 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v5, s2, v0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
; GFX10-NEXT: v_xor_b32_e32 v6, s2, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, v2, s8 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v4, v1, s0
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v5, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v0, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s2, v6, vcc_lo ; GFX10-NEXT: v_xor_b32_e32 v1, s2, v1
; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5] ; GFX10-NEXT: v_xor_b32_e32 v3, s2, v0
; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[6:7] ; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, v1, s2
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, s2, v3, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = sdiv i64 %x, %y %div = sdiv i64 %x, %y
store i64 %div, ptr addrspace(1) %out0 store i64 %div, ptr addrspace(1) %out0
%rem = srem i64 %x, %y %rem = srem i64 %x, %y
store i64 %rem, ptr addrspace(1) %out1 store i64 %rem, ptr addrspace(1) %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
; GFX9-NEXT: global_store_dwordx2 v4, v[2:3], s[2:3] ; GFX9-NEXT: global_store_dwordx2 v4, v[2:3], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdivrem_v2i32: ; GFX10-LABEL: sdivrem_v2i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_ashr_i32 s1, s10, 31 ; GFX10-NEXT: s_ashr_i32 s1, s10, 31
; GFX10-NEXT: s_ashr_i32 s2, s11, 31 ; GFX10-NEXT: s_ashr_i32 s3, s11, 31
; GFX10-NEXT: s_add_i32 s0, s10, s1 ; GFX10-NEXT: s_add_i32 s0, s10, s1
; GFX10-NEXT: s_add_i32 s3, s11, s2 ; GFX10-NEXT: s_xor_b32 s2, s0, s1
; GFX10-NEXT: s_xor_b32 s10, s0, s1 ; GFX10-NEXT: s_add_i32 s0, s11, s3
; GFX10-NEXT: s_xor_b32 s3, s3, s2 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s10 ; GFX10-NEXT: s_xor_b32 s10, s0, s3
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s3 ; GFX10-NEXT: s_sub_i32 s0, 0, s2
; GFX10-NEXT: s_sub_i32 s0, 0, s10 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s10
; GFX10-NEXT: s_sub_i32 s11, 0, s3 ; GFX10-NEXT: s_ashr_i32 s11, s8, 31
; GFX10-NEXT: s_ashr_i32 s12, s9, 31
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_xor_b32 s1, s11, s1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_mul_lo_u32 v2, s0, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s0, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s11, v1 ; GFX10-NEXT: s_sub_i32 s0, 0, s10
; GFX10-NEXT: s_ashr_i32 s11, s8, 31 ; GFX10-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX10-NEXT: s_add_i32 s0, s8, s11 ; GFX10-NEXT: s_add_i32 s0, s8, s11
; GFX10-NEXT: s_add_i32 s8, s9, s12 ; GFX10-NEXT: s_ashr_i32 s8, s9, 31
; GFX10-NEXT: s_xor_b32 s0, s0, s11 ; GFX10-NEXT: s_xor_b32 s0, s0, s11
; GFX10-NEXT: s_xor_b32 s8, s8, s12 ; GFX10-NEXT: s_add_i32 s9, s9, s8
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX10-NEXT: s_xor_b32 s9, s9, s8
; GFX10-NEXT: s_xor_b32 s1, s11, s1 ; GFX10-NEXT: s_xor_b32 s3, s8, s3
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: v_mul_hi_u32 v2, v1, v3
; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX10-NEXT: v_mul_hi_u32 v1, s8, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_lo_u32 v2, v0, s10 ; GFX10-NEXT: v_mul_lo_u32 v3, v0, s2
; GFX10-NEXT: v_mul_lo_u32 v3, v1, s3 ; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, s0, v3
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v0
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s0, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s8, v3 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s10, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v3 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, s10
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v2 ; GFX10-NEXT: v_sub_nc_u32_e32 v3, s9, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s3, v3 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v3
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s2, v2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s10, v3
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s0
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v2 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s10, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s3, v3
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT: s_xor_b32 s0, s12, s2
; GFX10-NEXT: v_xor_b32_e32 v0, s1, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, s1, v0
; GFX10-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: v_xor_b32_e32 v2, s11, v2
; GFX10-NEXT: v_xor_b32_e32 v3, s12, v3
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s1, v0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s1, v0
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s0, v1 ; GFX10-NEXT: v_xor_b32_e32 v1, s3, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s11, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s3, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s12, v3
; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5] ; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5]
; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[6:7] ; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s2, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s10, v3
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, v1, s0
; GFX10-NEXT: v_xor_b32_e32 v0, s11, v0
; GFX10-NEXT: v_xor_b32_e32 v1, s8, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s11, v0
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s8, v1
; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = sdiv <2 x i32> %x, %y %div = sdiv <2 x i32> %x, %y
store <2 x i32> %div, ptr addrspace(1) %out0 store <2 x i32> %div, ptr addrspace(1) %out0
%rem = srem <2 x i32> %x, %y %rem = srem <2 x i32> %x, %y
store <2 x i32> %rem, ptr addrspace(1) %out1 store <2 x i32> %rem, ptr addrspace(1) %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 277 Lines • ▼ Show 20 Lines
; GFX9-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] ; GFX9-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
; GFX9-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3] ; GFX9-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdivrem_v4i32: ; GFX10-LABEL: sdivrem_v4i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_ashr_i32 s0, s12, 31 ; GFX10-NEXT: s_ashr_i32 s3, s12, 31
; GFX10-NEXT: s_ashr_i32 s1, s13, 31 ; GFX10-NEXT: s_ashr_i32 s6, s13, 31
; GFX10-NEXT: s_ashr_i32 s2, s14, 31 ; GFX10-NEXT: s_add_i32 s0, s12, s3
; GFX10-NEXT: s_ashr_i32 s3, s15, 31 ; GFX10-NEXT: s_ashr_i32 s7, s14, 31
; GFX10-NEXT: s_add_i32 s6, s12, s0 ; GFX10-NEXT: s_xor_b32 s12, s0, s3
; GFX10-NEXT: s_add_i32 s7, s13, s1 ; GFX10-NEXT: s_add_i32 s0, s13, s6
; GFX10-NEXT: s_add_i32 s12, s14, s2 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX10-NEXT: s_add_i32 s13, s15, s3 ; GFX10-NEXT: s_xor_b32 s13, s0, s6
; GFX10-NEXT: s_xor_b32 s14, s6, s0 ; GFX10-NEXT: s_sub_i32 s0, 0, s12
; GFX10-NEXT: s_xor_b32 s15, s7, s1 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX10-NEXT: s_xor_b32 s12, s12, s2 ; GFX10-NEXT: s_ashr_i32 s16, s15, 31
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s14
; GFX10-NEXT: s_xor_b32 s13, s13, s3
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s15
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s12
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s13
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_sub_i32 s6, 0, s14 ; GFX10-NEXT: s_ashr_i32 s17, s8, 31
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX10-NEXT: s_xor_b32 s3, s17, s3
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX10-NEXT: s_sub_i32 s7, 0, s15
; GFX10-NEXT: s_sub_i32 s19, 0, s12
; GFX10-NEXT: s_ashr_i32 s16, s8, 31
; GFX10-NEXT: s_ashr_i32 s17, s9, 31
; GFX10-NEXT: s_ashr_i32 s18, s10, 31
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: s_xor_b32 s20, s16, s0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: s_xor_b32 s21, s17, s1
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX10-NEXT: v_mul_lo_u32 v2, s0, v0
; GFX10-NEXT: s_add_i32 s0, s14, s7
; GFX10-NEXT: s_xor_b32 s14, s0, s7
; GFX10-NEXT: s_sub_i32 s0, 0, s13
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s14
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX10-NEXT: s_sub_i32 s0, 0, s14
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: v_mul_lo_u32 v4, s6, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: s_sub_i32 s6, 0, s13 ; GFX10-NEXT: v_mul_lo_u32 v2, s0, v3
; GFX10-NEXT: v_mul_lo_u32 v5, s7, v1 ; GFX10-NEXT: s_add_i32 s0, s15, s16
; GFX10-NEXT: v_mul_lo_u32 v6, s19, v2 ; GFX10-NEXT: s_xor_b32 s15, s0, s16
; GFX10-NEXT: v_mul_lo_u32 v7, s6, v3 ; GFX10-NEXT: s_sub_i32 s0, 0, s15
; GFX10-NEXT: s_ashr_i32 s19, s11, 31 ; GFX10-NEXT: v_mul_hi_u32 v2, v3, v2
; GFX10-NEXT: s_add_i32 s6, s8, s16 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v3, v2
; GFX10-NEXT: s_add_i32 s7, s9, s17 ; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s15
; GFX10-NEXT: v_mul_hi_u32 v4, v0, v4 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX10-NEXT: s_add_i32 s8, s10, s18 ; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: v_mul_hi_u32 v6, v2, v6 ; GFX10-NEXT: v_mul_lo_u32 v4, s0, v3
; GFX10-NEXT: v_mul_hi_u32 v7, v3, v7 ; GFX10-NEXT: s_add_i32 s0, s8, s17
; GFX10-NEXT: s_add_i32 s9, s11, s19 ; GFX10-NEXT: s_ashr_i32 s8, s9, 31
; GFX10-NEXT: s_xor_b32 s10, s6, s16 ; GFX10-NEXT: s_xor_b32 s0, s0, s17
; GFX10-NEXT: s_xor_b32 s11, s7, s17 ; GFX10-NEXT: s_xor_b32 s6, s8, s6
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v4 ; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX10-NEXT: s_xor_b32 s8, s8, s18 ; GFX10-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v5 ; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v6 ; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v7 ; GFX10-NEXT: v_mul_lo_u32 v4, v0, s12
; GFX10-NEXT: s_xor_b32 s9, s9, s19 ; GFX10-NEXT: v_sub_nc_u32_e32 v4, s0, v4
; GFX10-NEXT: v_mul_hi_u32 v0, s10, v0 ; GFX10-NEXT: s_add_i32 s0, s9, s8
; GFX10-NEXT: v_mul_hi_u32 v1, s11, v1 ; GFX10-NEXT: s_ashr_i32 s9, s10, 31
; GFX10-NEXT: v_mul_hi_u32 v2, s8, v2 ; GFX10-NEXT: s_xor_b32 s0, s0, s8
; GFX10-NEXT: v_mul_hi_u32 v3, s9, v3 ; GFX10-NEXT: s_add_i32 s1, s10, s9
; GFX10-NEXT: s_xor_b32 s22, s18, s2 ; GFX10-NEXT: v_mul_hi_u32 v1, s0, v1
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s12, v4
; GFX10-NEXT: v_mul_lo_u32 v4, v0, s14 ; GFX10-NEXT: s_xor_b32 s1, s1, s9
; GFX10-NEXT: v_mul_lo_u32 v5, v1, s15 ; GFX10-NEXT: s_ashr_i32 s10, s11, 31
; GFX10-NEXT: v_mul_lo_u32 v6, v2, s12 ; GFX10-NEXT: v_mul_hi_u32 v2, s1, v2
; GFX10-NEXT: v_mul_lo_u32 v7, v3, s13 ; GFX10-NEXT: s_add_i32 s2, s11, s10
; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v1 ; GFX10-NEXT: s_xor_b32 s2, s2, s10
; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v2 ; GFX10-NEXT: v_mul_lo_u32 v5, v1, s13
; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v6, 1, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v4, s10, v4 ; GFX10-NEXT: v_mul_hi_u32 v3, s2, v3
; GFX10-NEXT: v_sub_nc_u32_e32 v5, s11, v5 ; GFX10-NEXT: v_add_nc_u32_e32 v7, 1, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v6, s8, v6 ; GFX10-NEXT: v_sub_nc_u32_e32 v5, s0, v5
; GFX10-NEXT: v_sub_nc_u32_e32 v7, s9, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s14, v4 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v5
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s15, v5 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s12, v6 ; GFX10-NEXT: v_mul_lo_u32 v6, v2, s14
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s13, v7 ; GFX10-NEXT: v_sub_nc_u32_e32 v6, s1, v6
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s14, v6
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s14, v4 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v7, s1
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0 ; GFX10-NEXT: v_mul_lo_u32 v7, v3, s15
; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s15, v5 ; GFX10-NEXT: v_sub_nc_u32_e32 v7, s2, v7
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s1 ; GFX10-NEXT: v_cmp_le_u32_e64 s2, s15, v7
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s12, v6 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v8, s2
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s12, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v11, s13, v7
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v9, s0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s13, v5
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s1 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s12, v4
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v8, s0
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s14, v6
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v5
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v8, s1
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s15, v7
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s14, v6
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v8, s2
; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s2 ; GFX10-NEXT: v_cmp_le_u32_e64 s2, s15, v7
; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v1
; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v2
; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s14, v4
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s15, v5
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s12, v6
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s13, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s14, v4 ; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v1
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0 ; GFX10-NEXT: v_xor_b32_e32 v0, s3, v0
; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s15, v5 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v8, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s1 ; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s12, v6 ; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s3, v0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s2 ; GFX10-NEXT: v_xor_b32_e32 v1, s6, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v11, s13, v7 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v8, s1
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo ; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v3
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v9, s0 ; GFX10-NEXT: s_xor_b32 s3, s9, s7
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s1 ; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s6, v1
; GFX10-NEXT: s_xor_b32 s0, s19, s3 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s2 ; GFX10-NEXT: v_xor_b32_e32 v2, s3, v2
; GFX10-NEXT: v_xor_b32_e32 v0, s20, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v8, s2
; GFX10-NEXT: v_xor_b32_e32 v1, s21, v1
; GFX10-NEXT: v_xor_b32_e32 v2, s22, v2
; GFX10-NEXT: v_xor_b32_e32 v3, s0, v3
; GFX10-NEXT: v_xor_b32_e32 v4, s16, v4
; GFX10-NEXT: v_xor_b32_e32 v5, s17, v5
; GFX10-NEXT: v_xor_b32_e32 v6, s18, v6
; GFX10-NEXT: v_xor_b32_e32 v7, s19, v7
; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s20, v0
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s21, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s22, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s0, v3
; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s16, v4 ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s3, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s17, v5 ; GFX10-NEXT: s_xor_b32 s3, s10, s16
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s18, v6 ; GFX10-NEXT: v_xor_b32_e32 v3, s3, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s19, v7 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s3, v3
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5] ; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5]
; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[6:7] ; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s12, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s13, v5
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s14, v6
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s15, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v2, s1
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s2
; GFX10-NEXT: v_xor_b32_e32 v0, s17, v0
; GFX10-NEXT: v_xor_b32_e32 v1, s8, v1
; GFX10-NEXT: v_xor_b32_e32 v2, s9, v2
; GFX10-NEXT: v_xor_b32_e32 v3, s10, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s17, v0
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s8, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s9, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s10, v3
; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = sdiv <4 x i32> %x, %y %div = sdiv <4 x i32> %x, %y
store <4 x i32> %div, ptr addrspace(1) %out0 store <4 x i32> %div, ptr addrspace(1) %out0
%rem = srem <4 x i32> %x, %y %rem = srem <4 x i32> %x, %y
store <4 x i32> %rem, ptr addrspace(1) %out1 store <4 x i32> %rem, ptr addrspace(1) %out1
ret void ret void
} }
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; GFX9-NEXT: global_store_dwordx4 v13, v[0:3], s[4:5] ; GFX9-NEXT: global_store_dwordx4 v13, v[0:3], s[4:5]
; GFX9-NEXT: global_store_dwordx4 v13, v[4:7], s[6:7] ; GFX9-NEXT: global_store_dwordx4 v13, v[4:7], s[6:7]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdivrem_v2i64: ; GFX10-LABEL: sdivrem_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_ashr_i32 s2, s9, 31 ; GFX10-NEXT: s_ashr_i32 s16, s9, 31
; GFX10-NEXT: s_ashr_i32 s6, s13, 31 ; GFX10-NEXT: s_ashr_i32 s0, s13, 31
; GFX10-NEXT: s_add_u32 s0, s8, s2 ; GFX10-NEXT: s_add_u32 s2, s8, s16
; GFX10-NEXT: s_addc_u32 s1, s9, s2 ; GFX10-NEXT: s_addc_u32 s3, s9, s16
; GFX10-NEXT: s_add_u32 s8, s12, s6 ; GFX10-NEXT: s_add_u32 s6, s12, s0
; GFX10-NEXT: s_mov_b32 s7, s6 ; GFX10-NEXT: s_mov_b32 s1, s0
; GFX10-NEXT: s_addc_u32 s9, s13, s6 ; GFX10-NEXT: s_addc_u32 s7, s13, s0
; GFX10-NEXT: s_mov_b32 s3, s2
; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]
; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX10-NEXT: s_sub_u32 s20, 0, s8
; GFX10-NEXT: s_subb_u32 s21, 0, s9
; GFX10-NEXT: s_ashr_i32 s12, s11, 31
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX10-NEXT: s_xor_b64 s[18:19], s[2:3], s[6:7]
; GFX10-NEXT: s_ashr_i32 s16, s15, 31
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
; GFX10-NEXT: s_add_u32 s6, s10, s12
; GFX10-NEXT: s_addc_u32 s7, s11, s12
; GFX10-NEXT: s_add_u32 s10, s14, s16
; GFX10-NEXT: s_mov_b32 s17, s16 ; GFX10-NEXT: s_mov_b32 s17, s16
; GFX10-NEXT: s_addc_u32 s11, s15, s16 ; GFX10-NEXT: s_xor_b64 s[8:9], s[6:7], s[0:1]
; GFX10-NEXT: v_add_f32_e32 v0, v1, v0 ; GFX10-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17]
; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[16:17] ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX10-NEXT: s_sub_u32 s22, 0, s8
; GFX10-NEXT: s_subb_u32 s23, 0, s9
; GFX10-NEXT: s_ashr_i32 s12, s11, 31
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: s_xor_b64 s[18:19], s[16:17], s[0:1]
; GFX10-NEXT: s_ashr_i32 s20, s15, 31
; GFX10-NEXT: s_add_u32 s0, s10, s12
; GFX10-NEXT: s_addc_u32 s1, s11, s12
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: s_mov_b32 s21, s20
; GFX10-NEXT: s_mov_b32 s13, s12 ; GFX10-NEXT: s_mov_b32 s13, s12
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s11
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s10
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_xor_b64 s[14:15], s[6:7], s[12:13]
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX10-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 ; GFX10-NEXT: v_trunc_f32_e32 v1, v1
; GFX10-NEXT: v_trunc_f32_e32 v2, v2 ; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX10-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v1 ; GFX10-NEXT: v_add_f32_e32 v0, v2, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0xcf800000, v2 ; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v5, v2 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v0
; GFX10-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 ; GFX10-NEXT: v_mul_lo_u32 v4, s22, v2
; GFX10-NEXT: v_add_f32_e32 v0, v1, v0 ; GFX10-NEXT: v_mul_lo_u32 v5, s23, v3
; GFX10-NEXT: v_mul_lo_u32 v7, s20, v5 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s6, s22, v3, 0
; GFX10-NEXT: v_trunc_f32_e32 v4, v4 ; GFX10-NEXT: v_add3_u32 v1, v1, v4, v5
; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v0 ; GFX10-NEXT: v_mul_lo_u32 v4, v2, v0
; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v4 ; GFX10-NEXT: v_mul_lo_u32 v5, v3, v1
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s3, s20, v6, 0 ; GFX10-NEXT: v_add_co_u32 v4, s6, v4, v5
; GFX10-NEXT: v_mul_lo_u32 v8, s21, v6 ; GFX10-NEXT: v_mul_hi_u32 v5, v3, v0
; GFX10-NEXT: v_add_f32_e32 v2, v2, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v4 ; GFX10-NEXT: v_mul_hi_u32 v0, v2, v0
; GFX10-NEXT: s_sub_u32 s3, 0, s10 ; GFX10-NEXT: v_add_co_u32 v4, s6, v4, v5
; GFX10-NEXT: s_subb_u32 s6, 0, s11 ; GFX10-NEXT: v_mul_lo_u32 v5, v2, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v4, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s6
; GFX10-NEXT: v_mul_lo_u32 v9, s3, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v4
; GFX10-NEXT: v_add3_u32 v7, v1, v7, v8 ; GFX10-NEXT: v_add_co_u32 v0, s6, v5, v0
; GFX10-NEXT: v_mul_lo_u32 v10, v5, v0 ; GFX10-NEXT: v_mul_hi_u32 v5, v3, v1
; GFX10-NEXT: v_mul_hi_u32 v11, v6, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s7, s3, v4, 0 ; GFX10-NEXT: v_add_co_u32 v0, s6, v0, v5
; GFX10-NEXT: v_mul_lo_u32 v8, s6, v4 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6
; GFX10-NEXT: v_mul_lo_u32 v12, v6, v7 ; GFX10-NEXT: v_add_co_u32 v4, s6, v0, v4
; GFX10-NEXT: v_mul_hi_u32 v0, v5, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, v2, v1
; GFX10-NEXT: v_mul_lo_u32 v13, v5, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v6, v5
; GFX10-NEXT: v_mul_hi_u32 v14, v6, v7 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s6
; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7 ; GFX10-NEXT: s_add_u32 s6, s14, s20
; GFX10-NEXT: v_add3_u32 v2, v2, v9, v8 ; GFX10-NEXT: s_addc_u32 s7, s15, s20
; GFX10-NEXT: v_add_co_u32 v10, s7, v10, v12 ; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v3, v4
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s7 ; GFX10-NEXT: s_xor_b64 s[10:11], s[6:7], s[20:21]
; GFX10-NEXT: v_add_co_u32 v0, s7, v13, v0 ; GFX10-NEXT: v_add3_u32 v5, v5, v1, v0
; GFX10-NEXT: v_mul_lo_u32 v8, v3, v1 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s11
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s7 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s10
; GFX10-NEXT: v_mul_lo_u32 v15, v4, v2 ; GFX10-NEXT: s_xor_b64 s[6:7], s[0:1], s[12:13]
; GFX10-NEXT: v_add_co_u32 v10, s7, v10, v11 ; GFX10-NEXT: s_sub_u32 s0, 0, s10
; GFX10-NEXT: v_mul_hi_u32 v9, v4, v1 ; GFX10-NEXT: s_subb_u32 s1, 0, s11
; GFX10-NEXT: v_mul_hi_u32 v1, v3, v1 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s7 ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32 v0, s7, v0, v14 ; GFX10-NEXT: v_mul_lo_u32 v4, s23, v3
; GFX10-NEXT: v_mul_lo_u32 v14, v3, v2 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s7 ; GFX10-NEXT: v_mul_lo_u32 v5, s22, v2
; GFX10-NEXT: v_add_nc_u32_e32 v10, v12, v10 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_add_co_u32 v8, s7, v8, v15 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s7 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX10-NEXT: v_mul_hi_u32 v16, v4, v2 ; GFX10-NEXT: v_trunc_f32_e32 v1, v1
; GFX10-NEXT: v_add_nc_u32_e32 v11, v13, v11 ; GFX10-NEXT: v_mul_f32_e32 v6, 0xcf800000, v1
; GFX10-NEXT: v_add_co_u32 v1, s7, v14, v1 ; GFX10-NEXT: v_add_f32_e32 v0, v6, v0
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s7 ; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v1
; GFX10-NEXT: v_add_co_u32 v0, s7, v0, v10 ; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v0
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s7 ; GFX10-NEXT: v_mul_lo_u32 v8, s0, v6
; GFX10-NEXT: v_add_co_u32 v8, s7, v8, v9 ; GFX10-NEXT: v_mul_lo_u32 v9, s1, v7
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s7 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s14, s0, v7, 0
; GFX10-NEXT: v_add_co_u32 v9, s7, v1, v16 ; GFX10-NEXT: v_add3_u32 v1, v1, v8, v9
; GFX10-NEXT: v_add3_u32 v7, v11, v10, v7 ; GFX10-NEXT: v_mul_lo_u32 v8, v6, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7 ; GFX10-NEXT: v_mul_lo_u32 v9, v7, v1
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v6, v0 ; GFX10-NEXT: v_add_co_u32 v8, s14, v8, v9
; GFX10-NEXT: v_add_nc_u32_e32 v8, v12, v8 ; GFX10-NEXT: v_mul_hi_u32 v9, v7, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s14
; GFX10-NEXT: v_mul_hi_u32 v2, v3, v2 ; GFX10-NEXT: v_mul_hi_u32 v0, v6, v0
; GFX10-NEXT: v_add_nc_u32_e32 v10, v13, v1 ; GFX10-NEXT: v_add_co_u32 v8, s14, v8, v9
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s7, s20, v6, 0 ; GFX10-NEXT: v_mul_lo_u32 v9, v6, v1
; GFX10-NEXT: v_add_co_u32 v7, s7, v9, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s14
; GFX10-NEXT: v_mul_lo_u32 v9, s21, v6 ; GFX10-NEXT: v_add_nc_u32_e32 v8, v10, v8
; GFX10-NEXT: v_mul_lo_u32 v11, s20, v5 ; GFX10-NEXT: v_add_co_u32 v0, s14, v9, v0
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s7 ; GFX10-NEXT: v_mul_hi_u32 v9, v7, v1
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v4, v7 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s14
; GFX10-NEXT: v_add3_u32 v2, v10, v8, v2 ; GFX10-NEXT: v_add_co_u32 v0, s14, v0, v9
; GFX10-NEXT: v_mul_lo_u32 v8, v5, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s14
; GFX10-NEXT: v_add3_u32 v7, v1, v11, v9 ; GFX10-NEXT: v_add_co_u32 v8, s14, v0, v8
; GFX10-NEXT: v_mul_hi_u32 v10, v6, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, v6, v1
; GFX10-NEXT: v_mul_hi_u32 v0, v5, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v9, v10, v9
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s14
; GFX10-NEXT: v_mul_lo_u32 v12, v6, v7 ; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v7, v8
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s7, s3, v4, 0 ; GFX10-NEXT: v_add3_u32 v9, v9, v1, v0
; GFX10-NEXT: v_mul_lo_u32 v9, s6, v4 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s14, s22, v3, 0
; GFX10-NEXT: v_mul_lo_u32 v11, s3, v3 ; GFX10-NEXT: v_mul_lo_u32 v8, s1, v7
; GFX10-NEXT: v_mul_lo_u32 v13, v5, v7 ; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v6, v9, vcc_lo
; GFX10-NEXT: v_mul_hi_u32 v14, v6, v7 ; GFX10-NEXT: v_add3_u32 v1, v1, v5, v4
; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7 ; GFX10-NEXT: v_mul_lo_u32 v4, v2, v0
; GFX10-NEXT: v_add_co_u32 v8, s3, v8, v12 ; GFX10-NEXT: v_mul_lo_u32 v9, s0, v6
; GFX10-NEXT: v_mul_lo_u32 v15, v3, v1 ; GFX10-NEXT: v_mul_lo_u32 v5, v3, v1
; GFX10-NEXT: v_mul_hi_u32 v16, v4, v1 ; GFX10-NEXT: v_add_co_u32 v4, s14, v4, v5
; GFX10-NEXT: v_add3_u32 v2, v2, v11, v9 ; GFX10-NEXT: v_mul_hi_u32 v5, v3, v0
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s14
; GFX10-NEXT: v_add_co_u32 v0, s3, v13, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, v2, v0
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s3 ; GFX10-NEXT: v_add_co_u32 v4, s14, v4, v5
; GFX10-NEXT: v_add_co_u32 v8, s3, v8, v10 ; GFX10-NEXT: v_mul_lo_u32 v5, v2, v1
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s14
; GFX10-NEXT: v_add_co_u32 v0, s3, v0, v14 ; GFX10-NEXT: v_add_nc_u32_e32 v4, v10, v4
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s3 ; GFX10-NEXT: v_add_co_u32 v0, s14, v5, v0
; GFX10-NEXT: v_mul_lo_u32 v12, v4, v2 ; GFX10-NEXT: v_mul_hi_u32 v5, v3, v1
; GFX10-NEXT: v_add_nc_u32_e32 v8, v9, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s14
; GFX10-NEXT: v_mul_hi_u32 v1, v3, v1 ; GFX10-NEXT: v_add_co_u32 v0, s14, v0, v5
; GFX10-NEXT: v_mul_lo_u32 v13, v3, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s14
; GFX10-NEXT: v_add_nc_u32_e32 v10, v11, v10 ; GFX10-NEXT: v_add_co_u32 v4, s14, v0, v4
; GFX10-NEXT: v_mul_hi_u32 v9, v4, v2 ; GFX10-NEXT: v_mul_hi_u32 v0, v2, v1
; GFX10-NEXT: v_add_co_u32 v0, s3, v0, v8 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v10, v5
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s14
; GFX10-NEXT: v_add_co_u32 v11, s3, v15, v12 ; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v3, v4
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v6, v0 ; GFX10-NEXT: v_add3_u32 v5, v5, v1, v0
; GFX10-NEXT: v_add3_u32 v7, v10, v8, v7 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s0, v7, 0
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s3 ; GFX10-NEXT: v_mul_lo_u32 v4, s3, v3
; GFX10-NEXT: v_add_co_u32 v1, s3, v13, v1 ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s3 ; GFX10-NEXT: v_add3_u32 v1, v1, v9, v8
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo ; GFX10-NEXT: v_mul_lo_u32 v8, v6, v0
; GFX10-NEXT: v_add_co_u32 v8, s3, v11, v16 ; GFX10-NEXT: v_mul_lo_u32 v5, s2, v2
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s3 ; GFX10-NEXT: v_mul_lo_u32 v9, v7, v1
; GFX10-NEXT: v_add_co_u32 v1, s3, v1, v9 ; GFX10-NEXT: v_add_co_u32 v8, s0, v8, v9
; GFX10-NEXT: v_mul_lo_u32 v7, s1, v0 ; GFX10-NEXT: v_mul_hi_u32 v9, v7, v0
; GFX10-NEXT: v_mul_lo_u32 v9, s0, v5 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v10, s1, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, v6, v0
; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX10-NEXT: v_add_co_u32 v8, s0, v8, v9
; GFX10-NEXT: v_mul_lo_u32 v11, s1, v5 ; GFX10-NEXT: v_mul_lo_u32 v9, v6, v1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s3
; GFX10-NEXT: v_add_nc_u32_e32 v8, v12, v8
; GFX10-NEXT: v_mul_hi_u32 v12, s0, v5
; GFX10-NEXT: v_mul_hi_u32 v5, s1, v5
; GFX10-NEXT: v_add_co_u32 v7, s3, v7, v9
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s3
; GFX10-NEXT: v_add_co_u32 v10, s3, v11, v10
; GFX10-NEXT: v_add_co_u32 v0, s6, v7, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s6
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s3
; GFX10-NEXT: v_add_co_u32 v10, s3, v10, v12
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s3
; GFX10-NEXT: v_add_nc_u32_e32 v0, v9, v0
; GFX10-NEXT: v_add_co_u32 v8, s3, v1, v8
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s3
; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v11
; GFX10-NEXT: v_add_co_u32 v9, s3, v10, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3
; GFX10-NEXT: v_mul_hi_u32 v2, v3, v2
; GFX10-NEXT: v_add_nc_u32_e32 v6, v13, v6
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v4, v8
; GFX10-NEXT: v_add3_u32 v5, v7, v0, v5
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_mul_hi_u32 v8, s14, v4
; GFX10-NEXT: v_add3_u32 v2, v6, v1, v2
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s3, s8, v9, 0
; GFX10-NEXT: v_mul_lo_u32 v6, s9, v9
; GFX10-NEXT: v_mul_lo_u32 v7, s8, v5
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v3, v2, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v3, s15, v4
; GFX10-NEXT: v_mul_hi_u32 v4, s15, v4
; GFX10-NEXT: v_mul_lo_u32 v10, s14, v2
; GFX10-NEXT: v_mul_lo_u32 v11, s15, v2
; GFX10-NEXT: v_add3_u32 v1, v1, v7, v6
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v9, 1
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v12, s1, v1
; GFX10-NEXT: v_sub_co_u32 v13, vcc_lo, s0, v0
; GFX10-NEXT: v_sub_co_ci_u32_e64 v14, s0, s1, v1, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, s9, v12, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s8, v13
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v12, vcc_lo, v13, s8
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v15, s0, 0, v0, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v14
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, s9, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v12
; GFX10-NEXT: v_cndmask_b32_e64 v17, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v15
; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, -1, s0
; GFX10-NEXT: v_add_co_u32 v19, s0, v6, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v20, s0, 0, v7, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v14
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v1, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v15
; GFX10-NEXT: v_cndmask_b32_e64 v17, v18, v17, s0
; GFX10-NEXT: v_add_co_u32 v1, s0, v3, v10
; GFX10-NEXT: v_mul_hi_u32 v10, s14, v2
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s0, v11, v4
; GFX10-NEXT: v_add_co_u32 v1, s1, v1, v8
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v10 ; GFX10-NEXT: v_add_nc_u32_e32 v8, v10, v8
; GFX10-NEXT: v_add_co_u32 v0, s0, v9, v0
; GFX10-NEXT: v_mul_hi_u32 v9, v7, v1
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v3, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, v6, v1
; GFX10-NEXT: v_mul_hi_u32 v2, s15, v2 ; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v9
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17 ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v3, v8, v10 ; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v8
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_mul_hi_u32 v5, s2, v3
; GFX10-NEXT: v_add_nc_u32_e32 v9, v10, v9
; GFX10-NEXT: v_mul_hi_u32 v3, s3, v3
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v7, v0
; GFX10-NEXT: v_add3_u32 v1, v9, v8, v1
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_mul_lo_u32 v5, s3, v2
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v4, v8, v4
; GFX10-NEXT: v_add_co_u32 v3, s0, v5, v3
; GFX10-NEXT: v_mul_hi_u32 v5, s2, v2
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v2, s3, v2
; GFX10-NEXT: v_add_co_u32 v3, s0, v3, v5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v3, s0, v3, v4
; GFX10-NEXT: v_add_nc_u32_e32 v5, v8, v5
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_mul_lo_u32 v7, s9, v3
; GFX10-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX10-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX10-NEXT: v_mul_lo_u32 v5, s6, v1
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_mul_hi_u32 v5, s6, v0
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_mul_lo_u32 v5, s7, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v4
; GFX10-NEXT: v_add_co_u32 v0, s0, v5, v0
; GFX10-NEXT: v_mul_hi_u32 v5, s6, v1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s0, v0, v4
; GFX10-NEXT: v_mul_hi_u32 v0, s7, v1
; GFX10-NEXT: v_add_nc_u32_e32 v5, v6, v5
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: v_sub_co_u32 v8, s0, v12, s8 ; GFX10-NEXT: v_mul_lo_u32 v6, s8, v2
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v10, s0, 0, v0, s0 ; GFX10-NEXT: v_mul_lo_u32 v17, s11, v4
; GFX10-NEXT: v_add3_u32 v2, v3, v1, v2 ; GFX10-NEXT: v_add3_u32 v5, v5, v1, v0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v6, v19, vcc_lo ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s8, v3, 0
; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v20, vcc_lo ; GFX10-NEXT: v_mul_lo_u32 v16, s10, v5
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s10, v4, 0 ; GFX10-NEXT: v_add3_u32 v1, v1, v6, v7
; GFX10-NEXT: v_mul_lo_u32 v7, s10, v2 ; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, s2, v0
; GFX10-NEXT: v_mul_lo_u32 v11, s11, v4 ; GFX10-NEXT: v_sub_co_ci_u32_e64 v7, s0, s3, v1, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v17 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v6
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16 ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s9, v7
; GFX10-NEXT: v_mov_b32_e32 v16, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v8, v12, v8, s0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v7
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, -1, s1
; GFX10-NEXT: v_add3_u32 v1, v1, v7, v11 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v0, v8, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v15, v10, s0 ; GFX10-NEXT: v_sub_nc_u32_e32 v0, s3, v1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v9, vcc_lo, s9, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v7, v13, v8, vcc_lo ; GFX10-NEXT: v_sub_co_u32 v10, vcc_lo, v6, s8
; GFX10-NEXT: v_sub_co_u32 v8, s0, s14, v0 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v11, s0, 0, v9, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e64 v9, s1, s15, v1, s0 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v10
; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s9, v11
; GFX10-NEXT: v_sub_nc_u32_e32 v1, s15, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, -1, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v11
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, -1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v12, v0, v1, s0
; GFX10-NEXT: v_add_co_u32 v0, s0, v3, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v13, s0, 0, v2, s0
; GFX10-NEXT: v_add_co_u32 v1, s0, v0, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v14, s0, 0, v13, s0
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v12
; GFX10-NEXT: v_cndmask_b32_e64 v15, v0, v1, s0
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s1, s10, v4, 0
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v14, s0
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v8
; GFX10-NEXT: v_add3_u32 v1, v1, v16, v17
; GFX10-NEXT: v_sub_co_u32 v8, s1, s6, v0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v15, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v13, s0
; GFX10-NEXT: v_sub_nc_u32_e32 v0, s7, v1
; GFX10-NEXT: v_sub_co_ci_u32_e64 v14, s2, s7, v1, s1
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v16, s1, s11, v0, s1
; GFX10-NEXT: v_sub_co_u32 v17, s1, v8, s10
; GFX10-NEXT: v_cmp_le_u32_e64 s6, s11, v14
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v18, s2, 0, v16, s1
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s10, v17
; GFX10-NEXT: v_cmp_le_u32_e64 s3, s11, v18
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s11, v18
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, -1, s3
; GFX10-NEXT: v_cmp_le_u32_e64 s3, s10, v8
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v1, s2
; GFX10-NEXT: v_add_co_u32 v1, s2, v4, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v19, s2, 0, v5, s2
; GFX10-NEXT: v_cndmask_b32_e64 v22, 0, -1, s3
; GFX10-NEXT: v_add_co_u32 v20, s2, v1, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v21, s2, 0, v19, s2
; GFX10-NEXT: v_cmp_ne_u32_e64 s2, 0, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, -1, s6
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, s11, v14
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v20, s2
; GFX10-NEXT: v_cndmask_b32_e64 v13, v19, v21, s2
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v22, s3
; GFX10-NEXT: v_cmp_ne_u32_e64 s3, 0, v0
; GFX10-NEXT: v_xor_b32_e32 v0, s18, v3 ; GFX10-NEXT: v_xor_b32_e32 v0, s18, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s11, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v1, s3
; GFX10-NEXT: v_xor_b32_e32 v3, s19, v5 ; GFX10-NEXT: v_xor_b32_e32 v1, s19, v2
; GFX10-NEXT: v_xor_b32_e32 v6, s2, v6 ; GFX10-NEXT: v_sub_co_u32 v0, s6, v0, s18
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v13, s3
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v10, vcc_lo, s11, v1, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v1, s6, s19, v1, s6
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s10, v8 ; GFX10-NEXT: s_xor_b64 s[6:7], s[12:13], s[20:21]
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc_lo ; GFX10-NEXT: v_xor_b32_e32 v3, s6, v4
; GFX10-NEXT: v_sub_co_u32 v12, vcc_lo, v8, s10 ; GFX10-NEXT: v_xor_b32_e32 v4, s7, v2
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v13, s0, 0, v10, vcc_lo ; GFX10-NEXT: v_sub_co_u32 v2, s6, v3, s6
; GFX10-NEXT: v_sub_co_u32 v0, s0, v0, s18 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v3, s6, s7, v4, s6
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v1, s0, s19, v3, s0 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s11, v9 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_xor_b32_e32 v3, s2, v7
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v11, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v13
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v12
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s0
; GFX10-NEXT: v_add_co_u32 v14, s0, v4, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v15, s0, 0, v2, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s11, v13
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s0
; GFX10-NEXT: v_add_co_u32 v11, s0, v14, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v17, s0, 0, v15, s0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
; GFX10-NEXT: v_sub_co_u32 v7, s0, v12, s10
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v10, s0, 0, v10, s0
; GFX10-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v5
; GFX10-NEXT: v_cndmask_b32_e32 v14, v15, v17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v12, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v7, v13, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v10, v4, v11, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v14, s0
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v9, v7, s0
; GFX10-NEXT: s_xor_b64 s[0:1], s[12:13], s[16:17]
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v3, s2
; GFX10-NEXT: v_xor_b32_e32 v3, s0, v10
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s2, v6, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v6, s1, v2
; GFX10-NEXT: v_xor_b32_e32 v8, s12, v8
; GFX10-NEXT: v_xor_b32_e32 v7, s12, v7
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v3, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v6, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, v8, s12
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s12, v7, vcc_lo
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v16, v[0:3], s[4:5] ; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]
; GFX10-NEXT: global_store_dwordx4 v16, v[4:7], s[6:7] ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, s9, v9, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v1, vcc_lo, v10, s8
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX10-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, vcc_lo, s11, v16, s1
; GFX10-NEXT: v_sub_co_u32 v3, vcc_lo, v17, s10
; GFX10-NEXT: v_cndmask_b32_e64 v1, v6, v1, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v17, v3, s2
; GFX10-NEXT: v_cndmask_b32_e64 v0, v7, v0, s0
; GFX10-NEXT: v_xor_b32_e32 v1, s16, v1
; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, v2, s2
; GFX10-NEXT: v_cndmask_b32_e64 v3, v8, v3, s3
; GFX10-NEXT: v_xor_b32_e32 v5, s16, v0
; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, v1, s16
; GFX10-NEXT: v_cndmask_b32_e64 v2, v14, v2, s3
; GFX10-NEXT: v_xor_b32_e32 v3, s12, v3
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, s16, v5, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v5, s12, v2
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v3, s12
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s12, v5, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = sdiv <2 x i64> %x, %y %div = sdiv <2 x i64> %x, %y
store <2 x i64> %div, ptr addrspace(1) %out0 store <2 x i64> %div, ptr addrspace(1) %out0
%rem = srem <2 x i64> %x, %y %rem = srem <2 x i64> %x, %y
store <2 x i64> %rem, ptr addrspace(1) %out1 store <2 x i64> %rem, ptr addrspace(1) %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 315 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: global_store_short v1, v0, s[2:3] ; GFX9-NEXT: global_store_short v1, v0, s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdivrem_v2i8: ; GFX10-LABEL: sdivrem_v2i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dword s0, s[4:5], 0x10 ; GFX10-NEXT: s_load_dword s0, s[4:5], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_bfe_i32 s1, s0, 0x80018 ; GFX10-NEXT: s_bfe_i32 s1, s0, 0x80010
; GFX10-NEXT: s_bfe_i32 s2, s0, 0x80010 ; GFX10-NEXT: s_bfe_i32 s2, s0, 0x80018
; GFX10-NEXT: s_ashr_i32 s3, s1, 31 ; GFX10-NEXT: s_ashr_i32 s6, s1, 31
; GFX10-NEXT: s_ashr_i32 s8, s2, 31 ; GFX10-NEXT: s_ashr_i32 s3, s2, 31
; GFX10-NEXT: s_add_i32 s1, s1, s3 ; GFX10-NEXT: s_add_i32 s1, s1, s6
; GFX10-NEXT: s_add_i32 s2, s2, s8 ; GFX10-NEXT: s_add_i32 s2, s2, s3
; GFX10-NEXT: s_xor_b32 s1, s1, s3 ; GFX10-NEXT: s_xor_b32 s1, s1, s6
; GFX10-NEXT: s_xor_b32 s2, s2, s8 ; GFX10-NEXT: s_xor_b32 s2, s2, s3
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s1 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s1
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s2 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s2
; GFX10-NEXT: s_sub_i32 s6, 0, s1 ; GFX10-NEXT: s_sub_i32 s7, 0, s1
; GFX10-NEXT: s_sub_i32 s7, 0, s2 ; GFX10-NEXT: s_sub_i32 s8, 0, s2
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_mul_lo_u32 v2, s6, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s7, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s7, v1 ; GFX10-NEXT: s_sext_i32_i8 s7, s0
; GFX10-NEXT: s_sext_i32_i8 s6, s0 ; GFX10-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX10-NEXT: s_ashr_i32 s9, s7, 31
; GFX10-NEXT: s_bfe_i32 s0, s0, 0x80008 ; GFX10-NEXT: s_bfe_i32 s0, s0, 0x80008
; GFX10-NEXT: s_ashr_i32 s9, s6, 31 ; GFX10-NEXT: s_add_i32 s7, s7, s9
; GFX10-NEXT: s_ashr_i32 s10, s0, 31 ; GFX10-NEXT: s_ashr_i32 s8, s0, 31
; GFX10-NEXT: s_add_i32 s6, s6, s9 ; GFX10-NEXT: s_xor_b32 s7, s7, s9
; GFX10-NEXT: s_add_i32 s0, s0, s10
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX10-NEXT: s_add_i32 s0, s0, s8
; GFX10-NEXT: s_xor_b32 s0, s0, s10 ; GFX10-NEXT: s_xor_b32 s0, s0, s8
; GFX10-NEXT: s_xor_b32 s6, s6, s9
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: v_mul_hi_u32 v2, v1, v3
; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX10-NEXT: v_mul_hi_u32 v1, s6, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_lo_u32 v2, v0, s1 ; GFX10-NEXT: v_mul_lo_u32 v3, v0, s1
; GFX10-NEXT: v_mul_lo_u32 v3, v1, s2 ; GFX10-NEXT: v_mul_hi_u32 v1, s0, v1
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v0 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, s7, v3
; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s0, v2 ; GFX10-NEXT: s_xor_b32 s7, s8, s3
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s6, v3
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v2 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s1, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s2, v3 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, s2
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s0, v3
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v3 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v3
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s1, v2
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s2, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v2 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s1, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s0
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v3 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s2, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX10-NEXT: s_xor_b32 s1, s10, s3
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s1, v2
; GFX10-NEXT: v_xor_b32_e32 v0, s1, v0 ; GFX10-NEXT: v_xor_b32_e32 v1, s7, v1
; GFX10-NEXT: v_xor_b32_e32 v2, s10, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: s_xor_b32 s0, s9, s8 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s2, v3
; GFX10-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s7, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s1, v0 ; GFX10-NEXT: v_xor_b32_e32 v2, s9, v2
; GFX10-NEXT: v_xor_b32_e32 v3, s9, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s0
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s10, v2 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-NEXT: s_movk_i32 s1, 0xff ; GFX10-NEXT: s_xor_b32 s4, s9, s6
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s0, v1 ; GFX10-NEXT: s_movk_i32 s5, 0xff
; GFX10-NEXT: v_and_b32_sdwa v0, v0, s1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_xor_b32_e32 v0, s4, v0
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s9, v3 ; GFX10-NEXT: v_xor_b32_e32 v3, s8, v3
; GFX10-NEXT: v_and_b32_sdwa v2, v2, s1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_and_b32_sdwa v1, v1, s5 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s9, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s4, v0
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s8, v3
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v3, v3, s5 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_short v1, v0, s[4:5] ; GFX10-NEXT: global_store_short v1, v0, s[0:1]
; GFX10-NEXT: global_store_short v1, v2, s[6:7] ; GFX10-NEXT: global_store_short v1, v2, s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = sdiv <2 x i8> %x, %y %div = sdiv <2 x i8> %x, %y
store <2 x i8> %div, ptr addrspace(1) %out0 store <2 x i8> %div, ptr addrspace(1) %out0
%rem = srem <2 x i8> %x, %y %rem = srem <2 x i8> %x, %y
store <2 x i8> %rem, ptr addrspace(1) %out1 store <2 x i8> %rem, ptr addrspace(1) %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 314 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdivrem_v2i16: ; GFX10-LABEL: sdivrem_v2i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_sext_i32_i16 s2, s1 ; GFX10-NEXT: s_sext_i32_i16 s2, s1
; GFX10-NEXT: s_bfe_i32 s1, s1, 0x100010 ; GFX10-NEXT: s_bfe_i32 s1, s1, 0x100010
; GFX10-NEXT: s_ashr_i32 s3, s2, 31 ; GFX10-NEXT: s_ashr_i32 s6, s2, 31
; GFX10-NEXT: s_ashr_i32 s8, s1, 31 ; GFX10-NEXT: s_ashr_i32 s7, s1, 31
; GFX10-NEXT: s_add_i32 s2, s2, s3 ; GFX10-NEXT: s_add_i32 s2, s2, s6
; GFX10-NEXT: s_add_i32 s1, s1, s8 ; GFX10-NEXT: s_add_i32 s1, s1, s7
; GFX10-NEXT: s_xor_b32 s2, s2, s3 ; GFX10-NEXT: s_xor_b32 s2, s2, s6
; GFX10-NEXT: s_xor_b32 s1, s1, s8 ; GFX10-NEXT: s_xor_b32 s1, s1, s7
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s1 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s1
; GFX10-NEXT: s_sub_i32 s6, 0, s2 ; GFX10-NEXT: s_sub_i32 s3, 0, s2
; GFX10-NEXT: s_sub_i32 s7, 0, s1 ; GFX10-NEXT: s_sub_i32 s8, 0, s1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_mul_lo_u32 v2, s6, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s3, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s7, v1 ; GFX10-NEXT: s_sext_i32_i16 s3, s0
; GFX10-NEXT: s_sext_i32_i16 s6, s0 ; GFX10-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX10-NEXT: s_ashr_i32 s9, s3, 31
; GFX10-NEXT: s_bfe_i32 s0, s0, 0x100010 ; GFX10-NEXT: s_bfe_i32 s0, s0, 0x100010
; GFX10-NEXT: s_ashr_i32 s9, s6, 31 ; GFX10-NEXT: s_add_i32 s3, s3, s9
; GFX10-NEXT: s_ashr_i32 s10, s0, 31 ; GFX10-NEXT: s_ashr_i32 s8, s0, 31
; GFX10-NEXT: s_add_i32 s6, s6, s9 ; GFX10-NEXT: s_xor_b32 s3, s3, s9
; GFX10-NEXT: s_add_i32 s0, s0, s10
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX10-NEXT: s_add_i32 s0, s0, s8
; GFX10-NEXT: s_xor_b32 s6, s6, s9 ; GFX10-NEXT: s_xor_b32 s0, s0, s8
; GFX10-NEXT: s_xor_b32 s0, s0, s10
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: v_mul_hi_u32 v2, v1, v3
; GFX10-NEXT: v_mul_hi_u32 v0, s6, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s3, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_lo_u32 v3, v0, s2
; GFX10-NEXT: v_mul_hi_u32 v1, s0, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, s0, v1
; GFX10-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, s3, v3
; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v3, v1, s1 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, s1
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s6, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s0, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v3, s0, v3
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s1, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s2, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s2, v2
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s1, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s1, v3
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v2 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s1, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s2, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s1, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: s_xor_b32 s1, s9, s3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s2, v2
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s1, v3
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT: s_xor_b32 s0, s10, s8
; GFX10-NEXT: v_xor_b32_e32 v0, s1, v0
; GFX10-NEXT: v_xor_b32_e32 v1, s0, v1
; GFX10-NEXT: v_xor_b32_e32 v2, s9, v2 ; GFX10-NEXT: v_xor_b32_e32 v2, s9, v2
; GFX10-NEXT: v_xor_b32_e32 v3, s10, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s0
; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s1, v0 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s0, v1 ; GFX10-NEXT: s_xor_b32 s4, s9, s6
; GFX10-NEXT: s_xor_b32 s5, s8, s7
; GFX10-NEXT: v_xor_b32_e32 v0, s4, v0
; GFX10-NEXT: v_xor_b32_e32 v1, s5, v1
; GFX10-NEXT: v_xor_b32_e32 v3, s8, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s9, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s9, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s10, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s4, v0
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s5, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s8, v3
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_perm_b32 v2, v3, v2, 0x5040100 ; GFX10-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dword v1, v0, s[4:5] ; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-NEXT: global_store_dword v1, v2, s[6:7] ; GFX10-NEXT: global_store_dword v1, v2, s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = sdiv <2 x i16> %x, %y %div = sdiv <2 x i16> %x, %y
store <2 x i16> %div, ptr addrspace(1) %out0 store <2 x i16> %div, ptr addrspace(1) %out0
%rem = srem <2 x i16> %x, %y %rem = srem <2 x i16> %x, %y
store <2 x i16> %rem, ptr addrspace(1) %out1 store <2 x i16> %rem, ptr addrspace(1) %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 301 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll

Show First 20 Lines • Show All 991 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 0, v[0:1] ; GFX9-NEXT: v_lshrrev_b64 v[0:1], 0, v[0:1]
; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX9-NEXT: v_bfe_u32 v1, v1, 0, 10 ; GFX9-NEXT: v_bfe_u32 v1, v1, 0, 10
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 10, v2 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 10, v2
; GFX9-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3] ; GFX9-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3]
; GFX9-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX9-NEXT: v_or_b32_e32 v1, v1, v4
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10PLUS-LABEL: v_sext_inreg_i65_22: ; GFX10-LABEL: v_sext_inreg_i65_22:
; GFX10PLUS: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10PLUS-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3]
; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, 10, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 10, v1
; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], 0, v[0:1] ; GFX10-NEXT: v_lshrrev_b64 v[0:1], 0, v[0:1]
; GFX10PLUS-NEXT: v_or_b32_e32 v2, v2, v3 ; GFX10-NEXT: v_or_b32_e32 v2, v2, v3
; GFX10PLUS-NEXT: v_bfe_u32 v1, v1, 0, 10 ; GFX10-NEXT: v_bfe_u32 v1, v1, 0, 10
; GFX10PLUS-NEXT: v_bfe_i32 v2, v2, 0, 1 ; GFX10-NEXT: v_bfe_i32 v2, v2, 0, 1
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 10, v2
; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v4, 10, v2 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10PLUS-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3] ; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX10PLUS-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX10-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3]
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_sext_inreg_i65_22:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3]
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 10, v1
; GFX11-NEXT: v_lshrrev_b64 v[0:1], 0, v[0:1]
; GFX11-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-NEXT: v_bfe_u32 v1, v1, 0, 10
; GFX11-NEXT: v_bfe_i32 v2, v2, 0, 1
; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 10, v2
; GFX11-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3]
; GFX11-NEXT: v_or_b32_e32 v1, v1, v4
; GFX11-NEXT: s_setpc_b64 s[30:31]
%shl = shl i65 %value, 22 %shl = shl i65 %value, 22
%ashr = ashr i65 %shl, 22 %ashr = ashr i65 %shl, 22
ret i65 %ashr ret i65 %ashr
} }
define i65 @v_sext_inreg_i65_33(i65 %value) { define i65 @v_sext_inreg_i65_33(i65 %value) {
; GFX6-LABEL: v_sext_inreg_i65_33: ; GFX6-LABEL: v_sext_inreg_i65_33:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
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; GFX9-NEXT: v_bfe_i32 v1, v2, 0, 1 ; GFX9-NEXT: v_bfe_i32 v1, v2, 0, 1
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2] ; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0 ; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 1, v2 ; GFX9-NEXT: v_ashrrev_i32_e32 v2, 1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10PLUS-LABEL: v_sext_inreg_i65_33: ; GFX10-LABEL: v_sext_inreg_i65_33:
; GFX10PLUS: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10PLUS-NEXT: v_mov_b32_e32 v3, v1 ; GFX10-NEXT: v_bfe_i32 v0, v2, 0, 1
; GFX10PLUS-NEXT: v_bfe_i32 v1, v2, 0, 1 ; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, 1, v3 ; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 1, v3
; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2] ; GFX10-NEXT: v_ashrrev_i32_e32 v2, 1, v1
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 1, v2 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]
; GFX10PLUS-NEXT: v_or_b32_e32 v0, v3, v0 ; GFX10-NEXT: v_or_b32_e32 v0, v3, v0
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_sext_inreg_i65_33:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_mov_b32_e32 v3, v1
; GFX11-NEXT: v_bfe_i32 v1, v2, 0, 1
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 1, v3
; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
; GFX11-NEXT: v_ashrrev_i32_e32 v2, 1, v2
; GFX11-NEXT: v_or_b32_e32 v0, v3, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%shl = shl i65 %value, 33 %shl = shl i65 %value, 33
%ashr = ashr i65 %value, 33 %ashr = ashr i65 %value, 33
ret i65 %ashr ret i65 %ashr
} }
define amdgpu_ps i65 @s_sext_inreg_i65_18(i65 inreg %value) { define amdgpu_ps i65 @s_sext_inreg_i65_18(i65 inreg %value) {
; GCN-LABEL: s_sext_inreg_i65_18: ; GCN-LABEL: s_sext_inreg_i65_18:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
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llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll

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; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_lshlrev_b32_e32 v15, v16, v15 ; GCN-NEXT: v_lshlrev_b32_e32 v15, v16, v15
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_shl_v16i32: ; GFX10-LABEL: v_shl_v16i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_lshlrev_b32_e32 v0, v16, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, v16, v0
; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GFX10-NEXT: v_lshlrev_b32_e32 v1, v17, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, v17, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v2, v18, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, v18, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v3, v19, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, v19, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, v20, v4 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, v20, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v5, v21, v5 ; GFX10-NEXT: v_lshlrev_b32_e32 v5, v21, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v6, v22, v6 ; GFX10-NEXT: v_lshlrev_b32_e32 v6, v22, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v7, v23, v7 ; GFX10-NEXT: v_lshlrev_b32_e32 v7, v23, v7
; GFX10-NEXT: v_lshlrev_b32_e32 v8, v24, v8 ; GFX10-NEXT: v_lshlrev_b32_e32 v8, v24, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v9, v25, v9 ; GFX10-NEXT: v_lshlrev_b32_e32 v9, v25, v9
; GFX10-NEXT: v_lshlrev_b32_e32 v10, v26, v10 ; GFX10-NEXT: v_lshlrev_b32_e32 v10, v26, v10
; GFX10-NEXT: v_lshlrev_b32_e32 v11, v27, v11 ; GFX10-NEXT: v_lshlrev_b32_e32 v11, v27, v11
; GFX10-NEXT: v_lshlrev_b32_e32 v12, v28, v12 ; GFX10-NEXT: v_lshlrev_b32_e32 v12, v28, v12
; GFX10-NEXT: v_lshlrev_b32_e32 v13, v29, v13 ; GFX10-NEXT: v_lshlrev_b32_e32 v13, v29, v13
; GFX10-NEXT: v_lshlrev_b32_e32 v14, v30, v14 ; GFX10-NEXT: v_lshlrev_b32_e32 v14, v30, v14
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshlrev_b32_e32 v15, v31, v15 ; GFX10-NEXT: v_lshlrev_b32_e32 v15, v16, v15
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_shl_v16i32: ; GFX11-LABEL: v_shl_v16i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_lshlrev_b32_e32 v0, v16, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, v16, v0
; GFX11-NEXT: scratch_load_b32 v16, off, s32
; GFX11-NEXT: v_lshlrev_b32_e32 v1, v17, v1 ; GFX11-NEXT: v_lshlrev_b32_e32 v1, v17, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v2, v18, v2 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, v18, v2
; GFX11-NEXT: v_lshlrev_b32_e32 v3, v19, v3 ; GFX11-NEXT: v_lshlrev_b32_e32 v3, v19, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v4, v20, v4 ; GFX11-NEXT: v_lshlrev_b32_e32 v4, v20, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v5, v21, v5 ; GFX11-NEXT: v_lshlrev_b32_e32 v5, v21, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, v22, v6 ; GFX11-NEXT: v_lshlrev_b32_e32 v6, v22, v6
; GFX11-NEXT: v_lshlrev_b32_e32 v7, v23, v7 ; GFX11-NEXT: v_lshlrev_b32_e32 v7, v23, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v8, v24, v8 ; GFX11-NEXT: v_lshlrev_b32_e32 v8, v24, v8
; GFX11-NEXT: v_lshlrev_b32_e32 v9, v25, v9 ; GFX11-NEXT: v_lshlrev_b32_e32 v9, v25, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v10, v26, v10 ; GFX11-NEXT: v_lshlrev_b32_e32 v10, v26, v10
; GFX11-NEXT: v_lshlrev_b32_e32 v11, v27, v11 ; GFX11-NEXT: v_lshlrev_b32_e32 v11, v27, v11
; GFX11-NEXT: v_lshlrev_b32_e32 v12, v28, v12 ; GFX11-NEXT: v_lshlrev_b32_e32 v12, v28, v12
; GFX11-NEXT: v_lshlrev_b32_e32 v13, v29, v13 ; GFX11-NEXT: v_lshlrev_b32_e32 v13, v29, v13
; GFX11-NEXT: v_lshlrev_b32_e32 v14, v30, v14 ; GFX11-NEXT: v_lshlrev_b32_e32 v14, v30, v14
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshlrev_b32_e32 v15, v31, v15 ; GFX11-NEXT: v_lshlrev_b32_e32 v15, v16, v15
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = shl <16 x i32> %value, %amount %result = shl <16 x i32> %value, %amount
ret <16 x i32> %result ret <16 x i32> %result
} }
define amdgpu_ps <16 x i32> @s_shl_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) { define amdgpu_ps <16 x i32> @s_shl_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) {
; GCN-LABEL: s_shl_v16i32: ; GCN-LABEL: s_shl_v16i32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
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; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_shl_i65: ; GFX10-LABEL: v_shl_i65:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_sub_nc_u32_e32 v6, 64, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v4, 64, v3
; GFX10-NEXT: v_lshlrev_b64 v[4:5], v3, v[2:3]
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 64, v3
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3 ; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3
; GFX10-NEXT: v_lshrrev_b64 v[5:6], v6, v[0:1] ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v3
; GFX10-NEXT: v_lshlrev_b64 v[6:7], v3, v[0:1] ; GFX10-NEXT: v_lshrrev_b64 v[4:5], v4, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[8:9], v8, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[5:6], v3, v[2:3]
; GFX10-NEXT: v_or_b32_e32 v1, v5, v4 ; GFX10-NEXT: v_or_b32_e32 v6, v4, v5
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc_lo ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, 64, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v1, vcc_lo ; GFX10-NEXT: v_lshlrev_b64 v[4:5], v4, v[0:1]
; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc_lo ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v3, v[0:1]
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v2, s4
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_shl_i65: ; GFX11-LABEL: v_shl_i65:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_sub_nc_u32_e32 v6, 64, v3 ; GFX11-NEXT: v_sub_nc_u32_e32 v6, 64, v3
; GFX11-NEXT: v_lshlrev_b64 v[4:5], v3, v[2:3] ; GFX11-NEXT: v_lshlrev_b64 v[4:5], v3, v[2:3]
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llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_ssubsat_v4i8: ; GFX10-LABEL: v_ssubsat_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 24, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 24, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 8, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 24, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 24, v1
; GFX10-NEXT: v_perm_b32 v2, v2, v0, 0x5040100 ; GFX10-NEXT: v_perm_b32 v2, v2, v0, 0x5040100
; GFX10-NEXT: v_alignbit_b32 v0, v3, v0, 16 ; GFX10-NEXT: v_alignbit_b32 v0, v3, v0, 16
; GFX10-NEXT: v_perm_b32 v3, v4, v1, 0x5040100 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX10-NEXT: v_alignbit_b32 v1, v5, v1, 16
; GFX10-NEXT: v_mov_b32_e32 v4, 24
; GFX10-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_perm_b32 v3, v3, v1, 0x5040100
; GFX10-NEXT: v_alignbit_b32 v1, v4, v1, 16
; GFX10-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_sub_i16 v2, v2, v3 clamp ; GFX10-NEXT: v_pk_sub_i16 v2, v2, v3 clamp
; GFX10-NEXT: v_mov_b32_e32 v3, 8
; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp ; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_mov_b32_e32 v1, 8 ; GFX10-NEXT: v_pk_ashrrev_i16 v1, 8, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_ashrrev_i16 v2, 8, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v0 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v0
; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; GFX10-NEXT: v_and_or_b32 v1, v1, 0xff, v2
; GFX10-NEXT: v_and_or_b32 v1, v2, 0xff, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, 24
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_or3_b32 v0, v1, v3, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_ssubsat_v4i8: ; GFX11-LABEL: v_ssubsat_v4i8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
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; GFX9-NEXT: v_sub_i32 v4, s4, v4 clamp ; GFX9-NEXT: v_sub_i32 v4, s4, v4 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v4 ; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: s_ssubsat_v5i32: ; GFX10-LABEL: s_ssubsat_v5i32:
; GFX10PLUS: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s5 clamp ; GFX10-NEXT: v_sub_nc_i32 v0, s0, s5 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v1, s1, s6 clamp ; GFX10-NEXT: v_sub_nc_i32 v1, s1, s6 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v2, s2, s7 clamp ; GFX10-NEXT: v_sub_nc_i32 v2, s2, s7 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v3, s3, s8 clamp ; GFX10-NEXT: v_sub_nc_i32 v3, s3, s8 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v4, s4, s9 clamp ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_sub_nc_i32 v0, s4, s9 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_ssubsat_v5i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_sub_nc_i32 v0, s0, s5 clamp
; GFX11-NEXT: v_sub_nc_i32 v1, s1, s6 clamp
; GFX11-NEXT: v_sub_nc_i32 v2, s2, s7 clamp
; GFX11-NEXT: v_sub_nc_i32 v3, s3, s8 clamp
; GFX11-NEXT: v_sub_nc_i32 v4, s4, s9 clamp
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) %result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result ret <5 x i32> %result
} }
define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) { define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v16i32: ; GFX6-LABEL: v_ssubsat_v16i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_i32 v15, v15, v16 clamp ; GFX9-NEXT: v_sub_i32 v15, v15, v16 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_ssubsat_v16i32: ; GFX10-LABEL: v_ssubsat_v16i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_sub_nc_i32 v0, v0, v16 clamp ; GFX10-NEXT: v_sub_nc_i32 v0, v0, v16 clamp
; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GFX10-NEXT: v_sub_nc_i32 v1, v1, v17 clamp ; GFX10-NEXT: v_sub_nc_i32 v1, v1, v17 clamp
; GFX10-NEXT: v_sub_nc_i32 v2, v2, v18 clamp ; GFX10-NEXT: v_sub_nc_i32 v2, v2, v18 clamp
; GFX10-NEXT: v_sub_nc_i32 v3, v3, v19 clamp ; GFX10-NEXT: v_sub_nc_i32 v3, v3, v19 clamp
; GFX10-NEXT: v_sub_nc_i32 v4, v4, v20 clamp ; GFX10-NEXT: v_sub_nc_i32 v4, v4, v20 clamp
; GFX10-NEXT: v_sub_nc_i32 v5, v5, v21 clamp ; GFX10-NEXT: v_sub_nc_i32 v5, v5, v21 clamp
; GFX10-NEXT: v_sub_nc_i32 v6, v6, v22 clamp ; GFX10-NEXT: v_sub_nc_i32 v6, v6, v22 clamp
; GFX10-NEXT: v_sub_nc_i32 v7, v7, v23 clamp ; GFX10-NEXT: v_sub_nc_i32 v7, v7, v23 clamp
; GFX10-NEXT: v_sub_nc_i32 v8, v8, v24 clamp ; GFX10-NEXT: v_sub_nc_i32 v8, v8, v24 clamp
; GFX10-NEXT: v_sub_nc_i32 v9, v9, v25 clamp ; GFX10-NEXT: v_sub_nc_i32 v9, v9, v25 clamp
; GFX10-NEXT: v_sub_nc_i32 v10, v10, v26 clamp ; GFX10-NEXT: v_sub_nc_i32 v10, v10, v26 clamp
; GFX10-NEXT: v_sub_nc_i32 v11, v11, v27 clamp ; GFX10-NEXT: v_sub_nc_i32 v11, v11, v27 clamp
; GFX10-NEXT: v_sub_nc_i32 v12, v12, v28 clamp ; GFX10-NEXT: v_sub_nc_i32 v12, v12, v28 clamp
; GFX10-NEXT: v_sub_nc_i32 v13, v13, v29 clamp ; GFX10-NEXT: v_sub_nc_i32 v13, v13, v29 clamp
; GFX10-NEXT: v_sub_nc_i32 v14, v14, v30 clamp ; GFX10-NEXT: v_sub_nc_i32 v14, v14, v30 clamp
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_sub_nc_i32 v15, v15, v31 clamp ; GFX10-NEXT: v_sub_nc_i32 v15, v15, v16 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_ssubsat_v16i32: ; GFX11-LABEL: v_ssubsat_v16i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_sub_nc_i32 v0, v0, v16 clamp ; GFX11-NEXT: v_sub_nc_i32 v0, v0, v16 clamp
; GFX11-NEXT: scratch_load_b32 v16, off, s32
; GFX11-NEXT: v_sub_nc_i32 v1, v1, v17 clamp ; GFX11-NEXT: v_sub_nc_i32 v1, v1, v17 clamp
; GFX11-NEXT: v_sub_nc_i32 v2, v2, v18 clamp ; GFX11-NEXT: v_sub_nc_i32 v2, v2, v18 clamp
; GFX11-NEXT: v_sub_nc_i32 v3, v3, v19 clamp ; GFX11-NEXT: v_sub_nc_i32 v3, v3, v19 clamp
; GFX11-NEXT: v_sub_nc_i32 v4, v4, v20 clamp ; GFX11-NEXT: v_sub_nc_i32 v4, v4, v20 clamp
; GFX11-NEXT: v_sub_nc_i32 v5, v5, v21 clamp ; GFX11-NEXT: v_sub_nc_i32 v5, v5, v21 clamp
; GFX11-NEXT: v_sub_nc_i32 v6, v6, v22 clamp ; GFX11-NEXT: v_sub_nc_i32 v6, v6, v22 clamp
; GFX11-NEXT: v_sub_nc_i32 v7, v7, v23 clamp ; GFX11-NEXT: v_sub_nc_i32 v7, v7, v23 clamp
; GFX11-NEXT: v_sub_nc_i32 v8, v8, v24 clamp ; GFX11-NEXT: v_sub_nc_i32 v8, v8, v24 clamp
; GFX11-NEXT: v_sub_nc_i32 v9, v9, v25 clamp ; GFX11-NEXT: v_sub_nc_i32 v9, v9, v25 clamp
; GFX11-NEXT: v_sub_nc_i32 v10, v10, v26 clamp ; GFX11-NEXT: v_sub_nc_i32 v10, v10, v26 clamp
; GFX11-NEXT: v_sub_nc_i32 v11, v11, v27 clamp ; GFX11-NEXT: v_sub_nc_i32 v11, v11, v27 clamp
; GFX11-NEXT: v_sub_nc_i32 v12, v12, v28 clamp ; GFX11-NEXT: v_sub_nc_i32 v12, v12, v28 clamp
; GFX11-NEXT: v_sub_nc_i32 v13, v13, v29 clamp ; GFX11-NEXT: v_sub_nc_i32 v13, v13, v29 clamp
; GFX11-NEXT: v_sub_nc_i32 v14, v14, v30 clamp ; GFX11-NEXT: v_sub_nc_i32 v14, v14, v30 clamp
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_sub_nc_i32 v15, v15, v31 clamp ; GFX11-NEXT: v_sub_nc_i32 v15, v15, v16 clamp
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define amdgpu_ps <16 x i32> @s_ssubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) { define amdgpu_ps <16 x i32> @s_ssubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v16i32: ; GFX6-LABEL: s_ssubsat_v16i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
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; GFX9-NEXT: v_readfirstlane_b32 s10, v10 ; GFX9-NEXT: v_readfirstlane_b32 s10, v10
; GFX9-NEXT: v_readfirstlane_b32 s11, v11 ; GFX9-NEXT: v_readfirstlane_b32 s11, v11
; GFX9-NEXT: v_readfirstlane_b32 s12, v12 ; GFX9-NEXT: v_readfirstlane_b32 s12, v12
; GFX9-NEXT: v_readfirstlane_b32 s13, v13 ; GFX9-NEXT: v_readfirstlane_b32 s13, v13
; GFX9-NEXT: v_readfirstlane_b32 s14, v14 ; GFX9-NEXT: v_readfirstlane_b32 s14, v14
; GFX9-NEXT: v_readfirstlane_b32 s15, v15 ; GFX9-NEXT: v_readfirstlane_b32 s15, v15
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: s_ssubsat_v16i32: ; GFX10-LABEL: s_ssubsat_v16i32:
; GFX10PLUS: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s16 clamp ; GFX10-NEXT: v_sub_nc_i32 v0, s0, s16 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v1, s1, s17 clamp ; GFX10-NEXT: v_sub_nc_i32 v1, s1, s17 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v2, s2, s18 clamp ; GFX10-NEXT: v_sub_nc_i32 v2, s2, s18 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v3, s3, s19 clamp ; GFX10-NEXT: v_sub_nc_i32 v3, s3, s19 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v4, s4, s20 clamp ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10PLUS-NEXT: v_sub_nc_i32 v5, s5, s21 clamp ; GFX10-NEXT: v_sub_nc_i32 v0, s4, s20 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v6, s6, s22 clamp ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10PLUS-NEXT: v_sub_nc_i32 v7, s7, s23 clamp ; GFX10-NEXT: v_sub_nc_i32 v1, s5, s21 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v8, s8, s24 clamp ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10PLUS-NEXT: v_sub_nc_i32 v9, s9, s25 clamp ; GFX10-NEXT: v_sub_nc_i32 v2, s6, s22 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v10, s10, s26 clamp ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10PLUS-NEXT: v_sub_nc_i32 v11, s11, s27 clamp ; GFX10-NEXT: v_sub_nc_i32 v3, s7, s23 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v12, s12, s28 clamp ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10PLUS-NEXT: v_sub_nc_i32 v13, s13, s29 clamp ; GFX10-NEXT: v_sub_nc_i32 v0, s8, s24 clamp
; GFX10PLUS-NEXT: v_sub_nc_i32 v14, s14, s30 clamp ; GFX10-NEXT: v_readfirstlane_b32 s5, v1
; GFX10PLUS-NEXT: v_sub_nc_i32 v15, s15, s31 clamp ; GFX10-NEXT: v_sub_nc_i32 v1, s9, s25 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s6, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_sub_nc_i32 v2, s10, s26 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s7, v3
; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_sub_nc_i32 v3, s11, s27 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s8, v0
; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5 ; GFX10-NEXT: v_sub_nc_i32 v0, s12, s28 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6 ; GFX10-NEXT: v_readfirstlane_b32 s9, v1
; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7 ; GFX10-NEXT: v_sub_nc_i32 v1, s13, s29 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v8 ; GFX10-NEXT: v_readfirstlane_b32 s10, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v9 ; GFX10-NEXT: v_sub_nc_i32 v2, s14, s30 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s10, v10 ; GFX10-NEXT: v_readfirstlane_b32 s11, v3
; GFX10PLUS-NEXT: v_readfirstlane_b32 s11, v11 ; GFX10-NEXT: v_sub_nc_i32 v3, s15, s31 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v12 ; GFX10-NEXT: v_readfirstlane_b32 s12, v0
; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v13 ; GFX10-NEXT: v_readfirstlane_b32 s13, v1
; GFX10PLUS-NEXT: v_readfirstlane_b32 s14, v14 ; GFX10-NEXT: v_readfirstlane_b32 s14, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s15, v15 ; GFX10-NEXT: v_readfirstlane_b32 s15, v3
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_ssubsat_v16i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_sub_nc_i32 v0, s0, s16 clamp
; GFX11-NEXT: v_sub_nc_i32 v1, s1, s17 clamp
; GFX11-NEXT: v_sub_nc_i32 v2, s2, s18 clamp
; GFX11-NEXT: v_sub_nc_i32 v3, s3, s19 clamp
; GFX11-NEXT: v_sub_nc_i32 v4, s4, s20 clamp
; GFX11-NEXT: v_sub_nc_i32 v5, s5, s21 clamp
; GFX11-NEXT: v_sub_nc_i32 v6, s6, s22 clamp
; GFX11-NEXT: v_sub_nc_i32 v7, s7, s23 clamp
; GFX11-NEXT: v_sub_nc_i32 v8, s8, s24 clamp
; GFX11-NEXT: v_sub_nc_i32 v9, s9, s25 clamp
; GFX11-NEXT: v_sub_nc_i32 v10, s10, s26 clamp
; GFX11-NEXT: v_sub_nc_i32 v11, s11, s27 clamp
; GFX11-NEXT: v_sub_nc_i32 v12, s12, s28 clamp
; GFX11-NEXT: v_sub_nc_i32 v13, s13, s29 clamp
; GFX11-NEXT: v_sub_nc_i32 v14, s14, s30 clamp
; GFX11-NEXT: v_sub_nc_i32 v15, s15, s31 clamp
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_readfirstlane_b32 s6, v6
; GFX11-NEXT: v_readfirstlane_b32 s7, v7
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9
; GFX11-NEXT: v_readfirstlane_b32 s10, v10
; GFX11-NEXT: v_readfirstlane_b32 s11, v11
; GFX11-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-NEXT: v_readfirstlane_b32 s13, v13
; GFX11-NEXT: v_readfirstlane_b32 s14, v14
; GFX11-NEXT: v_readfirstlane_b32 s15, v15
; GFX11-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) { define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) {
; GFX6-LABEL: v_ssubsat_i16: ; GFX6-LABEL: v_ssubsat_i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3]
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2 ; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3] ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[4:5], v[0:1] ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[4:5], v[0:1]
; GFX10-NEXT: v_add_co_u32 v1, s5, 0x80000000, v6 ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX10-NEXT: v_add_co_u32 v1, s5, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s4 ; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_ssubsat_i48: ; GFX11-LABEL: v_ssubsat_i48:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: ssubsat_i48_sv: ; GFX10-LABEL: ssubsat_i48_sv:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0 ; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0
; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[0:1]
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3] ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, 0, v[0:1] ; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], v[2:3]
; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v4 ; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: ssubsat_i48_sv: ; GFX11-LABEL: ssubsat_i48_sv:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
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; ;
; GFX10-LABEL: ssubsat_i48_vs: ; GFX10-LABEL: ssubsat_i48_vs:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0 ; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 0 ; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 0
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1] ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v4 ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: ssubsat_i48_vs: ; GFX11-LABEL: ssubsat_i48_vs:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
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; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_ssubsat_i64: ; GFX10-LABEL: v_ssubsat_i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2 ; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[2:3] ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[4:5], v[0:1]
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1] ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX10-NEXT: v_add_co_u32 v1, s5, 0x80000000, v6 ; GFX10-NEXT: v_add_co_u32 v1, s5, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_ssubsat_i64: ; GFX11-LABEL: v_ssubsat_i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2 ; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
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; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: ssubsat_i64_sv: ; GFX10-LABEL: ssubsat_i64_sv:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0 ; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0
; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[0:1]
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3] ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, 0, v[0:1] ; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], v[2:3]
; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v4 ; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: ssubsat_i64_sv: ; GFX11-LABEL: ssubsat_i64_sv:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0 ; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0
; GFX11-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo ; GFX11-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v3
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; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: ssubsat_i64_vs: ; GFX10-LABEL: ssubsat_i64_vs:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0 ; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 0 ; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 0
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1] ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v4 ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX10-NEXT: v_add_co_u32 v1, s1, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: ssubsat_i64_vs: ; GFX11-LABEL: ssubsat_i64_vs:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0 ; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
; GFX11-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo ; GFX11-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX11-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 0 ; GFX11-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 0
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; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_ssubsat_v2i64: ; GFX10-LABEL: v_ssubsat_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v0, v4 ; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v0, v4
; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v10, vcc_lo, v2, v6
; GFX10-NEXT: v_sub_co_ci_u32_e32 v11, vcc_lo, v3, v7, vcc_lo
; GFX10-NEXT: v_ashrrev_i32_e32 v12, 31, v9
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[4:5] ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[4:5]
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v11 ; GFX10-NEXT: v_sub_co_u32 v4, s5, v2, v6
; GFX10-NEXT: v_sub_co_ci_u32_e64 v5, s5, v3, v7, s5
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]
; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v9
; GFX10-NEXT: v_cmp_lt_i64_e64 s6, 0, v[6:7] ; GFX10-NEXT: v_cmp_lt_i64_e64 s6, 0, v[6:7]
; GFX10-NEXT: v_add_co_u32 v1, s5, 0x80000000, v12 ; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[4:5], v[2:3]
; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[10:11], v[2:3] ; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX10-NEXT: v_add_co_u32 v3, s7, 0x80000000, v4
; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v12, vcc_lo ; GFX10-NEXT: v_add_co_u32 v1, s4, 0x80000000, v0
; GFX10-NEXT: v_add_co_u32 v3, s4, 0x80000000, v2
; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
; GFX10-NEXT: s_xor_b32 vcc_lo, s6, s5 ; GFX10-NEXT: s_xor_b32 vcc_lo, s6, s5
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_ssubsat_v2i64: ; GFX11-LABEL: v_ssubsat_v2i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_sub_co_u32 v8, vcc_lo, v0, v4 ; GFX11-NEXT: v_sub_co_u32 v8, vcc_lo, v0, v4
; GFX11-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo ; GFX11-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo
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; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: ssubsat_i128_sv: ; GFX10-LABEL: ssubsat_i128_sv:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, s0, v0 ; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, s0, v0
; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, 0, v[0:1]
; GFX10-NEXT: v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1]
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3] ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_cmp_gt_u64_e64 s0, s[0:1], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; GFX10-NEXT: v_cmp_gt_i64_e64 s4, s[2:3], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v7 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX10-NEXT: v_cmp_eq_u64_e64 s0, s[2:3], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_add_co_u32 v3, s0, 0x80000000, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, v2, s0
; GFX10-NEXT: v_xor_b32_e32 v0, v0, v8 ; GFX10-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v7
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_add_co_u32 v3, s0, 0x80000000, v2
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: ssubsat_i128_sv: ; GFX11-LABEL: ssubsat_i128_sv:
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; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: ssubsat_i128_vs: ; GFX10-LABEL: ssubsat_i128_vs:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, s0 ; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1] ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[4:5], v[0:1]
; GFX10-NEXT: v_cmp_gt_u64_e64 s0, s[0:1], 0
; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0 ; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0
; GFX10-NEXT: s_cselect_b32 s4, 1, 0 ; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3] ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0 ; GFX10-NEXT: v_cmp_gt_u64_e64 s0, s[0:1], 0
; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[2:3], 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: s_and_b32 s3, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3] ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
; GFX10-NEXT: s_and_b32 s0, 1, s4
; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v3, s0, 0x80000000, v2 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v7
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: v_add_co_u32 v3, s0, 0x80000000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
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; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_ssubsat_v2i128: ; GFX10-LABEL: v_ssubsat_v2i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_sub_co_u32 v16, vcc_lo, v0, v8 ; GFX10-NEXT: v_sub_co_u32 v16, vcc_lo, v0, v8
; GFX10-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, 0, v[8:9]
; GFX10-NEXT: v_sub_co_ci_u32_e32 v19, vcc_lo, v3, v11, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v8, vcc_lo, v2, v10, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[0:1] ; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v3, v11, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[8:9]
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11] ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, 1, s4
; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v4, v12 ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[16:17], v[0:1]
; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo ; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[8:9], v[2:3]
; GFX10-NEXT: v_sub_co_ci_u32_e32 v20, vcc_lo, v6, v14, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v21, vcc_lo, v7, v15, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[4:5] ; GFX10-NEXT: v_cmp_eq_u64_e64 s4, v[8:9], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s5
; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v9
; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, v0, s4
; GFX10-NEXT: v_cndmask_b32_e32 v1, v19, v18, vcc_lo
; GFX10-NEXT: v_add_co_u32 v3, s4, 0x80000000, v2
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, 0, v[12:13]
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[20:21], v[6:7]
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[12:13] ; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v4, v12
; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v10, vcc_lo, v6, v14, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v11, vcc_lo, v7, v15, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[14:15] ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[14:15]
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s4
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[20:21], v[6:7] ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[8:9], v[4:5]
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v21 ; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[10:11], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15] ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v19 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
; GFX10-NEXT: v_add_co_u32 v7, s5, 0x80000000, v6 ; GFX10-NEXT: v_cmp_eq_u64_e64 s4, v[10:11], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s5
; GFX10-NEXT: v_add_co_u32 v4, s4, 0x80000000, v3 ; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v11
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, v4, s4
; GFX10-NEXT: v_xor_b32_e32 v1, v2, v1 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v12, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v3, vcc_lo ; GFX10-NEXT: v_add_co_u32 v7, s4, 0x80000000, v6
; GFX10-NEXT: v_cndmask_b32_e32 v2, v18, v3, vcc_lo ; GFX10-NEXT: v_xor_b32_e32 v4, v5, v4
; GFX10-NEXT: v_and_b32_e32 v5, 1, v1 ; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX10-NEXT: v_cndmask_b32_e32 v3, v19, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, v5 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v6, s4 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v6, s4 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v20, v6, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v21, v7, s4
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_ssubsat_v2i128: ; GFX11-LABEL: v_ssubsat_v2i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_sub_co_u32 v16, vcc_lo, v0, v8 ; GFX11-NEXT: v_sub_co_u32 v16, vcc_lo, v0, v8
; GFX11-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo ; GFX11-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo
; GFX11-NEXT: v_sub_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo ; GFX11-NEXT: v_sub_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo
; GFX11-NEXT: v_sub_co_ci_u32_e32 v19, vcc_lo, v3, v11, vcc_lo ; GFX11-NEXT: v_sub_co_ci_u32_e32 v19, vcc_lo, v3, v11, vcc_lo
; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[0:1] ; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[0:1]
; GFX11-NEXT: v_cmp_lt_u64_e64 s0, 0, v[8:9]
; GFX11-NEXT: v_sub_co_u32 v8, s1, v4, v12
; GFX11-NEXT: v_sub_co_ci_u32_e64 v9, s1, v5, v13, s1
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[2:3] ; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3] ; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[10:11]
; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[8:9]
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11]
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-NEXT: v_sub_co_u32 v8, vcc_lo, v4, v12
; GFX11-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo
; GFX11-NEXT: v_sub_co_ci_u32_e32 v20, vcc_lo, v6, v14, vcc_lo
; GFX11-NEXT: v_sub_co_ci_u32_e32 v21, vcc_lo, v7, v15, vcc_lo
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[4:5] ; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[4:5]
; GFX11-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX11-NEXT: v_cmp_eq_u64_e64 s0, 0, v[10:11]
; GFX11-NEXT: v_sub_co_ci_u32_e64 v10, s1, v6, v14, s1
; GFX11-NEXT: v_sub_co_ci_u32_e64 v11, s1, v7, v15, s1
; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, v2, s0
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[20:21], v[6:7] ; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[10:11], v[6:7]
; GFX11-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[12:13] ; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[12:13]
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[14:15] ; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[14:15]
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[20:21], v[6:7] ; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7]
; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v21 ; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v11
; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15] ; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v19 ; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v19
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-NEXT: v_add_co_u32 v7, null, 0x80000000, v6 ; GFX11-NEXT: v_add_co_u32 v7, null, 0x80000000, v6
; GFX11-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc_lo
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_add_co_u32 v4, null, 0x80000000, v3 ; GFX11-NEXT: v_add_co_u32 v4, null, 0x80000000, v3
; GFX11-NEXT: v_xor_b32_e32 v1, v2, v1 ; GFX11-NEXT: v_xor_b32_e32 v1, v2, v1
; GFX11-NEXT: v_cndmask_b32_e32 v0, v16, v3, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v0, v16, v3, vcc_lo
; GFX11-NEXT: v_dual_cndmask_b32 v2, v18, v3 :: v_dual_and_b32 v5, 1, v1 ; GFX11-NEXT: v_dual_cndmask_b32 v2, v18, v3 :: v_dual_and_b32 v5, 1, v1
; GFX11-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e32 v3, v19, v4, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v3, v19, v4, vcc_lo
; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, v5 ; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, v5
; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v6, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v6, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, v6, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, v6, s0
; GFX11-NEXT: v_cndmask_b32_e64 v6, v20, v6, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v6, v10, v6, s0
; GFX11-NEXT: v_cndmask_b32_e64 v7, v21, v7, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v7, v11, v7, s0
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs) %result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result ret <2 x i128> %result
} }
define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) { define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v2i128: ; GFX6-LABEL: s_ssubsat_v2i128:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
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; ;
; GFX10-LABEL: s_ssubsat_v2i128: ; GFX10-LABEL: s_ssubsat_v2i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_sub_u32 s16, s0, s8 ; GFX10-NEXT: s_sub_u32 s16, s0, s8
; GFX10-NEXT: s_subb_u32 s17, s1, s9 ; GFX10-NEXT: s_subb_u32 s17, s1, s9
; GFX10-NEXT: s_subb_u32 s18, s2, s10 ; GFX10-NEXT: s_subb_u32 s18, s2, s10
; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1] ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1]
; GFX10-NEXT: s_subb_u32 s19, s3, s11 ; GFX10-NEXT: s_subb_u32 s19, s3, s11
; GFX10-NEXT: v_cmp_gt_u64_e64 s1, s[8:9], 0
; GFX10-NEXT: s_cmp_eq_u64 s[18:19], s[2:3] ; GFX10-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
; GFX10-NEXT: s_cselect_b32 s20, 1, 0 ; GFX10-NEXT: s_cselect_b32 s20, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3] ; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3]
; GFX10-NEXT: v_cmp_gt_u64_e64 s2, s[8:9], 0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: s_and_b32 s0, 1, s20 ; GFX10-NEXT: s_and_b32 s0, 1, s20
; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0 ; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: s_cselect_b32 s1, 1, 0 ; GFX10-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2 ; GFX10-NEXT: s_ashr_i32 s2, s19, 31
; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[10:11], 0 ; GFX10-NEXT: s_and_b32 s0, 1, s0
; GFX10-NEXT: s_and_b32 s1, 1, s1
; GFX10-NEXT: s_ashr_i32 s0, s19, 31
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
; GFX10-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[10:11], 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1
; GFX10-NEXT: s_add_u32 s1, s2, 0x80000000
; GFX10-NEXT: s_sub_u32 s8, s4, s12 ; GFX10-NEXT: s_sub_u32 s8, s4, s12
; GFX10-NEXT: s_subb_u32 s9, s5, s13 ; GFX10-NEXT: s_subb_u32 s9, s5, s13
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[8:9], s[4:5]
; GFX10-NEXT: s_subb_u32 s10, s6, s14 ; GFX10-NEXT: s_subb_u32 s10, s6, s14
; GFX10-NEXT: v_cmp_lt_u64_e64 s3, s[8:9], s[4:5]
; GFX10-NEXT: s_subb_u32 s11, s7, s15 ; GFX10-NEXT: s_subb_u32 s11, s7, s15
; GFX10-NEXT: s_mov_b32 s3, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX10-NEXT: s_cmp_eq_u64 s[10:11], s[6:7] ; GFX10-NEXT: s_cmp_eq_u64 s[10:11], s[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4 ; GFX10-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[10:11], s[6:7] ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s3
; GFX10-NEXT: v_cmp_gt_u64_e64 s6, s[12:13], 0 ; GFX10-NEXT: v_cmp_lt_i64_e64 s3, s[10:11], s[6:7]
; GFX10-NEXT: s_and_b32 s0, 1, s0
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: v_mov_b32_e32 v1, s16 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: s_cselect_b32 s16, 1, 0
; GFX10-NEXT: v_mov_b32_e32 v2, s17
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
; GFX10-NEXT: s_and_b32 s4, 1, s16
; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0 ; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s3
; GFX10-NEXT: v_cmp_gt_i64_e64 s6, s[14:15], 0 ; GFX10-NEXT: v_cmp_gt_u64_e64 s3, s[12:13], 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 ; GFX10-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-NEXT: s_cselect_b32 s5, 1, 0
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: s_and_b32 s5, 1, s5 ; GFX10-NEXT: s_and_b32 s0, 1, s0
; GFX10-NEXT: s_mov_b32 s2, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s3
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5 ; GFX10-NEXT: v_cmp_gt_i64_e64 s3, s[14:15], 0
; GFX10-NEXT: v_mov_b32_e32 v7, s11 ; GFX10-NEXT: s_ashr_i32 s4, s11, 31
; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo ; GFX10-NEXT: s_add_u32 s5, s4, 0x80000000
; GFX10-NEXT: s_mov_b32 s7, s4
; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s3
; GFX10-NEXT: s_mov_b32 s3, s2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v3, s16
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s18 ; GFX10-NEXT: v_xor_b32_e32 v1, v2, v1
; GFX10-NEXT: v_mov_b32_e32 v5, s19 ; GFX10-NEXT: v_mov_b32_e32 v2, s18
; GFX10-NEXT: v_mov_b32_e32 v6, s9 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, s2, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v3, v4, v3 ; GFX10-NEXT: v_mov_b32_e32 v3, s17
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo ; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s1, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v0, s19
; GFX10-NEXT: v_and_b32_e32 v3, 1, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v5, s8 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: s_ashr_i32 s0, s11, 31 ; GFX10-NEXT: v_mov_b32_e32 v2, s9
; GFX10-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s1, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_readfirstlane_b32 s1, v3
; GFX10-NEXT: v_mov_b32_e32 v3, s10 ; GFX10-NEXT: v_mov_b32_e32 v3, s8
; GFX10-NEXT: s_mov_b32 s3, s0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
; GFX10-NEXT: s_mov_b32 s2, s0 ; GFX10-NEXT: v_mov_b32_e32 v1, s10
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s0, vcc_lo ; GFX10-NEXT: v_readfirstlane_b32 s3, v0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s3, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v0, s11
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s0, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s1, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s5, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s2, v0 ; GFX10-NEXT: v_readfirstlane_b32 s4, v3
; GFX10-NEXT: v_readfirstlane_b32 s3, v4 ; GFX10-NEXT: v_readfirstlane_b32 s5, v2
; GFX10-NEXT: v_readfirstlane_b32 s4, v5 ; GFX10-NEXT: v_readfirstlane_b32 s6, v1
; GFX10-NEXT: v_readfirstlane_b32 s5, v6 ; GFX10-NEXT: v_readfirstlane_b32 s7, v0
; GFX10-NEXT: v_readfirstlane_b32 s6, v3
; GFX10-NEXT: v_readfirstlane_b32 s7, v7
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_ssubsat_v2i128: ; GFX11-LABEL: s_ssubsat_v2i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_sub_u32 s16, s0, s8 ; GFX11-NEXT: s_sub_u32 s16, s0, s8
; GFX11-NEXT: s_subb_u32 s17, s1, s9 ; GFX11-NEXT: s_subb_u32 s17, s1, s9
; GFX11-NEXT: s_subb_u32 s18, s2, s10 ; GFX11-NEXT: s_subb_u32 s18, s2, s10
; GFX11-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1] ; GFX11-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1]
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llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll

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; ;
; GFX10-LABEL: store_lds_v4i32_align1: ; GFX10-LABEL: store_lds_v4i32_align1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_bfe_u32 s0, 8, 0x100000 ; GFX10-NEXT: s_bfe_u32 s0, 8, 0x100000
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_bfe_u32 s3, s4, 0x100000
; GFX10-NEXT: s_lshr_b32 s1, s4, 16
; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: s_lshr_b32 s2, s5, 16
; GFX10-NEXT: s_bfe_u32 s4, s5, 0x100000
; GFX10-NEXT: v_mov_b32_e32 v2, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s5
; GFX10-NEXT: s_bfe_u32 s3, s4, 0x100000
; GFX10-NEXT: s_lshr_b32 s1, s4, 16
; GFX10-NEXT: s_lshr_b32 s2, s5, 16
; GFX10-NEXT: s_lshr_b32 s3, s3, s0 ; GFX10-NEXT: s_lshr_b32 s3, s3, s0
; GFX10-NEXT: s_lshr_b32 s5, s6, 16 ; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: s_bfe_u32 s8, s6, 0x100000
; GFX10-NEXT: v_mov_b32_e32 v3, s6
; GFX10-NEXT: s_lshr_b32 s6, s1, s0
; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: s_lshr_b32 s1, s4, s0
; GFX10-NEXT: s_lshr_b32 s4, s2, s0
; GFX10-NEXT: v_mov_b32_e32 v6, s3
; GFX10-NEXT: v_mov_b32_e32 v7, s6
; GFX10-NEXT: v_mov_b32_e32 v5, s2
; GFX10-NEXT: s_lshr_b32 s2, s8, s0
; GFX10-NEXT: v_mov_b32_e32 v8, s1
; GFX10-NEXT: v_mov_b32_e32 v9, s4
; GFX10-NEXT: ds_write_b8 v1, v0 ; GFX10-NEXT: ds_write_b8 v1, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: s_bfe_u32 s4, s5, 0x100000
; GFX10-NEXT: ds_write_b8 v1, v2 offset:4 ; GFX10-NEXT: ds_write_b8 v1, v2 offset:4
; GFX10-NEXT: ds_write_b8 v1, v4 offset:2 ; GFX10-NEXT: v_mov_b32_e32 v2, s3
; GFX10-NEXT: ds_write_b8 v1, v6 offset:1 ; GFX10-NEXT: s_lshr_b32 s8, s1, s0
; GFX10-NEXT: ds_write_b8 v1, v7 offset:3 ; GFX10-NEXT: s_lshr_b32 s1, s4, s0
; GFX10-NEXT: ds_write_b8 v1, v8 offset:5 ; GFX10-NEXT: s_lshr_b32 s4, s2, s0
; GFX10-NEXT: ds_write_b8 v1, v5 offset:6 ; GFX10-NEXT: ds_write_b8 v1, v3 offset:2
; GFX10-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-NEXT: v_mov_b32_e32 v3, s8
; GFX10-NEXT: v_mov_b32_e32 v10, s2 ; GFX10-NEXT: ds_write_b8 v1, v0 offset:6
; GFX10-NEXT: v_mov_b32_e32 v0, s1
; GFX10-NEXT: s_bfe_u32 s5, s6, 0x100000
; GFX10-NEXT: ds_write_b8 v1, v2 offset:1
; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: s_lshr_b32 s1, s5, s0 ; GFX10-NEXT: s_lshr_b32 s1, s5, s0
; GFX10-NEXT: ds_write_b8 v1, v9 offset:7 ; GFX10-NEXT: s_lshr_b32 s2, s6, 16
; GFX10-NEXT: ds_write_b8 v1, v3 offset:8 ; GFX10-NEXT: ds_write_b8 v1, v3 offset:3
; GFX10-NEXT: ds_write_b8 v1, v10 offset:9 ; GFX10-NEXT: v_mov_b32_e32 v3, s6
; GFX10-NEXT: ds_write_b8 v1, v0 offset:10 ; GFX10-NEXT: ds_write_b8 v1, v0 offset:5
; GFX10-NEXT: ds_write_b8 v1, v2 offset:7
; GFX10-NEXT: v_mov_b32_e32 v0, s1 ; GFX10-NEXT: v_mov_b32_e32 v0, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: s_lshr_b32 s1, s2, s0
; GFX10-NEXT: ds_write_b8 v1, v3 offset:8
; GFX10-NEXT: ds_write_b8 v1, v0 offset:9
; GFX10-NEXT: ds_write_b8 v1, v2 offset:10
; GFX10-NEXT: v_mov_b32_e32 v0, s7
; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: s_bfe_u32 s1, s7, 0x100000 ; GFX10-NEXT: s_bfe_u32 s1, s7, 0x100000
; GFX10-NEXT: s_lshr_b32 s2, s7, 16 ; GFX10-NEXT: s_lshr_b32 s2, s7, 16
; GFX10-NEXT: s_lshr_b32 s1, s1, s0 ; GFX10-NEXT: s_lshr_b32 s1, s1, s0
; GFX10-NEXT: v_mov_b32_e32 v2, s7 ; GFX10-NEXT: ds_write_b8 v1, v0 offset:12
; GFX10-NEXT: v_mov_b32_e32 v3, s1 ; GFX10-NEXT: v_mov_b32_e32 v0, s1
; GFX10-NEXT: s_lshr_b32 s0, s2, s0 ; GFX10-NEXT: s_lshr_b32 s0, s2, s0
; GFX10-NEXT: v_mov_b32_e32 v4, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_mov_b32_e32 v5, s0 ; GFX10-NEXT: ds_write_b8 v1, v3 offset:11
; GFX10-NEXT: ds_write_b8 v1, v0 offset:11 ; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: ds_write_b8 v1, v2 offset:12 ; GFX10-NEXT: ds_write_b8 v1, v0 offset:13
; GFX10-NEXT: ds_write_b8 v1, v3 offset:13 ; GFX10-NEXT: ds_write_b8 v1, v2 offset:14
; GFX10-NEXT: ds_write_b8 v1, v4 offset:14 ; GFX10-NEXT: ds_write_b8 v1, v3 offset:15
; GFX10-NEXT: ds_write_b8 v1, v5 offset:15
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: store_lds_v4i32_align1: ; GFX11-LABEL: store_lds_v4i32_align1:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x10 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x10
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
; GFX11-NEXT: s_bfe_u32 s1, 8, 0x100000 ; GFX11-NEXT: s_bfe_u32 s1, 8, 0x100000
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; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: v_mov_b32_e32 v2, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s5
; GFX10-NEXT: s_lshr_b32 s0, s4, 16 ; GFX10-NEXT: s_lshr_b32 s0, s4, 16
; GFX10-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-NEXT: v_mov_b32_e32 v3, s6
; GFX10-NEXT: s_lshr_b32 s1, s5, 16 ; GFX10-NEXT: s_lshr_b32 s1, s5, 16
; GFX10-NEXT: s_lshr_b32 s2, s6, 16
; GFX10-NEXT: s_lshr_b32 s3, s7, 16
; GFX10-NEXT: v_mov_b32_e32 v4, s7
; GFX10-NEXT: v_mov_b32_e32 v5, s0
; GFX10-NEXT: v_mov_b32_e32 v6, s1
; GFX10-NEXT: v_mov_b32_e32 v7, s2
; GFX10-NEXT: v_mov_b32_e32 v8, s3
; GFX10-NEXT: ds_write_b16 v1, v0 ; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s7
; GFX10-NEXT: ds_write_b16 v1, v2 offset:4 ; GFX10-NEXT: ds_write_b16 v1, v2 offset:4
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_lshr_b32 s2, s6, 16
; GFX10-NEXT: s_lshr_b32 s3, s7, 16
; GFX10-NEXT: ds_write_b16 v1, v3 offset:8 ; GFX10-NEXT: ds_write_b16 v1, v3 offset:8
; GFX10-NEXT: ds_write_b16 v1, v4 offset:12 ; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: ds_write_b16 v1, v5 offset:2 ; GFX10-NEXT: ds_write_b16 v1, v0 offset:12
; GFX10-NEXT: ds_write_b16 v1, v6 offset:6 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: ds_write_b16 v1, v7 offset:10 ; GFX10-NEXT: ds_write_b16 v1, v2 offset:2
; GFX10-NEXT: ds_write_b16 v1, v8 offset:14 ; GFX10-NEXT: v_mov_b32_e32 v2, s3
; GFX10-NEXT: ds_write_b16 v1, v3 offset:6
; GFX10-NEXT: ds_write_b16 v1, v0 offset:10
; GFX10-NEXT: ds_write_b16 v1, v2 offset:14
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: store_lds_v4i32_align2: ; GFX11-LABEL: store_lds_v4i32_align2:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x10 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x10
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: v_mov_b32_e32 v2, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s5
; GFX10-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-NEXT: v_mov_b32_e32 v3, s6
; GFX10-NEXT: v_mov_b32_e32 v4, s7
; GFX10-NEXT: ds_write2_b32 v1, v0, v2 offset1:1 ; GFX10-NEXT: ds_write2_b32 v1, v0, v2 offset1:1
; GFX10-NEXT: ds_write2_b32 v1, v3, v4 offset0:2 offset1:3 ; GFX10-NEXT: v_mov_b32_e32 v0, s7
; GFX10-NEXT: ds_write2_b32 v1, v3, v0 offset0:2 offset1:3
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: store_lds_v4i32_align4: ; GFX11-LABEL: store_lds_v4i32_align4:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x10 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x10
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
Show All 40 Lines
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: v_mov_b32_e32 v2, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s5
; GFX10-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-NEXT: v_mov_b32_e32 v3, s6
; GFX10-NEXT: v_mov_b32_e32 v4, s7
; GFX10-NEXT: ds_write2_b32 v1, v0, v2 offset1:1 ; GFX10-NEXT: ds_write2_b32 v1, v0, v2 offset1:1
; GFX10-NEXT: ds_write2_b32 v1, v3, v4 offset0:2 offset1:3 ; GFX10-NEXT: v_mov_b32_e32 v0, s7
; GFX10-NEXT: ds_write2_b32 v1, v3, v0 offset0:2 offset1:3
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: store_lds_v4i32_align8: ; GFX11-LABEL: store_lds_v4i32_align8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x10 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x10
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll

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; GFX10-LABEL: store_lds_v3i32_align1: ; GFX10-LABEL: store_lds_v3i32_align1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_bfe_u32 s0, 8, 0x100000 ; GFX10-NEXT: s_bfe_u32 s0, 8, 0x100000
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_lshr_b32 s1, s4, 16 ; GFX10-NEXT: s_lshr_b32 s1, s4, 16
; GFX10-NEXT: s_bfe_u32 s3, s4, 0x100000
; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: s_lshr_b32 s2, s5, 16
; GFX10-NEXT: s_bfe_u32 s4, s5, 0x100000
; GFX10-NEXT: v_mov_b32_e32 v2, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s5
; GFX10-NEXT: s_lshr_b32 s5, s6, 16 ; GFX10-NEXT: s_bfe_u32 s3, s4, 0x100000
; GFX10-NEXT: s_bfe_u32 s7, s6, 0x100000 ; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-NEXT: s_lshr_b32 s2, s5, 16
; GFX10-NEXT: s_lshr_b32 s6, s1, s0
; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: s_lshr_b32 s1, s4, s0
; GFX10-NEXT: s_lshr_b32 s4, s2, s0
; GFX10-NEXT: s_lshr_b32 s3, s3, s0 ; GFX10-NEXT: s_lshr_b32 s3, s3, s0
; GFX10-NEXT: v_mov_b32_e32 v5, s2 ; GFX10-NEXT: s_lshr_b32 s7, s1, s0
; GFX10-NEXT: s_lshr_b32 s2, s7, s0
; GFX10-NEXT: v_mov_b32_e32 v9, s4
; GFX10-NEXT: v_mov_b32_e32 v6, s3
; GFX10-NEXT: v_mov_b32_e32 v7, s6
; GFX10-NEXT: v_mov_b32_e32 v8, s1
; GFX10-NEXT: ds_write_b8 v1, v0 ; GFX10-NEXT: ds_write_b8 v1, v0
; GFX10-NEXT: ds_write_b8 v1, v2 offset:4
; GFX10-NEXT: ds_write_b8 v1, v4 offset:2
; GFX10-NEXT: ds_write_b8 v1, v5 offset:6
; GFX10-NEXT: ds_write_b8 v1, v6 offset:1
; GFX10-NEXT: ds_write_b8 v1, v7 offset:3
; GFX10-NEXT: ds_write_b8 v1, v8 offset:5
; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: s_bfe_u32 s4, s5, 0x100000
; GFX10-NEXT: ds_write_b8 v1, v2 offset:4
; GFX10-NEXT: v_mov_b32_e32 v2, s3
; GFX10-NEXT: ds_write_b8 v1, v3 offset:2
; GFX10-NEXT: v_mov_b32_e32 v3, s7
; GFX10-NEXT: s_lshr_b32 s1, s4, s0
; GFX10-NEXT: s_lshr_b32 s4, s2, s0
; GFX10-NEXT: ds_write_b8 v1, v0 offset:6
; GFX10-NEXT: v_mov_b32_e32 v0, s1
; GFX10-NEXT: ds_write_b8 v1, v2 offset:1
; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: s_bfe_u32 s1, s6, 0x100000
; GFX10-NEXT: ds_write_b8 v1, v3 offset:3
; GFX10-NEXT: v_mov_b32_e32 v3, s6
; GFX10-NEXT: s_lshr_b32 s5, s6, 16
; GFX10-NEXT: s_lshr_b32 s1, s1, s0
; GFX10-NEXT: ds_write_b8 v1, v0 offset:5
; GFX10-NEXT: ds_write_b8 v1, v2 offset:7
; GFX10-NEXT: v_mov_b32_e32 v0, s1
; GFX10-NEXT: s_lshr_b32 s0, s5, s0 ; GFX10-NEXT: s_lshr_b32 s0, s5, s0
; GFX10-NEXT: v_mov_b32_e32 v2, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s5
; GFX10-NEXT: v_mov_b32_e32 v4, s0
; GFX10-NEXT: ds_write_b8 v1, v9 offset:7
; GFX10-NEXT: ds_write_b8 v1, v3 offset:8 ; GFX10-NEXT: ds_write_b8 v1, v3 offset:8
; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: ds_write_b8 v1, v0 offset:9 ; GFX10-NEXT: ds_write_b8 v1, v0 offset:9
; GFX10-NEXT: ds_write_b8 v1, v2 offset:10 ; GFX10-NEXT: ds_write_b8 v1, v2 offset:10
; GFX10-NEXT: ds_write_b8 v1, v4 offset:11 ; GFX10-NEXT: ds_write_b8 v1, v3 offset:11
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: store_lds_v3i32_align1: ; GFX11-LABEL: store_lds_v3i32_align1:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x10 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x10
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
; GFX11-NEXT: s_bfe_u32 s1, 8, 0x100000 ; GFX11-NEXT: s_bfe_u32 s1, 8, 0x100000
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; GFX10-LABEL: store_lds_v3i32_align2: ; GFX10-LABEL: store_lds_v3i32_align2:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: s_lshr_b32 s0, s4, 16
; GFX10-NEXT: v_mov_b32_e32 v2, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s5
; GFX10-NEXT: s_lshr_b32 s1, s5, 16
; GFX10-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-NEXT: v_mov_b32_e32 v3, s6
; GFX10-NEXT: s_lshr_b32 s0, s4, 16
; GFX10-NEXT: s_lshr_b32 s1, s5, 16
; GFX10-NEXT: s_lshr_b32 s2, s6, 16 ; GFX10-NEXT: s_lshr_b32 s2, s6, 16
; GFX10-NEXT: v_mov_b32_e32 v4, s0
; GFX10-NEXT: v_mov_b32_e32 v5, s1
; GFX10-NEXT: v_mov_b32_e32 v6, s2
; GFX10-NEXT: ds_write_b16 v1, v0 ; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: ds_write_b16 v1, v2 offset:4 ; GFX10-NEXT: ds_write_b16 v1, v2 offset:4
; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: ds_write_b16 v1, v3 offset:8 ; GFX10-NEXT: ds_write_b16 v1, v3 offset:8
; GFX10-NEXT: ds_write_b16 v1, v4 offset:2 ; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: ds_write_b16 v1, v5 offset:6 ; GFX10-NEXT: ds_write_b16 v1, v0 offset:2
; GFX10-NEXT: ds_write_b16 v1, v6 offset:10 ; GFX10-NEXT: ds_write_b16 v1, v2 offset:6
; GFX10-NEXT: ds_write_b16 v1, v3 offset:10
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: store_lds_v3i32_align2: ; GFX11-LABEL: store_lds_v3i32_align2:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x10 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x10
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

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; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_uaddsat_v4i8: ; GFX10-LABEL: v_uaddsat_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 24, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 24, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 8, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 24, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 24, v1
; GFX10-NEXT: v_perm_b32 v2, v2, v0, 0x5040100 ; GFX10-NEXT: v_perm_b32 v2, v2, v0, 0x5040100
; GFX10-NEXT: v_alignbit_b32 v0, v3, v0, 16 ; GFX10-NEXT: v_alignbit_b32 v0, v3, v0, 16
; GFX10-NEXT: v_perm_b32 v3, v4, v1, 0x5040100 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX10-NEXT: v_alignbit_b32 v1, v5, v1, 16
; GFX10-NEXT: v_mov_b32_e32 v4, 24
; GFX10-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_perm_b32 v3, v3, v1, 0x5040100
; GFX10-NEXT: v_alignbit_b32 v1, v4, v1, 16
; GFX10-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_add_u16 v2, v2, v3 clamp ; GFX10-NEXT: v_pk_add_u16 v2, v2, v3 clamp
; GFX10-NEXT: v_mov_b32_e32 v3, 8
; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 clamp ; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 clamp
; GFX10-NEXT: v_mov_b32_e32 v1, 8 ; GFX10-NEXT: v_pk_lshrrev_b16 v1, 8, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshrrev_b16 v2, 8, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v0 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v0
; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; GFX10-NEXT: v_and_or_b32 v1, v1, 0xff, v2
; GFX10-NEXT: v_and_or_b32 v1, v2, 0xff, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, 24
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_or3_b32 v0, v1, v3, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_uaddsat_v4i8: ; GFX11-LABEL: v_uaddsat_v4i8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
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; GFX9-NEXT: v_add_u32_e64 v4, s4, v4 clamp ; GFX9-NEXT: v_add_u32_e64 v4, s4, v4 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v4 ; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: s_uaddsat_v5i32: ; GFX10-LABEL: s_uaddsat_v5i32:
; GFX10PLUS: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, s0, s5 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s5 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v1, s1, s6 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s6 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v2, s2, s7 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s7 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v3, s3, s8 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v3, s3, s8 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v4, s4, s9 clamp ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_add_nc_u32_e64 v0, s4, s9 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_uaddsat_v5i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_add_nc_u32_e64 v0, s0, s5 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v1, s1, s6 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v2, s2, s7 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v3, s3, s8 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v4, s4, s9 clamp
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) %result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result ret <5 x i32> %result
} }
define <16 x i32> @v_uaddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) { define <16 x i32> @v_uaddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX6-LABEL: v_uaddsat_v16i32: ; GFX6-LABEL: v_uaddsat_v16i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e64 v15, v15, v16 clamp ; GFX9-NEXT: v_add_u32_e64 v15, v15, v16 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_uaddsat_v16i32: ; GFX10-LABEL: v_uaddsat_v16i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v16 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v16 clamp
; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v17 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v17 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v18 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v18 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v19 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v19 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v4, v4, v20 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v4, v4, v20 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v5, v5, v21 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v5, v5, v21 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v6, v6, v22 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v6, v6, v22 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v7, v7, v23 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v7, v7, v23 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v8, v8, v24 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v8, v8, v24 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v9, v9, v25 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v9, v9, v25 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v10, v10, v26 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v10, v10, v26 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v11, v11, v27 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v11, v11, v27 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v12, v12, v28 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v12, v12, v28 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v13, v13, v29 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v13, v13, v29 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v14, v14, v30 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v14, v14, v30 clamp
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_nc_u32_e64 v15, v15, v31 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v15, v15, v16 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_uaddsat_v16i32: ; GFX11-LABEL: v_uaddsat_v16i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_add_nc_u32_e64 v0, v0, v16 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v0, v0, v16 clamp
; GFX11-NEXT: scratch_load_b32 v16, off, s32
; GFX11-NEXT: v_add_nc_u32_e64 v1, v1, v17 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v1, v1, v17 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v2, v2, v18 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v2, v2, v18 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v3, v3, v19 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v3, v3, v19 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v4, v4, v20 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v4, v4, v20 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v5, v5, v21 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v5, v5, v21 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v6, v6, v22 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v6, v6, v22 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v7, v7, v23 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v7, v7, v23 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v8, v8, v24 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v8, v8, v24 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v9, v9, v25 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v9, v9, v25 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v10, v10, v26 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v10, v10, v26 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v11, v11, v27 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v11, v11, v27 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v12, v12, v28 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v12, v12, v28 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v13, v13, v29 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v13, v13, v29 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v14, v14, v30 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v14, v14, v30 clamp
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_add_nc_u32_e64 v15, v15, v31 clamp ; GFX11-NEXT: v_add_nc_u32_e64 v15, v15, v16 clamp
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define amdgpu_ps <16 x i32> @s_uaddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) { define amdgpu_ps <16 x i32> @s_uaddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v16i32: ; GFX6-LABEL: s_uaddsat_v16i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
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; GFX9-NEXT: v_readfirstlane_b32 s10, v10 ; GFX9-NEXT: v_readfirstlane_b32 s10, v10
; GFX9-NEXT: v_readfirstlane_b32 s11, v11 ; GFX9-NEXT: v_readfirstlane_b32 s11, v11
; GFX9-NEXT: v_readfirstlane_b32 s12, v12 ; GFX9-NEXT: v_readfirstlane_b32 s12, v12
; GFX9-NEXT: v_readfirstlane_b32 s13, v13 ; GFX9-NEXT: v_readfirstlane_b32 s13, v13
; GFX9-NEXT: v_readfirstlane_b32 s14, v14 ; GFX9-NEXT: v_readfirstlane_b32 s14, v14
; GFX9-NEXT: v_readfirstlane_b32 s15, v15 ; GFX9-NEXT: v_readfirstlane_b32 s15, v15
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: s_uaddsat_v16i32: ; GFX10-LABEL: s_uaddsat_v16i32:
; GFX10PLUS: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, s0, s16 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s16 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v1, s1, s17 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s17 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v2, s2, s18 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s18 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v3, s3, s19 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v3, s3, s19 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v4, s4, s20 clamp ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v5, s5, s21 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v0, s4, s20 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v6, s6, s22 clamp ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v7, s7, s23 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v1, s5, s21 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v8, s8, s24 clamp ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v9, s9, s25 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v2, s6, s22 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v10, s10, s26 clamp ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v11, s11, s27 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v3, s7, s23 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v12, s12, s28 clamp ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v13, s13, s29 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v0, s8, s24 clamp
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v14, s14, s30 clamp ; GFX10-NEXT: v_readfirstlane_b32 s5, v1
; GFX10PLUS-NEXT: v_add_nc_u32_e64 v15, s15, s31 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v1, s9, s25 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s6, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_add_nc_u32_e64 v2, s10, s26 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s7, v3
; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_add_nc_u32_e64 v3, s11, s27 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s8, v0
; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5 ; GFX10-NEXT: v_add_nc_u32_e64 v0, s12, s28 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6 ; GFX10-NEXT: v_readfirstlane_b32 s9, v1
; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7 ; GFX10-NEXT: v_add_nc_u32_e64 v1, s13, s29 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v8 ; GFX10-NEXT: v_readfirstlane_b32 s10, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v9 ; GFX10-NEXT: v_add_nc_u32_e64 v2, s14, s30 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s10, v10 ; GFX10-NEXT: v_readfirstlane_b32 s11, v3
; GFX10PLUS-NEXT: v_readfirstlane_b32 s11, v11 ; GFX10-NEXT: v_add_nc_u32_e64 v3, s15, s31 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v12 ; GFX10-NEXT: v_readfirstlane_b32 s12, v0
; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v13 ; GFX10-NEXT: v_readfirstlane_b32 s13, v1
; GFX10PLUS-NEXT: v_readfirstlane_b32 s14, v14 ; GFX10-NEXT: v_readfirstlane_b32 s14, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s15, v15 ; GFX10-NEXT: v_readfirstlane_b32 s15, v3
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_uaddsat_v16i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_add_nc_u32_e64 v0, s0, s16 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v1, s1, s17 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v2, s2, s18 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v3, s3, s19 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v4, s4, s20 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v5, s5, s21 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v6, s6, s22 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v7, s7, s23 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v8, s8, s24 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v9, s9, s25 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v10, s10, s26 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v11, s11, s27 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v12, s12, s28 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v13, s13, s29 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v14, s14, s30 clamp
; GFX11-NEXT: v_add_nc_u32_e64 v15, s15, s31 clamp
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_readfirstlane_b32 s6, v6
; GFX11-NEXT: v_readfirstlane_b32 s7, v7
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9
; GFX11-NEXT: v_readfirstlane_b32 s10, v10
; GFX11-NEXT: v_readfirstlane_b32 s11, v11
; GFX11-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-NEXT: v_readfirstlane_b32 s13, v13
; GFX11-NEXT: v_readfirstlane_b32 s14, v14
; GFX11-NEXT: v_readfirstlane_b32 s15, v15
; GFX11-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define i16 @v_uaddsat_i16(i16 %lhs, i16 %rhs) { define i16 @v_uaddsat_i16(i16 %lhs, i16 %rhs) {
; GFX6-LABEL: v_uaddsat_i16: ; GFX6-LABEL: v_uaddsat_i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll

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; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX10-NEXT: v_trunc_f32_e32 v1, v1 ; GFX10-NEXT: v_trunc_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX10-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX10-NEXT: v_add_f32_e32 v0, v2, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v0
; GFX10-NEXT: v_mul_lo_u32 v4, s0, v2 ; GFX10-NEXT: v_mul_lo_u32 v4, s0, v2
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, s0, v3, 0
; GFX10-NEXT: v_mul_lo_u32 v5, s1, v3 ; GFX10-NEXT: v_mul_lo_u32 v5, s1, v3
; GFX10-NEXT: v_mul_hi_u32 v6, v2, v0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, s0, v3, 0
; GFX10-NEXT: v_add3_u32 v1, v1, v4, v5 ; GFX10-NEXT: v_add3_u32 v1, v1, v4, v5
; GFX10-NEXT: v_mul_lo_u32 v4, v2, v0 ; GFX10-NEXT: v_mul_lo_u32 v4, v2, v0
; GFX10-NEXT: v_mul_hi_u32 v0, v3, v0
; GFX10-NEXT: v_mul_lo_u32 v5, v3, v1 ; GFX10-NEXT: v_mul_lo_u32 v5, v3, v1
; GFX10-NEXT: v_mul_lo_u32 v7, v2, v1
; GFX10-NEXT: v_mul_hi_u32 v8, v3, v1
; GFX10-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX10-NEXT: v_add_co_u32 v4, s2, v4, v5 ; GFX10-NEXT: v_add_co_u32 v4, s2, v4, v5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s2 ; GFX10-NEXT: v_mul_hi_u32 v5, v3, v0
; GFX10-NEXT: v_add_co_u32 v6, s2, v7, v6 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s2
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s2 ; GFX10-NEXT: v_mul_hi_u32 v0, v2, v0
; GFX10-NEXT: v_add_co_u32 v0, s2, v4, v0 ; GFX10-NEXT: v_add_co_u32 v4, s2, v4, v5
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2 ; GFX10-NEXT: v_mul_lo_u32 v5, v2, v1
; GFX10-NEXT: v_add_co_u32 v4, s2, v6, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s2
; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v4
; GFX10-NEXT: v_add_co_u32 v0, s2, v5, v0
; GFX10-NEXT: v_mul_hi_u32 v5, v3, v1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s2
; GFX10-NEXT: v_add_nc_u32_e32 v0, v5, v0 ; GFX10-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX10-NEXT: v_add_nc_u32_e32 v5, v7, v6 ; GFX10-NEXT: v_add_co_u32 v0, s2, v0, v5
; GFX10-NEXT: v_add_co_u32 v0, s2, v4, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s2
; GFX10-NEXT: v_add_co_u32 v0, s2, v0, v4
; GFX10-NEXT: v_add_nc_u32_e32 v5, v6, v5
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s2
; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v3, v0 ; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v3, v0
; GFX10-NEXT: v_add3_u32 v1, v5, v4, v1 ; GFX10-NEXT: v_add3_u32 v1, v5, v4, v1
; GFX10-NEXT: v_mul_lo_u32 v4, s1, v3 ; GFX10-NEXT: v_mul_lo_u32 v4, s1, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v1, vcc_lo
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, s0, v3, 0
; GFX10-NEXT: v_mul_lo_u32 v5, s0, v2 ; GFX10-NEXT: v_mul_lo_u32 v5, s0, v2
; GFX10-NEXT: v_mul_hi_u32 v6, v2, v0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s0, v3, 0
; GFX10-NEXT: v_add3_u32 v1, v1, v5, v4 ; GFX10-NEXT: v_add3_u32 v1, v1, v5, v4
; GFX10-NEXT: v_mul_lo_u32 v4, v2, v0 ; GFX10-NEXT: v_mul_lo_u32 v4, v2, v0
; GFX10-NEXT: v_mul_hi_u32 v0, v3, v0
; GFX10-NEXT: v_mul_lo_u32 v5, v3, v1 ; GFX10-NEXT: v_mul_lo_u32 v5, v3, v1
; GFX10-NEXT: v_mul_lo_u32 v7, v2, v1
; GFX10-NEXT: v_mul_hi_u32 v8, v3, v1
; GFX10-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5 ; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 ; GFX10-NEXT: v_mul_hi_u32 v5, v3, v0
; GFX10-NEXT: v_add_co_u32 v6, s0, v7, v6
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, s0, v4, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s0, v6, v8
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v0, v5, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, v2, v0
; GFX10-NEXT: v_add_nc_u32_e32 v5, v7, v6 ; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_add_co_u32 v0, s0, v4, v0 ; GFX10-NEXT: v_mul_lo_u32 v5, v2, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v4
; GFX10-NEXT: v_add_co_u32 v0, s0, v5, v0
; GFX10-NEXT: v_mul_hi_u32 v5, v3, v1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v4
; GFX10-NEXT: v_add_nc_u32_e32 v5, v6, v5
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v3, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v3, v0
; GFX10-NEXT: v_add3_u32 v1, v5, v4, v1 ; GFX10-NEXT: v_add3_u32 v1, v5, v4, v1
; GFX10-NEXT: v_mul_hi_u32 v4, s9, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v2, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v2, v1, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v2, s9, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s9, v0
; GFX10-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX10-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX10-NEXT: v_mul_lo_u32 v5, s9, v1
; GFX10-NEXT: v_mul_hi_u32 v6, s8, v1
; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v3
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 ; GFX10-NEXT: v_mul_hi_u32 v3, s8, v0
; GFX10-NEXT: v_add_co_u32 v4, s0, v5, v4
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, s0, v2, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v2, s0, v4, v6
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v0, v3, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s9, v0
; GFX10-NEXT: v_add_nc_u32_e32 v3, v5, v4 ; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v3
; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v0 ; GFX10-NEXT: v_mul_lo_u32 v3, s9, v1
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v2, v4, v2
; GFX10-NEXT: v_add_co_u32 v0, s0, v3, v0
; GFX10-NEXT: v_mul_hi_u32 v3, s8, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v3
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v2, s0, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v3, v4, v3
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX10-NEXT: v_mul_lo_u32 v4, s11, v2 ; GFX10-NEXT: v_mul_lo_u32 v4, s11, v2
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v2, 1
; GFX10-NEXT: v_add3_u32 v3, v3, v0, v1 ; GFX10-NEXT: v_add3_u32 v3, v3, v0, v1
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s10, v2, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s10, v2, 0
; GFX10-NEXT: v_mul_lo_u32 v5, s10, v3 ; GFX10-NEXT: v_mul_lo_u32 v5, s10, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: v_add3_u32 v1, v1, v5, v4 ; GFX10-NEXT: v_add3_u32 v1, v1, v5, v4
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v6, 1 ; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, s8, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v7, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e64 v5, s0, s9, v1, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v8, s9, v1 ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s10, v4
; GFX10-NEXT: v_sub_co_u32 v9, vcc_lo, s8, v0 ; GFX10-NEXT: v_sub_nc_u32_e32 v1, s9, v1
; GFX10-NEXT: v_sub_co_ci_u32_e64 v10, s0, s9, v1, vcc_lo ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v5
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, s11, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, -1, s1
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s10, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, -1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s11, v5
; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v9, s10 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, v0, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v11, s0, 0, v0, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s11, v1, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v10 ; GFX10-NEXT: v_sub_co_u32 v7, vcc_lo, v4, s10
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, s11, v0, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v8, s0, 0, v6, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s11, v11 ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s10, v7
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, s0 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v8
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, -1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v11 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s11, v8
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v1, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s11, v10 ; GFX10-NEXT: v_add_co_u32 v1, s0, v2, 1
; GFX10-NEXT: v_cndmask_b32_e64 v1, v12, v1, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v10, s0, 0, v3, s0
; GFX10-NEXT: v_cndmask_b32_e32 v12, v14, v13, vcc_lo ; GFX10-NEXT: v_add_co_u32 v11, s0, v1, 1
; GFX10-NEXT: v_sub_co_u32 v13, vcc_lo, v8, s10 ; GFX10-NEXT: v_add_co_ci_u32_e64 v12, s0, 0, v10, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v9
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v11, s0
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v12 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v12, s0
; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v1 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v2, vcc_lo, s11, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v8, v13, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, v0, s0 ; GFX10-NEXT: v_sub_co_u32 v3, vcc_lo, v7, s10
; GFX10-NEXT: v_mov_b32_e32 v7, 0 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v4, s1 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, v1, s1 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v9, v6, s1 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v10, v5, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v3, s0
; GFX10-NEXT: global_store_dwordx2 v7, v[0:1], s[4:5] ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: global_store_dwordx2 v7, v[2:3], s[6:7] ; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v6, s0
; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5]
; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = udiv i64 %x, %y %div = udiv i64 %x, %y
store i64 %div, ptr addrspace(1) %out0 store i64 %div, ptr addrspace(1) %out0
%rem = urem i64 %x, %y %rem = urem i64 %x, %y
store i64 %rem, ptr addrspace(1) %out1 store i64 %rem, ptr addrspace(1) %out1
ret void ret void
} }
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; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5]
; GFX9-NEXT: global_store_dwordx2 v4, v[2:3], s[6:7] ; GFX9-NEXT: global_store_dwordx2 v4, v[2:3], s[6:7]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udivrem_v2i32: ; GFX10-LABEL: udivrem_v2i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s10 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s10
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s11 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s11
; GFX10-NEXT: s_sub_i32 s0, 0, s10 ; GFX10-NEXT: s_sub_i32 s0, 0, s10
; GFX10-NEXT: s_sub_i32 s1, 0, s11
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_mul_lo_u32 v2, s0, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s0, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s1, v1 ; GFX10-NEXT: s_sub_i32 s0, 0, s11
; GFX10-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: v_mul_hi_u32 v2, v1, v3
; GFX10-NEXT: v_mul_hi_u32 v0, s8, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_lo_u32 v3, v0, s10
; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX10-NEXT: v_mul_lo_u32 v2, v0, s10 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, s8, v3
; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s10, v2
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v3, v1, s11 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, s11
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s8, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s9, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v3, s9, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s10, v2 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s11, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s10, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s11, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s11, v3
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s10, v2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v2 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s11, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s10, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s11, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s10, v2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s11, v3
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s0
; GFX10-NEXT: global_store_dwordx2 v8, v[0:1], s[4:5] ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: global_store_dwordx2 v8, v[2:3], s[6:7] ; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5]
; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = udiv <2 x i32> %x, %y %div = udiv <2 x i32> %x, %y
store <2 x i32> %div, ptr addrspace(1) %out0 store <2 x i32> %div, ptr addrspace(1) %out0
%rem = urem <2 x i32> %x, %y %rem = urem <2 x i32> %x, %y
store <2 x i32> %rem, ptr addrspace(1) %out1 store <2 x i32> %rem, ptr addrspace(1) %out1
ret void ret void
} }
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; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] ; GFX9-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
; GFX9-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3] ; GFX9-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udivrem_v4i32: ; GFX10-LABEL: udivrem_v4i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s12 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s13 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s14
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s15
; GFX10-NEXT: s_sub_i32 s0, 0, s12 ; GFX10-NEXT: s_sub_i32 s0, 0, s12
; GFX10-NEXT: s_sub_i32 s1, 0, s14
; GFX10-NEXT: s_sub_i32 s2, 0, s15
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX10-NEXT: s_sub_i32 s1, 0, s13
; GFX10-NEXT: s_sub_i32 s2, 0, s14
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_mul_lo_u32 v2, s0, v0
; GFX10-NEXT: s_sub_i32 s0, 0, s13
; GFX10-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v2, v1, v3
; GFX10-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_lo_u32 v3, v0, s12
; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s8, v3
; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s12, v2
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v3, v1, s13
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s9, v3
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v3
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s13, v3
; GFX10-NEXT: v_cndmask_b32_e64 v4, v3, v4, s0
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s12, v2
; GFX10-NEXT: v_cndmask_b32_e32 v5, v2, v3, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v2, 1, v1
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s13, v4
; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s12, v5
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s14
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX10-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX10-NEXT: v_mul_lo_u32 v3, s1, v2
; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3
; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v3
; GFX10-NEXT: v_mul_hi_u32 v2, s10, v2
; GFX10-NEXT: v_mul_lo_u32 v3, v2, s14
; GFX10-NEXT: v_add_nc_u32_e32 v6, 1, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s10, v3
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s14, v3
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s1
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s14, v3
; GFX10-NEXT: v_cndmask_b32_e64 v6, v3, v6, s1
; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v2
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s14, v6
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v3, s1
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s15
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: v_mul_lo_u32 v4, s0, v0 ; GFX10-NEXT: v_mul_lo_u32 v7, s2, v3
; GFX10-NEXT: v_mul_lo_u32 v5, s1, v1
; GFX10-NEXT: v_mul_lo_u32 v6, s2, v2
; GFX10-NEXT: s_sub_i32 s0, 0, s15
; GFX10-NEXT: v_mul_lo_u32 v7, s0, v3
; GFX10-NEXT: v_mul_hi_u32 v4, v0, v4
; GFX10-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX10-NEXT: v_mul_hi_u32 v6, v2, v6
; GFX10-NEXT: v_mul_hi_u32 v7, v3, v7 ; GFX10-NEXT: v_mul_hi_u32 v7, v3, v7
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v4
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v5
; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v6
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v7
; GFX10-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX10-NEXT: v_mul_hi_u32 v2, s10, v2
; GFX10-NEXT: v_mul_hi_u32 v3, s11, v3 ; GFX10-NEXT: v_mul_hi_u32 v3, s11, v3
; GFX10-NEXT: v_mul_lo_u32 v4, v0, s12
; GFX10-NEXT: v_mul_lo_u32 v5, v1, s13
; GFX10-NEXT: v_mul_lo_u32 v6, v2, s14
; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v0
; GFX10-NEXT: v_mul_lo_u32 v7, v3, s15 ; GFX10-NEXT: v_mul_lo_u32 v7, v3, s15
; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v3
; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v2
; GFX10-NEXT: v_add_nc_u32_e32 v12, 1, v3
; GFX10-NEXT: v_sub_nc_u32_e32 v4, s8, v4
; GFX10-NEXT: v_sub_nc_u32_e32 v5, s9, v5
; GFX10-NEXT: v_sub_nc_u32_e32 v6, s10, v6
; GFX10-NEXT: v_sub_nc_u32_e32 v7, s11, v7 ; GFX10-NEXT: v_sub_nc_u32_e32 v7, s11, v7
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s12, v4
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v5
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s14, v6
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s15, v7 ; GFX10-NEXT: v_cmp_le_u32_e64 s2, s15, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v8, s2
; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s12, v4 ; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s15, v7
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v10, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v8, s2
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s13, v5 ; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v3
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v11, s1
; GFX10-NEXT: v_subrev_nc_u32_e32 v11, s14, v6
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v12, s2
; GFX10-NEXT: v_subrev_nc_u32_e32 v12, s15, v7
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v11, s1
; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v12, s2
; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v1
; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s12, v4
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v5
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s14, v6
; GFX10-NEXT: v_add_nc_u32_e32 v12, 1, v3
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s15, v7 ; GFX10-NEXT: v_cmp_le_u32_e64 s2, s15, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v8, s2
; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s12, v4 ; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v10, s0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s13, v5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v11, s1
; GFX10-NEXT: v_subrev_nc_u32_e32 v11, s14, v6
; GFX10-NEXT: v_subrev_nc_u32_e32 v13, s15, v7
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v12, s2
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v11, s1
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v13, s2
; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5] ; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5]
; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[6:7] ; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s12, v5
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s13, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s14, v6
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s15, v7
; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v0, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v2, s1
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s2
; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = udiv <4 x i32> %x, %y %div = udiv <4 x i32> %x, %y
store <4 x i32> %div, ptr addrspace(1) %out0 store <4 x i32> %div, ptr addrspace(1) %out0
%rem = urem <4 x i32> %x, %y %rem = urem <4 x i32> %x, %y
store <4 x i32> %rem, ptr addrspace(1) %out1 store <4 x i32> %rem, ptr addrspace(1) %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 529 Lines • ▼ Show 20 Lines
; GFX9-NEXT: global_store_dwordx4 v13, v[4:7], s[6:7] ; GFX9-NEXT: global_store_dwordx4 v13, v[4:7], s[6:7]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udivrem_v2i64: ; GFX10-LABEL: udivrem_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s13 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s13
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s15 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s12
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s12
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s14
; GFX10-NEXT: s_sub_u32 s0, 0, s12 ; GFX10-NEXT: s_sub_u32 s0, 0, s12
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
; GFX10-NEXT: s_subb_u32 s1, 0, s13 ; GFX10-NEXT: s_subb_u32 s1, 0, s13
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX10-NEXT: v_trunc_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX10-NEXT: v_add_f32_e32 v0, v2, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v0
; GFX10-NEXT: v_mul_lo_u32 v4, s0, v2
; GFX10-NEXT: v_mul_lo_u32 v5, s1, v3
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, s0, v3, 0
; GFX10-NEXT: v_add3_u32 v1, v1, v4, v5
; GFX10-NEXT: v_mul_lo_u32 v4, v2, v0
; GFX10-NEXT: v_mul_lo_u32 v5, v3, v1
; GFX10-NEXT: v_add_co_u32 v4, s2, v4, v5
; GFX10-NEXT: v_mul_hi_u32 v5, v3, v0
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s2
; GFX10-NEXT: v_mul_hi_u32 v0, v2, v0
; GFX10-NEXT: v_add_co_u32 v4, s2, v4, v5
; GFX10-NEXT: v_mul_lo_u32 v5, v2, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s2
; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v4
; GFX10-NEXT: v_add_co_u32 v0, s2, v5, v0
; GFX10-NEXT: v_mul_hi_u32 v5, v3, v1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s2
; GFX10-NEXT: v_add_co_u32 v0, s2, v0, v5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s2
; GFX10-NEXT: v_add_co_u32 v4, s2, v0, v4
; GFX10-NEXT: v_mul_hi_u32 v0, v2, v1
; GFX10-NEXT: v_add_nc_u32_e32 v5, v6, v5
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
; GFX10-NEXT: s_sub_u32 s2, 0, s14 ; GFX10-NEXT: s_sub_u32 s2, 0, s14
; GFX10-NEXT: s_subb_u32 s3, 0, s15 ; GFX10-NEXT: s_subb_u32 s3, 0, s15
; GFX10-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v3, v4
; GFX10-NEXT: v_add_f32_e32 v1, v1, v3 ; GFX10-NEXT: v_add3_u32 v5, v5, v1, v0
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s15
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s14
; GFX10-NEXT: v_mul_lo_u32 v4, s1, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: v_mul_lo_u32 v5, s0, v2
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX10-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 ; GFX10-NEXT: v_trunc_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v3, 0x2f800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v6, 0xcf800000, v1
; GFX10-NEXT: v_trunc_f32_e32 v2, v2 ; GFX10-NEXT: v_add_f32_e32 v0, v6, v0
; GFX10-NEXT: v_trunc_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v1
; GFX10-NEXT: v_mul_f32_e32 v4, 0xcf800000, v2 ; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v0
; GFX10-NEXT: v_mul_f32_e32 v5, 0xcf800000, v3 ; GFX10-NEXT: v_mul_lo_u32 v8, s2, v6
; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v3 ; GFX10-NEXT: v_mul_lo_u32 v9, s3, v7
; GFX10-NEXT: v_add_f32_e32 v0, v4, v0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s6, s2, v7, 0
; GFX10-NEXT: v_add_f32_e32 v1, v5, v1 ; GFX10-NEXT: v_add3_u32 v1, v1, v8, v9
; GFX10-NEXT: v_cvt_u32_f32_e32 v4, v2 ; GFX10-NEXT: v_mul_lo_u32 v8, v6, v0
; GFX10-NEXT: v_mul_lo_u32 v10, s2, v6 ; GFX10-NEXT: v_mul_lo_u32 v9, v7, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v5, v0 ; GFX10-NEXT: v_add_co_u32 v8, s6, v8, v9
; GFX10-NEXT: v_cvt_u32_f32_e32 v8, v1 ; GFX10-NEXT: v_mul_hi_u32 v9, v7, v0
; GFX10-NEXT: v_mul_lo_u32 v7, s0, v4
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s6, s0, v5, 0
; GFX10-NEXT: v_mul_lo_u32 v9, s1, v5
; GFX10-NEXT: v_mad_u64_u32 v[2:3], s6, s2, v8, 0
; GFX10-NEXT: v_mul_lo_u32 v11, s3, v8
; GFX10-NEXT: v_add3_u32 v1, v1, v7, v9
; GFX10-NEXT: v_mul_lo_u32 v7, v4, v0
; GFX10-NEXT: v_mul_hi_u32 v9, v5, v0
; GFX10-NEXT: v_add3_u32 v3, v3, v10, v11
; GFX10-NEXT: v_mul_hi_u32 v0, v4, v0
; GFX10-NEXT: v_mul_lo_u32 v12, v5, v1
; GFX10-NEXT: v_mul_lo_u32 v13, v4, v1
; GFX10-NEXT: v_mul_lo_u32 v10, v6, v2
; GFX10-NEXT: v_mul_lo_u32 v15, v8, v3
; GFX10-NEXT: v_mul_hi_u32 v11, v8, v2
; GFX10-NEXT: v_mul_hi_u32 v2, v6, v2
; GFX10-NEXT: v_mul_lo_u32 v16, v6, v3
; GFX10-NEXT: v_mul_hi_u32 v14, v5, v1
; GFX10-NEXT: v_add_co_u32 v7, s6, v7, v12
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v0, s6, v13, v0
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v10, s6, v10, v15
; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v2, s6, v16, v2
; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v7, s6, v7, v9
; GFX10-NEXT: v_mul_hi_u32 v17, v8, v3
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v0, s6, v0, v14
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v10, s6, v10, v11
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6
; GFX10-NEXT: v_add_nc_u32_e32 v7, v12, v7 ; GFX10-NEXT: v_mul_hi_u32 v0, v6, v0
; GFX10-NEXT: v_add_co_u32 v2, s6, v2, v17 ; GFX10-NEXT: v_add_co_u32 v8, s6, v8, v9
; GFX10-NEXT: v_mul_hi_u32 v1, v4, v1 ; GFX10-NEXT: v_mul_lo_u32 v9, v6, v1
; GFX10-NEXT: v_add_nc_u32_e32 v10, v15, v10 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s6
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s6 ; GFX10-NEXT: v_add_nc_u32_e32 v8, v10, v8
; GFX10-NEXT: v_add_co_u32 v0, s6, v0, v7 ; GFX10-NEXT: v_add_co_u32 v0, s6, v9, v0
; GFX10-NEXT: v_add_nc_u32_e32 v9, v13, v9 ; GFX10-NEXT: v_mul_hi_u32 v9, v7, v1
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s6
; GFX10-NEXT: v_mul_hi_u32 v3, v6, v3
; GFX10-NEXT: v_add_co_u32 v2, s6, v2, v10
; GFX10-NEXT: v_add_nc_u32_e32 v11, v16, v11
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6
; GFX10-NEXT: v_add3_u32 v1, v9, v7, v1 ; GFX10-NEXT: v_add_co_u32 v0, s6, v0, v9
; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v5, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s6
; GFX10-NEXT: v_add3_u32 v3, v11, v10, v3 ; GFX10-NEXT: v_add_co_u32 v8, s6, v0, v8
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v1, vcc_lo ; GFX10-NEXT: v_mul_hi_u32 v0, v6, v1
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v8, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v9, v10, v9
; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v6, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s6
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s6, s0, v5, 0 ; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v7, v8
; GFX10-NEXT: v_mul_lo_u32 v7, s1, v5 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_mul_lo_u32 v9, s0, v4 ; GFX10-NEXT: v_add3_u32 v9, v9, v1, v0
; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, s2, v8, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s0, v3, 0
; GFX10-NEXT: v_mul_lo_u32 v10, s3, v8 ; GFX10-NEXT: v_mul_lo_u32 v8, s3, v7
; GFX10-NEXT: v_mul_lo_u32 v11, s2, v6 ; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v6, v9, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v12, v4, v0 ; GFX10-NEXT: v_add3_u32 v1, v1, v5, v4
; GFX10-NEXT: v_mul_hi_u32 v13, v5, v0 ; GFX10-NEXT: v_mul_lo_u32 v4, v2, v0
; GFX10-NEXT: v_mul_hi_u32 v0, v4, v0 ; GFX10-NEXT: v_mul_lo_u32 v9, s2, v6
; GFX10-NEXT: v_add3_u32 v1, v1, v9, v7 ; GFX10-NEXT: v_mul_lo_u32 v5, v3, v1
; GFX10-NEXT: v_mul_lo_u32 v7, v6, v2 ; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_mul_hi_u32 v9, v8, v2 ; GFX10-NEXT: v_mul_hi_u32 v5, v3, v0
; GFX10-NEXT: v_mul_hi_u32 v2, v6, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX10-NEXT: v_add3_u32 v3, v3, v11, v10 ; GFX10-NEXT: v_mul_hi_u32 v0, v2, v0
; GFX10-NEXT: v_mul_lo_u32 v10, v5, v1 ; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_mul_lo_u32 v11, v4, v1 ; GFX10-NEXT: v_mul_lo_u32 v5, v2, v1
; GFX10-NEXT: v_mul_hi_u32 v14, v5, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v1, v4, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v4, v10, v4
; GFX10-NEXT: v_mul_lo_u32 v15, v8, v3 ; GFX10-NEXT: v_add_co_u32 v0, s0, v5, v0
; GFX10-NEXT: v_mul_lo_u32 v16, v6, v3 ; GFX10-NEXT: v_mul_hi_u32 v5, v3, v1
; GFX10-NEXT: v_mul_hi_u32 v17, v8, v3
; GFX10-NEXT: v_mul_hi_u32 v3, v6, v3
; GFX10-NEXT: v_add_co_u32 v10, s0, v12, v10
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, s0, v11, v0
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v7, s0, v7, v15
; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v2, s0, v16, v2
; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v10, s0, v10, v13
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v14 ; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v5
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v7, s0, v7, v9 ; GFX10-NEXT: v_add_co_u32 v4, s0, v0, v4
; GFX10-NEXT: v_add_nc_u32_e32 v9, v12, v10 ; GFX10-NEXT: v_mul_hi_u32 v0, v2, v1
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v10, v5
; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v17 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v3, v4
; GFX10-NEXT: v_add3_u32 v5, v5, v1, v0
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s2, v7, 0
; GFX10-NEXT: v_mul_lo_u32 v4, s9, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
; GFX10-NEXT: v_add3_u32 v1, v1, v9, v8
; GFX10-NEXT: v_mul_lo_u32 v8, v6, v0
; GFX10-NEXT: v_mul_lo_u32 v5, s8, v2
; GFX10-NEXT: v_mul_lo_u32 v9, v7, v1
; GFX10-NEXT: v_add_co_u32 v8, s0, v8, v9
; GFX10-NEXT: v_mul_hi_u32 v9, v7, v0
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v0, v6, v0
; GFX10-NEXT: v_add_co_u32 v8, s0, v8, v9
; GFX10-NEXT: v_mul_lo_u32 v9, v6, v1
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v8, v10, v8
; GFX10-NEXT: v_add_co_u32 v0, s0, v9, v0
; GFX10-NEXT: v_mul_hi_u32 v9, v7, v1
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v1, v6, v1
; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v9 ; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v9
; GFX10-NEXT: v_add_nc_u32_e32 v11, v11, v13
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v7, v15, v7 ; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v8
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v5, v0
; GFX10-NEXT: v_add_nc_u32_e32 v10, v16, v10
; GFX10-NEXT: v_add3_u32 v1, v11, v9, v1
; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v7
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v5, s8, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v4, s9, v0
; GFX10-NEXT: v_add3_u32 v3, v10, v7, v3
; GFX10-NEXT: v_mul_hi_u32 v0, s9, v0
; GFX10-NEXT: v_mul_lo_u32 v7, s8, v1
; GFX10-NEXT: v_mul_lo_u32 v10, s9, v1
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v8, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v6, v3, vcc_lo
; GFX10-NEXT: v_mul_hi_u32 v6, s8, v1
; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v7
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, s0, v10, v0
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5 ; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_mul_hi_u32 v5, s8, v3
; GFX10-NEXT: v_add_nc_u32_e32 v9, v10, v9
; GFX10-NEXT: v_mul_hi_u32 v3, s9, v3
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v7, v0
; GFX10-NEXT: v_add3_u32 v1, v9, v8, v1
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_mul_lo_u32 v5, s9, v2
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v6 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v4, v8, v4
; GFX10-NEXT: v_add_co_u32 v3, s0, v5, v3
; GFX10-NEXT: v_mul_hi_u32 v5, s8, v2
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v2, s9, v2
; GFX10-NEXT: v_add_co_u32 v3, s0, v3, v5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_mul_lo_u32 v6, s11, v2 ; GFX10-NEXT: v_add_co_u32 v3, s0, v3, v4
; GFX10-NEXT: v_add_nc_u32_e32 v4, v7, v4
; GFX10-NEXT: v_mul_lo_u32 v7, s10, v3
; GFX10-NEXT: v_mul_lo_u32 v10, s11, v3
; GFX10-NEXT: v_add_nc_u32_e32 v5, v8, v5 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v8, v5
; GFX10-NEXT: v_mul_hi_u32 v8, s10, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s0, v0, v4 ; GFX10-NEXT: v_mul_lo_u32 v7, s13, v3
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX10-NEXT: v_mul_hi_u32 v2, s11, v2 ; GFX10-NEXT: v_mul_lo_u32 v4, s11, v0
; GFX10-NEXT: v_mul_hi_u32 v11, s10, v3 ; GFX10-NEXT: v_mul_lo_u32 v5, s10, v1
; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v7 ; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_add3_u32 v5, v5, v0, v1 ; GFX10-NEXT: v_mul_hi_u32 v5, s10, v0
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s12, v4, 0
; GFX10-NEXT: v_mul_lo_u32 v12, s13, v4
; GFX10-NEXT: v_mul_lo_u32 v13, s12, v5
; GFX10-NEXT: v_add_co_u32 v2, s0, v10, v2
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v8
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v11 ; GFX10-NEXT: v_mul_hi_u32 v0, s11, v0
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0 ; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_add3_u32 v1, v1, v13, v12 ; GFX10-NEXT: v_mul_lo_u32 v5, s11, v1
; GFX10-NEXT: v_add_nc_u32_e32 v6, v7, v6 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v3, s11, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v4
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX10-NEXT: v_add_co_u32 v0, s0, v5, v0
; GFX10-NEXT: v_add_nc_u32_e32 v7, v10, v8 ; GFX10-NEXT: v_mul_hi_u32 v5, s10, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v8, s9, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_sub_co_u32 v10, vcc_lo, s8, v0 ; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v5
; GFX10-NEXT: v_sub_co_ci_u32_e64 v11, s0, s9, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, s13, v8, vcc_lo ; GFX10-NEXT: v_add_co_u32 v4, s0, v0, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s12, v10 ; GFX10-NEXT: v_mul_hi_u32 v0, s11, v1
; GFX10-NEXT: v_mov_b32_e32 v9, 0 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v6, v5
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v10, s12
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v12, s0, 0, v0, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v11
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, s13, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s12, v8
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v12
; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, -1, s0
; GFX10-NEXT: v_add_co_u32 v16, s0, v4, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v17, s0, 0, v5, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s13, v11
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v1, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s13, v12
; GFX10-NEXT: v_cndmask_b32_e64 v14, v15, v14, s0
; GFX10-NEXT: v_add_co_u32 v6, s0, v2, v6
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v15, s0, v16, 1 ; GFX10-NEXT: v_mul_lo_u32 v6, s12, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v18, s0, 0, v17, s0 ; GFX10-NEXT: v_add3_u32 v5, v5, v1, v0
; GFX10-NEXT: v_add3_u32 v3, v7, v1, v3 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s12, v3, 0
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s0, s14, v6, 0 ; GFX10-NEXT: v_add3_u32 v1, v1, v6, v7
; GFX10-NEXT: v_mul_lo_u32 v19, s15, v6 ; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, s8, v0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX10-NEXT: v_sub_co_ci_u32_e64 v7, s0, s9, v1, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v7, s14, v3 ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s12, v6
; GFX10-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc_lo ; GFX10-NEXT: v_sub_nc_u32_e32 v1, s9, v1
; GFX10-NEXT: v_sub_co_u32 v16, s0, v8, s12 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v7
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v20, s0, 0, v0, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, -1, s1
; GFX10-NEXT: v_add3_u32 v2, v2, v7, v19
; GFX10-NEXT: v_sub_co_u32 v7, s0, s10, v1
; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
; GFX10-NEXT: v_sub_co_ci_u32_e64 v13, s1, s11, v2, s0
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s11, v2
; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v14
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v15, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s15, v13
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v17, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s0, s15, v2, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s14, v7
; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v16, s1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, -1, s2
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v20, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s15, v13
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s0
; GFX10-NEXT: v_sub_co_u32 v14, s0, v7, s14 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s13, v7
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v15, s2, 0, v2, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, v0, s0
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v8, s1 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s13, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc_lo ; GFX10-NEXT: v_sub_co_u32 v9, vcc_lo, v6, s12
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s0, s15, v2, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v10, s0, 0, v8, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s15, v15 ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s12, v9
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s1 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v10
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s14, v14 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, -1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, -1, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s0
; GFX10-NEXT: v_add_co_u32 v16, s1, v6, 1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s13, v10
; GFX10-NEXT: v_add_co_ci_u32_e64 v17, s1, 0, v3, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v1, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s15, v15 ; GFX10-NEXT: v_add_co_u32 v1, s0, v3, 1
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1 ; GFX10-NEXT: v_add_co_ci_u32_e64 v12, s0, 0, v2, s0
; GFX10-NEXT: v_add_co_u32 v10, s1, v16, 1 ; GFX10-NEXT: v_add_co_u32 v13, s0, v1, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v18, s1, 0, v17, s1 ; GFX10-NEXT: v_add_co_ci_u32_e64 v14, s0, 0, v12, s0
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v8 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v11
; GFX10-NEXT: v_sub_co_u32 v8, s1, v14, s14 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v13, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s1, 0, v2, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v14, s0
; GFX10-NEXT: v_cndmask_b32_e64 v10, v16, v10, s0 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
; GFX10-NEXT: v_cndmask_b32_e64 v16, v17, v18, s0 ; GFX10-NEXT: v_mul_lo_u32 v13, s14, v5
; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v5 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v8, v14, v8, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, v12, s0
; GFX10-NEXT: v_cndmask_b32_e64 v14, v15, v2, s0 ; GFX10-NEXT: v_mul_lo_u32 v12, s15, v4
; GFX10-NEXT: v_cndmask_b32_e32 v5, v11, v12, vcc_lo ; GFX10-NEXT: v_mad_u64_u32 v[2:3], s1, s14, v4, 0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v10, s1 ; GFX10-NEXT: v_add3_u32 v3, v3, v13, v12
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v16, s1 ; GFX10-NEXT: v_sub_co_u32 v12, s1, s10, v2
; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, v8, s1 ; GFX10-NEXT: v_sub_co_ci_u32_e64 v13, s2, s11, v3, s1
; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, v14, s1 ; GFX10-NEXT: v_cmp_le_u32_e64 s2, s14, v12
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s11, v3
; GFX10-NEXT: v_cmp_le_u32_e64 s3, s15, v13
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, -1, s2
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s15, v13
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, -1, s3
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v14, s2
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v14, s1, s15, v3, s1
; GFX10-NEXT: v_sub_co_u32 v15, s1, v12, s14
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v16, s2, 0, v14, s1
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s14, v15
; GFX10-NEXT: v_cmp_le_u32_e64 s3, s15, v16
; GFX10-NEXT: v_cndmask_b32_e64 v17, 0, -1, s2
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s15, v16
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, -1, s3
; GFX10-NEXT: v_cmp_ne_u32_e64 s3, 0, v2
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v17, s2
; GFX10-NEXT: v_add_co_u32 v17, s2, v4, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v18, s2, 0, v5, s2
; GFX10-NEXT: v_add_co_u32 v19, s2, v17, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v20, s2, 0, v18, s2
; GFX10-NEXT: v_cmp_ne_u32_e64 s2, 0, v3
; GFX10-NEXT: v_cndmask_b32_e64 v3, v17, v19, s2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v3, s3
; GFX10-NEXT: v_cndmask_b32_e64 v3, v18, v20, s2
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v3, s3
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v9, v[0:3], s[4:5] ; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]
; GFX10-NEXT: global_store_dwordx4 v9, v[4:7], s[6:7] ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, s13, v8, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v1, vcc_lo, v9, s12
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v7, v2, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, vcc_lo, s15, v14, s1
; GFX10-NEXT: v_sub_co_u32 v3, vcc_lo, v15, s14
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v15, v3, s2
; GFX10-NEXT: v_cndmask_b32_e64 v3, v16, v5, s2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v12, v2, s3
; GFX10-NEXT: v_cndmask_b32_e64 v3, v13, v3, s3
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = udiv <2 x i64> %x, %y %div = udiv <2 x i64> %x, %y
store <2 x i64> %div, ptr addrspace(1) %out0 store <2 x i64> %div, ptr addrspace(1) %out0
%rem = urem <2 x i64> %x, %y %rem = urem <2 x i64> %x, %y
store <2 x i64> %rem, ptr addrspace(1) %out1 store <2 x i64> %rem, ptr addrspace(1) %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 243 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_load_dword s0, s[4:5], 0x10 ; GFX10-NEXT: s_load_dword s0, s[4:5], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v0, s0 ; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v0, s0
; GFX10-NEXT: s_bfe_u32 s1, s0, 0x80010 ; GFX10-NEXT: s_bfe_u32 s1, s0, 0x80010
; GFX10-NEXT: s_lshr_b32 s2, s0, 24 ; GFX10-NEXT: s_lshr_b32 s2, s0, 24
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, s1 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, s1
; GFX10-NEXT: s_sub_i32 s3, 0, s2 ; GFX10-NEXT: s_sub_i32 s3, 0, s2
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_mul_lo_u32 v2, s3, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s3, v0
; GFX10-NEXT: s_sub_i32 s3, 0, s1 ; GFX10-NEXT: s_sub_i32 s3, 0, s1
; GFX10-NEXT: v_mul_lo_u32 v3, s3, v1 ; GFX10-NEXT: v_mul_lo_u32 v3, s3, v1
; GFX10-NEXT: s_bfe_u32 s3, s0, 0x80008 ; GFX10-NEXT: s_bfe_u32 s3, s0, 0x80008
; GFX10-NEXT: s_and_b32 s0, s0, 0xff ; GFX10-NEXT: s_and_b32 s0, s0, 0xff
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: v_mul_hi_u32 v2, v1, v3
; GFX10-NEXT: v_mul_hi_u32 v0, s3, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s3, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_lo_u32 v3, v0, s2
; GFX10-NEXT: v_mul_hi_u32 v1, s0, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, s0, v1
; GFX10-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, s3, v3
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v3, v1, s1 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, s1
; GFX10-NEXT: v_add_nc_u32_e32 v6, 1, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s3, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s0, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v3, s0, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s2, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s1, v3 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s1, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s1, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s2, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s1, v3
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s2, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s0
; GFX10-NEXT: v_add_nc_u32_e32 v6, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s1, v3 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s1, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s1, v3
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: s_movk_i32 s1, 0xff ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s2, v2
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_and_b32_sdwa v0, v0, s1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s1, v3
; GFX10-NEXT: v_and_b32_sdwa v2, v2, s1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s0
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-NEXT: s_movk_i32 s4, 0xff
; GFX10-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v2, v2, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_short v1, v0, s[4:5] ; GFX10-NEXT: global_store_short v1, v0, s[0:1]
; GFX10-NEXT: global_store_short v1, v2, s[6:7] ; GFX10-NEXT: global_store_short v1, v2, s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = udiv <2 x i8> %x, %y %div = udiv <2 x i8> %x, %y
store <2 x i8> %div, ptr addrspace(1) %out0 store <2 x i8> %div, ptr addrspace(1) %out0
%rem = urem <2 x i8> %x, %y %rem = urem <2 x i8> %x, %y
store <2 x i8> %rem, ptr addrspace(1) %out1 store <2 x i8> %rem, ptr addrspace(1) %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 239 Lines • ▼ Show 20 Lines
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s2, s1, 0xffff ; GFX10-NEXT: s_and_b32 s2, s1, 0xffff
; GFX10-NEXT: s_lshr_b32 s1, s1, 16 ; GFX10-NEXT: s_lshr_b32 s1, s1, 16
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s1 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s1
; GFX10-NEXT: s_sub_i32 s3, 0, s2 ; GFX10-NEXT: s_sub_i32 s3, 0, s2
; GFX10-NEXT: s_sub_i32 s6, 0, s1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_mul_lo_u32 v2, s3, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s3, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s6, v1 ; GFX10-NEXT: s_sub_i32 s3, 0, s1
; GFX10-NEXT: v_mul_lo_u32 v3, s3, v1
; GFX10-NEXT: s_and_b32 s3, s0, 0xffff ; GFX10-NEXT: s_and_b32 s3, s0, 0xffff
; GFX10-NEXT: s_lshr_b32 s0, s0, 16 ; GFX10-NEXT: s_lshr_b32 s0, s0, 16
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: v_mul_hi_u32 v2, v1, v3
; GFX10-NEXT: v_mul_hi_u32 v0, s3, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s3, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_lo_u32 v3, v0, s2
; GFX10-NEXT: v_mul_hi_u32 v1, s0, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, s0, v1
; GFX10-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, s3, v3
; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v3, v1, s1 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, s1
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s3, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s0, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v3, s0, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s2, v2 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s1, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s2, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s1, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s1, v3
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v2 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s1, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s2, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s1, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s2, v2
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s1, v3
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v4, s0
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-NEXT: v_perm_b32 v2, v3, v2, 0x5040100 ; GFX10-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dword v1, v0, s[4:5] ; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-NEXT: global_store_dword v1, v2, s[6:7] ; GFX10-NEXT: global_store_dword v1, v2, s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = udiv <2 x i16> %x, %y %div = udiv <2 x i16> %x, %y
store <2 x i16> %div, ptr addrspace(1) %out0 store <2 x i16> %div, ptr addrspace(1) %out0
%rem = urem <2 x i16> %x, %y %rem = urem <2 x i16> %x, %y
store <2 x i16> %rem, ptr addrspace(1) %out1 store <2 x i16> %rem, ptr addrspace(1) %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 235 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

Show First 20 Lines • Show All 484 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_usubsat_v4i8: ; GFX10-LABEL: v_usubsat_v4i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 24, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 24, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 8, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 24, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 24, v1
; GFX10-NEXT: v_perm_b32 v2, v2, v0, 0x5040100 ; GFX10-NEXT: v_perm_b32 v2, v2, v0, 0x5040100
; GFX10-NEXT: v_alignbit_b32 v0, v3, v0, 16 ; GFX10-NEXT: v_alignbit_b32 v0, v3, v0, 16
; GFX10-NEXT: v_perm_b32 v3, v4, v1, 0x5040100 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX10-NEXT: v_alignbit_b32 v1, v5, v1, 16
; GFX10-NEXT: v_mov_b32_e32 v4, 24
; GFX10-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_perm_b32 v3, v3, v1, 0x5040100
; GFX10-NEXT: v_alignbit_b32 v1, v4, v1, 16
; GFX10-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_sub_u16 v2, v2, v3 clamp ; GFX10-NEXT: v_pk_sub_u16 v2, v2, v3 clamp
; GFX10-NEXT: v_mov_b32_e32 v3, 8
; GFX10-NEXT: v_pk_sub_u16 v0, v0, v1 clamp ; GFX10-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
; GFX10-NEXT: v_mov_b32_e32 v1, 8 ; GFX10-NEXT: v_pk_lshrrev_b16 v1, 8, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshrrev_b16 v2, 8, v2 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1] ; GFX10-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v0 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v0
; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; GFX10-NEXT: v_and_or_b32 v1, v1, 0xff, v2
; GFX10-NEXT: v_and_or_b32 v1, v2, 0xff, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, 24
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0 ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_or3_b32 v0, v1, v3, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_usubsat_v4i8: ; GFX11-LABEL: v_usubsat_v4i8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
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; GFX9-NEXT: v_sub_u32_e64 v4, s4, v4 clamp ; GFX9-NEXT: v_sub_u32_e64 v4, s4, v4 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v4 ; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: s_usubsat_v5i32: ; GFX10-LABEL: s_usubsat_v5i32:
; GFX10PLUS: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s5 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s5 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, s1, s6 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s6 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, s2, s7 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s7 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v3, s3, s8 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v3, s3, s8 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v4, s4, s9 clamp ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_sub_nc_u32_e64 v0, s4, s9 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_usubsat_v5i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_sub_nc_u32_e64 v0, s0, s5 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v1, s1, s6 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v2, s2, s7 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v3, s3, s8 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v4, s4, s9 clamp
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) %result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result ret <5 x i32> %result
} }
define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) { define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX6-LABEL: v_usubsat_v16i32: ; GFX6-LABEL: v_usubsat_v16i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_u32_e64 v15, v15, v16 clamp ; GFX9-NEXT: v_sub_u32_e64 v15, v15, v16 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_usubsat_v16i32: ; GFX10-LABEL: v_usubsat_v16i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp
; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_sub_nc_u32_e64 v15, v15, v31 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v15, v15, v16 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_usubsat_v16i32: ; GFX11-LABEL: v_usubsat_v16i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp
; GFX11-NEXT: scratch_load_b32 v16, off, s32
; GFX11-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_sub_nc_u32_e64 v15, v15, v31 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v15, v15, v16 clamp
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define amdgpu_ps <16 x i32> @s_usubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) { define amdgpu_ps <16 x i32> @s_usubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v16i32: ; GFX6-LABEL: s_usubsat_v16i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
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; GFX9-NEXT: v_readfirstlane_b32 s10, v10 ; GFX9-NEXT: v_readfirstlane_b32 s10, v10
; GFX9-NEXT: v_readfirstlane_b32 s11, v11 ; GFX9-NEXT: v_readfirstlane_b32 s11, v11
; GFX9-NEXT: v_readfirstlane_b32 s12, v12 ; GFX9-NEXT: v_readfirstlane_b32 s12, v12
; GFX9-NEXT: v_readfirstlane_b32 s13, v13 ; GFX9-NEXT: v_readfirstlane_b32 s13, v13
; GFX9-NEXT: v_readfirstlane_b32 s14, v14 ; GFX9-NEXT: v_readfirstlane_b32 s14, v14
; GFX9-NEXT: v_readfirstlane_b32 s15, v15 ; GFX9-NEXT: v_readfirstlane_b32 s15, v15
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: s_usubsat_v16i32: ; GFX10-LABEL: s_usubsat_v16i32:
; GFX10PLUS: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s16 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s16 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, s1, s17 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s17 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, s2, s18 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s18 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v3, s3, s19 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v3, s3, s19 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v4, s4, s20 clamp ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v5, s5, s21 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v0, s4, s20 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v6, s6, s22 clamp ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v7, s7, s23 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v1, s5, s21 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v8, s8, s24 clamp ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v9, s9, s25 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v2, s6, s22 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v10, s10, s26 clamp ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v11, s11, s27 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v3, s7, s23 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v12, s12, s28 clamp ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v13, s13, s29 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v0, s8, s24 clamp
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v14, s14, s30 clamp ; GFX10-NEXT: v_readfirstlane_b32 s5, v1
; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v15, s15, s31 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v1, s9, s25 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s6, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_sub_nc_u32_e64 v2, s10, s26 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s7, v3
; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_sub_nc_u32_e64 v3, s11, s27 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s8, v0
; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5 ; GFX10-NEXT: v_sub_nc_u32_e64 v0, s12, s28 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6 ; GFX10-NEXT: v_readfirstlane_b32 s9, v1
; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7 ; GFX10-NEXT: v_sub_nc_u32_e64 v1, s13, s29 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v8 ; GFX10-NEXT: v_readfirstlane_b32 s10, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v9 ; GFX10-NEXT: v_sub_nc_u32_e64 v2, s14, s30 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s10, v10 ; GFX10-NEXT: v_readfirstlane_b32 s11, v3
; GFX10PLUS-NEXT: v_readfirstlane_b32 s11, v11 ; GFX10-NEXT: v_sub_nc_u32_e64 v3, s15, s31 clamp
; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v12 ; GFX10-NEXT: v_readfirstlane_b32 s12, v0
; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v13 ; GFX10-NEXT: v_readfirstlane_b32 s13, v1
; GFX10PLUS-NEXT: v_readfirstlane_b32 s14, v14 ; GFX10-NEXT: v_readfirstlane_b32 s14, v2
; GFX10PLUS-NEXT: v_readfirstlane_b32 s15, v15 ; GFX10-NEXT: v_readfirstlane_b32 s15, v3
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_usubsat_v16i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_sub_nc_u32_e64 v0, s0, s16 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v1, s1, s17 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v2, s2, s18 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v3, s3, s19 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v4, s4, s20 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v5, s5, s21 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v6, s6, s22 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v7, s7, s23 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v8, s8, s24 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v9, s9, s25 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v10, s10, s26 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v11, s11, s27 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v12, s12, s28 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v13, s13, s29 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v14, s14, s30 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v15, s15, s31 clamp
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_readfirstlane_b32 s6, v6
; GFX11-NEXT: v_readfirstlane_b32 s7, v7
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9
; GFX11-NEXT: v_readfirstlane_b32 s10, v10
; GFX11-NEXT: v_readfirstlane_b32 s11, v11
; GFX11-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-NEXT: v_readfirstlane_b32 s13, v13
; GFX11-NEXT: v_readfirstlane_b32 s14, v14
; GFX11-NEXT: v_readfirstlane_b32 s15, v15
; GFX11-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) { define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {
; GFX6-LABEL: v_usubsat_i16: ; GFX6-LABEL: v_usubsat_i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll

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; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc ; GFX1032-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: .LBB10_2: ; GFX1032-NEXT: .LBB10_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: v_readfirstlane_b32 s0, v0
; GFX1032-NEXT: v_mad_u64_u32 v[3:4], s0, s2, v2, 0
; GFX1032-NEXT: v_readfirstlane_b32 s1, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s1, v1
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mad_u64_u32 v[0:1], s2, s2, v2, 0
; GFX1032-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s7, 0x31016000
; GFX1032-NEXT: s_mov_b32 s6, -1 ; GFX1032-NEXT: s_mov_b32 s6, -1
; GFX1032-NEXT: v_mad_u64_u32 v[4:5], s0, s3, v2, v[4:5] ; GFX1032-NEXT: v_mad_u64_u32 v[1:2], s2, s3, v2, v[1:2]
; GFX1032-NEXT: v_readfirstlane_b32 s0, v0 ; GFX1032-NEXT: v_sub_co_u32 v0, vcc_lo, s0, v0
; GFX1032-NEXT: v_sub_co_u32 v0, vcc_lo, s0, v3
; GFX1032-NEXT: v_mov_b32_e32 v1, v4
; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo ; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: s_endpgm
; ;
; GFX1164-LABEL: sub_i64_uniform: ; GFX1164-LABEL: sub_i64_uniform:
; GFX1164: ; %bb.0: ; %entry ; GFX1164: ; %bb.0: ; %entry
; GFX1164-NEXT: s_clause 0x1 ; GFX1164-NEXT: s_clause 0x1
; GFX1164-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 ; GFX1164-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
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llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX7LESS %s ; RUN: llc -march=amdgcn -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX7LESS %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX8 %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX8 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX10,GFX1064 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX10,GFX1064 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX10,GFX1032 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX10,GFX1032 %s
; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX1164 %s ; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX1164 %s
; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX1132 %s ; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX1132 %s
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; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1] ; GFX1032-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1]
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB12_2: ; GFX1032-NEXT: .LBB12_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: v_readfirstlane_b32 s4, v0
; GFX1032-NEXT: v_readfirstlane_b32 s5, v1
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mad_u64_u32 v[3:4], s2, s2, v2, 0 ; GFX1032-NEXT: v_mad_u64_u32 v[0:1], s2, s2, v2, 0
; GFX1032-NEXT: v_readfirstlane_b32 s4, v1 ; GFX1032-NEXT: v_mad_u64_u32 v[1:2], s2, s3, v2, v[1:2]
; GFX1032-NEXT: v_mad_u64_u32 v[4:5], s2, s3, v2, v[4:5] ; GFX1032-NEXT: v_sub_co_u32 v0, vcc_lo, s4, v0
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: v_sub_co_u32 v0, vcc_lo, s2, v3
; GFX1032-NEXT: v_mov_b32_e32 v1, v4
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s4, v1, vcc_lo ; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: s_endpgm
; ;
; GFX1164-LABEL: sub_i64_uniform: ; GFX1164-LABEL: sub_i64_uniform:
; GFX1164: ; %bb.0: ; %entry ; GFX1164: ; %bb.0: ; %entry
; GFX1164-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 ; GFX1164-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX1164-NEXT: s_mov_b64 s[6:7], exec ; GFX1164-NEXT: s_mov_b64 s[6:7], exec
; GFX1164-NEXT: v_mov_b32_e32 v3, 0 ; GFX1164-NEXT: v_mov_b32_e32 v3, 0
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llvm/test/CodeGen/AMDGPU/bf16.ll

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; GFX9-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], 0 offen offset:128 ; GFX9-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], 0 offen offset:128
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: test_overflow_stack: ; GFX10-LABEL: test_overflow_stack:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:8
; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4
; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s32
; GFX10-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:112 ; GFX10-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:112
; GFX10-NEXT: buffer_store_dword v29, v0, s[0:3], 0 offen offset:108 ; GFX10-NEXT: buffer_store_dword v29, v0, s[0:3], 0 offen offset:108
; GFX10-NEXT: buffer_store_dword v28, v0, s[0:3], 0 offen offset:104 ; GFX10-NEXT: buffer_store_dword v28, v0, s[0:3], 0 offen offset:104
; GFX10-NEXT: buffer_store_dword v27, v0, s[0:3], 0 offen offset:100 ; GFX10-NEXT: buffer_store_dword v27, v0, s[0:3], 0 offen offset:100
; GFX10-NEXT: buffer_store_dword v26, v0, s[0:3], 0 offen offset:96 ; GFX10-NEXT: buffer_store_dword v26, v0, s[0:3], 0 offen offset:96
; GFX10-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:92 ; GFX10-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:92
; GFX10-NEXT: buffer_store_dword v24, v0, s[0:3], 0 offen offset:88 ; GFX10-NEXT: buffer_store_dword v24, v0, s[0:3], 0 offen offset:88
; GFX10-NEXT: buffer_store_dword v23, v0, s[0:3], 0 offen offset:84 ; GFX10-NEXT: buffer_store_dword v23, v0, s[0:3], 0 offen offset:84
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; GFX10-NEXT: buffer_store_dword v10, v0, s[0:3], 0 offen offset:32 ; GFX10-NEXT: buffer_store_dword v10, v0, s[0:3], 0 offen offset:32
; GFX10-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28 ; GFX10-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
; GFX10-NEXT: buffer_store_dword v8, v0, s[0:3], 0 offen offset:24 ; GFX10-NEXT: buffer_store_dword v8, v0, s[0:3], 0 offen offset:24
; GFX10-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:20 ; GFX10-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:20
; GFX10-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen offset:16 ; GFX10-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen offset:16
; GFX10-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:12 ; GFX10-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:12
; GFX10-NEXT: buffer_store_dword v4, v0, s[0:3], 0 offen offset:8 ; GFX10-NEXT: buffer_store_dword v4, v0, s[0:3], 0 offen offset:8
; GFX10-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:4 ; GFX10-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:4
; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8
; GFX10-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen ; GFX10-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4
; GFX10-NEXT: buffer_store_dword v31, v0, s[0:3], 0 offen offset:124
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: buffer_store_dword v32, v0, s[0:3], 0 offen offset:120 ; GFX10-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:124
; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s32
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:120
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_store_dword v33, v0, s[0:3], 0 offen offset:116 ; GFX10-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:116
; GFX10-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], 0 offen offset:128 ; GFX10-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], 0 offen offset:128
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%ins.0 = insertvalue { <32 x i32>, bfloat } poison, <32 x i32> %b, 0 %ins.0 = insertvalue { <32 x i32>, bfloat } poison, <32 x i32> %b, 0
%ins.1 = insertvalue { <32 x i32>, bfloat } %ins.0 ,bfloat %a, 1 %ins.1 = insertvalue { <32 x i32>, bfloat } %ins.0 ,bfloat %a, 1
ret { <32 x i32>, bfloat } %ins.1 ret { <32 x i32>, bfloat } %ins.1
} }
Context not available.

llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll

Show All 13 Lines
; ISA-NEXT: v_mov_b32_e32 v7, 0 ; ISA-NEXT: v_mov_b32_e32 v7, 0
; ISA-NEXT: s_waitcnt lgkmcnt(0) ; ISA-NEXT: s_waitcnt lgkmcnt(0)
; ISA-NEXT: s_cmp_lg_u32 s4, 0 ; ISA-NEXT: s_cmp_lg_u32 s4, 0
; ISA-NEXT: s_cselect_b32 s6, -1, 0 ; ISA-NEXT: s_cselect_b32 s6, -1, 0
; ISA-NEXT: s_and_b32 s6, s6, exec_lo ; ISA-NEXT: s_and_b32 s6, s6, exec_lo
; ISA-NEXT: s_cselect_b32 s6, s5, 0 ; ISA-NEXT: s_cselect_b32 s6, s5, 0
; ISA-NEXT: s_lshr_b32 s7, 1, s4 ; ISA-NEXT: s_lshr_b32 s7, 1, s4
; ISA-NEXT: s_cmp_lg_u32 s4, 0 ; ISA-NEXT: s_cmp_lg_u32 s4, 0
; ISA-NEXT: v_cvt_f32_i32_e32 v0, s6 ; ISA-NEXT: v_cvt_f32_i32_e32 v4, s6
; ISA-NEXT: s_cselect_b32 s8, -1, 0 ; ISA-NEXT: s_cselect_b32 s8, -1, 0
; ISA-NEXT: s_and_b32 s8, s8, exec_lo ; ISA-NEXT: s_and_b32 s8, s8, exec_lo
; ISA-NEXT: s_cselect_b32 s7, s7, 0 ; ISA-NEXT: s_cselect_b32 s7, s7, 0
; ISA-NEXT: s_lshr_b32 s5, s5, 1 ; ISA-NEXT: s_lshr_b32 s5, s5, 1
; ISA-NEXT: s_cmp_lg_u32 s4, 0 ; ISA-NEXT: s_cmp_lg_u32 s4, 0
; ISA-NEXT: v_cvt_f32_ubyte0_e32 v4, s7 ; ISA-NEXT: v_cvt_f32_ubyte0_e32 v5, s7
; ISA-NEXT: s_cselect_b32 s4, -1, 0 ; ISA-NEXT: s_cselect_b32 s4, -1, 0
; ISA-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s4 ; ISA-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s4
; ISA-NEXT: s_and_b32 s4, s4, exec_lo ; ISA-NEXT: s_and_b32 s4, s4, exec_lo
; ISA-NEXT: s_cselect_b32 s4, s5, 0 ; ISA-NEXT: s_cselect_b32 s4, s5, 0
; ISA-NEXT: v_cvt_f32_i32_e32 v5, s4 ; ISA-NEXT: v_cvt_f32_i32_e32 v0, s4
; ISA-NEXT: s_mov_b32 s4, 0 ; ISA-NEXT: s_mov_b32 s4, 0
; ISA-NEXT: v_and_b32_e32 v5, 0x7fffffff, v5 ; ISA-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; ISA-NEXT: .LBB0_1: ; %bb14 ; ISA-NEXT: .LBB0_1: ; %bb14
; ISA-NEXT: ; =>This Inner Loop Header: Depth=1 ; ISA-NEXT: ; =>This Inner Loop Header: Depth=1
; ISA-NEXT: v_mov_b32_e32 v6, v7 ; ISA-NEXT: v_mov_b32_e32 v6, v7
; ISA-NEXT: s_and_b32 s5, exec_lo, vcc_lo ; ISA-NEXT: s_and_b32 s5, exec_lo, vcc_lo
; ISA-NEXT: s_or_b32 s4, s5, s4 ; ISA-NEXT: s_or_b32 s4, s5, s4
; ISA-NEXT: v_add_f32_e32 v7, v6, v3 ; ISA-NEXT: v_add_f32_e32 v7, v6, v3
; ISA-NEXT: v_add_f32_e32 v7, v7, v0
; ISA-NEXT: v_add_f32_e32 v7, v7, v5 ; ISA-NEXT: v_add_f32_e32 v7, v7, v5
; ISA-NEXT: v_add_f32_e32 v7, v7, v4 ; ISA-NEXT: v_add_f32_e32 v7, v7, v4
; ISA-NEXT: v_add_f32_e32 v7, v7, v0
; ISA-NEXT: s_andn2_b32 exec_lo, exec_lo, s4 ; ISA-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
; ISA-NEXT: s_cbranch_execnz .LBB0_1 ; ISA-NEXT: s_cbranch_execnz .LBB0_1
; ISA-NEXT: ; %bb.2: ; %bb21 ; ISA-NEXT: ; %bb.2: ; %bb21
; ISA-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; ISA-NEXT: s_or_b32 exec_lo, exec_lo, s4
; ISA-NEXT: flat_store_dword v[1:2], v6 ; ISA-NEXT: flat_store_dword v[1:2], v6
; ISA-NEXT: s_waitcnt lgkmcnt(0) ; ISA-NEXT: s_waitcnt lgkmcnt(0)
; ISA-NEXT: s_waitcnt_vscnt null, 0x0 ; ISA-NEXT: s_waitcnt_vscnt null, 0x0
; ISA-NEXT: s_setpc_b64 s[30:31] ; ISA-NEXT: s_setpc_b64 s[30:31]
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llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll

Show First 20 Lines • Show All 519 Lines • ▼ Show 20 Lines
; GFX10_DEFAULT-NEXT: s_waitcnt vmcnt(0) ; GFX10_DEFAULT-NEXT: s_waitcnt vmcnt(0)
; GFX10_DEFAULT-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:6 ; GFX10_DEFAULT-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:6
; GFX10_DEFAULT-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10_DEFAULT-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10_DEFAULT-NEXT: global_load_ushort v0, v2, s[4:5] offset:4 ; GFX10_DEFAULT-NEXT: global_load_ushort v0, v2, s[4:5] offset:4
; GFX10_DEFAULT-NEXT: s_waitcnt vmcnt(0) ; GFX10_DEFAULT-NEXT: s_waitcnt vmcnt(0)
; GFX10_DEFAULT-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:8 ; GFX10_DEFAULT-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:8
; GFX10_DEFAULT-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10_DEFAULT-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10_DEFAULT-NEXT: s_clause 0x1 ; GFX10_DEFAULT-NEXT: s_clause 0x1
; GFX10_DEFAULT-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:6 ; GFX10_DEFAULT-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4
; GFX10_DEFAULT-NEXT: buffer_load_ushort v3, off, s[0:3], 0 offset:4 ; GFX10_DEFAULT-NEXT: buffer_load_ushort v1, off, s[0:3], 0 offset:6
; GFX10_DEFAULT-NEXT: s_waitcnt vmcnt(1)
; GFX10_DEFAULT-NEXT: v_mov_b32_e32 v1, v0
; GFX10_DEFAULT-NEXT: s_waitcnt vmcnt(0) ; GFX10_DEFAULT-NEXT: s_waitcnt vmcnt(0)
; GFX10_DEFAULT-NEXT: v_perm_b32 v0, v0, v3, 0x5040100 ; GFX10_DEFAULT-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX10_DEFAULT-NEXT: buffer_load_short_d16_hi v1, off, s[0:3], 0 offset:8 ; GFX10_DEFAULT-NEXT: buffer_load_short_d16_hi v1, off, s[0:3], 0 offset:8
; GFX10_DEFAULT-NEXT: s_waitcnt vmcnt(0) ; GFX10_DEFAULT-NEXT: s_waitcnt vmcnt(0)
; GFX10_DEFAULT-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] ; GFX10_DEFAULT-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX10_DEFAULT-NEXT: s_endpgm ; GFX10_DEFAULT-NEXT: s_endpgm
; ;
; FLATSCR_GFX10-LABEL: vload2_private: ; FLATSCR_GFX10-LABEL: vload2_private:
; FLATSCR_GFX10: ; %bb.0: ; %entry ; FLATSCR_GFX10: ; %bb.0: ; %entry
; FLATSCR_GFX10-NEXT: s_add_u32 s2, s2, s5 ; FLATSCR_GFX10-NEXT: s_add_u32 s2, s2, s5
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llvm/test/CodeGen/AMDGPU/cluster_stores.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; GFX9-NEXT: flat_store_dword v[0:1], v4 offset:16 ; GFX9-NEXT: flat_store_dword v[0:1], v4 offset:16
; GFX9-NEXT: flat_store_dword v[0:1], v5 offset:24 ; GFX9-NEXT: flat_store_dword v[0:1], v5 offset:24
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: cluster_load_cluster_store: ; GFX10-LABEL: cluster_load_cluster_store:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_add_u32 s4, s0, 8
; GFX10-NEXT: s_addc_u32 s5, s1, 0
; GFX10-NEXT: s_add_u32 s6, s0, 16
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: s_addc_u32 s7, s1, 0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_add_u32 s4, s0, 8
; GFX10-NEXT: s_addc_u32 s5, s1, 0
; GFX10-NEXT: flat_load_dword v2, v[0:1]
; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: s_add_u32 s4, s0, 16
; GFX10-NEXT: s_addc_u32 s5, s1, 0
; GFX10-NEXT: s_add_u32 s0, s0, 24 ; GFX10-NEXT: s_add_u32 s0, s0, 24
; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: v_mov_b32_e32 v3, s5 ; GFX10-NEXT: flat_load_dword v3, v[0:1]
; GFX10-NEXT: v_mov_b32_e32 v4, s6 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v5, s7 ; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: v_mov_b32_e32 v7, s1 ; GFX10-NEXT: flat_load_dword v4, v[0:1]
; GFX10-NEXT: v_mov_b32_e32 v6, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: s_clause 0x3 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: flat_load_dword v8, v[0:1]
; GFX10-NEXT: flat_load_dword v9, v[2:3]
; GFX10-NEXT: flat_load_dword v10, v[4:5]
; GFX10-NEXT: flat_load_dword v11, v[6:7]
; GFX10-NEXT: s_add_u32 s0, s2, 8 ; GFX10-NEXT: s_add_u32 s0, s2, 8
; GFX10-NEXT: s_addc_u32 s1, s3, 0 ; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: flat_load_dword v5, v[0:1]
; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_add_u32 s0, s2, 16
; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: v_mov_b32_e32 v1, s3 ; GFX10-NEXT: v_mov_b32_e32 v1, s3
; GFX10-NEXT: s_add_u32 s2, s2, 24
; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: v_mov_b32_e32 v5, s1
; GFX10-NEXT: v_mov_b32_e32 v4, s0
; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: v_mov_b32_e32 v6, s2
; GFX10-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3) ; GFX10-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)
; GFX10-NEXT: flat_store_dword v[0:1], v8 ; GFX10-NEXT: flat_store_dword v[0:1], v2
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_add_u32 s0, s2, 16
; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: s_waitcnt vmcnt(2) lgkmcnt(3) ; GFX10-NEXT: s_waitcnt vmcnt(2) lgkmcnt(3)
; GFX10-NEXT: flat_store_dword v[2:3], v9 ; GFX10-NEXT: flat_store_dword v[0:1], v3
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_add_u32 s0, s2, 24
; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: s_waitcnt vmcnt(1) lgkmcnt(3) ; GFX10-NEXT: s_waitcnt vmcnt(1) lgkmcnt(3)
; GFX10-NEXT: flat_store_dword v[4:5], v10 ; GFX10-NEXT: flat_store_dword v[0:1], v4
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(3) ; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(3)
; GFX10-NEXT: flat_store_dword v[6:7], v11 ; GFX10-NEXT: flat_store_dword v[0:1], v5
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: cluster_load_cluster_store: ; GFX11-LABEL: cluster_load_cluster_store:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: s_clause 0x3
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; GFX9-NEXT: flat_store_dword v[0:1], v2 offset:8 ; GFX9-NEXT: flat_store_dword v[0:1], v2 offset:8
; GFX9-NEXT: flat_store_dword v[0:1], v5 offset:24 ; GFX9-NEXT: flat_store_dword v[0:1], v5 offset:24
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: cluster_load_valu_cluster_store: ; GFX10-LABEL: cluster_load_valu_cluster_store:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_add_u32 s4, s0, 8 ; GFX10-NEXT: s_add_u32 s4, s0, 8
; GFX10-NEXT: s_addc_u32 s5, s1, 0 ; GFX10-NEXT: s_addc_u32 s5, s1, 0
; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: s_add_u32 s6, s0, 16 ; GFX10-NEXT: s_add_u32 s6, s0, 16
; GFX10-NEXT: v_mov_b32_e32 v3, s5
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: s_addc_u32 s7, s1, 0 ; GFX10-NEXT: s_addc_u32 s7, s1, 0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: flat_load_dword v2, v[0:1]
; GFX10-NEXT: v_mov_b32_e32 v0, s6
; GFX10-NEXT: v_mov_b32_e32 v1, s7
; GFX10-NEXT: s_add_u32 s0, s0, 24 ; GFX10-NEXT: s_add_u32 s0, s0, 24
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: v_mov_b32_e32 v4, s6 ; GFX10-NEXT: flat_load_dword v3, v[0:1]
; GFX10-NEXT: v_mov_b32_e32 v5, s7 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: flat_load_dword v6, v[2:3] ; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: v_mov_b32_e32 v3, s1 ; GFX10-NEXT: flat_load_dword v4, v[0:1]
; GFX10-NEXT: v_mov_b32_e32 v2, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: flat_load_dword v8, v[0:1]
; GFX10-NEXT: flat_load_dword v9, v[4:5]
; GFX10-NEXT: flat_load_dword v10, v[2:3]
; GFX10-NEXT: s_add_u32 s0, s2, 8 ; GFX10-NEXT: s_add_u32 s0, s2, 8
; GFX10-NEXT: s_addc_u32 s1, s3, 0 ; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: s_add_u32 s4, s2, 16 ; GFX10-NEXT: s_add_u32 s4, s2, 16
; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: s_addc_u32 s5, s3, 0 ; GFX10-NEXT: s_addc_u32 s5, s3, 0
; GFX10-NEXT: flat_load_dword v5, v[0:1]
; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_add_u32 s0, s2, 24
; GFX10-NEXT: v_mov_b32_e32 v1, s3 ; GFX10-NEXT: v_mov_b32_e32 v1, s3
; GFX10-NEXT: v_mov_b32_e32 v4, s4
; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: v_mov_b32_e32 v5, s5
; GFX10-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3) ; GFX10-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)
; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v6 ; GFX10-NEXT: flat_store_dword v[0:1], v2
; GFX10-NEXT: v_mov_b32_e32 v7, s1 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v6, s0 ; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2) ; GFX10-NEXT: s_waitcnt vmcnt(2) lgkmcnt(3)
; GFX10-NEXT: flat_store_dword v[0:1], v8 ; GFX10-NEXT: flat_store_dword v[0:1], v3
; GFX10-NEXT: s_waitcnt vmcnt(1) lgkmcnt(2) ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: flat_store_dword v[4:5], v9 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: flat_store_dword v[2:3], v11 ; GFX10-NEXT: s_add_u32 s0, s2, 24
; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: s_waitcnt vmcnt(1) lgkmcnt(3)
; GFX10-NEXT: v_add_nc_u32_e32 v2, 1, v4
; GFX10-NEXT: flat_store_dword v[0:1], v2
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(3) ; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(3)
; GFX10-NEXT: flat_store_dword v[6:7], v10 ; GFX10-NEXT: flat_store_dword v[0:1], v5
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: cluster_load_valu_cluster_store: ; GFX11-LABEL: cluster_load_valu_cluster_store:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: s_clause 0x3
▲ Show 20 Lines • Show All 185 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_add_f32_e32 v4, v4, v8 ; GFX9-NEXT: v_add_f32_e32 v4, v4, v8
; GFX9-NEXT: v_add_f32_e32 v3, v3, v7 ; GFX9-NEXT: v_add_f32_e32 v3, v3, v7
; GFX9-NEXT: v_add_f32_e32 v2, v2, v6 ; GFX9-NEXT: v_add_f32_e32 v2, v2, v6
; GFX9-NEXT: image_store v[2:5], v[0:1], s[12:19] dmask:0xf unorm ; GFX9-NEXT: image_store v[2:5], v[0:1], s[12:19] dmask:0xf unorm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: cluster_image_sample: ; GFX10-LABEL: cluster_image_sample:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_cvt_f32_i32_e32 v8, v0 ; GFX10-NEXT: v_cvt_f32_i32_e32 v12, v0
; GFX10-NEXT: v_cvt_f32_i32_e32 v9, v1
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v10, 1.0 ; GFX10-NEXT: v_cvt_f32_i32_e32 v13, v1
; GFX10-NEXT: v_add_f32_e32 v2, 1.0, v8 ; GFX10-NEXT: v_add_f32_e32 v2, 1.0, v12
; GFX10-NEXT: v_add_f32_e32 v3, 1.0, v9
; GFX10-NEXT: v_mov_b32_e32 v5, v4 ; GFX10-NEXT: v_mov_b32_e32 v5, v4
; GFX10-NEXT: v_add_f32_e32 v3, 1.0, v13
; GFX10-NEXT: v_mov_b32_e32 v6, v4 ; GFX10-NEXT: v_mov_b32_e32 v6, v4
; GFX10-NEXT: v_mov_b32_e32 v7, v4 ; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: v_add_f32_e32 v8, 2.0, v8 ; GFX10-NEXT: image_sample_d v[8:11], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10-NEXT: v_add_f32_e32 v9, 2.0, v9 ; GFX10-NEXT: v_mov_b32_e32 v4, 1.0
; GFX10-NEXT: v_mov_b32_e32 v11, v10 ; GFX10-NEXT: v_add_f32_e32 v2, 2.0, v12
; GFX10-NEXT: v_mov_b32_e32 v12, v10 ; GFX10-NEXT: v_add_f32_e32 v3, 2.0, v13
; GFX10-NEXT: v_mov_b32_e32 v13, v10 ; GFX10-NEXT: v_mov_b32_e32 v5, v4
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: v_mov_b32_e32 v6, v4
; GFX10-NEXT: image_sample_d v[14:17], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: image_sample_d v[18:21], v[8:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; GFX10-NEXT: image_sample_d v[2:5], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_f32_e32 v5, v17, v21 ; GFX10-NEXT: v_add_f32_e32 v5, v11, v5
; GFX10-NEXT: v_add_f32_e32 v4, v16, v20 ; GFX10-NEXT: v_add_f32_e32 v4, v10, v4
; GFX10-NEXT: v_add_f32_e32 v3, v15, v19 ; GFX10-NEXT: v_add_f32_e32 v3, v9, v3
; GFX10-NEXT: v_add_f32_e32 v2, v14, v18 ; GFX10-NEXT: v_add_f32_e32 v2, v8, v2
; GFX10-NEXT: image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ; GFX10-NEXT: image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: cluster_image_sample: ; GFX11-LABEL: cluster_image_sample:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cvt_f32_i32_e32 v9, v1 ; GFX11-NEXT: v_cvt_f32_i32_e32 v9, v1
; GFX11-NEXT: v_cvt_f32_i32_e32 v8, v0 ; GFX11-NEXT: v_cvt_f32_i32_e32 v8, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
Show All 35 Lines

llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll

Show First 20 Lines • Show All 991 Lines • ▼ Show 20 Lines
; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX10-LABEL: load_v4i8_to_v4f32_unaligned: ; GFX10-LABEL: load_v4i8_to_v4f32_unaligned:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v6, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x3 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3] offset:3 ; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3] offset:3
; GFX10-NEXT: global_load_ubyte v2, v0, s[2:3] offset:2 ; GFX10-NEXT: global_load_ubyte v2, v0, s[2:3] offset:2
; GFX10-NEXT: global_load_ubyte v4, v0, s[2:3] offset:1 ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: global_load_ubyte v5, v0, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, v1 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, v1
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3] offset:1
; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v2, v2 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, v4 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v5 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX10-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1] ; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-LABEL: load_v4i8_to_v4f32_unaligned: ; GFX9-LABEL: load_v4i8_to_v4f32_unaligned:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_or_b32_e32 v0, v0, v1 ; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX10-LABEL: load_v4i8_to_v4f32_2_uses: ; GFX10-LABEL: load_v4i8_to_v4f32_2_uses:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v1, 24 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] ; GFX10-NEXT: global_load_dword v4, v0, s[2:3]
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v3, v4
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v2, v4
; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff00, v0 ; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
; GFX10-NEXT: v_add_nc_u16 v4, v0, 9 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v4
; GFX10-NEXT: v_add_nc_u16 v2, v2, 9 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v5, v[0:3], s[0:1]
; GFX10-NEXT: v_mov_b32_e32 v0, 24
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v4
; GFX10-NEXT: v_add_nc_u16 v2, v4, 9
; GFX10-NEXT: v_lshrrev_b32_sdwa v0, v0, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_add_nc_u16 v1, v1, 9
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff00, v4
; GFX10-NEXT: v_add_nc_u16 v0, v0, 0x900
; GFX10-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_or_b32_sdwa v2, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
; GFX10-NEXT: v_add_nc_u16 v1, v1, 0x900 ; GFX10-NEXT: v_add_nc_u16 v1, v1, 0x900
; GFX10-NEXT: v_add_nc_u16 v5, v2, 0x900 ; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v2, v0 ; GFX10-NEXT: global_store_dword v5, v0, s[2:3]
; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX10-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: global_store_dword v4, v5, s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-LABEL: load_v4i8_to_v4f32_2_uses: ; GFX9-LABEL: load_v4i8_to_v4f32_2_uses:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_mov_b32_e32 v6, 9 ; GFX9-NEXT: v_mov_b32_e32 v6, 9
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; VI-NEXT: v_cvt_f32_ubyte0_e32 v4, v9 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v4, v9
; VI-NEXT: buffer_store_dwordx3 v[4:6], off, s[0:3], 0 offset:16 ; VI-NEXT: buffer_store_dwordx3 v[4:6], off, s[0:3], 0 offset:16
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX10-LABEL: load_v7i8_to_v7f32: ; GFX10-LABEL: load_v7i8_to_v7f32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: v_mov_b32_e32 v6, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x5 ; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: global_load_ubyte v4, v0, s[2:3] offset:6 ; GFX10-NEXT: global_load_ubyte v5, v4, s[2:3] offset:6
; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3] offset:3 ; GFX10-NEXT: global_load_ubyte v0, v4, s[2:3] offset:3
; GFX10-NEXT: global_load_ubyte v2, v0, s[2:3] offset:2 ; GFX10-NEXT: global_load_ubyte v1, v4, s[2:3] offset:2
; GFX10-NEXT: global_load_ubyte v5, v0, s[2:3] offset:1 ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: global_load_short_d16 v7, v0, s[2:3] offset:4 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, v0
; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] ; GFX10-NEXT: global_load_ubyte v0, v4, s[2:3] offset:1
; GFX10-NEXT: s_waitcnt vmcnt(5)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, v4
; GFX10-NEXT: s_waitcnt vmcnt(4)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, v1
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, v5
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v5, v7 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v2, v1
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v4, v7
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, v0
; GFX10-NEXT: global_load_ubyte v0, v4, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX10-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1]
; GFX10-NEXT: global_load_short_d16 v0, v4, s[2:3] offset:4
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v2, v5
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX10-NEXT: global_store_dwordx3 v8, v[4:6], s[0:1] offset:16 ; GFX10-NEXT: global_store_dwordx3 v6, v[0:2], s[0:1] offset:16
; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-LABEL: load_v7i8_to_v7f32: ; GFX9-LABEL: load_v7i8_to_v7f32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX9-NEXT: v_mov_b32_e32 v10, 0 ; GFX9-NEXT: v_mov_b32_e32 v10, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 ; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX10-LABEL: load_v8i8_to_v8f32: ; GFX10-LABEL: load_v8i8_to_v8f32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX10-NEXT: v_mov_b32_e32 v10, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dwordx2 v[8:9], v0, s[2:3] ; GFX10-NEXT: global_load_dwordx2 v[4:5], v0, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v7, v9 ; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v3, v5
; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v6, v9 ; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v2, v5
; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v5, v9 ; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v1, v5
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v4, v9 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v5
; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v3, v8 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v2, v8 ; GFX10-NEXT: global_store_dwordx4 v5, v[0:3], s[0:1] offset:16
; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v1, v8 ; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v3, v4
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v8 ; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v2, v4
; GFX10-NEXT: global_store_dwordx4 v10, v[4:7], s[0:1] offset:16 ; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
; GFX10-NEXT: global_store_dwordx4 v10, v[0:3], s[0:1] ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v4
; GFX10-NEXT: global_store_dwordx4 v5, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-LABEL: load_v8i8_to_v8f32: ; GFX9-LABEL: load_v8i8_to_v8f32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX9-NEXT: v_mov_b32_e32 v9, 0 ; GFX9-NEXT: v_mov_b32_e32 v9, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX10-LABEL: v4i8_zext_v4i32_to_v4f32: ; GFX10-LABEL: v4i8_zext_v4i32_to_v4f32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v6, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x3 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3] offset:3 ; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3] offset:3
; GFX10-NEXT: global_load_ubyte v2, v0, s[2:3] offset:2 ; GFX10-NEXT: global_load_ubyte v2, v0, s[2:3] offset:2
; GFX10-NEXT: global_load_ubyte v4, v0, s[2:3] offset:1 ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: global_load_ubyte v5, v0, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, v1 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, v1
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3] offset:1
; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v2, v2 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, v4 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v5 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX10-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1] ; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-LABEL: v4i8_zext_v4i32_to_v4f32: ; GFX9-LABEL: v4i8_zext_v4i32_to_v4f32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
define amdgpu_ps float @_amdgpu_ps_main() #0 { define amdgpu_ps float @_amdgpu_ps_main() #0 {
; GCN-LABEL: _amdgpu_ps_main: ; GCN-LABEL: _amdgpu_ps_main:
; GCN: ; %bb.0: ; %.entry ; GCN: ; %bb.0: ; %.entry
; GCN-NEXT: image_sample v[0:1], v[0:1], s[0:7], s[0:3] dmask:0x3 dim:SQ_RSRC_IMG_2D ; GCN-NEXT: image_sample v[0:1], v[0:1], s[0:7], s[0:3] dmask:0x3 dim:SQ_RSRC_IMG_2D
; GCN-NEXT: v_mov_b32_e32 v4, 0 ; GCN-NEXT: s_clause 0x2
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_buffer_load_dword s8, s[0:3], 0x5c
; GCN-NEXT: s_clause 0x1 ; GCN-NEXT: s_buffer_load_dword s9, s[0:3], 0x7c
; GCN-NEXT: image_sample v2, v[0:1], s[0:7], s[0:3] dmask:0x4 dim:SQ_RSRC_IMG_2D
; GCN-NEXT: image_sample v3, v[0:1], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: image_load_mip v4, v[2:4], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D unorm
; GCN-NEXT: s_clause 0x3
; GCN-NEXT: s_buffer_load_dword s24, s[0:3], 0x5c
; GCN-NEXT: s_buffer_load_dword s28, s[0:3], 0x7c
; GCN-NEXT: s_buffer_load_dword s29, s[0:3], 0xc0
; GCN-NEXT: s_waitcnt_depctr 0xffe3 ; GCN-NEXT: s_waitcnt_depctr 0xffe3
; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_nop 0
; GCN-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], 0x40 ; GCN-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], 0x60
; GCN-NEXT: ; kill: killed $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_clause 0x1 ; GCN-NEXT: s_buffer_load_dwordx4 s[4:7], s[0:3], 0x20
; GCN-NEXT: v_sub_f32_e64 v2, s8, s9
; GCN-NEXT: ; kill: killed $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-NEXT: ; kill: killed $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-NEXT: ; kill: killed $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mul_f32_e32 v3, s2, v0
; GCN-NEXT: v_fma_f32 v1, v1, v2, s9
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_fma_f32 v0, -v0, s2, s6
; GCN-NEXT: v_max_f32_e64 v2, s0, s0 clamp
; GCN-NEXT: v_fmac_f32_e32 v3, v0, v2
; GCN-NEXT: image_sample v0, v[0:1], s[0:7], s[0:3] dmask:0x4 dim:SQ_RSRC_IMG_2D
; GCN-NEXT: s_waitcnt_depctr 0xffe3
; GCN-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], 0x40
; GCN-NEXT: ; kill: killed $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-NEXT: ; kill: killed $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mad_f32 v5, s2, v2, v0
; GCN-NEXT: s_buffer_load_dwordx4 s[4:7], s[0:3], 0x50 ; GCN-NEXT: s_buffer_load_dwordx4 s[4:7], s[0:3], 0x50
; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_fma_f32 v4, -s2, v2, s6
; GCN-NEXT: s_buffer_load_dword s0, s[0:3], 0x2c ; GCN-NEXT: s_buffer_load_dword s0, s[0:3], 0x2c
; GCN-NEXT: v_sub_f32_e64 v5, s24, s28 ; GCN-NEXT: v_fmac_f32_e32 v5, v4, v2
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_clause 0x4 ; GCN-NEXT: v_sub_f32_e32 v4, s0, v1
; GCN-NEXT: s_buffer_load_dwordx4 s[8:11], s[0:3], 0x60 ; GCN-NEXT: v_fmac_f32_e32 v1, v2, v4
; GCN-NEXT: s_buffer_load_dwordx4 s[12:15], s[0:3], 0x20 ; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: s_buffer_load_dwordx4 s[16:19], s[0:3], 0x0 ; GCN-NEXT: image_load_mip v4, v[2:4], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D unorm
; GCN-NEXT: s_buffer_load_dwordx4 s[20:23], s[0:3], 0x70 ; GCN-NEXT: s_waitcnt_depctr 0xffe3
; GCN-NEXT: s_buffer_load_dwordx4 s[24:27], s[0:3], 0x10 ; GCN-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], 0x70
; GCN-NEXT: v_fma_f32 v1, v1, v5, s28 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_max_f32_e64 v6, s0, s0 clamp ; GCN-NEXT: v_add_f32_e32 v4, v4, v5
; GCN-NEXT: v_add_f32_e64 v5, s29, -1.0
; GCN-NEXT: v_sub_f32_e32 v8, s0, v1
; GCN-NEXT: v_fma_f32 v7, -s2, v6, s6
; GCN-NEXT: v_fma_f32 v5, v6, v5, 1.0
; GCN-NEXT: v_mad_f32 v10, s2, v6, v2
; GCN-NEXT: s_mov_b32 s0, 0x3c23d70a
; GCN-NEXT: v_fmac_f32_e32 v1, v6, v8
; GCN-NEXT: v_fmac_f32_e32 v10, v7, v6
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mul_f32_e32 v9, s10, v0 ; GCN-NEXT: image_sample v5, v[0:1], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GCN-NEXT: v_fma_f32 v0, -v0, s10, s14
; GCN-NEXT: v_mul_f32_e32 v8, s18, v2
; GCN-NEXT: v_mul_f32_e32 v3, s22, v3
; GCN-NEXT: v_fmac_f32_e32 v9, v0, v6
; GCN-NEXT: v_sub_f32_e32 v0, v1, v5
; GCN-NEXT: v_mul_f32_e32 v1, v8, v6
; GCN-NEXT: v_mul_f32_e32 v7, v6, v3
; GCN-NEXT: v_fma_f32 v3, -v6, v3, v9
; GCN-NEXT: v_fmac_f32_e32 v5, v0, v6
; GCN-NEXT: v_fma_f32 v0, v2, s26, -v1
; GCN-NEXT: v_fmac_f32_e32 v7, v3, v6
; GCN-NEXT: v_fmac_f32_e32 v1, v0, v6
; GCN-NEXT: v_mul_f32_e32 v0, v2, v6
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_f32_e32 v4, v4, v10 ; GCN-NEXT: v_mul_f32_e32 v5, s2, v5
; GCN-NEXT: v_mul_f32_e32 v3, v4, v6 ; GCN-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], 0x0
; GCN-NEXT: v_fmaak_f32 v4, s0, v5, 0x3ca3d70a ; GCN-NEXT: ; kill: killed $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-NEXT: v_mul_f32_e32 v1, v3, v1 ; GCN-NEXT: ; kill: killed $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-NEXT: v_mul_f32_e32 v2, v7, v4 ; GCN-NEXT: v_fma_f32 v3, -v2, v5, v3
; GCN-NEXT: v_mul_f32_e32 v5, v2, v5
; GCN-NEXT: v_fmac_f32_e32 v5, v3, v2
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: s_buffer_load_dwordx4 s[4:7], s[0:3], 0x10
; GCN-NEXT: s_nop 0
; GCN-NEXT: s_buffer_load_dword s0, s[0:3], 0xc0
; GCN-NEXT: v_mul_f32_e32 v3, s2, v0
; GCN-NEXT: v_mul_f32_e32 v3, v3, v2
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_fma_f32 v6, v0, s6, -v3
; GCN-NEXT: v_mul_f32_e32 v0, v0, v2
; GCN-NEXT: v_fmac_f32_e32 v3, v6, v2
; GCN-NEXT: v_add_f32_e64 v6, s0, -1.0
; GCN-NEXT: s_mov_b32 s0, 0x3c23d70a
; GCN-NEXT: v_fma_f32 v6, v2, v6, 1.0
; GCN-NEXT: v_sub_f32_e32 v1, v1, v6
; GCN-NEXT: v_fmac_f32_e32 v6, v1, v2
; GCN-NEXT: v_mul_f32_e32 v1, v4, v2
; GCN-NEXT: v_fmaak_f32 v2, s0, v6, 0x3ca3d70a
; GCN-NEXT: v_mul_f32_e32 v1, v1, v3
; GCN-NEXT: v_mul_f32_e32 v2, v5, v2
; GCN-NEXT: v_fmac_f32_e32 v1, v2, v0 ; GCN-NEXT: v_fmac_f32_e32 v1, v2, v0
; GCN-NEXT: v_max_f32_e32 v0, 0, v1 ; GCN-NEXT: v_max_f32_e32 v0, 0, v1
; GCN-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
.entry: .entry:
%0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0) %0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
%.i2243 = extractelement <3 x float> %0, i32 2 %.i2243 = extractelement <3 x float> %0, i32 2
%1 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 0, i32 0) %1 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 0, i32 0)
%2 = shufflevector <3 x i32> %1, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> %2 = shufflevector <3 x i32> %1, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
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llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: write_ds_sub0_offset0_global_clamp_bit: ; GFX10-LABEL: write_ds_sub0_offset0_global_clamp_bit:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX10-NEXT: s_mov_b32 vcc_lo, 0 ; GFX10-NEXT: s_mov_b32 vcc_lo, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0x7b ; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0, v0
; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0, v0 ; GFX10-NEXT: ds_write_b32 v0, v1 offset:12
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: ds_write_b32 v2, v3 offset:12
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_div_fmas_f32 v4, s0, s0, s0 ; GFX10-NEXT: v_div_fmas_f32 v2, s0, s0, s0
; GFX10-NEXT: global_store_dword v[0:1], v4, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: write_ds_sub0_offset0_global_clamp_bit: ; GFX11-LABEL: write_ds_sub0_offset0_global_clamp_bit:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
; GFX11-NEXT: v_dual_mov_b32 v3, 0x7b :: v_dual_lshlrev_b32 v0, 2, v0 ; GFX11-NEXT: v_dual_mov_b32 v3, 0x7b :: v_dual_lshlrev_b32 v0, 2, v0
; GFX11-NEXT: s_mov_b32 vcc_lo, 0 ; GFX11-NEXT: s_mov_b32 vcc_lo, 0
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: write_ds_sub_max_offset_global_clamp_bit: ; GFX10-LABEL: write_ds_sub_max_offset_global_clamp_bit:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-NEXT: v_not_b32_e32 v0, v0 ; GFX10-NEXT: v_not_b32_e32 v0, v0
; GFX10-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX10-NEXT: s_mov_b32 vcc_lo, 0 ; GFX10-NEXT: s_mov_b32 vcc_lo, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0x7b ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX10-NEXT: ds_write_b32 v0, v1 offset:65532
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: ds_write_b32 v2, v3 offset:65532
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_div_fmas_f32 v4, s0, s0, s0 ; GFX10-NEXT: v_div_fmas_f32 v2, s0, s0, s0
; GFX10-NEXT: global_store_dword v[0:1], v4, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: write_ds_sub_max_offset_global_clamp_bit: ; GFX11-LABEL: write_ds_sub_max_offset_global_clamp_bit:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
; GFX11-NEXT: v_not_b32_e32 v0, v0 ; GFX11-NEXT: v_not_b32_e32 v0, v0
; GFX11-NEXT: s_mov_b32 vcc_lo, 0 ; GFX11-NEXT: s_mov_b32 vcc_lo, 0
▲ Show 20 Lines • Show All 367 Lines • ▼ Show 20 Lines
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit: ; GFX10-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_mov_b32_e32 v2, 0x7b
; GFX10-NEXT: s_mov_b32 vcc_lo, 0 ; GFX10-NEXT: s_mov_b32 vcc_lo, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0, v0
; GFX10-NEXT: v_mov_b32_e32 v4, 0x7b ; GFX10-NEXT: ds_write_b32 v0, v1 offset:1023
; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0, v0 ; GFX10-NEXT: ds_write_b32 v0, v2 offset:1019
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: ds_write_b32 v2, v3 offset:1023
; GFX10-NEXT: ds_write_b32 v2, v4 offset:1019
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_div_fmas_f32 v5, s0, s0, s0 ; GFX10-NEXT: v_div_fmas_f32 v2, s0, s0, s0
; GFX10-NEXT: global_store_dword v[0:1], v5, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit: ; GFX11-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
; GFX11-NEXT: v_dual_mov_b32 v3, 0x7b :: v_dual_lshlrev_b32 v0, 2, v0 ; GFX11-NEXT: v_dual_mov_b32 v3, 0x7b :: v_dual_lshlrev_b32 v0, 2, v0
; GFX11-NEXT: s_mov_b32 vcc_lo, 0 ; GFX11-NEXT: s_mov_b32 vcc_lo, 0
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fdiv.ll

Show First 20 Lines • Show All 313 Lines • ▼ Show 20 Linesentry:
store float %fdiv, ptr addrspace(1) %out store float %fdiv, ptr addrspace(1) %out
ret void ret void
} }
; FUNC-LABEL: {{^}}fdiv_f32_denorms_correctly_rounded_divide_sqrt: ; FUNC-LABEL: {{^}}fdiv_f32_denorms_correctly_rounded_divide_sqrt:
; GCN: v_div_scale_f32 [[NUM_SCALE:v[0-9]+]] ; GCN: v_div_scale_f32 [[NUM_SCALE:v[0-9]+]]
; GCN-DAG: v_rcp_f32_e32 [[NUM_RCP:v[0-9]+]], [[NUM_SCALE]] ; PREGFX10-DAG: v_rcp_f32_e32 [[NUM_RCP:v[0-9]+]], [[NUM_SCALE]]
; PREGFX10-DAG: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]] ; PREGFX10-DAG: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]]
; PREGFX10-NOT: s_setreg ; PREGFX10-NOT: s_setreg
; PREGFX10: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0 ; PREGFX10: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0
; PREGFX10: v_fma_f32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]], [[NUM_RCP]] ; PREGFX10: v_fma_f32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]], [[NUM_RCP]]
; PREGFX10: v_mul_f32_e32 [[C:v[0-9]+]], [[DEN_SCALE]], [[B]] ; PREGFX10: v_mul_f32_e32 [[C:v[0-9]+]], [[DEN_SCALE]], [[B]]
; PREGFX10: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]] ; PREGFX10: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]]
; PREGFX10: v_fma_f32 [[E:v[0-9]+]], [[D]], [[B]], [[C]] ; PREGFX10: v_fma_f32 [[E:v[0-9]+]], [[D]], [[B]], [[C]]
; PREGFX10: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]] ; PREGFX10: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
; PREGFX10-NOT: s_setreg ; PREGFX10-NOT: s_setreg
; GFX10-NOT: s_denorm_mode ; GFX10-NOT: s_denorm_mode
; GFX10: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0 ; GFX10-DAG: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]], {{[^,]+}}, 1.0
; GFX10: v_fmac_f32_e32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]] ; GFX10-DAG: v_rcp_f32_e32 [[NUM_RCP:v[0-9]+]], [[NUM_SCALE]]
; GFX10: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]] ; GFX10-DAG: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0
; GFX10-DAG: v_fmac_f32_e32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]]
; GFX10: v_mul_f32_e32 [[C:v[0-9]+]], [[DEN_SCALE]], [[B]] ; GFX10: v_mul_f32_e32 [[C:v[0-9]+]], [[DEN_SCALE]], [[B]]
; GFX10: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]] ; GFX10: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]]
; GFX10: v_fmac_f32_e32 [[E:v[0-9]+]], [[D]], [[B]] ; GFX10: v_fmac_f32_e32 [[E:v[0-9]+]], [[D]], [[B]]
; GFX10: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]] ; GFX10: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
; GFX10-NOT: s_denorm_mode ; GFX10-NOT: s_denorm_mode
; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]] ; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
; GCN: v_div_fixup_f32 v{{[0-9]+}}, [[FMAS]], ; GCN: v_div_fixup_f32 v{{[0-9]+}}, [[FMAS]],
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llvm/test/CodeGen/AMDGPU/fshl.ll

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; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX10-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54 ; GFX10-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v0, s7, s11, 1 ; GFX10-NEXT: v_alignbit_b32 v0, s7, s11, 1
; GFX10-NEXT: v_alignbit_b32 v1, s6, s10, 1
; GFX10-NEXT: v_alignbit_b32 v5, s5, s9, 1
; GFX10-NEXT: v_alignbit_b32 v6, s4, s8, 1
; GFX10-NEXT: s_lshr_b32 s2, s7, 1 ; GFX10-NEXT: s_lshr_b32 s2, s7, 1
; GFX10-NEXT: s_not_b32 s3, s15 ; GFX10-NEXT: s_not_b32 s3, s15
; GFX10-NEXT: v_alignbit_b32 v1, s6, s10, 1
; GFX10-NEXT: s_lshr_b32 s6, s6, 1 ; GFX10-NEXT: s_lshr_b32 s6, s6, 1
; GFX10-NEXT: s_not_b32 s7, s14
; GFX10-NEXT: s_lshr_b32 s5, s5, 1
; GFX10-NEXT: s_not_b32 s9, s13
; GFX10-NEXT: s_lshr_b32 s4, s4, 1
; GFX10-NEXT: s_not_b32 s8, s12
; GFX10-NEXT: v_alignbit_b32 v3, s2, v0, s3 ; GFX10-NEXT: v_alignbit_b32 v3, s2, v0, s3
; GFX10-NEXT: v_alignbit_b32 v0, s5, s9, 1
; GFX10-NEXT: s_not_b32 s7, s14
; GFX10-NEXT: s_lshr_b32 s2, s5, 1
; GFX10-NEXT: s_not_b32 s3, s13
; GFX10-NEXT: v_alignbit_b32 v2, s6, v1, s7 ; GFX10-NEXT: v_alignbit_b32 v2, s6, v1, s7
; GFX10-NEXT: v_alignbit_b32 v1, s5, v5, s9 ; GFX10-NEXT: v_alignbit_b32 v1, s2, v0, s3
; GFX10-NEXT: v_alignbit_b32 v0, s4, v6, s8 ; GFX10-NEXT: v_alignbit_b32 v0, s4, s8, 1
; GFX10-NEXT: s_lshr_b32 s2, s4, 1
; GFX10-NEXT: s_not_b32 s3, s12
; GFX10-NEXT: v_alignbit_b32 v0, s2, v0, s3
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] ; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: fshl_v4i32: ; GFX11-LABEL: fshl_v4i32:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_clause 0x2 ; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: s_load_b256 s[4:11], s[0:1], 0x34 ; GFX11-NEXT: s_load_b256 s[4:11], s[0:1], 0x34
; GFX11-NEXT: s_load_b128 s[12:15], s[0:1], 0x54 ; GFX11-NEXT: s_load_b128 s[12:15], s[0:1], 0x54
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llvm/test/CodeGen/AMDGPU/fshr.ll

Show First 20 Lines • Show All 442 Lines • ▼ Show 20 Lines
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, PV.W, ; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, PV.W,
; R600-NEXT: MOV * T1.W, KC0[5].Y, ; R600-NEXT: MOV * T1.W, KC0[5].Y,
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, PV.W, ; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; ;
; GFX10-LABEL: fshr_v4i32: ; GFX10-LABEL: fshr_v4i32:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54 ; GFX10-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54
; GFX10-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v6, 0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s15 ; GFX10-NEXT: v_mov_b32_e32 v0, s15
; GFX10-NEXT: v_mov_b32_e32 v1, s14 ; GFX10-NEXT: v_mov_b32_e32 v1, s14
; GFX10-NEXT: v_mov_b32_e32 v4, s13
; GFX10-NEXT: v_mov_b32_e32 v5, s12
; GFX10-NEXT: v_alignbit_b32 v3, s7, s11, v0 ; GFX10-NEXT: v_alignbit_b32 v3, s7, s11, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s13
; GFX10-NEXT: v_alignbit_b32 v2, s6, s10, v1 ; GFX10-NEXT: v_alignbit_b32 v2, s6, s10, v1
; GFX10-NEXT: v_alignbit_b32 v1, s5, s9, v4 ; GFX10-NEXT: v_alignbit_b32 v1, s5, s9, v0
; GFX10-NEXT: v_alignbit_b32 v0, s4, s8, v5 ; GFX10-NEXT: v_mov_b32_e32 v0, s12
; GFX10-NEXT: global_store_dwordx4 v6, v[0:3], s[2:3] ; GFX10-NEXT: v_alignbit_b32 v0, s4, s8, v0
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: fshr_v4i32: ; GFX11-LABEL: fshr_v4i32:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_clause 0x2 ; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: s_load_b128 s[12:15], s[0:1], 0x54 ; GFX11-NEXT: s_load_b128 s[12:15], s[0:1], 0x54
; GFX11-NEXT: s_load_b256 s[4:11], s[0:1], 0x34 ; GFX11-NEXT: s_load_b256 s[4:11], s[0:1], 0x34
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; GFX10-LABEL: v_fshr_v3i16: ; GFX10-LABEL: v_fshr_v3i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v0 ; GFX10-NEXT: v_lshlrev_b16 v6, 1, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v4 ; GFX10-NEXT: v_xor_b32_e32 v7, -1, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v2 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX10-NEXT: v_xor_b32_e32 v10, -1, v4
; GFX10-NEXT: v_lshlrev_b16 v6, 1, v6
; GFX10-NEXT: v_xor_b32_e32 v9, -1, v7
; GFX10-NEXT: v_lshlrev_b16 v1, 1, v1 ; GFX10-NEXT: v_lshlrev_b16 v1, 1, v1
; GFX10-NEXT: v_lshrrev_b16 v7, v7, v8 ; GFX10-NEXT: v_lshrrev_b16 v3, v5, v3
; GFX10-NEXT: v_lshlrev_b16 v0, v10, v0 ; GFX10-NEXT: v_lshlrev_b16 v6, v7, v6
; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX10-NEXT: v_lshrrev_b16 v2, v4, v2 ; GFX10-NEXT: v_lshrrev_b16 v2, v4, v2
; GFX10-NEXT: v_lshlrev_b16 v6, v9, v6 ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX10-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX10-NEXT: v_or_b32_e32 v2, v6, v2
; GFX10-NEXT: v_lshrrev_b16 v7, v4, v7
; GFX10-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX10-NEXT: v_lshlrev_b16 v0, v4, v0
; GFX10-NEXT: v_xor_b32_e32 v4, -1, v5 ; GFX10-NEXT: v_xor_b32_e32 v4, -1, v5
; GFX10-NEXT: v_lshrrev_b16 v3, v5, v3 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v7
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v5, v6, v7
; GFX10-NEXT: v_lshlrev_b16 v1, v4, v1 ; GFX10-NEXT: v_lshlrev_b16 v1, v4, v1
; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x5040100 ; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x5040100
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_v3i16: ; GFX11-LABEL: v_fshr_v3i16:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v0
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; ;
; GFX10-LABEL: v_fshr_v4i16: ; GFX10-LABEL: v_fshr_v4i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v5
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v4 ; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v2 ; GFX10-NEXT: v_lshlrev_b16 v1, 1, v1
; GFX10-NEXT: v_lshrrev_b16 v6, v7, v6 ; GFX10-NEXT: v_lshrrev_b16 v6, v7, v6
; GFX10-NEXT: v_lshlrev_b16 v8, 1, v8 ; GFX10-NEXT: v_lshlrev_b16 v8, 1, v8
; GFX10-NEXT: v_xor_b32_e32 v7, -1, v7 ; GFX10-NEXT: v_xor_b32_e32 v7, -1, v7
; GFX10-NEXT: v_lshlrev_b16 v9, 1, v9 ; GFX10-NEXT: v_lshlrev_b16 v10, 1, v10
; GFX10-NEXT: v_xor_b32_e32 v12, -1, v10
; GFX10-NEXT: v_lshlrev_b16 v1, 1, v1
; GFX10-NEXT: v_xor_b32_e32 v13, -1, v5
; GFX10-NEXT: v_lshlrev_b16 v0, 1, v0 ; GFX10-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX10-NEXT: v_xor_b32_e32 v14, -1, v4 ; GFX10-NEXT: v_lshrrev_b16 v3, v5, v3
; GFX10-NEXT: v_lshlrev_b16 v7, v7, v8 ; GFX10-NEXT: v_lshlrev_b16 v7, v7, v8
; GFX10-NEXT: v_lshrrev_b16 v8, v10, v11 ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX10-NEXT: v_lshlrev_b16 v9, v12, v9
; GFX10-NEXT: v_lshlrev_b16 v1, v13, v1
; GFX10-NEXT: v_lshlrev_b16 v0, v14, v0
; GFX10-NEXT: v_lshrrev_b16 v2, v4, v2 ; GFX10-NEXT: v_lshrrev_b16 v2, v4, v2
; GFX10-NEXT: v_lshrrev_b16 v3, v5, v3 ; GFX10-NEXT: v_lshrrev_b16 v8, v9, v8
; GFX10-NEXT: v_or_b32_e32 v4, v7, v6 ; GFX10-NEXT: v_xor_b32_e32 v9, -1, v9
; GFX10-NEXT: v_lshlrev_b16 v9, v9, v10
; GFX10-NEXT: v_xor_b32_e32 v10, -1, v5
; GFX10-NEXT: v_or_b32_e32 v5, v9, v8 ; GFX10-NEXT: v_or_b32_e32 v5, v9, v8
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX10-NEXT: v_lshlrev_b16 v1, v10, v1
; GFX10-NEXT: v_xor_b32_e32 v10, -1, v4
; GFX10-NEXT: v_or_b32_e32 v4, v7, v6
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x5040100 ; GFX10-NEXT: v_lshlrev_b16 v0, v10, v0
; GFX10-NEXT: v_perm_b32 v1, v4, v1, 0x5040100 ; GFX10-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_v4i16: ; GFX11-LABEL: v_fshr_v4i16:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v3 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v5
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; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; GFX10-LABEL: v_fshr_i64: ; GFX10-LABEL: v_fshr_i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX10-NEXT: v_not_b32_e32 v5, v4
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v4, v[2:3] ; GFX10-NEXT: v_lshrrev_b64 v[2:3], v4, v[2:3]
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v5, v[0:1] ; GFX10-NEXT: v_not_b32_e32 v4, v4
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_i64: ; GFX11-LABEL: v_fshr_i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; GFX10-LABEL: v_fshr_v2i64: ; GFX10-LABEL: v_fshr_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX10-NEXT: v_not_b32_e32 v9, v8
; GFX10-NEXT: v_not_b32_e32 v11, v10
; GFX10-NEXT: v_lshrrev_b64 v[4:5], v8, v[4:5] ; GFX10-NEXT: v_lshrrev_b64 v[4:5], v8, v[4:5]
; GFX10-NEXT: v_lshrrev_b64 v[6:7], v10, v[6:7] ; GFX10-NEXT: v_not_b32_e32 v8, v8
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX10-NEXT: v_lshlrev_b64 v[2:3], v11, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
; GFX10-NEXT: v_or_b32_e32 v1, v1, v5 ; GFX10-NEXT: v_or_b32_e32 v1, v1, v5
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6 ; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
; GFX10-NEXT: v_or_b32_e32 v3, v3, v7 ; GFX10-NEXT: v_lshrrev_b64 v[4:5], v10, v[6:7]
; GFX10-NEXT: v_not_b32_e32 v6, v10
; GFX10-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3]
; GFX10-NEXT: v_or_b32_e32 v2, v2, v4
; GFX10-NEXT: v_or_b32_e32 v3, v3, v5
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_v2i64: ; GFX11-LABEL: v_fshr_v2i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] ; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
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; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; GFX10-LABEL: v_fshr_v2i24: ; GFX10-LABEL: v_fshr_v2i24:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v4 ; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v4
; GFX10-NEXT: v_and_b32_e32 v7, 0xffffff, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 8, v3 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX10-NEXT: v_mul_hi_u32 v6, 0xaaaaaab, v6 ; GFX10-NEXT: v_mul_hi_u32 v6, 0xaaaaaab, v6
; GFX10-NEXT: v_mul_hi_u32 v7, 0xaaaaaab, v7
; GFX10-NEXT: v_mul_u32_u24_e32 v6, 24, v6 ; GFX10-NEXT: v_mul_u32_u24_e32 v6, 24, v6
; GFX10-NEXT: v_mul_u32_u24_e32 v7, 24, v7
; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6 ; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6
; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v7
; GFX10-NEXT: v_add_nc_u32_e32 v4, 8, v4 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 8, v4
; GFX10-NEXT: v_add_nc_u32_e32 v5, 8, v5
; GFX10-NEXT: v_alignbit_b32 v0, v0, v2, v4 ; GFX10-NEXT: v_alignbit_b32 v0, v0, v2, v4
; GFX10-NEXT: v_alignbit_b32 v1, v1, v3, v5 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v5
; GFX10-NEXT: v_mul_hi_u32 v2, 0xaaaaaab, v2
; GFX10-NEXT: v_mul_u32_u24_e32 v2, 24, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v2, v5, v2
; GFX10-NEXT: v_add_nc_u32_e32 v2, 8, v2
; GFX10-NEXT: v_alignbit_b32 v1, v1, v3, v2
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_v2i24: ; GFX11-LABEL: v_fshr_v2i24:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v4 ; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v4
; GFX11-NEXT: v_and_b32_e32 v7, 0xffffff, v5 ; GFX11-NEXT: v_and_b32_e32 v7, 0xffffff, v5
Show All 21 Lines

llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll

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Show First 20 Lines • Show All 991 Lines • ▼ Show 20 Lines
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v41, s34, 0 ; GFX10-NEXT: v_writelane_b32 v41, s34, 0
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[36:37]
; GFX10-NEXT: s_add_u32 s36, s36, external_void_func_v8i32@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s37, s37, external_void_func_v8i32@rel32@hi+12
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx4 v[0:3], v8, s[34:35] ; GFX10-NEXT: global_load_dwordx4 v[0:3], v8, s[34:35]
; GFX10-NEXT: global_load_dwordx4 v[4:7], v8, s[34:35] offset:16 ; GFX10-NEXT: global_load_dwordx4 v[4:7], v8, s[34:35] offset:16
; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_getpc_b64 s[34:35] ; GFX10-NEXT: s_swappc_b64 s[30:31], s[36:37]
; GFX10-NEXT: s_add_u32 s34, s34, external_void_func_v8i32@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_v8i32@rel32@hi+12
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s34, v41, 0 ; GFX10-NEXT: v_readlane_b32 s34, v41, 0
; GFX10-NEXT: s_or_saveexec_b32 s35, -1 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
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; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v41, s0, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v41, s0, 0
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v8, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: s_getpc_b64 s[2:3]
; GFX10-SCRATCH-NEXT: s_add_u32 s2, s2, external_void_func_v8i32@rel32@lo+4
; GFX10-SCRATCH-NEXT: s_addc_u32 s3, s3, external_void_func_v8i32@rel32@hi+12
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v8, s[0:1] ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v8, s[0:1]
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v8, s[0:1] offset:16 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v8, s[0:1] offset:16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_getpc_b64 s[0:1] ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX10-SCRATCH-NEXT: s_add_u32 s0, s0, external_void_func_v8i32@rel32@lo+4
; GFX10-SCRATCH-NEXT: s_addc_u32 s1, s1, external_void_func_v8i32@rel32@hi+12
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v41, 0 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v41, 0
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33 offset:4 ; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33 offset:4
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
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; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v41, s34, 0 ; GFX10-NEXT: v_writelane_b32 v41, s34, 0
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: v_mov_b32_e32 v16, 0 ; GFX10-NEXT: v_mov_b32_e32 v16, 0
; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[36:37]
; GFX10-NEXT: s_add_u32 s36, s36, external_void_func_v16i32@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s37, s37, external_void_func_v16i32@rel32@hi+12
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x3 ; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: global_load_dwordx4 v[0:3], v16, s[34:35] ; GFX10-NEXT: global_load_dwordx4 v[0:3], v16, s[34:35]
; GFX10-NEXT: global_load_dwordx4 v[4:7], v16, s[34:35] offset:16 ; GFX10-NEXT: global_load_dwordx4 v[4:7], v16, s[34:35] offset:16
; GFX10-NEXT: global_load_dwordx4 v[8:11], v16, s[34:35] offset:32 ; GFX10-NEXT: global_load_dwordx4 v[8:11], v16, s[34:35] offset:32
; GFX10-NEXT: global_load_dwordx4 v[12:15], v16, s[34:35] offset:48 ; GFX10-NEXT: global_load_dwordx4 v[12:15], v16, s[34:35] offset:48
; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_getpc_b64 s[34:35] ; GFX10-NEXT: s_swappc_b64 s[30:31], s[36:37]
; GFX10-NEXT: s_add_u32 s34, s34, external_void_func_v16i32@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_v16i32@rel32@hi+12
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s34, v41, 0 ; GFX10-NEXT: v_readlane_b32 s34, v41, 0
; GFX10-NEXT: s_or_saveexec_b32 s35, -1 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
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; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v41, s0, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v41, s0, 0
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v16, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v16, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: s_getpc_b64 s[2:3]
; GFX10-SCRATCH-NEXT: s_add_u32 s2, s2, external_void_func_v16i32@rel32@lo+4
; GFX10-SCRATCH-NEXT: s_addc_u32 s3, s3, external_void_func_v16i32@rel32@hi+12
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_clause 0x3 ; GFX10-SCRATCH-NEXT: s_clause 0x3
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v16, s[0:1] ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v16, s[0:1]
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v16, s[0:1] offset:16 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v16, s[0:1] offset:16
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[8:11], v16, s[0:1] offset:32 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[8:11], v16, s[0:1] offset:32
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[12:15], v16, s[0:1] offset:48 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[12:15], v16, s[0:1] offset:48
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_getpc_b64 s[0:1] ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX10-SCRATCH-NEXT: s_add_u32 s0, s0, external_void_func_v16i32@rel32@lo+4
; GFX10-SCRATCH-NEXT: s_addc_u32 s1, s1, external_void_func_v16i32@rel32@hi+12
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v41, 0 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v41, 0
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33 offset:4 ; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33 offset:4
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v41, s34, 0 ; GFX10-NEXT: v_writelane_b32 v41, s34, 0
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: v_mov_b32_e32 v32, 0 ; GFX10-NEXT: v_mov_b32_e32 v32, 0
; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[36:37]
; GFX10-NEXT: s_add_u32 s36, s36, external_void_func_v32i32@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s37, s37, external_void_func_v32i32@rel32@hi+12
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x7 ; GFX10-NEXT: s_clause 0x7
; GFX10-NEXT: global_load_dwordx4 v[0:3], v32, s[34:35] ; GFX10-NEXT: global_load_dwordx4 v[0:3], v32, s[34:35]
; GFX10-NEXT: global_load_dwordx4 v[4:7], v32, s[34:35] offset:16 ; GFX10-NEXT: global_load_dwordx4 v[4:7], v32, s[34:35] offset:16
; GFX10-NEXT: global_load_dwordx4 v[8:11], v32, s[34:35] offset:32 ; GFX10-NEXT: global_load_dwordx4 v[8:11], v32, s[34:35] offset:32
; GFX10-NEXT: global_load_dwordx4 v[12:15], v32, s[34:35] offset:48 ; GFX10-NEXT: global_load_dwordx4 v[12:15], v32, s[34:35] offset:48
; GFX10-NEXT: global_load_dwordx4 v[16:19], v32, s[34:35] offset:64 ; GFX10-NEXT: global_load_dwordx4 v[16:19], v32, s[34:35] offset:64
; GFX10-NEXT: global_load_dwordx4 v[20:23], v32, s[34:35] offset:80 ; GFX10-NEXT: global_load_dwordx4 v[20:23], v32, s[34:35] offset:80
; GFX10-NEXT: global_load_dwordx4 v[24:27], v32, s[34:35] offset:96 ; GFX10-NEXT: global_load_dwordx4 v[24:27], v32, s[34:35] offset:96
; GFX10-NEXT: global_load_dwordx4 v[28:31], v32, s[34:35] offset:112 ; GFX10-NEXT: global_load_dwordx4 v[28:31], v32, s[34:35] offset:112
; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_getpc_b64 s[34:35] ; GFX10-NEXT: s_swappc_b64 s[30:31], s[36:37]
; GFX10-NEXT: s_add_u32 s34, s34, external_void_func_v32i32@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_v32i32@rel32@hi+12
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s34, v41, 0 ; GFX10-NEXT: v_readlane_b32 s34, v41, 0
; GFX10-NEXT: s_or_saveexec_b32 s35, -1 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
Show All 14 Lines
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; GFX11-NEXT: scratch_store_b32 off, v40, s33
; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:4 ; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:4
; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v41, s0, 0 ; GFX11-NEXT: v_writelane_b32 v41, s0, 0
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: v_mov_b32_e32 v28, 0 ; GFX11-NEXT: v_mov_b32_e32 v28, 0
; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v32i32@rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v32i32@rel32@hi+12
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0x7 ; GFX11-NEXT: s_clause 0x7
; GFX11-NEXT: global_load_b128 v[0:3], v28, s[0:1] ; GFX11-NEXT: global_load_b128 v[0:3], v28, s[0:1]
; GFX11-NEXT: global_load_b128 v[4:7], v28, s[0:1] offset:16 ; GFX11-NEXT: global_load_b128 v[4:7], v28, s[0:1] offset:16
; GFX11-NEXT: global_load_b128 v[8:11], v28, s[0:1] offset:32 ; GFX11-NEXT: global_load_b128 v[8:11], v28, s[0:1] offset:32
; GFX11-NEXT: global_load_b128 v[12:15], v28, s[0:1] offset:48 ; GFX11-NEXT: global_load_b128 v[12:15], v28, s[0:1] offset:48
; GFX11-NEXT: global_load_b128 v[16:19], v28, s[0:1] offset:64 ; GFX11-NEXT: global_load_b128 v[16:19], v28, s[0:1] offset:64
; GFX11-NEXT: global_load_b128 v[20:23], v28, s[0:1] offset:80 ; GFX11-NEXT: global_load_b128 v[20:23], v28, s[0:1] offset:80
; GFX11-NEXT: global_load_b128 v[24:27], v28, s[0:1] offset:96 ; GFX11-NEXT: global_load_b128 v[24:27], v28, s[0:1] offset:96
; GFX11-NEXT: global_load_b128 v[28:31], v28, s[0:1] offset:112 ; GFX11-NEXT: global_load_b128 v[28:31], v28, s[0:1] offset:112
; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_v32i32@rel32@lo+4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: s_addc_u32 s1, s1, external_void_func_v32i32@rel32@hi+12
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s0, v41, 0 ; GFX11-NEXT: v_readlane_b32 s0, v41, 0
; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_load_b32 v40, off, s33 ; GFX11-NEXT: scratch_load_b32 v40, off, s33
; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:4 ; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:4
; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: s_mov_b32 exec_lo, s1
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; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v41, s0, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v41, s0, 0
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v32, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v32, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: s_getpc_b64 s[2:3]
; GFX10-SCRATCH-NEXT: s_add_u32 s2, s2, external_void_func_v32i32@rel32@lo+4
; GFX10-SCRATCH-NEXT: s_addc_u32 s3, s3, external_void_func_v32i32@rel32@hi+12
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_clause 0x7 ; GFX10-SCRATCH-NEXT: s_clause 0x7
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v32, s[0:1] ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v32, s[0:1]
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v32, s[0:1] offset:16 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v32, s[0:1] offset:16
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[8:11], v32, s[0:1] offset:32 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[8:11], v32, s[0:1] offset:32
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[12:15], v32, s[0:1] offset:48 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[12:15], v32, s[0:1] offset:48
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[16:19], v32, s[0:1] offset:64 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[16:19], v32, s[0:1] offset:64
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[20:23], v32, s[0:1] offset:80 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[20:23], v32, s[0:1] offset:80
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[24:27], v32, s[0:1] offset:96 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[24:27], v32, s[0:1] offset:96
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[28:31], v32, s[0:1] offset:112 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[28:31], v32, s[0:1] offset:112
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_getpc_b64 s[0:1] ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX10-SCRATCH-NEXT: s_add_u32 s0, s0, external_void_func_v32i32@rel32@lo+4
; GFX10-SCRATCH-NEXT: s_addc_u32 s1, s1, external_void_func_v32i32@rel32@hi+12
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v41, 0 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v41, 0
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33 offset:4 ; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33 offset:4
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
▲ Show 20 Lines • Show All 1,213 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s6, s33 ; GFX10-NEXT: s_mov_b32 s6, s33
; GFX10-NEXT: s_mov_b32 s33, s32 ; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s4, -1 ; GFX10-NEXT: s_or_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s4 ; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:20 ; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s33 offset:20
; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:16 ; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:16
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s33
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_addk_i32 s32, 0x400 ; GFX10-NEXT: s_addk_i32 s32, 0x400
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, byval_align16_f64_arg@rel32@lo+4 ; GFX10-NEXT: s_add_u32 s4, s4, byval_align16_f64_arg@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, byval_align16_f64_arg@rel32@hi+12 ; GFX10-NEXT: s_addc_u32 s5, s5, byval_align16_f64_arg@rel32@hi+12
; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:4
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s33
; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_writelane_b32 v40, s35, 3 ; GFX10-NEXT: v_writelane_b32 v40, s35, 3
; GFX10-NEXT: v_writelane_b32 v40, s36, 4 ; GFX10-NEXT: v_writelane_b32 v40, s36, 4
; GFX10-NEXT: v_writelane_b32 v40, s37, 5 ; GFX10-NEXT: v_writelane_b32 v40, s37, 5
; GFX10-NEXT: v_writelane_b32 v40, s38, 6 ; GFX10-NEXT: v_writelane_b32 v40, s38, 6
; GFX10-NEXT: v_writelane_b32 v40, s39, 7 ; GFX10-NEXT: v_writelane_b32 v40, s39, 7
; GFX10-NEXT: v_writelane_b32 v40, s40, 8 ; GFX10-NEXT: v_writelane_b32 v40, s40, 8
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_mov_b32 s4, s33 ; GFX11-NEXT: s_mov_b32 s4, s33
; GFX11-NEXT: s_mov_b32 s33, s32 ; GFX11-NEXT: s_mov_b32 s33, s32
; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:24 ; 4-byte Folded Spill ; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:24 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0 ; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: scratch_load_b64 v[31:32], off, s33 offset:16
; GFX11-NEXT: scratch_load_b64 v[32:33], off, s33 offset:16
; GFX11-NEXT: scratch_load_b32 v31, off, s33
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_add_i32 s32, s32, 32 ; GFX11-NEXT: s_add_i32 s32, s32, 32
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, byval_align16_f64_arg@rel32@lo+4 ; GFX11-NEXT: s_add_u32 s0, s0, byval_align16_f64_arg@rel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, byval_align16_f64_arg@rel32@hi+12 ; GFX11-NEXT: s_addc_u32 s1, s1, byval_align16_f64_arg@rel32@hi+12
; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_writelane_b32 v40, s34, 2 ; GFX11-NEXT: v_writelane_b32 v40, s34, 2
; GFX11-NEXT: v_writelane_b32 v40, s35, 3 ; GFX11-NEXT: v_writelane_b32 v40, s35, 3
; GFX11-NEXT: v_writelane_b32 v40, s36, 4 ; GFX11-NEXT: v_writelane_b32 v40, s36, 4
; GFX11-NEXT: v_writelane_b32 v40, s37, 5 ; GFX11-NEXT: v_writelane_b32 v40, s37, 5
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; GFX11-NEXT: v_writelane_b32 v40, s56, 24 ; GFX11-NEXT: v_writelane_b32 v40, s56, 24
; GFX11-NEXT: v_writelane_b32 v40, s57, 25 ; GFX11-NEXT: v_writelane_b32 v40, s57, 25
; GFX11-NEXT: v_writelane_b32 v40, s58, 26 ; GFX11-NEXT: v_writelane_b32 v40, s58, 26
; GFX11-NEXT: v_writelane_b32 v40, s59, 27 ; GFX11-NEXT: v_writelane_b32 v40, s59, 27
; GFX11-NEXT: v_writelane_b32 v40, s60, 28 ; GFX11-NEXT: v_writelane_b32 v40, s60, 28
; GFX11-NEXT: v_writelane_b32 v40, s61, 29 ; GFX11-NEXT: v_writelane_b32 v40, s61, 29
; GFX11-NEXT: v_writelane_b32 v40, s62, 30 ; GFX11-NEXT: v_writelane_b32 v40, s62, 30
; GFX11-NEXT: v_writelane_b32 v40, s63, 31 ; GFX11-NEXT: v_writelane_b32 v40, s63, 31
; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: scratch_store_b64 off, v[32:33], s32 ; GFX11-NEXT: scratch_store_b64 off, v[31:32], s32
; GFX11-NEXT: scratch_load_b32 v31, off, s33
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: v_readlane_b32 s63, v40, 31 ; GFX11-NEXT: v_readlane_b32 s63, v40, 31
; GFX11-NEXT: v_readlane_b32 s62, v40, 30 ; GFX11-NEXT: v_readlane_b32 s62, v40, 30
; GFX11-NEXT: v_readlane_b32 s61, v40, 29 ; GFX11-NEXT: v_readlane_b32 s61, v40, 29
; GFX11-NEXT: v_readlane_b32 s60, v40, 28 ; GFX11-NEXT: v_readlane_b32 s60, v40, 28
; GFX11-NEXT: v_readlane_b32 s59, v40, 27 ; GFX11-NEXT: v_readlane_b32 s59, v40, 27
; GFX11-NEXT: v_readlane_b32 s58, v40, 26 ; GFX11-NEXT: v_readlane_b32 s58, v40, 26
; GFX11-NEXT: v_readlane_b32 s57, v40, 25 ; GFX11-NEXT: v_readlane_b32 s57, v40, 25
Show All 35 Lines
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-SCRATCH-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s4, s33 ; GFX10-SCRATCH-NEXT: s_mov_b32 s4, s33
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32 ; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s0, -1 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s0, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:24 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:24 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s0 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s0
; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[31:32], off, s33 offset:16
; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[32:33], off, s33 offset:16
; GFX10-SCRATCH-NEXT: scratch_load_dword v31, off, s33
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_getpc_b64 s[0:1] ; GFX10-SCRATCH-NEXT: s_getpc_b64 s[0:1]
; GFX10-SCRATCH-NEXT: s_add_u32 s0, s0, byval_align16_f64_arg@rel32@lo+4 ; GFX10-SCRATCH-NEXT: s_add_u32 s0, s0, byval_align16_f64_arg@rel32@lo+4
; GFX10-SCRATCH-NEXT: s_addc_u32 s1, s1, byval_align16_f64_arg@rel32@hi+12 ; GFX10-SCRATCH-NEXT: s_addc_u32 s1, s1, byval_align16_f64_arg@rel32@hi+12
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s35, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s35, 3
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s36, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s36, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s37, 5 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s37, 5
Show All 18 Lines
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s56, 24 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s56, 24
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s57, 25 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s57, 25
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s58, 26 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s58, 26
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s59, 27 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s59, 27
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s60, 28 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s60, 28
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s61, 29 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s61, 29
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s62, 30 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s62, 30
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s63, 31 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s63, 31
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(1) ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[32:33], s32 ; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[31:32], s32
; GFX10-SCRATCH-NEXT: scratch_load_dword v31, off, s33
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s63, v40, 31 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s63, v40, 31
; GFX10-SCRATCH-NEXT: v_readlane_b32 s62, v40, 30 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s62, v40, 30
; GFX10-SCRATCH-NEXT: v_readlane_b32 s61, v40, 29 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s61, v40, 29
; GFX10-SCRATCH-NEXT: v_readlane_b32 s60, v40, 28 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s60, v40, 28
; GFX10-SCRATCH-NEXT: v_readlane_b32 s59, v40, 27 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s59, v40, 27
; GFX10-SCRATCH-NEXT: v_readlane_b32 s58, v40, 26 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s58, v40, 26
; GFX10-SCRATCH-NEXT: v_readlane_b32 s57, v40, 25 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s57, v40, 25
▲ Show 20 Lines • Show All 1,982 Lines • ▼ Show 20 Lines
; GFX10-NEXT: v_writelane_b32 v40, s21, 17 ; GFX10-NEXT: v_writelane_b32 v40, s21, 17
; GFX10-NEXT: v_writelane_b32 v40, s22, 18 ; GFX10-NEXT: v_writelane_b32 v40, s22, 18
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s46 ; GFX10-NEXT: v_mov_b32_e32 v0, s46
; GFX10-NEXT: v_writelane_b32 v40, s23, 19 ; GFX10-NEXT: v_writelane_b32 v40, s23, 19
; GFX10-NEXT: v_mov_b32_e32 v1, s47 ; GFX10-NEXT: v_mov_b32_e32 v1, s47
; GFX10-NEXT: v_mov_b32_e32 v2, s48 ; GFX10-NEXT: v_mov_b32_e32 v2, s48
; GFX10-NEXT: v_mov_b32_e32 v3, s49 ; GFX10-NEXT: v_mov_b32_e32 v3, s49
; GFX10-NEXT: s_mov_b32 s20, s36 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX10-NEXT: v_writelane_b32 v40, s24, 20 ; GFX10-NEXT: v_writelane_b32 v40, s24, 20
; GFX10-NEXT: v_mov_b32_e32 v0, s50
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX10-NEXT: v_mov_b32_e32 v1, s51
; GFX10-NEXT: s_mov_b32 s20, s36
; GFX10-NEXT: v_writelane_b32 v40, s25, 21
; GFX10-NEXT: s_mov_b32 s21, s37 ; GFX10-NEXT: s_mov_b32 s21, s37
; GFX10-NEXT: s_mov_b32 s22, s38 ; GFX10-NEXT: s_mov_b32 s22, s38
; GFX10-NEXT: s_mov_b32 s23, s39 ; GFX10-NEXT: s_mov_b32 s23, s39
; GFX10-NEXT: s_mov_b32 s24, s40 ; GFX10-NEXT: s_mov_b32 s24, s40
; GFX10-NEXT: v_writelane_b32 v40, s25, 21 ; GFX10-NEXT: v_writelane_b32 v40, s26, 22
; GFX10-NEXT: s_mov_b32 s25, s41 ; GFX10-NEXT: s_mov_b32 s25, s41
; GFX10-NEXT: v_mov_b32_e32 v4, s50 ; GFX10-NEXT: s_mov_b32 s26, s42
; GFX10-NEXT: v_mov_b32_e32 v5, s51
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12 ; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12
; GFX10-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:16 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; GFX10-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:20 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:20
; GFX10-NEXT: v_writelane_b32 v40, s26, 22
; GFX10-NEXT: s_mov_b32 s26, s42
; GFX10-NEXT: v_writelane_b32 v40, s27, 23 ; GFX10-NEXT: v_writelane_b32 v40, s27, 23
; GFX10-NEXT: s_mov_b32 s27, s43 ; GFX10-NEXT: s_mov_b32 s27, s43
; GFX10-NEXT: v_writelane_b32 v40, s28, 24 ; GFX10-NEXT: v_writelane_b32 v40, s28, 24
; GFX10-NEXT: s_mov_b32 s28, s44 ; GFX10-NEXT: s_mov_b32 s28, s44
; GFX10-NEXT: v_writelane_b32 v40, s29, 25 ; GFX10-NEXT: v_writelane_b32 v40, s29, 25
; GFX10-NEXT: s_mov_b32 s29, s45 ; GFX10-NEXT: s_mov_b32 s29, s45
; GFX10-NEXT: v_writelane_b32 v40, s30, 26 ; GFX10-NEXT: v_writelane_b32 v40, s30, 26
; GFX10-NEXT: v_writelane_b32 v40, s31, 27 ; GFX10-NEXT: v_writelane_b32 v40, s31, 27
▲ Show 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
; GFX10-SCRATCH-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_getpc_b64 s[0:1] ; GFX10-SCRATCH-NEXT: s_getpc_b64 s[0:1]
; GFX10-SCRATCH-NEXT: s_add_u32 s0, s0, external_void_func_v32i32_inreg@rel32@lo+4 ; GFX10-SCRATCH-NEXT: s_add_u32 s0, s0, external_void_func_v32i32_inreg@rel32@lo+4
; GFX10-SCRATCH-NEXT: s_addc_u32 s1, s1, external_void_func_v32i32_inreg@rel32@hi+12 ; GFX10-SCRATCH-NEXT: s_addc_u32 s1, s1, external_void_func_v32i32_inreg@rel32@hi+12
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s20, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s20, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s21, 17 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s21, 17
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s22, 18 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s22, 18
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, s50 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s50
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s23, 19 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s23, 19
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, s51 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, s51
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s46
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, s47
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, s48 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, s48
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s24, 20
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, s49 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, s49
; GFX10-SCRATCH-NEXT: s_mov_b32 s20, s36 ; GFX10-SCRATCH-NEXT: s_mov_b32 s20, s36
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s24, 20
; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[0:1], s32 offset:16
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s46
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, s47
; GFX10-SCRATCH-NEXT: s_mov_b32 s21, s37 ; GFX10-SCRATCH-NEXT: s_mov_b32 s21, s37
; GFX10-SCRATCH-NEXT: s_mov_b32 s22, s38
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s25, 21 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s25, 21
; GFX10-SCRATCH-NEXT: s_mov_b32 s22, s38
; GFX10-SCRATCH-NEXT: s_mov_b32 s23, s39 ; GFX10-SCRATCH-NEXT: s_mov_b32 s23, s39
; GFX10-SCRATCH-NEXT: s_mov_b32 s24, s40 ; GFX10-SCRATCH-NEXT: s_mov_b32 s24, s40
; GFX10-SCRATCH-NEXT: s_mov_b32 s25, s41 ; GFX10-SCRATCH-NEXT: s_mov_b32 s25, s41
; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[4:5], s32 offset:16
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s26, 22 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s26, 22
; GFX10-SCRATCH-NEXT: s_mov_b32 s26, s42 ; GFX10-SCRATCH-NEXT: s_mov_b32 s26, s42
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s27, 23 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s27, 23
; GFX10-SCRATCH-NEXT: s_mov_b32 s27, s43 ; GFX10-SCRATCH-NEXT: s_mov_b32 s27, s43
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s28, 24 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s28, 24
; GFX10-SCRATCH-NEXT: s_mov_b32 s28, s44 ; GFX10-SCRATCH-NEXT: s_mov_b32 s28, s44
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s29, 25 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s29, 25
; GFX10-SCRATCH-NEXT: s_mov_b32 s29, s45 ; GFX10-SCRATCH-NEXT: s_mov_b32 s29, s45
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27
▲ Show 20 Lines • Show All 197 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_getpc_b64 s[34:35] ; GFX10-NEXT: s_getpc_b64 s[34:35]
; GFX10-NEXT: s_add_u32 s34, s34, external_void_func_v32i32_i32_inreg@rel32@lo+4 ; GFX10-NEXT: s_add_u32 s34, s34, external_void_func_v32i32_i32_inreg@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_v32i32_i32_inreg@rel32@hi+12 ; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_v32i32_i32_inreg@rel32@hi+12
; GFX10-NEXT: v_writelane_b32 v40, s20, 16 ; GFX10-NEXT: v_writelane_b32 v40, s20, 16
; GFX10-NEXT: v_writelane_b32 v40, s21, 17 ; GFX10-NEXT: v_writelane_b32 v40, s21, 17
; GFX10-NEXT: v_writelane_b32 v40, s22, 18 ; GFX10-NEXT: v_writelane_b32 v40, s22, 18
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s52 ; GFX10-NEXT: v_mov_b32_e32 v0, s52
; GFX10-NEXT: v_mov_b32_e32 v1, s47 ; GFX10-NEXT: v_mov_b32_e32 v1, s46
; GFX10-NEXT: v_writelane_b32 v40, s23, 19 ; GFX10-NEXT: v_writelane_b32 v40, s23, 19
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
; GFX10-NEXT: v_mov_b32_e32 v0, s46 ; GFX10-NEXT: v_mov_b32_e32 v0, s47
; GFX10-NEXT: v_mov_b32_e32 v2, s48 ; GFX10-NEXT: v_mov_b32_e32 v2, s48
; GFX10-NEXT: v_mov_b32_e32 v3, s49 ; GFX10-NEXT: v_mov_b32_e32 v3, s49
; GFX10-NEXT: v_writelane_b32 v40, s24, 20 ; GFX10-NEXT: v_writelane_b32 v40, s24, 20
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX10-NEXT: v_mov_b32_e32 v1, s50
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4
; GFX10-NEXT: v_mov_b32_e32 v0, s51
; GFX10-NEXT: v_writelane_b32 v40, s25, 21
; GFX10-NEXT: s_mov_b32 s20, s36 ; GFX10-NEXT: s_mov_b32 s20, s36
; GFX10-NEXT: s_mov_b32 s21, s37 ; GFX10-NEXT: s_mov_b32 s21, s37
; GFX10-NEXT: s_mov_b32 s22, s38 ; GFX10-NEXT: s_mov_b32 s22, s38
; GFX10-NEXT: s_mov_b32 s23, s39 ; GFX10-NEXT: s_mov_b32 s23, s39
; GFX10-NEXT: v_writelane_b32 v40, s25, 21 ; GFX10-NEXT: v_writelane_b32 v40, s26, 22
; GFX10-NEXT: s_mov_b32 s24, s40 ; GFX10-NEXT: s_mov_b32 s24, s40
; GFX10-NEXT: s_mov_b32 s25, s41 ; GFX10-NEXT: s_mov_b32 s25, s41
; GFX10-NEXT: v_mov_b32_e32 v4, s50
; GFX10-NEXT: v_mov_b32_e32 v5, s51
; GFX10-NEXT: v_writelane_b32 v40, s26, 22
; GFX10-NEXT: s_mov_b32 s26, s42 ; GFX10-NEXT: s_mov_b32 s26, s42
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12 ; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12
; GFX10-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:16 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:16
; GFX10-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:20 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20
; GFX10-NEXT: v_writelane_b32 v40, s27, 23 ; GFX10-NEXT: v_writelane_b32 v40, s27, 23
; GFX10-NEXT: s_mov_b32 s27, s43 ; GFX10-NEXT: s_mov_b32 s27, s43
; GFX10-NEXT: v_writelane_b32 v40, s28, 24 ; GFX10-NEXT: v_writelane_b32 v40, s28, 24
; GFX10-NEXT: s_mov_b32 s28, s44 ; GFX10-NEXT: s_mov_b32 s28, s44
; GFX10-NEXT: v_writelane_b32 v40, s29, 25 ; GFX10-NEXT: v_writelane_b32 v40, s29, 25
; GFX10-NEXT: s_mov_b32 s29, s45 ; GFX10-NEXT: s_mov_b32 s29, s45
; GFX10-NEXT: v_writelane_b32 v40, s30, 26 ; GFX10-NEXT: v_writelane_b32 v40, s30, 26
; GFX10-NEXT: v_writelane_b32 v40, s31, 27 ; GFX10-NEXT: v_writelane_b32 v40, s31, 27
▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
; GFX10-SCRATCH-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_getpc_b64 s[0:1] ; GFX10-SCRATCH-NEXT: s_getpc_b64 s[0:1]
; GFX10-SCRATCH-NEXT: s_add_u32 s0, s0, external_void_func_v32i32_i32_inreg@rel32@lo+4 ; GFX10-SCRATCH-NEXT: s_add_u32 s0, s0, external_void_func_v32i32_i32_inreg@rel32@lo+4
; GFX10-SCRATCH-NEXT: s_addc_u32 s1, s1, external_void_func_v32i32_i32_inreg@rel32@hi+12 ; GFX10-SCRATCH-NEXT: s_addc_u32 s1, s1, external_void_func_v32i32_i32_inreg@rel32@hi+12
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s20, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s20, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s21, 17 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s21, 17
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s22, 18 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s22, 18
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, s2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, s2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, s50 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s50
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s23, 19 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s23, 19
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, s51 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, s51
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v2, s32 offset:24
; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[0:1], s32 offset:16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s24, 20
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s46 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s46
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, s47 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, s47
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, s48 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, s48
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s24, 20
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, s49 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, s49
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s25, 21
; GFX10-SCRATCH-NEXT: s_mov_b32 s20, s36 ; GFX10-SCRATCH-NEXT: s_mov_b32 s20, s36
; GFX10-SCRATCH-NEXT: s_mov_b32 s21, s37 ; GFX10-SCRATCH-NEXT: s_mov_b32 s21, s37
; GFX10-SCRATCH-NEXT: s_mov_b32 s22, s38 ; GFX10-SCRATCH-NEXT: s_mov_b32 s22, s38
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s25, 21
; GFX10-SCRATCH-NEXT: s_mov_b32 s23, s39 ; GFX10-SCRATCH-NEXT: s_mov_b32 s23, s39
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s26, 22
; GFX10-SCRATCH-NEXT: s_mov_b32 s24, s40 ; GFX10-SCRATCH-NEXT: s_mov_b32 s24, s40
; GFX10-SCRATCH-NEXT: s_mov_b32 s25, s41 ; GFX10-SCRATCH-NEXT: s_mov_b32 s25, s41
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v6, s32 offset:24
; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[4:5], s32 offset:16
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s26, 22
; GFX10-SCRATCH-NEXT: s_mov_b32 s26, s42 ; GFX10-SCRATCH-NEXT: s_mov_b32 s26, s42
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s27, 23 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s27, 23
; GFX10-SCRATCH-NEXT: s_mov_b32 s27, s43 ; GFX10-SCRATCH-NEXT: s_mov_b32 s27, s43
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s28, 24 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s28, 24
; GFX10-SCRATCH-NEXT: s_mov_b32 s28, s44 ; GFX10-SCRATCH-NEXT: s_mov_b32 s28, s44
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s29, 25 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s29, 25
; GFX10-SCRATCH-NEXT: s_mov_b32 s29, s45 ; GFX10-SCRATCH-NEXT: s_mov_b32 s29, s45
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s34, s33 ; GFX10-NEXT: s_mov_b32 s34, s33
; GFX10-NEXT: s_mov_b32 s33, s32 ; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33 ; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:4
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_addk_i32 s32, 0x400 ; GFX10-NEXT: s_addk_i32 s32, 0x400
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v41, s34, 0 ; GFX10-NEXT: v_writelane_b32 v41, s34, 0
; GFX10-NEXT: s_getpc_b64 s[34:35] ; GFX10-NEXT: s_getpc_b64 s[34:35]
; GFX10-NEXT: s_add_u32 s34, s34, stack_passed_f64_arg@rel32@lo+4 ; GFX10-NEXT: s_add_u32 s34, s34, stack_passed_f64_arg@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s35, s35, stack_passed_f64_arg@rel32@hi+12 ; GFX10-NEXT: s_addc_u32 s35, s35, stack_passed_f64_arg@rel32@hi+12
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:4
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 ; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:4
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s34, v41, 0 ; GFX10-NEXT: v_readlane_b32 s34, v41, 0
; GFX10-NEXT: s_or_saveexec_b32 s35, -1 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:12 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:12
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; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 8 ; GFX10-NEXT: v_mov_b32_e32 v0, 8
; GFX10-NEXT: v_mov_b32_e32 v1, 9 ; GFX10-NEXT: v_mov_b32_e32 v1, 9
; GFX10-NEXT: v_mov_b32_e32 v2, 10 ; GFX10-NEXT: v_mov_b32_e32 v2, 10
; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_mov_b32_e32 v3, 14 ; GFX10-NEXT: v_mov_b32_e32 v3, 11
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
; GFX10-NEXT: v_mov_b32_e32 v0, 11 ; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12
; GFX10-NEXT: v_mov_b32_e32 v1, 12 ; GFX10-NEXT: v_mov_b32_e32 v0, 12
; GFX10-NEXT: v_mov_b32_e32 v2, 13 ; GFX10-NEXT: v_mov_b32_e32 v1, 13
; GFX10-NEXT: v_mov_b32_e32 v4, 15 ; GFX10-NEXT: v_mov_b32_e32 v2, 14
; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:16 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:20
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:20 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:24
; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:24 ; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:28
; GFX10-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:28
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 1 ; GFX10-NEXT: v_mov_b32_e32 v5, 1
; GFX10-NEXT: v_mov_b32_e32 v6, 1 ; GFX10-NEXT: v_mov_b32_e32 v6, 1
; GFX10-NEXT: v_mov_b32_e32 v7, 1 ; GFX10-NEXT: v_mov_b32_e32 v7, 1
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; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 12 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 12
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 13 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 13
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 14 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 14
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 15
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 8
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 9
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 10
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 11
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:16
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[4:7], s32
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 1
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:16
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 8
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 9
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 10
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 11
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v8, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v8, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v9, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v9, 1
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v10, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v10, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v11, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v11, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v12, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v12, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v13, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v13, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v14, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v14, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v15, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v15, 3
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v16, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v16, 3
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v17, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v17, 3
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; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 0x41000000 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x41000000
; GFX10-NEXT: v_mov_b32_e32 v1, 0x41100000 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x41100000
; GFX10-NEXT: v_mov_b32_e32 v2, 0x41200000 ; GFX10-NEXT: v_mov_b32_e32 v2, 0x41200000
; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_mov_b32_e32 v3, 0x41600000 ; GFX10-NEXT: v_mov_b32_e32 v3, 0x41300000
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
; GFX10-NEXT: v_mov_b32_e32 v0, 0x41300000 ; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12
; GFX10-NEXT: v_mov_b32_e32 v1, 0x41400000 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x41400000
; GFX10-NEXT: v_mov_b32_e32 v2, 0x41500000 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x41500000
; GFX10-NEXT: v_mov_b32_e32 v4, 0x41700000 ; GFX10-NEXT: v_mov_b32_e32 v2, 0x41600000
; GFX10-NEXT: v_mov_b32_e32 v3, 0x41700000
; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:16 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:20
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:20 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:24
; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:24 ; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:28
; GFX10-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:28
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 1.0 ; GFX10-NEXT: v_mov_b32_e32 v5, 1.0
; GFX10-NEXT: v_mov_b32_e32 v6, 1.0 ; GFX10-NEXT: v_mov_b32_e32 v6, 1.0
; GFX10-NEXT: v_mov_b32_e32 v7, 1.0 ; GFX10-NEXT: v_mov_b32_e32 v7, 1.0
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x41400000 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x41400000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x41500000 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x41500000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0x41600000 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0x41600000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0x41700000 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0x41700000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0x41000000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 0x41100000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 0x41200000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 0x41300000
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:16
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[4:7], s32
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 1.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 1.0
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:16
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x41000000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x41100000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0x41200000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0x41300000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 1.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 1.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 1.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 1.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v8, 1.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v8, 1.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v9, 1.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v9, 1.0
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v10, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v10, 2.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v11, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v11, 2.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v12, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v12, 2.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v13, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v13, 2.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v14, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v14, 2.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v15, 0x40400000 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v15, 0x40400000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v16, 0x40400000 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v16, 0x40400000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v17, 0x40400000 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v17, 0x40400000
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llvm/test/CodeGen/AMDGPU/idiv-licm.ll

Show First 20 Lines • Show All 662 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udiv16_invariant_denom: ; GFX10-LABEL: udiv16_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_mov_b32 s5, 0
; GFX10-NEXT: s_mov_b32 s1, 0 ; GFX10-NEXT: s_mov_b32 s1, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s0, 0xffff, s4 ; GFX10-NEXT: s_and_b32 s0, 0xffff, s4
; GFX10-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s0 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GFX10-NEXT: .LBB4_1: ; %bb3 ; GFX10-NEXT: .LBB4_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_and_b32 s0, 0xffff, s4 ; GFX10-NEXT: v_add_nc_u16 v3, s1, 1
; GFX10-NEXT: v_add_nc_u16 v3, s4, 1 ; GFX10-NEXT: s_and_b32 s4, 0xffff, s1
; GFX10-NEXT: v_cvt_f32_u32_e32 v4, s0 ; GFX10-NEXT: s_lshl_b64 s[6:7], s[4:5], 1
; GFX10-NEXT: s_lshl_b64 s[4:5], s[0:1], 1 ; GFX10-NEXT: s_add_u32 s6, s2, s6
; GFX10-NEXT: s_add_u32 s6, s2, s4 ; GFX10-NEXT: v_readfirstlane_b32 s1, v3
; GFX10-NEXT: v_readfirstlane_b32 s4, v3
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v3 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v3
; GFX10-NEXT: v_mul_f32_e32 v3, v4, v1 ; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s4
; GFX10-NEXT: s_addc_u32 s7, s3, s5 ; GFX10-NEXT: s_addc_u32 s7, s3, s7
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo ; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-NEXT: v_trunc_f32_e32 v3, v3 ; GFX10-NEXT: v_mul_f32_e32 v4, v3, v1
; GFX10-NEXT: v_mad_f32 v4, -v3, v0, v4 ; GFX10-NEXT: v_trunc_f32_e32 v4, v4
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX10-NEXT: v_mad_f32 v3, -v4, v0, v3
; GFX10-NEXT: v_cmp_ge_f32_e64 s0, |v4|, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, 0, v3, s0 ; GFX10-NEXT: v_cmp_ge_f32_e64 s0, |v3|, v0
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, 0, v4, s0
; GFX10-NEXT: global_store_short v2, v3, s[6:7] ; GFX10-NEXT: global_store_short v2, v3, s[6:7]
; GFX10-NEXT: s_cbranch_vccz .LBB4_1 ; GFX10-NEXT: s_cbranch_vccz .LBB4_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: udiv16_invariant_denom: ; GFX11-LABEL: udiv16_invariant_denom:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
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; GFX10-LABEL: urem16_invariant_denom: ; GFX10-LABEL: urem16_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s1, 0xffff, s4 ; GFX10-NEXT: s_and_b32 s0, 0xffff, s4
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s1 ; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v2 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v2
; GFX10-NEXT: .LBB5_1: ; %bb3 ; GFX10-NEXT: .LBB5_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v4 ; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v4
; GFX10-NEXT: v_add_nc_u16 v4, v4, 1 ; GFX10-NEXT: v_add_nc_u16 v4, v4, 1
; GFX10-NEXT: v_cvt_f32_u32_e32 v7, v0 ; GFX10-NEXT: v_cvt_f32_u32_e32 v7, v0
; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1]
; GFX10-NEXT: v_mul_f32_e32 v8, v7, v3 ; GFX10-NEXT: v_mul_f32_e32 v8, v7, v3
; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5 ; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, s2, v5
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
; GFX10-NEXT: v_trunc_f32_e32 v8, v8 ; GFX10-NEXT: v_trunc_f32_e32 v8, v8
; GFX10-NEXT: v_mad_f32 v7, -v8, v2, v7 ; GFX10-NEXT: v_mad_f32 v7, -v8, v2, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v8, v8 ; GFX10-NEXT: v_cvt_u32_f32_e32 v8, v8
; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v7|, v2 ; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v7|, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
; GFX10-NEXT: v_mul_lo_u32 v7, v7, s1 ; GFX10-NEXT: v_mul_lo_u32 v7, v7, s0
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v7 ; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v7
; GFX10-NEXT: global_store_short v[5:6], v0, off ; GFX10-NEXT: global_store_short v[5:6], v0, off
; GFX10-NEXT: s_cbranch_vccz .LBB5_1 ; GFX10-NEXT: s_cbranch_vccz .LBB5_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: urem16_invariant_denom: ; GFX11-LABEL: urem16_invariant_denom:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
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; GFX10-NEXT: s_mov_b32 s5, 0 ; GFX10-NEXT: s_mov_b32 s5, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_sext_i32_i16 s4, s4 ; GFX10-NEXT: s_sext_i32_i16 s4, s4
; GFX10-NEXT: v_cvt_f32_i32_e32 v0, s4 ; GFX10-NEXT: v_cvt_f32_i32_e32 v0, s4
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GFX10-NEXT: .LBB6_1: ; %bb3 ; GFX10-NEXT: .LBB6_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_sext_i32_i16 s0, s5 ; GFX10-NEXT: s_sext_i32_i16 s0, s5
; GFX10-NEXT: v_add_nc_u16 v3, s5, 1 ; GFX10-NEXT: v_cvt_f32_i32_e32 v3, s0
; GFX10-NEXT: v_cvt_f32_i32_e32 v4, s0
; GFX10-NEXT: s_xor_b32 s0, s0, s4 ; GFX10-NEXT: s_xor_b32 s0, s0, s4
; GFX10-NEXT: s_ashr_i32 s0, s0, 30 ; GFX10-NEXT: s_ashr_i32 s0, s0, 30
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v3
; GFX10-NEXT: v_mul_f32_e32 v5, v4, v1
; GFX10-NEXT: s_or_b32 s0, s0, 1 ; GFX10-NEXT: s_or_b32 s0, s0, 1
; GFX10-NEXT: v_trunc_f32_e32 v5, v5 ; GFX10-NEXT: v_mul_f32_e32 v4, v3, v1
; GFX10-NEXT: v_mad_f32 v4, -v5, v0, v4 ; GFX10-NEXT: v_trunc_f32_e32 v4, v4
; GFX10-NEXT: v_cmp_ge_f32_e64 s6, |v4|, |v0| ; GFX10-NEXT: v_mad_f32 v3, -v4, v0, v3
; GFX10-NEXT: v_cvt_i32_f32_e32 v4, v5 ; GFX10-NEXT: v_cmp_ge_f32_e64 s6, |v3|, |v0|
; GFX10-NEXT: v_add_nc_u16 v3, s5, 1
; GFX10-NEXT: s_and_b32 s6, s6, exec_lo ; GFX10-NEXT: s_and_b32 s6, s6, exec_lo
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v3
; GFX10-NEXT: s_cselect_b32 s6, s0, 0 ; GFX10-NEXT: s_cselect_b32 s6, s0, 0
; GFX10-NEXT: s_and_b32 s0, s5, 0xffff ; GFX10-NEXT: s_and_b32 s0, s5, 0xffff
; GFX10-NEXT: v_readfirstlane_b32 s5, v3 ; GFX10-NEXT: v_readfirstlane_b32 s5, v3
; GFX10-NEXT: v_add_nc_u32_e32 v3, s6, v4 ; GFX10-NEXT: v_cvt_i32_f32_e32 v3, v4
; GFX10-NEXT: v_add_nc_u32_e32 v3, s6, v3
; GFX10-NEXT: s_lshl_b64 s[6:7], s[0:1], 1 ; GFX10-NEXT: s_lshl_b64 s[6:7], s[0:1], 1
; GFX10-NEXT: s_add_u32 s6, s2, s6 ; GFX10-NEXT: s_add_u32 s6, s2, s6
; GFX10-NEXT: s_addc_u32 s7, s3, s7 ; GFX10-NEXT: s_addc_u32 s7, s3, s7
; GFX10-NEXT: global_store_short v2, v3, s[6:7] ; GFX10-NEXT: global_store_short v2, v3, s[6:7]
; GFX10-NEXT: s_cbranch_vccz .LBB6_1 ; GFX10-NEXT: s_cbranch_vccz .LBB6_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
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; GFX10-NEXT: s_mov_b32 s5, 0 ; GFX10-NEXT: s_mov_b32 s5, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_sext_i32_i16 s4, s4 ; GFX10-NEXT: s_sext_i32_i16 s4, s4
; GFX10-NEXT: v_cvt_f32_i32_e32 v0, s4 ; GFX10-NEXT: v_cvt_f32_i32_e32 v0, s4
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GFX10-NEXT: .LBB7_1: ; %bb3 ; GFX10-NEXT: .LBB7_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_sext_i32_i16 s8, s5 ; GFX10-NEXT: s_sext_i32_i16 s8, s5
; GFX10-NEXT: v_cvt_f32_i32_e32 v3, s8
; GFX10-NEXT: s_xor_b32 s6, s8, s4
; GFX10-NEXT: s_ashr_i32 s6, s6, 30
; GFX10-NEXT: s_or_b32 s6, s6, 1
; GFX10-NEXT: v_mul_f32_e32 v4, v3, v1
; GFX10-NEXT: v_trunc_f32_e32 v4, v4
; GFX10-NEXT: v_mad_f32 v3, -v4, v0, v3
; GFX10-NEXT: v_cmp_ge_f32_e64 s0, |v3|, |v0|
; GFX10-NEXT: v_add_nc_u16 v3, s5, 1 ; GFX10-NEXT: v_add_nc_u16 v3, s5, 1
; GFX10-NEXT: v_cvt_f32_i32_e32 v4, s8 ; GFX10-NEXT: s_and_b32 s0, s0, exec_lo
; GFX10-NEXT: s_xor_b32 s0, s8, s4
; GFX10-NEXT: s_ashr_i32 s0, s0, 30
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v3 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v3
; GFX10-NEXT: v_mul_f32_e32 v5, v4, v1 ; GFX10-NEXT: s_cselect_b32 s6, s6, 0
; GFX10-NEXT: s_or_b32 s0, s0, 1
; GFX10-NEXT: v_trunc_f32_e32 v5, v5
; GFX10-NEXT: v_mad_f32 v4, -v5, v0, v4
; GFX10-NEXT: v_cmp_ge_f32_e64 s6, |v4|, |v0|
; GFX10-NEXT: v_cvt_i32_f32_e32 v4, v5
; GFX10-NEXT: s_and_b32 s6, s6, exec_lo
; GFX10-NEXT: s_cselect_b32 s6, s0, 0
; GFX10-NEXT: s_and_b32 s0, s5, 0xffff ; GFX10-NEXT: s_and_b32 s0, s5, 0xffff
; GFX10-NEXT: v_add_nc_u32_e32 v4, s6, v4
; GFX10-NEXT: v_readfirstlane_b32 s5, v3 ; GFX10-NEXT: v_readfirstlane_b32 s5, v3
; GFX10-NEXT: v_cvt_i32_f32_e32 v3, v4
; GFX10-NEXT: v_add_nc_u32_e32 v3, s6, v3
; GFX10-NEXT: s_lshl_b64 s[6:7], s[0:1], 1 ; GFX10-NEXT: s_lshl_b64 s[6:7], s[0:1], 1
; GFX10-NEXT: s_add_u32 s6, s2, s6 ; GFX10-NEXT: s_add_u32 s6, s2, s6
; GFX10-NEXT: v_mul_lo_u32 v3, v4, s4
; GFX10-NEXT: s_addc_u32 s7, s3, s7 ; GFX10-NEXT: s_addc_u32 s7, s3, s7
; GFX10-NEXT: v_mul_lo_u32 v3, v3, s4
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s8, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v3, s8, v3
; GFX10-NEXT: global_store_short v2, v3, s[6:7] ; GFX10-NEXT: global_store_short v2, v3, s[6:7]
; GFX10-NEXT: s_cbranch_vccz .LBB7_1 ; GFX10-NEXT: s_cbranch_vccz .LBB7_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: srem16_invariant_denom: ; GFX11-LABEL: srem16_invariant_denom:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/idot4s.ll

Show First 20 Lines • Show All 323 Lines • ▼ Show 20 Lines
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: idot4_acc16: ; GFX10-DL-LABEL: idot4_acc16:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-DL-NEXT: global_load_ushort v4, v1, s[2:3]
; GFX10-DL-NEXT: global_load_ushort v3, v0, s[2:3]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2) ; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_bfe_i32 v4, v1, 0, 8 ; GFX10-DL-NEXT: v_bfe_i32 v0, v2, 0, 8
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v2 ; GFX10-DL-NEXT: v_bfe_i32 v5, v3, 0, 8
; GFX10-DL-NEXT: v_bfe_i32 v7, v2, 0, 8
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v9, 16, v2
; GFX10-DL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX10-DL-NEXT: v_bfe_i32 v6, v6, 0, 8
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v3, v4, v7, v3 ; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4
; GFX10-DL-NEXT: v_bfe_i32 v4, v8, 0, 8 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v2
; GFX10-DL-NEXT: v_bfe_i32 v7, v9, 0, 8 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1 ; GFX10-DL-NEXT: v_bfe_i32 v4, v4, 0, 8
; GFX10-DL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX10-DL-NEXT: v_mad_u16 v3, v5, v6, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX10-DL-NEXT: v_bfe_i32 v1, v1, 0, 8 ; GFX10-DL-NEXT: v_bfe_i32 v4, v4, 0, 8
; GFX10-DL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX10-DL-NEXT: v_bfe_i32 v2, v2, 0, 8 ; GFX10-DL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX10-DL-NEXT: v_mad_u16 v3, v4, v7, v3 ; GFX10-DL-NEXT: v_bfe_i32 v3, v3, 0, 8
; GFX10-DL-NEXT: v_mad_u16 v1, v1, v2, v3 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: global_store_short v0, v1, s[2:3] ; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0
; GFX10-DL-NEXT: global_store_short v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <4 x i8>, ptr addrspace(1) %gep1 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
%gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
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; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3] ; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v2
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v4, v2, v3, v4 ; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v7, 16, v3 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0
; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3] ; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
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; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_bfe_i32 v0, v1, 0, 8 ; GFX10-DL-NEXT: v_bfe_i32 v0, v1, 0, 8
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_bfe_i32 v3, v2, 0, 8 ; GFX10-DL-NEXT: v_bfe_i32 v3, v2, 0, 8
; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v4, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1 ; GFX10-DL-NEXT: v_mul_i32_i24_e32 v4, v0, v3
; GFX10-DL-NEXT: v_mul_i32_i24_e32 v5, v0, v3
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_mad_i32_i24 v0, v0, v3, s2 ; GFX10-DL-NEXT: v_mad_i32_i24 v0, v0, v3, s2
; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v3, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
; GFX10-DL-NEXT: v_add3_u32 v0, v3, v0, v4
; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v3, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2 ; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v3, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3 ; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
; GFX10-DL-NEXT: v_add3_u32 v0, v4, v0, v5
; GFX10-DL-NEXT: v_add3_u32 v0, v0, v3, v1 ; GFX10-DL-NEXT: v_add3_u32 v0, v0, v3, v1
; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1] ; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
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; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_lshrrev_b16 v0, 8, v1 ; GFX10-DL-NEXT: v_lshrrev_b16 v0, 8, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_lshrrev_b16 v3, 8, v2 ; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v3, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v4, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 ; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v4, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v0, sext(v0), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v3, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3 ; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
; GFX10-DL-NEXT: v_lshrrev_b16 v2, 8, v2
; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v0, sext(v0), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_add3_u32 v0, v4, s2, v0 ; GFX10-DL-NEXT: v_add3_u32 v0, v3, s2, v0
; GFX10-DL-NEXT: v_add3_u32 v0, v0, v3, v1 ; GFX10-DL-NEXT: v_add3_u32 v0, v0, v4, v1
; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1] ; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <4 x i8>, ptr addrspace(1) %gep1 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
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; ;
; GFX10-DL-LABEL: idot4_acc16_vecMul: ; GFX10-DL-LABEL: idot4_acc16_vecMul:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: global_load_ushort v3, v0, s[0:1]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_ashrrev_i16 v4, 8, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_ashrrev_i16 v5, 8, v2 ; GFX10-DL-NEXT: v_ashrrev_i16 v0, 8, v1
; GFX10-DL-NEXT: v_bfe_i32 v6, v2, 0, 8 ; GFX10-DL-NEXT: v_bfe_i32 v3, v1, 0, 8
; GFX10-DL-NEXT: v_bfe_i32 v7, v1, 0, 8 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_bfe_i32 v4, v2, 0, 8
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX10-DL-NEXT: v_perm_b32 v0, v0, v3, 0x5040100
; GFX10-DL-NEXT: v_ashrrev_i16 v3, 8, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX10-DL-NEXT: v_perm_b32 v5, v5, v6, 0x5040100 ; GFX10-DL-NEXT: v_perm_b32 v3, v3, v4, 0x5040100
; GFX10-DL-NEXT: v_perm_b32 v4, v4, v7, 0x5040100 ; GFX10-DL-NEXT: v_ashrrev_i16 v4, 8, v1
; GFX10-DL-NEXT: v_ashrrev_i16 v6, 8, v1
; GFX10-DL-NEXT: v_ashrrev_i16 v7, 8, v2
; GFX10-DL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX10-DL-NEXT: v_bfe_i32 v1, v1, 0, 8 ; GFX10-DL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v0, v3, v0
; GFX10-DL-NEXT: v_perm_b32 v2, v7, v2, 0x5040100 ; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
; GFX10-DL-NEXT: v_perm_b32 v1, v6, v1, 0x5040100 ; GFX10-DL-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX10-DL-NEXT: v_ashrrev_i16 v4, 8, v2
; GFX10-DL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX10-DL-NEXT: v_perm_b32 v2, v4, v2, 0x5040100
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v1, v2, v1
; GFX10-DL-NEXT: global_load_ushort v2, v3, s[0:1]
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u16 v3, v4, v3 ; GFX10-DL-NEXT: v_add_nc_u16 v2, v0, v2
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v1, v1, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-DL-NEXT: v_add_nc_u16 v2, v3, v5 ; GFX10-DL-NEXT: v_add_nc_u16 v0, v2, v0
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 16, v1 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX10-DL-NEXT: v_add_nc_u16 v1, v2, v1 ; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v1
; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v3 ; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v2
; GFX10-DL-NEXT: global_store_short v0, v1, s[0:1] ; GFX10-DL-NEXT: global_store_short v3, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <4 x i8>, ptr addrspace(1) %gep1 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
%gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
Show All 22 Lines

llvm/test/CodeGen/AMDGPU/idot4u.ll

Show First 20 Lines • Show All 305 Lines • ▼ Show 20 Lines
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: udot4_acc16: ; GFX10-DL-LABEL: udot4_acc16:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v8, 0xff ; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-DL-NEXT: global_load_ushort v4, v1, s[2:3]
; GFX10-DL-NEXT: global_load_ushort v3, v0, s[2:3]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2) ; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_and_b32_e32 v4, 0xff, v1 ; GFX10-DL-NEXT: v_and_b32_e32 v0, 0xff, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v5, 0xff, v3
; GFX10-DL-NEXT: v_and_b32_e32 v7, 0xff, v2
; GFX10-DL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX10-DL-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v3, v4, v7, v3 ; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4
; GFX10-DL-NEXT: v_and_b32_sdwa v4, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v2
; GFX10-DL-NEXT: v_and_b32_sdwa v7, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1 ; GFX10-DL-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX10-DL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v4, 0xff
; GFX10-DL-NEXT: v_and_b32_sdwa v5, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-DL-NEXT: v_and_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX10-DL-NEXT: v_mad_u16 v3, v5, v6, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX10-DL-NEXT: v_mad_u16 v3, v4, v7, v3 ; GFX10-DL-NEXT: v_mad_u16 v0, v5, v4, v0
; GFX10-DL-NEXT: v_mad_u16 v1, v1, v2, v3 ; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0
; GFX10-DL-NEXT: global_store_short v0, v1, s[2:3] ; GFX10-DL-NEXT: global_store_short v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <4 x i8>, ptr addrspace(1) %gep1 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
%gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3] ; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v2
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v4, v2, v3, v4 ; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v7, 16, v3 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0
; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3] ; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
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; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3] ; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v2
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v2, v2, v3, v4 ; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v4
; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 8, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v3
; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0
; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3] ; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <4 x i8>, ptr addrspace(1) %gep1 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
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; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3] ; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v2
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v4, v3, v2, v4 ; GFX10-DL-NEXT: v_mad_u16 v0, v3, v2, v4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v7, 16, v3 ; GFX10-DL-NEXT: v_mad_u16 v0, v5, v4, v0
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX10-DL-NEXT: v_mad_u16 v0, v5, v0, v4 ; GFX10-DL-NEXT: v_mad_u16 v0, v5, v4, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v7, v6, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v3, v2, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v3, v2, v0
; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3] ; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
▲ Show 20 Lines • Show All 341 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_and_b32_e32 v0, 0xff, v1 ; GFX10-DL-NEXT: v_and_b32_e32 v0, 0xff, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_and_b32_e32 v3, 0xff, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v3, 0xff, v2
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v4, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1 ; GFX10-DL-NEXT: v_mul_u32_u24_e32 v4, v0, v3
; GFX10-DL-NEXT: v_mul_u32_u24_e32 v5, v0, v3
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v0, v0, v3, s2 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, v0, v3, s2
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
; GFX10-DL-NEXT: v_add3_u32 v0, v3, v0, v4
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2 ; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3 ; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
; GFX10-DL-NEXT: v_add3_u32 v0, v4, v0, v5
; GFX10-DL-NEXT: v_add3_u32 v0, v0, v3, v1 ; GFX10-DL-NEXT: v_add3_u32 v0, v0, v3, v1
; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1] ; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_bfe_u32 v0, v1, 8, 8 ; GFX10-DL-NEXT: v_bfe_u32 v0, v1, 8, 8
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_bfe_u32 v3, v2, 8, 8 ; GFX10-DL-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v4, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 ; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v4, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v0, v0, v3, s2 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, v0, v3, s2
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2 ; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3 ; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, s2, v0 ; GFX10-DL-NEXT: v_add3_u32 v2, v0, v3, v4
; GFX10-DL-NEXT: v_add3_u32 v0, v0, v4, v3 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
; GFX10-DL-NEXT: v_add3_u32 v0, v0, v1, v2 ; GFX10-DL-NEXT: v_add3_u32 v0, v2, v1, v0
; GFX10-DL-NEXT: global_store_dword v3, v0, s[0:1] ; GFX10-DL-NEXT: global_store_dword v3, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <4 x i8>, ptr addrspace(1) %gep1 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
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; GFX9-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2 ; GFX9-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v8, v9, v3 ; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v8, v9, v3
; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3 ; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3
; GFX9-DL-NEXT: global_store_short v0, v1, s[2:3] ; GFX9-DL-NEXT: global_store_short v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: notdot4_mixedtypes: ; GFX10-DL-LABEL: notdot4_mixedtypes:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v7, 0xff ; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NEXT: v_mov_b32_e32 v4, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-DL-NEXT: global_load_ushort v5, v4, s[0:1]
; GFX10-DL-NEXT: global_load_ushort v3, v0, s[2:3]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2) ; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v1 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v2
; GFX10-DL-NEXT: v_bfe_i32 v6, v1, 0, 8 ; GFX10-DL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-DL-NEXT: v_bfe_i32 v8, v2, 0, 8 ; GFX10-DL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX10-DL-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX10-DL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v3, v4, v5, v3 ; GFX10-DL-NEXT: v_mad_u16 v0, v0, v3, v5
; GFX10-DL-NEXT: v_and_b32_sdwa v4, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-DL-NEXT: v_bfe_i32 v3, v1, 0, 8
; GFX10-DL-NEXT: v_and_b32_sdwa v5, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-DL-NEXT: v_bfe_i32 v5, v2, 0, 8
; GFX10-DL-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0xff
; GFX10-DL-NEXT: v_and_b32_sdwa v5, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-DL-NEXT: v_and_b32_sdwa v3, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX10-DL-NEXT: v_mad_u16 v3, v6, v8, v3 ; GFX10-DL-NEXT: v_mad_u16 v0, v5, v3, v0
; GFX10-DL-NEXT: v_mad_u16 v3, v4, v5, v3 ; GFX10-DL-NEXT: v_mad_u16 v0, v1, v2, v0
; GFX10-DL-NEXT: v_mad_u16 v1, v1, v2, v3 ; GFX10-DL-NEXT: global_store_short v4, v0, s[0:1]
; GFX10-DL-NEXT: global_store_short v0, v1, s[2:3]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <4 x i8>, ptr addrspace(1) %gep1 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
%gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
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; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0xffff ; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0xffff
; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_and_b32_sdwa v3, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 ; GFX10-DL-NEXT: v_and_b32_sdwa v3, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 ; GFX10-DL-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v4, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 ; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v4, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX10-DL-NEXT: v_mul_u32_u24_e32 v0, v3, v0 ; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3 ; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
; GFX10-DL-NEXT: v_mul_u32_u24_e32 v0, v3, v0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_add3_u32 v0, v4, s2, v0 ; GFX10-DL-NEXT: v_add3_u32 v0, v4, s2, v0
; GFX10-DL-NEXT: v_add3_u32 v0, v0, v3, v1 ; GFX10-DL-NEXT: v_add3_u32 v0, v0, v5, v1
; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1] ; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <4 x i8>, ptr addrspace(1) %gep1 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
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; GFX9-DL-NEXT: v_add_u16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX9-DL-NEXT: v_add_u16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-DL-NEXT: global_store_short v0, v1, s[2:3] ; GFX9-DL-NEXT: global_store_short v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: udot4_acc16_vecMul: ; GFX10-DL-LABEL: udot4_acc16_vecMul:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0xff
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NEXT: v_mov_b32_e32 v8, 0xff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v0, v0, s[4:5]
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: global_load_ushort v3, v0, s[0:1]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_lshrrev_b16 v4, 8, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_lshrrev_b16 v5, 8, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v1
; GFX10-DL-NEXT: v_and_b32_e32 v6, 0xff, v2 ; GFX10-DL-NEXT: v_and_b32_sdwa v4, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-DL-NEXT: v_and_b32_e32 v7, 0xff, v1 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_perm_b32 v5, v5, v6, 0x5040100 ; GFX10-DL-NEXT: v_and_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-DL-NEXT: v_perm_b32 v4, v4, v7, 0x5040100 ; GFX10-DL-NEXT: v_perm_b32 v3, v3, v4, 0x5040100
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 24, v1 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v7, 24, v2 ; GFX10-DL-NEXT: v_perm_b32 v2, v4, v2, 0x5040100
; GFX10-DL-NEXT: v_and_b32_sdwa v2, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-DL-NEXT: v_lshrrev_b16 v4, 8, v1
; GFX10-DL-NEXT: v_and_b32_sdwa v1, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-DL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v2, v2, v3
; GFX10-DL-NEXT: v_perm_b32 v2, v7, v2, 0x5040100 ; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
; GFX10-DL-NEXT: v_perm_b32 v1, v6, v1, 0x5040100 ; GFX10-DL-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX10-DL-NEXT: v_lshrrev_b16 v4, 8, v0
; GFX10-DL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-DL-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v0, v0, v1
; GFX10-DL-NEXT: global_load_ushort v1, v3, s[0:1]
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u16 v3, v4, v3 ; GFX10-DL-NEXT: v_add_nc_u16 v1, v0, v1
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v1, v1, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-DL-NEXT: v_add_nc_u16 v2, v3, v5 ; GFX10-DL-NEXT: v_add_nc_u16 v0, v1, v0
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 16, v1 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX10-DL-NEXT: v_add_nc_u16 v1, v2, v1 ; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v2
; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v3 ; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v1
; GFX10-DL-NEXT: global_store_short v0, v1, s[0:1] ; GFX10-DL-NEXT: global_store_short v3, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <4 x i8>, ptr addrspace(1) %gep1 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
%gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
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; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: global_load_ubyte v3, v0, s[0:1]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 24, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 24, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 24, v1
; GFX10-DL-NEXT: v_lshrrev_b16 v6, 8, v1 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v7, 16, v1 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 16, v2 ; GFX10-DL-NEXT: v_lshrrev_b16 v4, 8, v2
; GFX10-DL-NEXT: v_lshrrev_b16 v9, 8, v2 ; GFX10-DL-NEXT: v_mul_lo_u16 v0, v0, v3
; GFX10-DL-NEXT: v_mul_lo_u16 v4, v4, v5 ; GFX10-DL-NEXT: v_lshrrev_b16 v3, 8, v1
; GFX10-DL-NEXT: v_lshlrev_b16 v0, 8, v0
; GFX10-DL-NEXT: v_mul_lo_u16 v3, v3, v4
; GFX10-DL-NEXT: v_mov_b32_e32 v4, 0
; GFX10-DL-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX10-DL-NEXT: global_load_ubyte v5, v4, s[0:1]
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v5, v1, v2, v5
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX10-DL-NEXT: v_mul_lo_u16 v6, v1, v2
; GFX10-DL-NEXT: v_or_b32_sdwa v6, v6, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX10-DL-NEXT: v_or_b32_sdwa v3, v3, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v3
; GFX10-DL-NEXT: v_add_nc_u16 v3, v5, v3
; GFX10-DL-NEXT: v_mad_u16 v1, v1, v2, v3 ; GFX10-DL-NEXT: v_mad_u16 v1, v1, v2, v3
; GFX10-DL-NEXT: v_mul_lo_u16 v5, v7, v8 ; GFX10-DL-NEXT: v_add_nc_u16 v0, v1, v0
; GFX10-DL-NEXT: v_mul_lo_u16 v6, v6, v9 ; GFX10-DL-NEXT: global_store_byte v4, v0, s[0:1]
; GFX10-DL-NEXT: v_lshlrev_b16 v4, 8, v4
; GFX10-DL-NEXT: v_lshlrev_b16 v6, 8, v6
; GFX10-DL-NEXT: v_or_b32_sdwa v5, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 8, v4
; GFX10-DL-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v5
; GFX10-DL-NEXT: v_mad_u16 v1, v7, v8, v1
; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v2
; GFX10-DL-NEXT: global_store_byte v0, v1, s[0:1]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <4 x i8>, ptr addrspace(1) %gep1 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
%gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
Show All 19 Lines

llvm/test/CodeGen/AMDGPU/idot8s.ll

Show First 20 Lines • Show All 616 Lines • ▼ Show 20 Lines
; GFX9-DL-NEXT: global_store_short v0, v1, s[2:3] ; GFX9-DL-NEXT: global_store_short v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-XNACK-LABEL: idot8_acc16: ; GFX10-DL-XNACK-LABEL: idot8_acc16:
; GFX10-DL-XNACK: ; %bb.0: ; %entry ; GFX10-DL-XNACK: ; %bb.0: ; %entry
; GFX10-DL-XNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-XNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-XNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-XNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-XNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-XNACK-NEXT: v_mov_b32_e32 v4, 0
; GFX10-DL-XNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-XNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-XNACK-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s10, -1
; GFX10-DL-XNACK-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-DL-XNACK-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-XNACK-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-XNACK-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-XNACK-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-XNACK-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-XNACK-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-XNACK-NEXT: s_clause 0x1 ; GFX10-DL-XNACK-NEXT: s_clause 0x1
; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-XNACK-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-DL-XNACK-NEXT: global_load_ushort v5, v4, s[0:1]
; GFX10-DL-XNACK-NEXT: global_load_ushort v3, v0, s[0:1]
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(2) ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v4, 28, v1 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v0, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 24, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 20, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v8, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v9, 8, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v10, 4, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v16, 4, v2 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v17, 12, v2 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v0, 12, v0
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v11, 28, v2 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v12, 24, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v13, 20, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v15, 12, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v2, 8, v2
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v10, 12, v10
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v16, 12, v16
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v17, 12, v17
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v2, 12, v2
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v10, 12, v10
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v16, 12, v16
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v1, v17, v3 ; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v0, v3, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v9 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 4, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v2 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 4, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 12, v8 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v9, 12, v15
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v10, v16, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v10, 12, v14
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v3, v2, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v7
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v10
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v7, 12, v13
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v8, v9, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 12, v12 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v2, v3, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v8
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v4, 12, v4
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v11
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v6, v7, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v4, 12, v4
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v2, v3, v1 ; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v4, v5, v1 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX10-DL-XNACK-NEXT: global_store_short v0, v1, s[0:1] ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 8, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 12, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 20, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 20, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 24, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 24, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v1, 28, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v2, 28, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v2, 12, v2
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v2
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v1, v2, v0
; GFX10-DL-XNACK-NEXT: global_store_short v4, v0, s[0:1]
; GFX10-DL-XNACK-NEXT: s_endpgm ; GFX10-DL-XNACK-NEXT: s_endpgm
; ;
; GFX10-DL-NOXNACK-LABEL: idot8_acc16: ; GFX10-DL-NOXNACK-LABEL: idot8_acc16:
; GFX10-DL-NOXNACK: ; %bb.0: ; %entry ; GFX10-DL-NOXNACK: ; %bb.0: ; %entry
; GFX10-DL-NOXNACK-NEXT: s_clause 0x1 ; GFX10-DL-NOXNACK-NEXT: s_clause 0x1
; GFX10-DL-NOXNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NOXNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NOXNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NOXNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NOXNACK-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-DL-NOXNACK-NEXT: v_mov_b32_e32 v2, 0
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s10, -1
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-DL-NOXNACK-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-NOXNACK-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-NOXNACK-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-NOXNACK-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-NOXNACK-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NOXNACK-NEXT: s_clause 0x1 ; GFX10-DL-NOXNACK-NEXT: s_clause 0x1
; GFX10-DL-NOXNACK-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NOXNACK-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NOXNACK-NEXT: global_load_dword v0, v0, s[6:7] ; GFX10-DL-NOXNACK-NEXT: global_load_dword v0, v0, s[6:7]
; GFX10-DL-NOXNACK-NEXT: global_load_ushort v3, v2, s[0:1] ; GFX10-DL-NOXNACK-NEXT: global_load_ushort v3, v2, s[0:1]
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(2) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 4, v1
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 4, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 8, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v3, v6, v9, v3
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v4, 28, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v4, 28, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 24, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v6, 24, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v6, 20, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v9, 20, v1
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v3, v7, v8, v3
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 12, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v9, 8, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v11, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 4, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 28, v0
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v3, v5, v10, v3
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v1, 12, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v16, 4, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 24, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v17, 12, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v11, 28, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v12, 24, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v0, 20, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v13, 20, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v14, 16, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v15, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v1 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v10 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v16, 12, v16 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v17, 12, v17 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v9 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v0, 12, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v0, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v10, 12, v10 ; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v1, v1, v11, v3
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v16, 12, v16 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v3, 12, v6
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v1, v1, v17, v3
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v3, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v0, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v15
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v1, v10, v16, v1
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v14
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v3, v0, v1 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v0, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v7 ; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v1, v7, v5, v1
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v3, 12, v10 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v6 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v13
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v8, v9, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 12, v12
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v1, v3, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v3, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v4, 12, v4 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v4, 12, v4
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v11 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v6, v7, v0 ; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v9, v0, v1
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v4, 12, v4 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v4
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v5 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v4, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v1, v3, v0 ; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v1, v4, v0
; GFX10-DL-NOXNACK-NEXT: global_store_short v2, v0, s[0:1] ; GFX10-DL-NOXNACK-NEXT: global_store_short v2, v0, s[0:1]
; GFX10-DL-NOXNACK-NEXT: s_endpgm ; GFX10-DL-NOXNACK-NEXT: s_endpgm
; GFX10-DL-LABEL: idot8_acc16: ; GFX10-DL-LABEL: idot8_acc16:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 ; GFX10-DL-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX10-DL-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 ; GFX10-DL-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
▲ Show 20 Lines • Show All 409 Lines • ▼ Show 20 Lines
; GFX9-DL-NEXT: global_store_byte v0, v1, s[2:3] ; GFX9-DL-NEXT: global_store_byte v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-XNACK-LABEL: idot8_acc8: ; GFX10-DL-XNACK-LABEL: idot8_acc8:
; GFX10-DL-XNACK: ; %bb.0: ; %entry ; GFX10-DL-XNACK: ; %bb.0: ; %entry
; GFX10-DL-XNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-XNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-XNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-XNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-XNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-XNACK-NEXT: v_mov_b32_e32 v4, 0
; GFX10-DL-XNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-XNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-XNACK-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s10, -1
; GFX10-DL-XNACK-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-DL-XNACK-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-XNACK-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-XNACK-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-XNACK-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-XNACK-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-XNACK-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-XNACK-NEXT: s_clause 0x1 ; GFX10-DL-XNACK-NEXT: s_clause 0x1
; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-XNACK-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-DL-XNACK-NEXT: global_load_ubyte v5, v4, s[0:1]
; GFX10-DL-XNACK-NEXT: global_load_ubyte v3, v0, s[0:1]
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(2) ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v4, 28, v1 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v0, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 24, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 20, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v8, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v9, 8, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v10, 4, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v16, 4, v2 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v17, 12, v2 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v0, 12, v0
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v11, 28, v2 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v12, 24, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v13, 20, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v15, 12, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v2, 8, v2
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v10, 12, v10
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v16, 12, v16
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v17, 12, v17
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v2, 12, v2
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v10, 12, v10
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v16, 12, v16
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v1, v17, v3 ; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v0, v3, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v9 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 4, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v2 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 4, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 12, v8 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v9, 12, v15
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v10, v16, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v10, 12, v14
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v3, v2, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v7
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v10
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v7, 12, v13
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v8, v9, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 12, v12 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v6 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v7, 12, v7 ; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v2, v3, v1 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v5 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 8, v2
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v8 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v4, 12, v4 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v11 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v6, v7, v1 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v4, 12, v4 ; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 12, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v2, v3, v1 ; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-XNACK-NEXT: v_mad_u16 v1, v4, v5, v1 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX10-DL-XNACK-NEXT: global_store_byte v0, v1, s[0:1] ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 20, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 20, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 24, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 24, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v1, 28, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v2, 28, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v2, 12, v2
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v2
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v1, v2, v0
; GFX10-DL-XNACK-NEXT: global_store_byte v4, v0, s[0:1]
; GFX10-DL-XNACK-NEXT: s_endpgm ; GFX10-DL-XNACK-NEXT: s_endpgm
; ;
; GFX10-DL-NOXNACK-LABEL: idot8_acc8: ; GFX10-DL-NOXNACK-LABEL: idot8_acc8:
; GFX10-DL-NOXNACK: ; %bb.0: ; %entry ; GFX10-DL-NOXNACK: ; %bb.0: ; %entry
; GFX10-DL-NOXNACK-NEXT: s_clause 0x1 ; GFX10-DL-NOXNACK-NEXT: s_clause 0x1
; GFX10-DL-NOXNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NOXNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NOXNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NOXNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NOXNACK-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-DL-NOXNACK-NEXT: v_mov_b32_e32 v2, 0
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s10, -1
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-DL-NOXNACK-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-NOXNACK-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-NOXNACK-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-NOXNACK-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-NOXNACK-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NOXNACK-NEXT: s_clause 0x1 ; GFX10-DL-NOXNACK-NEXT: s_clause 0x1
; GFX10-DL-NOXNACK-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NOXNACK-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NOXNACK-NEXT: global_load_dword v0, v0, s[6:7] ; GFX10-DL-NOXNACK-NEXT: global_load_dword v0, v0, s[6:7]
; GFX10-DL-NOXNACK-NEXT: global_load_ubyte v3, v2, s[0:1] ; GFX10-DL-NOXNACK-NEXT: global_load_ubyte v3, v2, s[0:1]
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(2) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 4, v1
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 4, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 8, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v3, v6, v9, v3
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v4, 28, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v4, 28, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 24, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v6, 24, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v6, 20, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v9, 20, v1
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v3, v7, v8, v3
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 12, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v9, 8, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v11, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 4, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 28, v0
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v3, v5, v10, v3
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v1, 12, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v16, 4, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 24, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v17, 12, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v11, 28, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v12, 24, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v0, 20, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v13, 20, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v14, 16, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v15, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v1 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v10 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v16, 12, v16 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v17, 12, v17 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v9 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v0, 12, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v0, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v10, 12, v10 ; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v1, v1, v11, v3
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v16, 12, v16 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v3, 12, v6
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v1, v1, v17, v3
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v3, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v0, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v15
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v1, v10, v16, v1
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v14
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v3, v0, v1 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v0, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v7 ; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v1, v7, v5, v1
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v3, 12, v10 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v6 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v13
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v8, v9, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 12, v12
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v1, v3, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v3, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v4, 12, v4 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v4, 12, v4
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v11 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v6, v7, v0 ; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v9, v0, v1
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v4, 12, v4 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v4
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v5 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v4, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v1, v3, v0 ; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v3, v5, v0
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v1, v4, v0
; GFX10-DL-NOXNACK-NEXT: global_store_byte v2, v0, s[0:1] ; GFX10-DL-NOXNACK-NEXT: global_store_byte v2, v0, s[0:1]
; GFX10-DL-NOXNACK-NEXT: s_endpgm ; GFX10-DL-NOXNACK-NEXT: s_endpgm
; GFX10-DL-LABEL: idot8_acc8: ; GFX10-DL-LABEL: idot8_acc8:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 ; GFX10-DL-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX10-DL-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 ; GFX10-DL-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
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; GFX10-DL-XNACK-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-XNACK-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-XNACK-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-XNACK-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-XNACK-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-XNACK-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-XNACK-NEXT: s_clause 0x1 ; GFX10-DL-XNACK-NEXT: s_clause 0x1
; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-XNACK-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-DL-XNACK-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v0, v1, 0, 4 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v0, v1, 4, 4
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v3, v1, 4, 4
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v4, v2, 4, 4 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v3, v2, 4, 4
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v5, v1, 8, 4 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v4, v2, 8, 4
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v6, v2, 8, 4 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v5, v2, 0, 4
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v7, v2, 0, 4 ; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v0, v0, v3
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v8, v1, 12, 4 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v3, v1, 8, 4
; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v3, v3, v4 ; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v3, v3, v4
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v9, v2, 12, 4 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v4, v1, 0, 4
; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v4, v5, v6
; GFX10-DL-XNACK-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-XNACK-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-XNACK-NEXT: v_mad_i32_i24 v5, v0, v7, s2 ; GFX10-DL-XNACK-NEXT: v_mad_i32_i24 v6, v4, v5, s2
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v6, v1, 16, 4 ; GFX10-DL-XNACK-NEXT: v_mad_i32_i24 v4, v4, v5, v6
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v10, v2, 16, 4 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v5, v2, 16, 4
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v11, v1, 20, 4 ; GFX10-DL-XNACK-NEXT: v_add3_u32 v0, v4, v0, v3
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v12, v2, 20, 4 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v3, v1, 12, 4
; GFX10-DL-XNACK-NEXT: v_mad_i32_i24 v0, v0, v7, v5 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v4, v2, 12, 4
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v7, v1, 24, 4 ; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v3, v3, v4
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v13, v2, 24, 4 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v4, v1, 16, 4
; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v8, v8, v9 ; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v4, v4, v5
; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v6, v6, v10 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v5, v2, 24, 4
; GFX10-DL-XNACK-NEXT: v_add3_u32 v0, v0, v3, v4 ; GFX10-DL-XNACK-NEXT: v_add3_u32 v0, v0, v3, v4
; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v3, v11, v12 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v3, v1, 20, 4
; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v4, v7, v13 ; GFX10-DL-XNACK-NEXT: v_bfe_i32 v4, v2, 20, 4
; GFX10-DL-XNACK-NEXT: v_ashrrev_i32_e32 v1, 28, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i32_e32 v2, 28, v2 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i32_e32 v2, 28, v2
; GFX10-DL-XNACK-NEXT: v_add3_u32 v0, v0, v8, v6 ; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v3, v3, v4
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v4, v1, 24, 4
; GFX10-DL-XNACK-NEXT: v_ashrrev_i32_e32 v1, 28, v1
; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v4, v4, v5
; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v1, v1, v2 ; GFX10-DL-XNACK-NEXT: v_mul_i32_i24_e32 v1, v1, v2
; GFX10-DL-XNACK-NEXT: v_add3_u32 v0, v0, v3, v4
; GFX10-DL-XNACK-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-DL-XNACK-NEXT: v_mov_b32_e32 v2, 0
; GFX10-DL-XNACK-NEXT: v_add3_u32 v0, v0, v1, v5 ; GFX10-DL-XNACK-NEXT: v_add3_u32 v0, v0, v3, v4
; GFX10-DL-XNACK-NEXT: v_add3_u32 v0, v0, v1, v6
; GFX10-DL-XNACK-NEXT: global_store_dword v2, v0, s[0:1] ; GFX10-DL-XNACK-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-DL-XNACK-NEXT: s_endpgm ; GFX10-DL-XNACK-NEXT: s_endpgm
; ;
; GFX10-DL-NOXNACK-LABEL: idot8_multiuses_mul1: ; GFX10-DL-NOXNACK-LABEL: idot8_multiuses_mul1:
; GFX10-DL-NOXNACK: ; %bb.0: ; %entry ; GFX10-DL-NOXNACK: ; %bb.0: ; %entry
; GFX10-DL-NOXNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NOXNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NOXNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NOXNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s10, -1
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-DL-NOXNACK-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-NOXNACK-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-NOXNACK-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-NOXNACK-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-NOXNACK-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NOXNACK-NEXT: s_clause 0x1 ; GFX10-DL-NOXNACK-NEXT: s_clause 0x1
; GFX10-DL-NOXNACK-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NOXNACK-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NOXNACK-NEXT: global_load_dword v0, v0, s[6:7] ; GFX10-DL-NOXNACK-NEXT: global_load_dword v0, v0, s[6:7]
; GFX10-DL-NOXNACK-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-DL-NOXNACK-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v2, v1, 0, 4 ; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v2, v1, 0, 4
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v3, v1, 4, 4
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v4, v0, 4, 4 ; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v3, v0, 0, 4
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v5, v1, 8, 4 ; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v4, v1, 4, 4
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v6, v0, 8, 4 ; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v5, v0, 4, 4
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v7, v0, 0, 4 ; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v6, v1, 8, 4
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v7, v0, 8, 4
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v8, v1, 12, 4 ; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v8, v1, 12, 4
; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v3, v3, v4
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v9, v0, 12, 4 ; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v9, v0, 12, 4
; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v4, v5, v6 ; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v4, v4, v5
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v10, v1, 16, 4
; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v5, v6, v7
; GFX10-DL-NOXNACK-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NOXNACK-NEXT: v_mad_i32_i24 v5, v2, v7, s2 ; GFX10-DL-NOXNACK-NEXT: v_mad_i32_i24 v6, v2, v3, s2
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v6, v1, 16, 4 ; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v11, v0, 16, 4
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v10, v0, 16, 4 ; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v7, v8, v9
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v11, v1, 20, 4 ; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v9, v1, 20, 4
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v12, v0, 20, 4 ; GFX10-DL-NOXNACK-NEXT: v_mad_i32_i24 v2, v2, v3, v6
; GFX10-DL-NOXNACK-NEXT: v_mad_i32_i24 v2, v2, v7, v5 ; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v8, v10, v11
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v7, v1, 24, 4 ; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v10, v0, 20, 4
; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v13, v0, 24, 4 ; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v3, v1, 24, 4
; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v8, v8, v9 ; GFX10-DL-NOXNACK-NEXT: v_bfe_i32 v11, v0, 24, 4
; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v6, v6, v10 ; GFX10-DL-NOXNACK-NEXT: v_add3_u32 v2, v2, v4, v5
; GFX10-DL-NOXNACK-NEXT: v_add3_u32 v2, v2, v3, v4
; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v3, v11, v12
; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v4, v7, v13
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i32_e32 v1, 28, v1 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i32_e32 v1, 28, v1
; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v4, v9, v10
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i32_e32 v0, 28, v0 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i32_e32 v0, 28, v0
; GFX10-DL-NOXNACK-NEXT: v_add3_u32 v2, v2, v8, v6 ; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v3, v3, v11
; GFX10-DL-NOXNACK-NEXT: v_add3_u32 v2, v2, v7, v8
; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v0, v1, v0 ; GFX10-DL-NOXNACK-NEXT: v_mul_i32_i24_e32 v0, v1, v0
; GFX10-DL-NOXNACK-NEXT: v_add3_u32 v1, v2, v3, v4 ; GFX10-DL-NOXNACK-NEXT: v_add3_u32 v1, v2, v4, v3
; GFX10-DL-NOXNACK-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-DL-NOXNACK-NEXT: v_mov_b32_e32 v2, 0
; GFX10-DL-NOXNACK-NEXT: v_add3_u32 v0, v1, v0, v5 ; GFX10-DL-NOXNACK-NEXT: v_add3_u32 v0, v1, v0, v6
; GFX10-DL-NOXNACK-NEXT: global_store_dword v2, v0, s[0:1] ; GFX10-DL-NOXNACK-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-DL-NOXNACK-NEXT: s_endpgm ; GFX10-DL-NOXNACK-NEXT: s_endpgm
; GFX10-DL-LABEL: idot8_multiuses_mul1: ; GFX10-DL-LABEL: idot8_multiuses_mul1:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-NEXT: s_mov_b32 s10, -1
; GFX10-DL-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-NEXT: s_mov_b32 s11, 0x31c16000
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; GFX10-DL-XNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-XNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-XNACK-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s10, -1
; GFX10-DL-XNACK-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-DL-XNACK-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-XNACK-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-XNACK-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-XNACK-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-XNACK-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-XNACK-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-XNACK-NEXT: s_clause 0x1 ; GFX10-DL-XNACK-NEXT: s_clause 0x1
; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[6:7]
; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-XNACK-NEXT: global_load_dword v0, v0, s[4:5]
; GFX10-DL-XNACK-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-XNACK-NEXT: global_load_ushort v3, v0, s[0:1]
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 4, v1
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v12, 4, v2 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v2, 24, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v4, 12, v1 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 28, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v11, 12, v2 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v4, 20, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 8, v1 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 12, v1
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 12, v0
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v2, 12, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v4, 12, v4
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v12, 12, v12 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v7, 12, v1 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v8, 16, v1 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v13, 8, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v14, 12, v2
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v4, 12, v4 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v4, 12, v4
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v11, 12, v11
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v12, 12, v12
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 12, v6 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v7, 12, v7 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v7, 12, v0
; GFX10-DL-XNACK-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v8, 20, v0
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 12, v8 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 12, v8
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v13, 12, v13 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v14, 12, v14 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-XNACK-NEXT: v_perm_b32 v11, v12, v11, 0x5040100 ; GFX10-DL-XNACK-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v4, 8, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v4, 12, v4
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v4, 12, v4
; GFX10-DL-XNACK-NEXT: v_perm_b32 v4, v5, v4, 0x5040100 ; GFX10-DL-XNACK-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v9, 20, v1 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 8, v0
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v15, 16, v2 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v16, 20, v2 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 4, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: v_pk_mul_lo_u16 v4, v5, v4
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: v_mov_b32_e32 v5, 0
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v6 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_perm_b32 v1, v6, v1, 0x5040100
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 4, v0
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_perm_b32 v6, v6, v7, 0x5040100
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX10-DL-XNACK-NEXT: v_pk_mul_lo_u16 v1, v6, v1
; GFX10-DL-XNACK-NEXT: global_load_ushort v6, v5, s[0:1]
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v7, 12, v7 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v8 ; GFX10-DL-XNACK-NEXT: v_perm_b32 v7, v8, v7, 0x5040100
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v8, 12, v13 ; GFX10-DL-XNACK-NEXT: v_pk_mul_lo_u16 v3, v7, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v12, 12, v14
; GFX10-DL-XNACK-NEXT: v_pk_mul_lo_u16 v4, v4, v11
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v15, 12, v15
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v16, 12, v16
; GFX10-DL-XNACK-NEXT: v_perm_b32 v8, v12, v8, 0x5040100
; GFX10-DL-XNACK-NEXT: v_perm_b32 v6, v7, v6, 0x5040100
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v4
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v3, v4, v3 ; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v6, v1, v6
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v10, 24, v1 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v1, 28, v1 ; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v1, v6, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v17, 24, v2 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 24, v0
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v9, 12, v9 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v0, 28, v0
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v11, 12, v15 ; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v1, v1, v4
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v2, 28, v2 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v4, 12, v16 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v0, 12, v0
; GFX10-DL-XNACK-NEXT: v_pk_mul_lo_u16 v6, v6, v8 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v3, v3, v7 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v10, 12, v10 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v0, 12, v0
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v1, 12, v1 ; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v1, v1, v4
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v12, 12, v17 ; GFX10-DL-XNACK-NEXT: v_perm_b32 v0, v0, v6, 0x5040100
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v2, 12, v2
; GFX10-DL-XNACK-NEXT: v_perm_b32 v4, v4, v11, 0x5040100
; GFX10-DL-XNACK-NEXT: v_perm_b32 v5, v9, v5, 0x5040100
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v6
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v3, v3, v6
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v10, 12, v10
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v12
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v2
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: v_pk_mul_lo_u16 v4, v5, v4
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v3, v3, v7
; GFX10-DL-XNACK-NEXT: v_perm_b32 v2, v2, v6, 0x5040100
; GFX10-DL-XNACK-NEXT: v_perm_b32 v1, v1, v10, 0x5040100
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 16, v4
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v3, v3, v4
; GFX10-DL-XNACK-NEXT: v_pk_mul_lo_u16 v1, v1, v2
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v2, v3, v5
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v1, v2, v1
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v1, v1, v3 ; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v1, v1, v3
; GFX10-DL-XNACK-NEXT: global_store_short v0, v1, s[0:1] ; GFX10-DL-XNACK-NEXT: v_pk_mul_lo_u16 v0, v0, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v1, v1, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v1, v0
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v0, v2
; GFX10-DL-XNACK-NEXT: global_store_short v5, v0, s[0:1]
; GFX10-DL-XNACK-NEXT: s_endpgm ; GFX10-DL-XNACK-NEXT: s_endpgm
; ;
; GFX10-DL-NOXNACK-LABEL: idot8_acc16_vecMul: ; GFX10-DL-NOXNACK-LABEL: idot8_acc16_vecMul:
; GFX10-DL-NOXNACK: ; %bb.0: ; %entry ; GFX10-DL-NOXNACK: ; %bb.0: ; %entry
; GFX10-DL-NOXNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NOXNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NOXNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NOXNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NOXNACK-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-DL-NOXNACK-NEXT: v_mov_b32_e32 v2, 0
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s10, -1
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-DL-NOXNACK-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-NOXNACK-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-NOXNACK-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-NOXNACK-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-NOXNACK-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NOXNACK-NEXT: s_clause 0x1 ; GFX10-DL-NOXNACK-NEXT: s_clause 0x1
; GFX10-DL-NOXNACK-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NOXNACK-NEXT: global_load_dword v1, v0, s[6:7]
; GFX10-DL-NOXNACK-NEXT: global_load_dword v0, v0, s[6:7] ; GFX10-DL-NOXNACK-NEXT: global_load_dword v0, v0, s[4:5]
; GFX10-DL-NOXNACK-NEXT: global_load_ushort v3, v2, s[0:1] ; GFX10-DL-NOXNACK-NEXT: global_load_ushort v3, v2, s[0:1]
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(2) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 4, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v4, 8, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 12, v1
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v12, 4, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 4, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v4, 12, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v11, 12, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v9, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v6, 8, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v4, 12, v4
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v5 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v12, 12, v12 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v11, 4, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 12, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 16, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v13, 8, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v14, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v4, 12, v4 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v4, 12, v4
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v12, 12, v12
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v5 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v6 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 12, v8 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v13, 12, v13
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v14, 12, v14
; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v11, v12, v11, 0x5040100
; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v4, v5, v4, 0x5040100 ; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v9, 20, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v15, 16, v0 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v16, 20, v0 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v6, 12, v6 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v8 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v8, 12, v13 ; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v8, v9, v8, 0x5040100
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v12, 12, v14 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 16, v0
; GFX10-DL-NOXNACK-NEXT: v_pk_mul_lo_u16 v4, v4, v11 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v9, 20, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v15, 12, v15
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v16, 12, v16
; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v8, v12, v8, 0x5040100
; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v6, v7, v6, 0x5040100 ; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v6, v7, v6, 0x5040100
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v4 ; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v5, v11, v5, 0x5040100
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX10-DL-NOXNACK-NEXT: v_pk_mul_lo_u16 v4, v8, v4
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 20, v1
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_pk_mul_lo_u16 v5, v6, v5
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v11, 24, v0
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v3, v4, v3 ; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v3, v5, v3
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 24, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v1, 28, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v17, 24, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v11, 12, v15
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v0, 28, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v0, 28, v0
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v4, 12, v16 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v6, 24, v1
; GFX10-DL-NOXNACK-NEXT: v_pk_mul_lo_u16 v6, v6, v8
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v3, v3, v7
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v12, 12, v17
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v0, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v4, v4, v11, 0x5040100
; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v5, v9, v5, 0x5040100
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v6
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v3, v3, v6
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v10, 12, v10 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v6, 12, v12 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v0, 12, v0 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v1, 28, v1
; GFX10-DL-NOXNACK-NEXT: v_pk_mul_lo_u16 v4, v5, v4 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v3, v3, v7 ; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v3, v3, v5
; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v0, v0, v6, 0x5040100 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v1, v1, v10, 0x5040100 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v0, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v5, v8, v7, 0x5040100
; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v7, v9, v10, 0x5040100
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 16, v4
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v3, v3, v4 ; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v3, v3, v4
; GFX10-DL-NOXNACK-NEXT: v_pk_mul_lo_u16 v0, v1, v0 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v1, v3, v5 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v4, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v0, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_pk_mul_lo_u16 v5, v7, v5
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v3, v3, v8
; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v1, v1, v4, 0x5040100
; GFX10-DL-NOXNACK-NEXT: v_perm_b32 v0, v0, v11, 0x5040100
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v4, 16, v5
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v3, v3, v5
; GFX10-DL-NOXNACK-NEXT: v_pk_mul_lo_u16 v0, v0, v1
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v1, v3, v4
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v3, 16, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v1, v0 ; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v1, v0
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v0, v3 ; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v0, v3
; GFX10-DL-NOXNACK-NEXT: global_store_short v2, v0, s[0:1] ; GFX10-DL-NOXNACK-NEXT: global_store_short v2, v0, s[0:1]
; GFX10-DL-NOXNACK-NEXT: s_endpgm ; GFX10-DL-NOXNACK-NEXT: s_endpgm
; GFX10-DL-LABEL: idot8_acc16_vecMul: ; GFX10-DL-LABEL: idot8_acc16_vecMul:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
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; GFX9-DL-NEXT: global_store_byte v3, v0, s[2:3] ; GFX9-DL-NEXT: global_store_byte v3, v0, s[2:3]
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-XNACK-LABEL: idot8_acc8_vecMul: ; GFX10-DL-XNACK-LABEL: idot8_acc8_vecMul:
; GFX10-DL-XNACK: ; %bb.0: ; %entry ; GFX10-DL-XNACK: ; %bb.0: ; %entry
; GFX10-DL-XNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-XNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-XNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-XNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-XNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-XNACK-NEXT: v_mov_b32_e32 v4, 0
; GFX10-DL-XNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-XNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-XNACK-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s10, -1
; GFX10-DL-XNACK-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-XNACK-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-DL-XNACK-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-XNACK-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-XNACK-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-XNACK-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-XNACK-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-XNACK-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-XNACK-NEXT: s_clause 0x1 ; GFX10-DL-XNACK-NEXT: s_clause 0x1
; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-XNACK-NEXT: global_load_ubyte v3, v4, s[0:1]
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v8, 12, v1
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v15, 12, v2 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v0, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v9, 8, v1 ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v16, 8, v2 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v10, 4, v1 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v4, 20, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 28, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 12, v2
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v0, 12, v0
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v4, 12, v4
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v7, 8, v2
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v0, v0, v3
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 20, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v4, 12, v4
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v8, 4, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v9, 16, v2
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 12, v8 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 12, v8
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v15, 12, v15
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v17, 4, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v9, 12, v9 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v16, 12, v16 ; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v3, v3, v4
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v4, 28, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v8, 12, v8 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v15, 12, v15
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v0, 20, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 28, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v11, 20, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v13, 28, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v10, 12, v10
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v17, 12, v17
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v9, 12, v9 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v16, 12, v16 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v8, v8, v15 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v4, 12, v4
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 16, v1 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v4, 12, v4
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v7, 24, v1 ; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v4, v4, v5
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v12, 16, v2 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v14, 24, v2 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v4, 8, v4
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v2, 12, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v0, 12, v0
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v13, 12, v13
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v11, 12, v11
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v10, 12, v10
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v15, 12, v17
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v9, v9, v16
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 8, v8
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v2 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v14, 12, v14 ; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v5, v5, v6
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v12, 12, v12 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 8, v1
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v6 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v0, 12, v0 ; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v6, v6, v7
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v13, 12, v13 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v7, 4, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v11, 12, v11 ; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v10, v10, v15 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v7, 12, v7 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5 ; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v7, v7, v8
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v14, 12, v14 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v12, 12, v12 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 8, v7
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v1, v1, v2 ; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 12, v8
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v2, v0, v11 ; GFX10-DL-XNACK-NEXT: v_mov_b32_e32 v7, 0
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v6, v6, v13 ; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v0, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v9, 8, v10 ; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-XNACK-NEXT: v_lshlrev_b32_e32 v0, 16, v8 ; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v10, v8, v9
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v10, v5, v12 ; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v3, v10, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v11, v7, v14 ; GFX10-DL-XNACK-NEXT: global_load_ubyte v10, v7, s[0:1]
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v2, 8, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 8, v6
; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v13, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v2, v10, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v9, v11, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v10, 8, v13
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v3, v1, v3 ; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v10, v0, v10
; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v1, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v0, 24, v1
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v9, v3, v10 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v1, 24, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v0, 12, v0
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v11, 12, v0
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v12, 12, v1
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v0, v11, v12
; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v1, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-DL-XNACK-NEXT: v_lshlrev_b32_e32 v0, 16, v5
; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v2, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v2, 8, v2
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v2, v10, v2
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v5, v2, v5
; GFX10-DL-XNACK-NEXT: v_lshrrev_b64 v[2:3], 24, v[0:1] ; GFX10-DL-XNACK-NEXT: v_lshrrev_b64 v[2:3], 24, v[0:1]
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v1 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v9, v8 ; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v5, v2
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v0, v2 ; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v8, v9, v0
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v5, v12, v0
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v0, v1 ; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v0, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v6 ; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v4
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v7, v14, v0 ; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v11, v12, v0
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v0, v1 ; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v0, v1
; GFX10-DL-XNACK-NEXT: global_store_byte v4, v0, s[0:1] ; GFX10-DL-XNACK-NEXT: global_store_byte v7, v0, s[0:1]
; GFX10-DL-XNACK-NEXT: s_endpgm ; GFX10-DL-XNACK-NEXT: s_endpgm
; ;
; GFX10-DL-NOXNACK-LABEL: idot8_acc8_vecMul: ; GFX10-DL-NOXNACK-LABEL: idot8_acc8_vecMul:
; GFX10-DL-NOXNACK: ; %bb.0: ; %entry ; GFX10-DL-NOXNACK: ; %bb.0: ; %entry
; GFX10-DL-NOXNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NOXNACK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NOXNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NOXNACK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NOXNACK-NEXT: v_mov_b32_e32 v4, 0
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s10, -1
; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-NOXNACK-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-DL-NOXNACK-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-NOXNACK-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-NOXNACK-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-NOXNACK-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-NOXNACK-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NOXNACK-NEXT: s_clause 0x1 ; GFX10-DL-NOXNACK-NEXT: s_clause 0x1
; GFX10-DL-NOXNACK-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NOXNACK-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NOXNACK-NEXT: global_load_dword v0, v0, s[6:7] ; GFX10-DL-NOXNACK-NEXT: global_load_dword v0, v0, s[6:7]
; GFX10-DL-NOXNACK-NEXT: global_load_ubyte v2, v4, s[0:1]
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 12, v1
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v15, 12, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v3, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v9, 8, v1 ; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v16, 8, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v4, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 4, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v2, 20, v1
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v15, 12, v15
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v17, 4, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v16, 12, v16
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v15, 12, v15
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v3, 20, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v6, 28, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v6, 28, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v11, 20, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v13, 28, v0 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v4, 12, v4
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 20, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v11, 28, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v2, 12, v2
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v3, v3, v4
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v4, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v10 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v17, 12, v17
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v16, 12, v16
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v8, v8, v15
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v12, 16, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v14, 24, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v6 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v3, 12, v3
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v13, 12, v13
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v11, 12, v11 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v1, 12, v1 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v2, 12, v2
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v0, 12, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v4, 12, v4
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v10, 12, v10 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v15, 12, v17
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v9, v9, v16
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 8, v8
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v14, 12, v14
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v12, 12, v12
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v6, 12, v6 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v6, 12, v6
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v13, 12, v13
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v11, 12, v11 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v0, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v10, v10, v15
; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v4, 12, v4
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 8, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v9, 4, v1
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v2, v2, v10
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 16, v0
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v6, v6, v11
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v11, 4, v0
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v4, v7, v4
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 8, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v8, 12, v8
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v5 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v5
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v14, 12, v14 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v12, 12, v12 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v3, v3, v11 ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v11, 12, v11
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v6, v6, v13 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v2, 8, v2
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v1, v1, v0 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v1, 24, v1
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 8, v10 ; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v7, v8, v7
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 16, v8 ; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v8, v5, v10
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v10, v5, v12 ; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v9, v9, v11
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v11, v7, v14 ; GFX10-DL-NOXNACK-NEXT: v_mov_b32_e32 v11, 0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v3, 8, v3 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v0, 24, v0
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v2, v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 8, v6 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 8, v6
; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v13, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX10-DL-NOXNACK-NEXT: global_load_ubyte v8, v11, s[0:1]
; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v0, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v3, v10, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v12, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v9, v11, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v1, 8, v4
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 8, v13 ; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 8, v9
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v4, 12, v0
; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v7, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v0, v12, v4
; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v0, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v1, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 16, v7
; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v2, v3, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v3, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v3, 8, v3
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v2, v1, v2 ; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v2, v2, v8
; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v1, v3, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v8, v2, v3
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v9, v2, v10
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b64 v[2:3], 24, v[0:1] ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b64 v[2:3], 24, v[0:1]
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v1 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v9, v8 ; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v8, v7
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v0, v2 ; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v0, v2
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v5, v12, v0 ; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v5, v10, v0
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v0, v1 ; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v0, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v6 ; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v6
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v7, v14, v0 ; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v12, v4, v0
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v0, v1 ; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v0, v1
; GFX10-DL-NOXNACK-NEXT: global_store_byte v4, v0, s[0:1] ; GFX10-DL-NOXNACK-NEXT: global_store_byte v11, v0, s[0:1]
; GFX10-DL-NOXNACK-NEXT: s_endpgm ; GFX10-DL-NOXNACK-NEXT: s_endpgm
; GFX10-DL-LABEL: idot8_acc8_vecMul: ; GFX10-DL-LABEL: idot8_acc8_vecMul:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0 ; GFX10-DL-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0
; GFX10-DL-NEXT: s_mov_b32 s21, SCRATCH_RSRC_DWORD1 ; GFX10-DL-NEXT: s_mov_b32 s21, SCRATCH_RSRC_DWORD1
; GFX10-DL-NEXT: s_mov_b32 s22, -1 ; GFX10-DL-NEXT: s_mov_b32 s22, -1
▲ Show 20 Lines • Show All 126 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/idot8u.ll

Show First 20 Lines • Show All 491 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ushort v4, v1, s[2:3] ; GFX10-DL-NEXT: global_load_ushort v4, v1, s[2:3]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2) ; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v2
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v3 ; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v3
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v3, 4, 4
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4 ; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 4, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 8, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 8, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 8, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 8, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 12, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v3, 12, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 12, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 16, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 16, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 16, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 16, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 20, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 20, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v3, 20, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 20, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 24, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 24, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 24, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 24, 4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 28, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 28, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 28, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 28, v3
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0
; GFX10-DL-NEXT: global_store_short v1, v0, s[2:3] ; GFX10-DL-NEXT: global_store_short v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
▲ Show 20 Lines • Show All 281 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3] ; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2) ; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v2
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v3 ; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v3
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v3, 4, 4
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4 ; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 4, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 8, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 8, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 8, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 8, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 12, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v3, 12, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 12, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 16, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 16, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 16, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 16, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 20, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 20, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v3, 20, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 20, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 24, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 24, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 24, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 24, 4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 28, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 28, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 28, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 28, v3
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0
; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3] ; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
▲ Show 20 Lines • Show All 285 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3] ; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2) ; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v2
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v3 ; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v3
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v3, 4, 4
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4 ; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 4, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 8, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 8, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 8, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 8, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 12, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v3, 12, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 12, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 16, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 16, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 16, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 16, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 20, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 20, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v3, 20, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 20, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 24, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 24, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 24, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 24, v3
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 28, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 28, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 28, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 28, v3
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0
; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v0 ; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v0
; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3] ; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
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; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3] ; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2) ; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v2
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v3 ; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v3
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v3, 4, 4
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4 ; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 4, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 8, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 8, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 8, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 8, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 12, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v3, 12, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 12, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 16, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 16, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 16, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 16, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 20, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 20, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v3, 20, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v3, 20, 4
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 24, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 24, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 24, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 24, v3
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 28, v2 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 28, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 28, v3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 28, v3
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v4, v5, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0
; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v0 ; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v0
; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3] ; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
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; GFX10-DL-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_and_b32_e32 v8, 15, v1 ; GFX10-DL-NEXT: v_bfe_u32 v0, v1, 8, 4
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_and_b32_e32 v9, 15, v2 ; GFX10-DL-NEXT: v_bfe_u32 v3, v2, 8, 4
; GFX10-DL-NEXT: v_bfe_u32 v0, v1, 4, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 12, 4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 28, v1 ; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v2
; GFX10-DL-NEXT: v_bfe_u32 v4, v1, 24, 4 ; GFX10-DL-NEXT: v_bfe_u32 v6, v1, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v5, v1, 20, 4 ; GFX10-DL-NEXT: v_bfe_u32 v7, v2, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v6, v1, 16, 4 ; GFX10-DL-NEXT: v_mul_u32_u24_e32 v0, v0, v3
; GFX10-DL-NEXT: v_bfe_u32 v7, v1, 12, 4 ; GFX10-DL-NEXT: v_bfe_u32 v3, v1, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v1, v1, 8, 4 ; GFX10-DL-NEXT: v_mul_u32_u24_e32 v3, v3, v4
; GFX10-DL-NEXT: v_bfe_u32 v10, v2, 4, 4 ; GFX10-DL-NEXT: v_and_b32_e32 v4, 15, v1
; GFX10-DL-NEXT: v_bfe_u32 v11, v2, 8, 4
; GFX10-DL-NEXT: v_bfe_u32 v12, v2, 12, 4
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v13, v8, v9, s2 ; GFX10-DL-NEXT: v_mad_u32_u24 v8, v4, v5, s2
; GFX10-DL-NEXT: v_bfe_u32 v14, v2, 20, 4 ; GFX10-DL-NEXT: v_mad_u32_u24 v6, v6, v7, v8
; GFX10-DL-NEXT: v_bfe_u32 v15, v2, 16, 4 ; GFX10-DL-NEXT: v_bfe_u32 v7, v2, 20, 4
; GFX10-DL-NEXT: v_mul_u32_u24_e32 v1, v1, v11 ; GFX10-DL-NEXT: v_add3_u32 v0, v6, v0, v3
; GFX10-DL-NEXT: v_mul_u32_u24_e32 v7, v7, v12 ; GFX10-DL-NEXT: v_bfe_u32 v3, v1, 16, 4
; GFX10-DL-NEXT: v_mad_u32_u24 v0, v0, v10, v13 ; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 16, 4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v10, 28, v2 ; GFX10-DL-NEXT: v_mul_u32_u24_e32 v3, v3, v6
; GFX10-DL-NEXT: v_bfe_u32 v2, v2, 24, 4 ; GFX10-DL-NEXT: v_bfe_u32 v6, v1, 20, 4
; GFX10-DL-NEXT: v_mul_u32_u24_e32 v6, v6, v15 ; GFX10-DL-NEXT: v_mul_u32_u24_e32 v6, v6, v7
; GFX10-DL-NEXT: v_mul_u32_u24_e32 v5, v5, v14 ; GFX10-DL-NEXT: v_add3_u32 v0, v0, v3, v6
; GFX10-DL-NEXT: v_add3_u32 v0, v0, v1, v7 ; GFX10-DL-NEXT: v_bfe_u32 v3, v1, 24, 4
; GFX10-DL-NEXT: v_mul_u32_u24_e32 v1, v4, v2 ; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 24, 4
; GFX10-DL-NEXT: v_mul_u32_u24_e32 v2, v3, v10 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 28, v1
; GFX10-DL-NEXT: v_mul_u32_u24_e32 v3, v8, v9 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 28, v2
; GFX10-DL-NEXT: v_add3_u32 v0, v0, v6, v5 ; GFX10-DL-NEXT: v_mul_u32_u24_e32 v3, v3, v6
; GFX10-DL-NEXT: v_add3_u32 v0, v0, v1, v2 ; GFX10-DL-NEXT: v_mul_u32_u24_e32 v1, v1, v2
; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
; GFX10-DL-NEXT: v_add3_u32 v0, v3, v13, v0 ; GFX10-DL-NEXT: v_add3_u32 v0, v0, v3, v1
; GFX10-DL-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10-DL-NEXT: v_mul_u32_u24_e32 v1, v4, v5
; GFX10-DL-NEXT: v_add3_u32 v0, v1, v8, v0
; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <8 x i4>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <8 x i4>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <8 x i4>, ptr addrspace(1) %gep1 %vec1 = load <8 x i4>, ptr addrspace(1) %gep1
%gep2 = getelementptr <8 x i4>, ptr addrspace(1) %src2, i32 %idx %gep2 = getelementptr <8 x i4>, ptr addrspace(1) %src2, i32 %idx
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; GFX10-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-NEXT: s_mov_b32 s10, -1
; GFX10-DL-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-DL-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v0, v0, s[4:5]
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: global_load_ushort v3, v0, s[0:1]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_and_b32_e32 v4, 15, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v2 ; GFX10-DL-NEXT: v_bfe_u32 v2, v1, 24, 4
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 4, 4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 28, v1
; GFX10-DL-NEXT: v_bfe_u32 v7, v1, 4, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v1, 20, 4
; GFX10-DL-NEXT: v_bfe_u32 v8, v2, 12, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v1, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v9, v1, 12, 4 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_bfe_u32 v10, v1, 20, 4 ; GFX10-DL-NEXT: v_bfe_u32 v6, v0, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v0, 4, 4
; GFX10-DL-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
; GFX10-DL-NEXT: v_bfe_u32 v3, v1, 16, 4
; GFX10-DL-NEXT: v_bfe_u32 v8, v0, 20, 4
; GFX10-DL-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
; GFX10-DL-NEXT: v_bfe_u32 v4, v1, 8, 4
; GFX10-DL-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
; GFX10-DL-NEXT: v_bfe_u32 v5, v0, 8, 4
; GFX10-DL-NEXT: v_perm_b32 v5, v6, v5, 0x5040100 ; GFX10-DL-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
; GFX10-DL-NEXT: v_perm_b32 v4, v7, v4, 0x5040100 ; GFX10-DL-NEXT: v_and_b32_e32 v6, 15, v1
; GFX10-DL-NEXT: v_bfe_u32 v6, v1, 8, 4 ; GFX10-DL-NEXT: v_bfe_u32 v1, v1, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v2, 8, 4 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v5, v4
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5 ; GFX10-DL-NEXT: v_mov_b32_e32 v5, 0
; GFX10-DL-NEXT: v_perm_b32 v6, v9, v6, 0x5040100 ; GFX10-DL-NEXT: v_perm_b32 v1, v1, v6, 0x5040100
; GFX10-DL-NEXT: v_and_b32_e32 v6, 15, v0
; GFX10-DL-NEXT: v_perm_b32 v6, v7, v6, 0x5040100
; GFX10-DL-NEXT: v_bfe_u32 v7, v0, 16, 4
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v1, v6, v1
; GFX10-DL-NEXT: global_load_ushort v6, v5, s[0:1]
; GFX10-DL-NEXT: v_perm_b32 v7, v8, v7, 0x5040100 ; GFX10-DL-NEXT: v_perm_b32 v7, v8, v7, 0x5040100
; GFX10-DL-NEXT: v_bfe_u32 v5, v1, 16, 4 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v7, v3
; GFX10-DL-NEXT: v_bfe_u32 v9, v2, 20, 4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 16, v4
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u16 v3, v4, v3 ; GFX10-DL-NEXT: v_add_nc_u16 v6, v1, v6
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 16, 4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v6, v6, v7 ; GFX10-DL-NEXT: v_add_nc_u16 v1, v6, v1
; GFX10-DL-NEXT: v_perm_b32 v5, v10, v5, 0x5040100 ; GFX10-DL-NEXT: v_bfe_u32 v6, v0, 24, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v1, 24, 4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 28, v0
; GFX10-DL-NEXT: v_add_nc_u16 v3, v3, v8 ; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v4
; GFX10-DL-NEXT: v_perm_b32 v4, v9, v4, 0x5040100 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 16, v6 ; GFX10-DL-NEXT: v_perm_b32 v0, v0, v6, 0x5040100
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 28, v1 ; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v4
; GFX10-DL-NEXT: v_add_nc_u16 v3, v3, v6 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v0, v0, v2
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 24, 4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 28, v2
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v5, v4
; GFX10-DL-NEXT: v_perm_b32 v1, v1, v7, 0x5040100
; GFX10-DL-NEXT: v_add_nc_u16 v3, v3, v8
; GFX10-DL-NEXT: v_perm_b32 v2, v2, v6, 0x5040100
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v4
; GFX10-DL-NEXT: v_add_nc_u16 v3, v3, v4
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v1, v1, v2
; GFX10-DL-NEXT: v_add_nc_u16 v2, v3, v5
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX10-DL-NEXT: v_add_nc_u16 v1, v2, v1
; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v3 ; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v3
; GFX10-DL-NEXT: global_store_short v0, v1, s[0:1] ; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX10-DL-NEXT: v_add_nc_u16 v0, v1, v0
; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v2
; GFX10-DL-NEXT: global_store_short v5, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <8 x i4>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <8 x i4>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <8 x i4>, ptr addrspace(1) %gep1 %vec1 = load <8 x i4>, ptr addrspace(1) %gep1
%gep2 = getelementptr <8 x i4>, ptr addrspace(1) %src2, i32 %idx %gep2 = getelementptr <8 x i4>, ptr addrspace(1) %src2, i32 %idx
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; GFX9-DL-NEXT: global_store_byte v3, v0, s[2:3] ; GFX9-DL-NEXT: global_store_byte v3, v0, s[2:3]
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: udot8_acc8_vecMul: ; GFX10-DL-LABEL: udot8_acc8_vecMul:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NEXT: v_mov_b32_e32 v4, 0
; GFX10-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-NEXT: s_mov_b32 s10, -1
; GFX10-DL-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-DL-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ubyte v3, v4, s[0:1]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_bfe_u32 v6, v1, 12, 4
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_bfe_u32 v9, v2, 12, 4 ; GFX10-DL-NEXT: v_bfe_u32 v0, v1, 20, 4
; GFX10-DL-NEXT: v_bfe_u32 v0, v1, 4, 4 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v1 ; GFX10-DL-NEXT: v_bfe_u32 v3, v2, 20, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v1, 8, 4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 28, v2
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 28, v1 ; GFX10-DL-NEXT: v_bfe_u32 v5, v2, 8, 4
; GFX10-DL-NEXT: v_bfe_u32 v10, v1, 24, 4 ; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v11, v1, 20, 4 ; GFX10-DL-NEXT: v_and_b32_e32 v7, 15, v2
; GFX10-DL-NEXT: v_bfe_u32 v12, v1, 16, 4 ; GFX10-DL-NEXT: v_mul_lo_u16 v0, v0, v3
; GFX10-DL-NEXT: v_bfe_u32 v1, v2, 8, 4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 28, v1
; GFX10-DL-NEXT: v_mul_lo_u16 v6, v6, v9 ; GFX10-DL-NEXT: v_bfe_u32 v8, v2, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v9, v2, 4, 4 ; GFX10-DL-NEXT: v_bfe_u32 v9, v2, 16, 4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v14, 28, v2 ; GFX10-DL-NEXT: v_bfe_u32 v11, v2, 24, 4
; GFX10-DL-NEXT: v_bfe_u32 v15, v2, 20, 4 ; GFX10-DL-NEXT: v_lshlrev_b16 v0, 8, v0
; GFX10-DL-NEXT: v_mul_lo_u16 v1, v7, v1 ; GFX10-DL-NEXT: v_mul_lo_u16 v3, v3, v4
; GFX10-DL-NEXT: v_lshlrev_b16 v6, 8, v6 ; GFX10-DL-NEXT: v_bfe_u32 v4, v1, 8, 4
; GFX10-DL-NEXT: v_and_b32_e32 v13, 15, v2 ; GFX10-DL-NEXT: v_lshlrev_b16 v12, 8, v3
; GFX10-DL-NEXT: v_mul_lo_u16 v0, v0, v9 ; GFX10-DL-NEXT: v_mul_lo_u16 v4, v4, v5
; GFX10-DL-NEXT: v_bfe_u32 v7, v2, 16, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v1, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v16, v2, 24, 4 ; GFX10-DL-NEXT: v_mul_lo_u16 v5, v5, v6
; GFX10-DL-NEXT: v_or_b32_e32 v6, v1, v6 ; GFX10-DL-NEXT: v_and_b32_e32 v6, 15, v1
; GFX10-DL-NEXT: v_mul_lo_u16 v2, v11, v15 ; GFX10-DL-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX10-DL-NEXT: v_mul_lo_u16 v8, v8, v14 ; GFX10-DL-NEXT: v_mul_lo_u16 v6, v6, v7
; GFX10-DL-NEXT: v_lshlrev_b16 v9, 8, v0 ; GFX10-DL-NEXT: v_bfe_u32 v7, v1, 4, 4
; GFX10-DL-NEXT: v_mul_lo_u16 v5, v5, v13 ; GFX10-DL-NEXT: v_or_b32_e32 v4, v4, v5
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 16, v6 ; GFX10-DL-NEXT: v_mul_lo_u16 v7, v7, v8
; GFX10-DL-NEXT: v_mul_lo_u16 v1, v12, v7 ; GFX10-DL-NEXT: v_bfe_u32 v8, v1, 16, 4
; GFX10-DL-NEXT: v_mul_lo_u16 v11, v10, v16 ; GFX10-DL-NEXT: v_lshlrev_b16 v5, 8, v7
; GFX10-DL-NEXT: v_lshlrev_b16 v2, 8, v2 ; GFX10-DL-NEXT: v_mul_lo_u16 v10, v8, v9
; GFX10-DL-NEXT: v_lshlrev_b16 v8, 8, v8 ; GFX10-DL-NEXT: v_mov_b32_e32 v7, 0
; GFX10-DL-NEXT: v_or_b32_sdwa v13, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX10-DL-NEXT: v_or_b32_e32 v6, v6, v5
; GFX10-DL-NEXT: v_or_b32_e32 v5, v5, v9 ; GFX10-DL-NEXT: v_or_b32_e32 v0, v10, v0
; GFX10-DL-NEXT: v_or_b32_e32 v1, v1, v2 ; GFX10-DL-NEXT: global_load_ubyte v10, v7, s[0:1]
; GFX10-DL-NEXT: v_or_b32_sdwa v2, v11, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v9, 8, v13
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u16 v3, v5, v3 ; GFX10-DL-NEXT: v_add_nc_u16 v6, v6, v10
; GFX10-DL-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX10-DL-NEXT: v_bfe_u32 v10, v1, 24, 4
; GFX10-DL-NEXT: v_add_nc_u16 v5, v3, v9 ; GFX10-DL-NEXT: v_mul_lo_u16 v1, v10, v11
; GFX10-DL-NEXT: v_or_b32_sdwa v1, v1, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-DL-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 16, v4
; GFX10-DL-NEXT: v_or_b32_sdwa v2, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 8, v2
; GFX10-DL-NEXT: v_add_nc_u16 v2, v6, v2
; GFX10-DL-NEXT: v_add_nc_u16 v4, v2, v4
; GFX10-DL-NEXT: v_lshrrev_b64 v[2:3], 24, v[0:1] ; GFX10-DL-NEXT: v_lshrrev_b64 v[2:3], 24, v[0:1]
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 8, v1 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX10-DL-NEXT: v_add_nc_u16 v0, v5, v6 ; GFX10-DL-NEXT: v_add_nc_u16 v0, v4, v2
; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v2 ; GFX10-DL-NEXT: v_mad_u16 v0, v8, v9, v0
; GFX10-DL-NEXT: v_mad_u16 v0, v12, v7, v0
; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v1 ; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v1
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 8, v8 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 8, v12
; GFX10-DL-NEXT: v_mad_u16 v0, v10, v16, v0 ; GFX10-DL-NEXT: v_mad_u16 v0, v10, v11, v0
; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v1 ; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v1
; GFX10-DL-NEXT: global_store_byte v4, v0, s[0:1] ; GFX10-DL-NEXT: global_store_byte v7, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <8 x i4>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <8 x i4>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <8 x i4>, ptr addrspace(1) %gep1 %vec1 = load <8 x i4>, ptr addrspace(1) %gep1
%gep2 = getelementptr <8 x i4>, ptr addrspace(1) %src2, i32 %idx %gep2 = getelementptr <8 x i4>, ptr addrspace(1) %src2, i32 %idx
▲ Show 20 Lines • Show All 263 Lines • ▼ Show 20 Lines
; GFX10-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-DL-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-DL-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-DL-NEXT: s_mov_b32 s10, -1 ; GFX10-DL-NEXT: s_mov_b32 s10, -1
; GFX10-DL-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-DL-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-DL-NEXT: s_add_u32 s8, s8, s3 ; GFX10-DL-NEXT: s_add_u32 s8, s8, s3
; GFX10-DL-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-DL-NEXT: s_addc_u32 s9, s9, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] ; GFX10-DL-NEXT: global_load_dword v0, v0, s[4:5]
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: global_load_ubyte v3, v0, s[0:1]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NEXT: v_and_b32_e32 v4, 15, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(1) ; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v2 ; GFX10-DL-NEXT: v_bfe_u32 v2, v1, 24, 4
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 4, 4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 28, v1
; GFX10-DL-NEXT: v_bfe_u32 v7, v1, 4, 4 ; GFX10-DL-NEXT: v_bfe_u32 v4, v1, 20, 4
; GFX10-DL-NEXT: v_bfe_u32 v8, v2, 12, 4 ; GFX10-DL-NEXT: v_bfe_u32 v5, v1, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v9, v1, 12, 4 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_bfe_u32 v10, v1, 20, 4 ; GFX10-DL-NEXT: v_bfe_u32 v6, v0, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v0, 4, 4
; GFX10-DL-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
; GFX10-DL-NEXT: v_bfe_u32 v3, v1, 16, 4
; GFX10-DL-NEXT: v_bfe_u32 v8, v0, 20, 4
; GFX10-DL-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
; GFX10-DL-NEXT: v_bfe_u32 v4, v1, 8, 4
; GFX10-DL-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
; GFX10-DL-NEXT: v_bfe_u32 v5, v0, 8, 4
; GFX10-DL-NEXT: v_perm_b32 v5, v6, v5, 0x5040100 ; GFX10-DL-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
; GFX10-DL-NEXT: v_perm_b32 v4, v7, v4, 0x5040100 ; GFX10-DL-NEXT: v_and_b32_e32 v6, 15, v1
; GFX10-DL-NEXT: v_bfe_u32 v6, v1, 8, 4 ; GFX10-DL-NEXT: v_bfe_u32 v1, v1, 4, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v2, 8, 4 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v5, v4
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5 ; GFX10-DL-NEXT: v_mov_b32_e32 v5, 0
; GFX10-DL-NEXT: v_perm_b32 v6, v9, v6, 0x5040100 ; GFX10-DL-NEXT: v_perm_b32 v1, v1, v6, 0x5040100
; GFX10-DL-NEXT: v_and_b32_e32 v6, 15, v0
; GFX10-DL-NEXT: v_perm_b32 v6, v7, v6, 0x5040100
; GFX10-DL-NEXT: v_bfe_u32 v7, v0, 16, 4
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v1, v6, v1
; GFX10-DL-NEXT: global_load_ubyte v6, v5, s[0:1]
; GFX10-DL-NEXT: v_perm_b32 v7, v8, v7, 0x5040100 ; GFX10-DL-NEXT: v_perm_b32 v7, v8, v7, 0x5040100
; GFX10-DL-NEXT: v_bfe_u32 v5, v1, 16, 4 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v7, v3
; GFX10-DL-NEXT: v_bfe_u32 v9, v2, 20, 4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 16, v4
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u16 v3, v4, v3 ; GFX10-DL-NEXT: v_add_nc_u16 v6, v1, v6
; GFX10-DL-NEXT: v_bfe_u32 v4, v2, 16, 4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v6, v6, v7 ; GFX10-DL-NEXT: v_add_nc_u16 v1, v6, v1
; GFX10-DL-NEXT: v_perm_b32 v5, v10, v5, 0x5040100 ; GFX10-DL-NEXT: v_bfe_u32 v6, v0, 24, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v1, 24, 4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 28, v0
; GFX10-DL-NEXT: v_add_nc_u16 v3, v3, v8 ; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v4
; GFX10-DL-NEXT: v_perm_b32 v4, v9, v4, 0x5040100 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 16, v6 ; GFX10-DL-NEXT: v_perm_b32 v0, v0, v6, 0x5040100
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 28, v1 ; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v4
; GFX10-DL-NEXT: v_add_nc_u16 v3, v3, v6 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v0, v0, v2
; GFX10-DL-NEXT: v_bfe_u32 v6, v2, 24, 4 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 28, v2
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v5, v4
; GFX10-DL-NEXT: v_perm_b32 v1, v1, v7, 0x5040100
; GFX10-DL-NEXT: v_add_nc_u16 v3, v3, v8
; GFX10-DL-NEXT: v_perm_b32 v2, v2, v6, 0x5040100
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v4
; GFX10-DL-NEXT: v_add_nc_u16 v3, v3, v4
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v1, v1, v2
; GFX10-DL-NEXT: v_add_nc_u16 v2, v3, v5
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX10-DL-NEXT: v_add_nc_u16 v1, v2, v1
; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v3 ; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v3
; GFX10-DL-NEXT: v_and_b32_e32 v1, 15, v1 ; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v2
; GFX10-DL-NEXT: global_store_byte v0, v1, s[0:1] ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX10-DL-NEXT: v_add_nc_u16 v0, v1, v0
; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v2
; GFX10-DL-NEXT: v_and_b32_e32 v0, 15, v0
; GFX10-DL-NEXT: global_store_byte v5, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm ; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2, ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) { ptr addrspace(1) nocapture %dst) {
entry: entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x() %idx = call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr <8 x i4>, ptr addrspace(1) %src1, i32 %idx %gep1 = getelementptr <8 x i4>, ptr addrspace(1) %src1, i32 %idx
%vec1 = load <8 x i4>, ptr addrspace(1) %gep1 %vec1 = load <8 x i4>, ptr addrspace(1) %gep1
%gep2 = getelementptr <8 x i4>, ptr addrspace(1) %src2, i32 %idx %gep2 = getelementptr <8 x i4>, ptr addrspace(1) %src2, i32 %idx
▲ Show 20 Lines • Show All 260 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll

Show First 20 Lines • Show All 991 Lines • ▼ Show 20 Lines
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_b128 v[0:3], v8, s[6:7] ; GFX11-NEXT: global_load_b128 v[0:3], v8, s[6:7]
; GFX11-NEXT: global_load_b128 v[4:7], v8, s[6:7] offset:16 ; GFX11-NEXT: global_load_b128 v[4:7], v8, s[6:7] offset:16
; GFX11-NEXT: s_cmp_eq_u32 s1, 6 ; GFX11-NEXT: s_cmp_eq_u32 s1, 6
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 7 ; GFX11-NEXT: s_cmp_eq_u32 s1, 7
; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_cndmask_b32_e64 v9, v3, s0, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v9, v3, s0, s2
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 4 ; GFX11-NEXT: s_cmp_eq_u32 s1, 4
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-NEXT: s_cselect_b32 s3, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 5
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s0, s3
; GFX11-NEXT: s_cselect_b32 s3, -1, 0 ; GFX11-NEXT: s_cselect_b32 s3, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 5
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s0, s2
; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 2 ; GFX11-NEXT: s_cmp_eq_u32 s1, 2
; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v1
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s0, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s0, s3
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s0, s2
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 3 ; GFX11-NEXT: s_cmp_eq_u32 s1, 3
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s0, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s0, s2
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 0 ; GFX11-NEXT: s_cmp_eq_u32 s1, 0
; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v0
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s0, s2 ; GFX11-NEXT: v_perm_b32 v2, v10, v2, 0x5040100
; GFX11-NEXT: v_cndmask_b32_e64 v10, v11, s0, s2
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 1 ; GFX11-NEXT: s_cmp_eq_u32 s1, 1
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s0, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s0, s2
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 14 ; GFX11-NEXT: s_cmp_eq_u32 s1, 14
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 16, v7 ; GFX11-NEXT: v_lshrrev_b32_e32 v13, 16, v7
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s0, s3 ; GFX11-NEXT: v_cndmask_b32_e64 v11, v12, s0, s2
; GFX11-NEXT: v_perm_b32 v3, v3, v9, 0x5040100
; GFX11-NEXT: v_cndmask_b32_e64 v9, v12, s0, s2
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 15 ; GFX11-NEXT: s_cmp_eq_u32 s1, 15
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s0, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s0, s2
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 12 ; GFX11-NEXT: s_cmp_eq_u32 s1, 12
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v6 ; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v6
; GFX11-NEXT: v_perm_b32 v2, v10, v2, 0x5040100 ; GFX11-NEXT: v_cndmask_b32_e64 v12, v13, s0, s2
; GFX11-NEXT: v_cndmask_b32_e64 v10, v13, s0, s2
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 13 ; GFX11-NEXT: s_cmp_eq_u32 s1, 13
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s0, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s0, s2
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 10 ; GFX11-NEXT: s_cmp_eq_u32 s1, 10
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 16, v5 ; GFX11-NEXT: v_lshrrev_b32_e32 v15, 16, v5
; GFX11-NEXT: v_cndmask_b32_e64 v12, v14, s0, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v13, v14, s0, s2
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 11 ; GFX11-NEXT: s_cmp_eq_u32 s1, 11
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s0, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s0, s2
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 8 ; GFX11-NEXT: s_cmp_eq_u32 s1, 8
; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v4 ; GFX11-NEXT: v_perm_b32 v3, v3, v9, 0x5040100
; GFX11-NEXT: v_cndmask_b32_e64 v13, v15, s0, s2 ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v4
; GFX11-NEXT: v_cndmask_b32_e64 v14, v15, s0, s2
; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-NEXT: s_cmp_eq_u32 s1, 9 ; GFX11-NEXT: s_cmp_eq_u32 s1, 9
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s0, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s0, s2
; GFX11-NEXT: s_cselect_b32 s1, -1, 0 ; GFX11-NEXT: s_cselect_b32 s1, -1, 0
; GFX11-NEXT: v_perm_b32 v7, v10, v7, 0x5040100 ; GFX11-NEXT: v_perm_b32 v7, v12, v7, 0x5040100
; GFX11-NEXT: v_cndmask_b32_e64 v14, v16, s0, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, s0, s1
; GFX11-NEXT: v_perm_b32 v6, v12, v6, 0x5040100 ; GFX11-NEXT: v_perm_b32 v6, v13, v6, 0x5040100
; GFX11-NEXT: v_perm_b32 v5, v13, v5, 0x5040100 ; GFX11-NEXT: v_perm_b32 v5, v14, v5, 0x5040100
; GFX11-NEXT: v_perm_b32 v1, v11, v1, 0x5040100 ; GFX11-NEXT: v_perm_b32 v1, v10, v1, 0x5040100
; GFX11-NEXT: v_perm_b32 v0, v9, v0, 0x5040100 ; GFX11-NEXT: v_perm_b32 v0, v11, v0, 0x5040100
; GFX11-NEXT: v_perm_b32 v4, v14, v4, 0x5040100 ; GFX11-NEXT: v_perm_b32 v4, v9, v4, 0x5040100
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b128 v8, v[4:7], s[4:5] offset:16 ; GFX11-NEXT: global_store_b128 v8, v[4:7], s[4:5] offset:16
; GFX11-NEXT: global_store_b128 v8, v[0:3], s[4:5] ; GFX11-NEXT: global_store_b128 v8, v[0:3], s[4:5]
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <16 x half>, ptr addrspace(1) %in, i64 %tid.ext %in.gep = getelementptr inbounds <16 x half>, ptr addrspace(1) %in, i64 %tid.ext
Show All 14 Lines

llvm/test/CodeGen/AMDGPU/lds-atomic-fmin-fmax.ll

Show First 20 Lines • Show All 718 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4 ; GFX9-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4
; GFX9-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen ; GFX9-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: lds_ds_fmin_f64: ; GFX10-LABEL: lds_ds_fmin_f64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; GFX10-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-NEXT: s_mov_b32 s10, -1 ; GFX10-NEXT: s_mov_b32 s10, -1
; GFX10-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-NEXT: s_add_u32 s8, s8, s3 ; GFX10-NEXT: s_add_u32 s8, s8, s3
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX10-NEXT: s_mov_b32 s3, 0x40450000
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: s_mov_b32 s0, 0
; GFX10-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-NEXT: s_addc_u32 s9, s9, 0
; GFX10-NEXT: s_mov_b32 s1, 0x40450000 ; GFX10-NEXT: v_mov_b32_e32 v1, s3
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_lshl_b32 s5, s4, 3 ; GFX10-NEXT: s_lshl_b32 s2, s4, 3
; GFX10-NEXT: s_lshl_b32 s0, s4, 4 ; GFX10-NEXT: s_lshl_b32 s3, s4, 4
; GFX10-NEXT: v_mov_b32_e32 v2, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_mov_b32_e32 v4, s0 ; GFX10-NEXT: v_mov_b32_e32 v4, s3
; GFX10-NEXT: v_mov_b32_e32 v5, s3
; GFX10-NEXT: ds_min_rtn_f64 v[2:3], v2, v[0:1] offset:32 ; GFX10-NEXT: ds_min_rtn_f64 v[2:3], v2, v[0:1] offset:32
; GFX10-NEXT: ds_min_f64 v4, v[0:1] offset:64 ; GFX10-NEXT: ds_min_f64 v4, v[0:1] offset:64
; GFX10-NEXT: v_mov_b32_e32 v0, s1
; GFX10-NEXT: s_waitcnt lgkmcnt(1) ; GFX10-NEXT: s_waitcnt lgkmcnt(1)
; GFX10-NEXT: ds_min_rtn_f64 v[0:1], v5, v[2:3] ; GFX10-NEXT: ds_min_rtn_f64 v[0:1], v0, v[2:3]
; GFX10-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4 ; GFX10-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4
; GFX10-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen ; GFX10-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; G_SI-LABEL: lds_ds_fmin_f64: ; G_SI-LABEL: lds_ds_fmin_f64:
; G_SI: ; %bb.0: ; G_SI: ; %bb.0:
; G_SI-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; G_SI-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; G_GFX9-NEXT: v_mov_b32_e32 v2, s2 ; G_GFX9-NEXT: v_mov_b32_e32 v2, s2
; G_GFX9-NEXT: s_waitcnt lgkmcnt(0) ; G_GFX9-NEXT: s_waitcnt lgkmcnt(0)
; G_GFX9-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen ; G_GFX9-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen
; G_GFX9-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4 ; G_GFX9-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4
; G_GFX9-NEXT: s_endpgm ; G_GFX9-NEXT: s_endpgm
; ;
; G_GFX10-LABEL: lds_ds_fmin_f64: ; G_GFX10-LABEL: lds_ds_fmin_f64:
; G_GFX10: ; %bb.0: ; G_GFX10: ; %bb.0:
; G_GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; G_GFX10-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; G_GFX10-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; G_GFX10-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; G_GFX10-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; G_GFX10-NEXT: s_mov_b32 s10, -1 ; G_GFX10-NEXT: s_mov_b32 s10, -1
; G_GFX10-NEXT: s_mov_b32 s11, 0x31c16000 ; G_GFX10-NEXT: s_mov_b32 s11, 0x31c16000
; G_GFX10-NEXT: s_add_u32 s8, s8, s3 ; G_GFX10-NEXT: s_add_u32 s8, s8, s3
; G_GFX10-NEXT: s_clause 0x1 ; G_GFX10-NEXT: s_mov_b32 s2, 0
; G_GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; G_GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; G_GFX10-NEXT: s_addc_u32 s9, s9, 0 ; G_GFX10-NEXT: s_addc_u32 s9, s9, 0
; G_GFX10-NEXT: s_mov_b32 s0, 0 ; G_GFX10-NEXT: s_mov_b32 s3, 0x40450000
; G_GFX10-NEXT: s_mov_b32 s1, 0x40450000 ; G_GFX10-NEXT: v_mov_b32_e32 v0, s2
; G_GFX10-NEXT: v_mov_b32_e32 v0, s0 ; G_GFX10-NEXT: v_mov_b32_e32 v1, s3
; G_GFX10-NEXT: v_mov_b32_e32 v1, s1 ; G_GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; G_GFX10-NEXT: s_waitcnt lgkmcnt(0) ; G_GFX10-NEXT: s_waitcnt lgkmcnt(0)
; G_GFX10-NEXT: s_add_i32 s4, s4, 4 ; G_GFX10-NEXT: s_add_i32 s4, s4, 4
; G_GFX10-NEXT: v_mov_b32_e32 v5, s3 ; G_GFX10-NEXT: s_lshl_b32 s2, s4, 3
; G_GFX10-NEXT: s_lshl_b32 s5, s4, 3 ; G_GFX10-NEXT: s_lshl_b32 s3, s4, 4
; G_GFX10-NEXT: s_lshl_b32 s0, s4, 4 ; G_GFX10-NEXT: v_mov_b32_e32 v2, s2
; G_GFX10-NEXT: v_mov_b32_e32 v2, s5 ; G_GFX10-NEXT: v_mov_b32_e32 v4, s3
; G_GFX10-NEXT: v_mov_b32_e32 v4, s0
; G_GFX10-NEXT: ds_min_rtn_f64 v[2:3], v2, v[0:1] ; G_GFX10-NEXT: ds_min_rtn_f64 v[2:3], v2, v[0:1]
; G_GFX10-NEXT: ds_min_f64 v4, v[0:1] ; G_GFX10-NEXT: ds_min_f64 v4, v[0:1]
; G_GFX10-NEXT: v_mov_b32_e32 v0, s1
; G_GFX10-NEXT: s_waitcnt lgkmcnt(1) ; G_GFX10-NEXT: s_waitcnt lgkmcnt(1)
; G_GFX10-NEXT: ds_min_rtn_f64 v[0:1], v5, v[2:3] ; G_GFX10-NEXT: ds_min_rtn_f64 v[0:1], v0, v[2:3]
; G_GFX10-NEXT: v_mov_b32_e32 v2, s2 ; G_GFX10-NEXT: v_mov_b32_e32 v2, s0
; G_GFX10-NEXT: s_waitcnt lgkmcnt(0) ; G_GFX10-NEXT: s_waitcnt lgkmcnt(0)
; G_GFX10-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen ; G_GFX10-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen
; G_GFX10-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4 ; G_GFX10-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4
; G_GFX10-NEXT: s_endpgm ; G_GFX10-NEXT: s_endpgm
%idx.add = add nuw i32 %idx, 4 %idx.add = add nuw i32 %idx, 4
%shl0 = shl i32 %idx.add, 3 %shl0 = shl i32 %idx.add, 3
%shl1 = shl i32 %idx.add, 4 %shl1 = shl i32 %idx.add, 4
%ptr0 = inttoptr i32 %shl0 to ptr addrspace(3) %ptr0 = inttoptr i32 %shl0 to ptr addrspace(3)
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4 ; GFX9-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4
; GFX9-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen ; GFX9-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: lds_ds_fmax_f64: ; GFX10-LABEL: lds_ds_fmax_f64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; GFX10-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GFX10-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GFX10-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-NEXT: s_mov_b32 s10, -1 ; GFX10-NEXT: s_mov_b32 s10, -1
; GFX10-NEXT: s_mov_b32 s11, 0x31c16000 ; GFX10-NEXT: s_mov_b32 s11, 0x31c16000
; GFX10-NEXT: s_add_u32 s8, s8, s3 ; GFX10-NEXT: s_add_u32 s8, s8, s3
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX10-NEXT: s_mov_b32 s3, 0x40450000
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: s_mov_b32 s0, 0
; GFX10-NEXT: s_addc_u32 s9, s9, 0 ; GFX10-NEXT: s_addc_u32 s9, s9, 0
; GFX10-NEXT: s_mov_b32 s1, 0x40450000 ; GFX10-NEXT: v_mov_b32_e32 v1, s3
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_lshl_b32 s5, s4, 3 ; GFX10-NEXT: s_lshl_b32 s2, s4, 3
; GFX10-NEXT: s_lshl_b32 s0, s4, 4 ; GFX10-NEXT: s_lshl_b32 s3, s4, 4
; GFX10-NEXT: v_mov_b32_e32 v2, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_mov_b32_e32 v4, s0 ; GFX10-NEXT: v_mov_b32_e32 v4, s3
; GFX10-NEXT: v_mov_b32_e32 v5, s3
; GFX10-NEXT: ds_max_rtn_f64 v[2:3], v2, v[0:1] offset:32 ; GFX10-NEXT: ds_max_rtn_f64 v[2:3], v2, v[0:1] offset:32
; GFX10-NEXT: ds_max_f64 v4, v[0:1] offset:64 ; GFX10-NEXT: ds_max_f64 v4, v[0:1] offset:64
; GFX10-NEXT: v_mov_b32_e32 v0, s1
; GFX10-NEXT: s_waitcnt lgkmcnt(1) ; GFX10-NEXT: s_waitcnt lgkmcnt(1)
; GFX10-NEXT: ds_max_rtn_f64 v[0:1], v5, v[2:3] ; GFX10-NEXT: ds_max_rtn_f64 v[0:1], v0, v[2:3]
; GFX10-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4 ; GFX10-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4
; GFX10-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen ; GFX10-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; G_SI-LABEL: lds_ds_fmax_f64: ; G_SI-LABEL: lds_ds_fmax_f64:
; G_SI: ; %bb.0: ; G_SI: ; %bb.0:
; G_SI-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; G_SI-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
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; G_GFX9-NEXT: v_mov_b32_e32 v2, s2 ; G_GFX9-NEXT: v_mov_b32_e32 v2, s2
; G_GFX9-NEXT: s_waitcnt lgkmcnt(0) ; G_GFX9-NEXT: s_waitcnt lgkmcnt(0)
; G_GFX9-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen ; G_GFX9-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen
; G_GFX9-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4 ; G_GFX9-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4
; G_GFX9-NEXT: s_endpgm ; G_GFX9-NEXT: s_endpgm
; ;
; G_GFX10-LABEL: lds_ds_fmax_f64: ; G_GFX10-LABEL: lds_ds_fmax_f64:
; G_GFX10: ; %bb.0: ; G_GFX10: ; %bb.0:
; G_GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; G_GFX10-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; G_GFX10-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; G_GFX10-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; G_GFX10-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; G_GFX10-NEXT: s_mov_b32 s10, -1 ; G_GFX10-NEXT: s_mov_b32 s10, -1
; G_GFX10-NEXT: s_mov_b32 s11, 0x31c16000 ; G_GFX10-NEXT: s_mov_b32 s11, 0x31c16000
; G_GFX10-NEXT: s_add_u32 s8, s8, s3 ; G_GFX10-NEXT: s_add_u32 s8, s8, s3
; G_GFX10-NEXT: s_clause 0x1 ; G_GFX10-NEXT: s_mov_b32 s2, 0
; G_GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; G_GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; G_GFX10-NEXT: s_addc_u32 s9, s9, 0 ; G_GFX10-NEXT: s_addc_u32 s9, s9, 0
; G_GFX10-NEXT: s_mov_b32 s0, 0 ; G_GFX10-NEXT: s_mov_b32 s3, 0x40450000
; G_GFX10-NEXT: s_mov_b32 s1, 0x40450000 ; G_GFX10-NEXT: v_mov_b32_e32 v0, s2
; G_GFX10-NEXT: v_mov_b32_e32 v0, s0 ; G_GFX10-NEXT: v_mov_b32_e32 v1, s3
; G_GFX10-NEXT: v_mov_b32_e32 v1, s1 ; G_GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; G_GFX10-NEXT: s_waitcnt lgkmcnt(0) ; G_GFX10-NEXT: s_waitcnt lgkmcnt(0)
; G_GFX10-NEXT: s_add_i32 s4, s4, 4 ; G_GFX10-NEXT: s_add_i32 s4, s4, 4
; G_GFX10-NEXT: v_mov_b32_e32 v5, s3 ; G_GFX10-NEXT: s_lshl_b32 s2, s4, 3
; G_GFX10-NEXT: s_lshl_b32 s5, s4, 3 ; G_GFX10-NEXT: s_lshl_b32 s3, s4, 4
; G_GFX10-NEXT: s_lshl_b32 s0, s4, 4 ; G_GFX10-NEXT: v_mov_b32_e32 v2, s2
; G_GFX10-NEXT: v_mov_b32_e32 v2, s5 ; G_GFX10-NEXT: v_mov_b32_e32 v4, s3
; G_GFX10-NEXT: v_mov_b32_e32 v4, s0
; G_GFX10-NEXT: ds_max_rtn_f64 v[2:3], v2, v[0:1] ; G_GFX10-NEXT: ds_max_rtn_f64 v[2:3], v2, v[0:1]
; G_GFX10-NEXT: ds_max_f64 v4, v[0:1] ; G_GFX10-NEXT: ds_max_f64 v4, v[0:1]
; G_GFX10-NEXT: v_mov_b32_e32 v0, s1
; G_GFX10-NEXT: s_waitcnt lgkmcnt(1) ; G_GFX10-NEXT: s_waitcnt lgkmcnt(1)
; G_GFX10-NEXT: ds_max_rtn_f64 v[0:1], v5, v[2:3] ; G_GFX10-NEXT: ds_max_rtn_f64 v[0:1], v0, v[2:3]
; G_GFX10-NEXT: v_mov_b32_e32 v2, s2 ; G_GFX10-NEXT: v_mov_b32_e32 v2, s0
; G_GFX10-NEXT: s_waitcnt lgkmcnt(0) ; G_GFX10-NEXT: s_waitcnt lgkmcnt(0)
; G_GFX10-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen ; G_GFX10-NEXT: buffer_store_dword v0, v2, s[8:11], 0 offen
; G_GFX10-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4 ; G_GFX10-NEXT: buffer_store_dword v1, v2, s[8:11], 0 offen offset:4
; G_GFX10-NEXT: s_endpgm ; G_GFX10-NEXT: s_endpgm
%idx.add = add nuw i32 %idx, 4 %idx.add = add nuw i32 %idx, 4
%shl0 = shl i32 %idx.add, 3 %shl0 = shl i32 %idx.add, 3
%shl1 = shl i32 %idx.add, 4 %shl1 = shl i32 %idx.add, 4
%ptr0 = inttoptr i32 %shl0 to ptr addrspace(3) %ptr0 = inttoptr i32 %shl0 to ptr addrspace(3)
%ptr1 = inttoptr i32 %shl1 to ptr addrspace(3) %ptr1 = inttoptr i32 %shl1 to ptr addrspace(3)
%a1 = call double @llvm.amdgcn.ds.fmax.f64(ptr addrspace(3) %ptr0, double 4.2e+1, i32 0, i32 0, i1 false) %a1 = call double @llvm.amdgcn.ds.fmax.f64(ptr addrspace(3) %ptr0, double 4.2e+1, i32 0, i32 0, i1 false)
%a2 = call double @llvm.amdgcn.ds.fmax.f64(ptr addrspace(3) %ptr1, double 4.2e+1, i32 0, i32 0, i1 false) %a2 = call double @llvm.amdgcn.ds.fmax.f64(ptr addrspace(3) %ptr1, double 4.2e+1, i32 0, i32 0, i1 false)
%a3 = call double @llvm.amdgcn.ds.fmax.f64(ptr addrspace(3) %ptrf, double %a1, i32 0, i32 0, i1 false) %a3 = call double @llvm.amdgcn.ds.fmax.f64(ptr addrspace(3) %ptrf, double %a1, i32 0, i32 0, i1 false)
store double %a3, ptr addrspace(5) %out store double %a3, ptr addrspace(5) %out
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll

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; GFX9-NEXT: v_mov_b32_e32 v10, v5 ; GFX9-NEXT: v_mov_b32_e32 v10, v5
; GFX9-NEXT: v_mov_b32_e32 v8, v2 ; GFX9-NEXT: v_mov_b32_e32 v8, v2
; GFX9-NEXT: v_perm_b32 v11, v7, v6, s12 ; GFX9-NEXT: v_perm_b32 v11, v7, v6, s12
; GFX9-NEXT: v_perm_b32 v9, v4, v3, s12 ; GFX9-NEXT: v_perm_b32 v9, v4, v3, s12
; GFX9-NEXT: v_perm_b32 v7, v1, v0, s12 ; GFX9-NEXT: v_perm_b32 v7, v1, v0, s12
; GFX9-NEXT: image_sample_d v[0:3], v[7:12], s[0:7], s[8:11] dmask:0xf a16 ; GFX9-NEXT: image_sample_d v[0:3], v[7:12], s[0:7], s[8:11] dmask:0xf a16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: sample_d_3d:
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v12, v8
; GFX10-NEXT: v_mov_b32_e32 v10, v5
; GFX10-NEXT: v_mov_b32_e32 v8, v2
; GFX10-NEXT: v_perm_b32 v11, v7, v6, 0x5040100
; GFX10-NEXT: v_perm_b32 v9, v4, v3, 0x5040100
; GFX10-NEXT: v_perm_b32 v7, v1, v0, 0x5040100
; GFX10-NEXT: image_sample_d_g16 v[0:3], v[7:12], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, half %s, half %t, half %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, half %s, half %t, half %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s) { define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s) {
; GFX9-LABEL: sample_c_d_1d: ; GFX9-LABEL: sample_c_d_1d:
; GFX9: ; %bb.0: ; %main_body ; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: v_mov_b32_e32 v9, v1 ; GFX9-NEXT: v_mov_b32_e32 v9, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v0 ; GFX9-NEXT: v_mov_b32_e32 v8, v0
; GFX9-NEXT: v_perm_b32 v12, v7, v6, s12 ; GFX9-NEXT: v_perm_b32 v12, v7, v6, s12
; GFX9-NEXT: v_perm_b32 v11, v5, v4, s12 ; GFX9-NEXT: v_perm_b32 v11, v5, v4, s12
; GFX9-NEXT: v_perm_b32 v10, v3, v2, s12 ; GFX9-NEXT: v_perm_b32 v10, v3, v2, s12
; GFX9-NEXT: image_sample_c_d_o v0, v[8:13], s[0:7], s[8:11] dmask:0x4 a16 da ; GFX9-NEXT: image_sample_c_d_o v0, v[8:13], s[0:7], s[8:11] dmask:0x4 a16 da
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: sample_c_d_o_2darray_V1:
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v13, v8
; GFX10-NEXT: v_mov_b32_e32 v9, v1
; GFX10-NEXT: v_mov_b32_e32 v8, v0
; GFX10-NEXT: v_perm_b32 v12, v7, v6, 0x5040100
; GFX10-NEXT: v_perm_b32 v11, v5, v4, 0x5040100
; GFX10-NEXT: v_perm_b32 v10, v3, v2, 0x5040100
; GFX10-NEXT: image_sample_c_d_o_g16 v0, v[8:13], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f16(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f16(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret float %v ret float %v
} }
define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice) { define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice) {
; GFX9-LABEL: sample_c_d_o_2darray_V2: ; GFX9-LABEL: sample_c_d_o_2darray_V2:
; GFX9: ; %bb.0: ; %main_body ; GFX9: ; %bb.0: ; %main_body
; GFX9-NEXT: s_mov_b32 s12, 0x5040100 ; GFX9-NEXT: s_mov_b32 s12, 0x5040100
; GFX9-NEXT: v_mov_b32_e32 v13, v8 ; GFX9-NEXT: v_mov_b32_e32 v13, v8
; GFX9-NEXT: v_mov_b32_e32 v9, v1 ; GFX9-NEXT: v_mov_b32_e32 v9, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v0 ; GFX9-NEXT: v_mov_b32_e32 v8, v0
; GFX9-NEXT: v_perm_b32 v12, v7, v6, s12 ; GFX9-NEXT: v_perm_b32 v12, v7, v6, s12
; GFX9-NEXT: v_perm_b32 v11, v5, v4, s12 ; GFX9-NEXT: v_perm_b32 v11, v5, v4, s12
; GFX9-NEXT: v_perm_b32 v10, v3, v2, s12 ; GFX9-NEXT: v_perm_b32 v10, v3, v2, s12
; GFX9-NEXT: image_sample_c_d_o v[0:1], v[8:13], s[0:7], s[8:11] dmask:0x6 a16 da ; GFX9-NEXT: image_sample_c_d_o v[0:1], v[8:13], s[0:7], s[8:11] dmask:0x6 a16 da
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: sample_c_d_o_2darray_V2:
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v13, v8
; GFX10-NEXT: v_mov_b32_e32 v9, v1
; GFX10-NEXT: v_mov_b32_e32 v8, v0
; GFX10-NEXT: v_perm_b32 v12, v7, v6, 0x5040100
; GFX10-NEXT: v_perm_b32 v11, v5, v4, 0x5040100
; GFX10-NEXT: v_perm_b32 v10, v3, v2, 0x5040100
; GFX10-NEXT: image_sample_c_d_o_g16 v[0:1], v[8:13], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f16(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f16(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <2 x float> %v ret <2 x float> %v
} }
declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f16(i32, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f16(i32, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
declare <8 x float> @llvm.amdgcn.image.sample.1d.v8f32.f16(i32, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 declare <8 x float> @llvm.amdgcn.image.sample.1d.v8f32.f16(i32, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f16(i32, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f16(i32, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll

Show All 37 Lines
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %drdh, float %dsdv, float %dtdv, float %drdv, half %s, half %t, half %r) { define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %drdh, float %dsdv, float %dtdv, float %drdv, half %s, half %t, half %r) {
; GFX10-LABEL: sample_d_3d: ; GFX10-LABEL: sample_d_3d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v15, v8 ; GFX10-NEXT: v_mov_b32_e32 v9, v7
; GFX10-NEXT: v_mov_b32_e32 v13, v5 ; GFX10-NEXT: v_mov_b32_e32 v7, v8
; GFX10-NEXT: v_mov_b32_e32 v12, v4 ; GFX10-NEXT: v_perm_b32 v6, v9, v6, 0x5040100
; GFX10-NEXT: v_mov_b32_e32 v11, v3 ; GFX10-NEXT: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
; GFX10-NEXT: v_mov_b32_e32 v10, v2
; GFX10-NEXT: v_mov_b32_e32 v9, v1
; GFX10-NEXT: v_mov_b32_e32 v8, v0
; GFX10-NEXT: v_perm_b32 v14, v7, v6, 0x5040100
; GFX10-NEXT: image_sample_d v[0:3], v[8:15], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX10GISEL-LABEL: sample_d_3d: ; GFX10GISEL-LABEL: sample_d_3d:
; GFX10GISEL: ; %bb.0: ; %main_body ; GFX10GISEL: ; %bb.0: ; %main_body
; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v7 ; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v7
; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v8 ; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v8
; GFX10GISEL-NEXT: v_perm_b32 v6, v9, v6, 0x5040100 ; GFX10GISEL-NEXT: v_perm_b32 v6, v9, v6, 0x5040100
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main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) { define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) {
; GFX10-LABEL: sample_d_cl_2d: ; GFX10-LABEL: sample_d_cl_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v11, v6 ; GFX10-NEXT: v_mov_b32_e32 v7, v5
; GFX10-NEXT: v_mov_b32_e32 v9, v3 ; GFX10-NEXT: v_mov_b32_e32 v5, v6
; GFX10-NEXT: v_mov_b32_e32 v8, v2 ; GFX10-NEXT: v_perm_b32 v4, v7, v4, 0x5040100
; GFX10-NEXT: v_mov_b32_e32 v7, v1 ; GFX10-NEXT: image_sample_d_cl v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: v_mov_b32_e32 v6, v0
; GFX10-NEXT: v_perm_b32 v10, v5, v4, 0x5040100
; GFX10-NEXT: image_sample_d_cl v[0:3], v[6:11], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX10GISEL-LABEL: sample_d_cl_2d: ; GFX10GISEL-LABEL: sample_d_cl_2d:
; GFX10GISEL: ; %bb.0: ; %main_body ; GFX10GISEL: ; %bb.0: ; %main_body
; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v5 ; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX10GISEL-NEXT: v_mov_b32_e32 v5, v6 ; GFX10GISEL-NEXT: v_mov_b32_e32 v5, v6
; GFX10GISEL-NEXT: v_perm_b32 v4, v7, v4, 0x5040100 ; GFX10GISEL-NEXT: v_perm_b32 v4, v7, v4, 0x5040100
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main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) { define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) {
; GFX10-LABEL: sample_c_d_cl_2d: ; GFX10-LABEL: sample_c_d_cl_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v13, v7 ; GFX10-NEXT: v_mov_b32_e32 v8, v6
; GFX10-NEXT: v_mov_b32_e32 v11, v4 ; GFX10-NEXT: v_mov_b32_e32 v6, v7
; GFX10-NEXT: v_mov_b32_e32 v10, v3 ; GFX10-NEXT: v_perm_b32 v5, v8, v5, 0x5040100
; GFX10-NEXT: v_mov_b32_e32 v9, v2 ; GFX10-NEXT: image_sample_c_d_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: v_mov_b32_e32 v8, v1
; GFX10-NEXT: v_mov_b32_e32 v7, v0
; GFX10-NEXT: v_perm_b32 v12, v6, v5, 0x5040100
; GFX10-NEXT: image_sample_c_d_cl v[0:3], v[7:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX10GISEL-LABEL: sample_c_d_cl_2d: ; GFX10GISEL-LABEL: sample_c_d_cl_2d:
; GFX10GISEL: ; %bb.0: ; %main_body ; GFX10GISEL: ; %bb.0: ; %main_body
; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v6 ; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v6
; GFX10GISEL-NEXT: v_mov_b32_e32 v6, v7 ; GFX10GISEL-NEXT: v_mov_b32_e32 v6, v7
; GFX10GISEL-NEXT: v_perm_b32 v5, v8, v5, 0x5040100 ; GFX10GISEL-NEXT: v_perm_b32 v5, v8, v5, 0x5040100
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main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) { define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) {
; GFX10-LABEL: sample_cd_cl_2d: ; GFX10-LABEL: sample_cd_cl_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v11, v6 ; GFX10-NEXT: v_mov_b32_e32 v7, v5
; GFX10-NEXT: v_mov_b32_e32 v9, v3 ; GFX10-NEXT: v_mov_b32_e32 v5, v6
; GFX10-NEXT: v_mov_b32_e32 v8, v2 ; GFX10-NEXT: v_perm_b32 v4, v7, v4, 0x5040100
; GFX10-NEXT: v_mov_b32_e32 v7, v1 ; GFX10-NEXT: image_sample_cd_cl v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: v_mov_b32_e32 v6, v0
; GFX10-NEXT: v_perm_b32 v10, v5, v4, 0x5040100
; GFX10-NEXT: image_sample_cd_cl v[0:3], v[6:11], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX10GISEL-LABEL: sample_cd_cl_2d: ; GFX10GISEL-LABEL: sample_cd_cl_2d:
; GFX10GISEL: ; %bb.0: ; %main_body ; GFX10GISEL: ; %bb.0: ; %main_body
; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v5 ; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v5
; GFX10GISEL-NEXT: v_mov_b32_e32 v5, v6 ; GFX10GISEL-NEXT: v_mov_b32_e32 v5, v6
; GFX10GISEL-NEXT: v_perm_b32 v4, v7, v4, 0x5040100 ; GFX10GISEL-NEXT: v_perm_b32 v4, v7, v4, 0x5040100
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main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) { define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) {
; GFX10-LABEL: sample_c_cd_cl_2d: ; GFX10-LABEL: sample_c_cd_cl_2d:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v13, v7 ; GFX10-NEXT: v_mov_b32_e32 v8, v6
; GFX10-NEXT: v_mov_b32_e32 v11, v4 ; GFX10-NEXT: v_mov_b32_e32 v6, v7
; GFX10-NEXT: v_mov_b32_e32 v10, v3 ; GFX10-NEXT: v_perm_b32 v5, v8, v5, 0x5040100
; GFX10-NEXT: v_mov_b32_e32 v9, v2 ; GFX10-NEXT: image_sample_c_cd_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: v_mov_b32_e32 v8, v1
; GFX10-NEXT: v_mov_b32_e32 v7, v0
; GFX10-NEXT: v_perm_b32 v12, v6, v5, 0x5040100
; GFX10-NEXT: image_sample_c_cd_cl v[0:3], v[7:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX10GISEL-LABEL: sample_c_cd_cl_2d: ; GFX10GISEL-LABEL: sample_c_cd_cl_2d:
; GFX10GISEL: ; %bb.0: ; %main_body ; GFX10GISEL: ; %bb.0: ; %main_body
; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v6 ; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v6
; GFX10GISEL-NEXT: v_mov_b32_e32 v6, v7 ; GFX10GISEL-NEXT: v_mov_b32_e32 v6, v7
; GFX10GISEL-NEXT: v_perm_b32 v5, v8, v5, 0x5040100 ; GFX10GISEL-NEXT: v_perm_b32 v5, v8, v5, 0x5040100
; GFX10GISEL-NEXT: image_sample_c_cd_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10GISEL-NEXT: image_sample_c_cd_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog ; GFX10GISEL-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice) { define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice) {
; GFX10-LABEL: sample_c_d_o_2darray_V1: ; GFX10-LABEL: sample_c_d_o_2darray_V1:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v15, v8 ; GFX10-NEXT: v_mov_b32_e32 v9, v7
; GFX10-NEXT: v_mov_b32_e32 v13, v5 ; GFX10-NEXT: v_mov_b32_e32 v7, v8
; GFX10-NEXT: v_mov_b32_e32 v12, v4 ; GFX10-NEXT: v_perm_b32 v6, v9, v6, 0x5040100
; GFX10-NEXT: v_mov_b32_e32 v11, v3 ; GFX10-NEXT: image_sample_c_d_o v0, v[0:7], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX10-NEXT: v_mov_b32_e32 v10, v2
; GFX10-NEXT: v_mov_b32_e32 v9, v1
; GFX10-NEXT: v_mov_b32_e32 v8, v0
; GFX10-NEXT: v_perm_b32 v14, v7, v6, 0x5040100
; GFX10-NEXT: image_sample_c_d_o v0, v[8:15], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX10GISEL-LABEL: sample_c_d_o_2darray_V1: ; GFX10GISEL-LABEL: sample_c_d_o_2darray_V1:
; GFX10GISEL: ; %bb.0: ; %main_body ; GFX10GISEL: ; %bb.0: ; %main_body
; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v7 ; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v7
; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v8 ; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v8
; GFX10GISEL-NEXT: v_perm_b32 v6, v9, v6, 0x5040100 ; GFX10GISEL-NEXT: v_perm_b32 v6, v9, v6, 0x5040100
; GFX10GISEL-NEXT: image_sample_c_d_o v0, v[0:7], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; GFX10GISEL-NEXT: image_sample_c_d_o v0, v[0:7], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10GISEL-NEXT: ; return to shader part epilog ; GFX10GISEL-NEXT: ; return to shader part epilog
main_body: main_body:
%v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f32.f16(i32 4, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f32.f16(i32 4, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret float %v ret float %v
} }
define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice) { define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice) {
; GFX10-LABEL: sample_c_d_o_2darray_V2: ; GFX10-LABEL: sample_c_d_o_2darray_V2:
; GFX10: ; %bb.0: ; %main_body ; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v15, v8 ; GFX10-NEXT: v_mov_b32_e32 v9, v7
; GFX10-NEXT: v_mov_b32_e32 v13, v5 ; GFX10-NEXT: v_mov_b32_e32 v7, v8
; GFX10-NEXT: v_mov_b32_e32 v12, v4 ; GFX10-NEXT: v_perm_b32 v6, v9, v6, 0x5040100
; GFX10-NEXT: v_mov_b32_e32 v11, v3 ; GFX10-NEXT: image_sample_c_d_o v[0:1], v[0:7], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX10-NEXT: v_mov_b32_e32 v10, v2
; GFX10-NEXT: v_mov_b32_e32 v9, v1
; GFX10-NEXT: v_mov_b32_e32 v8, v0
; GFX10-NEXT: v_perm_b32 v14, v7, v6, 0x5040100
; GFX10-NEXT: image_sample_c_d_o v[0:1], v[8:15], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX10GISEL-LABEL: sample_c_d_o_2darray_V2: ; GFX10GISEL-LABEL: sample_c_d_o_2darray_V2:
; GFX10GISEL: ; %bb.0: ; %main_body ; GFX10GISEL: ; %bb.0: ; %main_body
; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v7 ; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v7
; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v8 ; GFX10GISEL-NEXT: v_mov_b32_e32 v7, v8
; GFX10GISEL-NEXT: v_perm_b32 v6, v9, v6, 0x5040100 ; GFX10GISEL-NEXT: v_perm_b32 v6, v9, v6, 0x5040100
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll

Show First 20 Lines • Show All 116 Lines • ▼ Show 20 Linesentry:
%tmp2 = getelementptr float, ptr addrspace(3) %lds, i32 4 %tmp2 = getelementptr float, ptr addrspace(3) %lds, i32 4
store float 0.0, ptr addrspace(3) %tmp2 store float 0.0, ptr addrspace(3) %tmp2
ret float %val ret float %val
} }
;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_and: ;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_and:
;CHECK-NEXT: %bb. ;CHECK-NEXT: %bb.
;GFX10-NEXT: s_clause ;GFX10-NEXT: s_clause
;CHECK-NEXT: buffer_load_{{dwordx4|b128}} v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 ;CHECK-DAG: buffer_load_{{dwordx4|b128}} v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
;CHECK-NEXT: buffer_load_{{dwordx2|b64}} v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 ;CHECK-DAG: buffer_load_{{dwordx2|b64}} v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define amdgpu_ps void @buffer_load_x1_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) { define amdgpu_ps void @buffer_load_x1_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) {
main_body: main_body:
%a1 = add i32 %a, 4 %a1 = add i32 %a, 4
%a2 = add i32 %a, 8 %a2 = add i32 %a, 8
%a3 = add i32 %a, 12 %a3 = add i32 %a, 12
%a4 = add i32 %a, 16 %a4 = add i32 %a, 16
%a5 = add i32 %a, 28 %a5 = add i32 %a, 28
%a6 = add i32 %a, 32 %a6 = add i32 %a, 32
%r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0) %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
%r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0) %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
%r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 0) %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 0)
%r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 0) %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 0)
%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0) %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0)
%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0) %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_or: ;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_or:
;CHECK-NEXT: %bb. ;CHECK-NEXT: %bb.
;CHECK-NEXT: v_lshlrev_b32_e32 v{{[0-9]}}, 6, v0 ;CHECK-NEXT: v_lshlrev_b32_e32 v{{[0-9]}}, 6, v0
;GFX10-NEXT: s_clause ;GFX10-NEXT: s_clause
;CHECK-NEXT: buffer_load_{{dwordx4|b128}} v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4 ;CHECK-DAG: buffer_load_{{dwordx4|b128}} v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4
;CHECK-NEXT: buffer_load_{{dwordx2|b64}} v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:28 ;CHECK-DAG: buffer_load_{{dwordx2|b64}} v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:28
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) { define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) {
main_body: main_body:
%a = shl i32 %inp, 6 %a = shl i32 %inp, 6
%a1 = or i32 %a, 4 %a1 = or i32 %a, 4
%a2 = or i32 %a, 8 %a2 = or i32 %a, 8
%a3 = or i32 %a, 12 %a3 = or i32 %a, 12
%a4 = or i32 %a, 16 %a4 = or i32 %a, 16
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Linesmain_body:
%r2 = extractelement <2 x float> %vr1, i32 1 %r2 = extractelement <2 x float> %vr1, i32 1
%r3 = extractelement <2 x float> %vr2, i32 0 %r3 = extractelement <2 x float> %vr2, i32 0
%r4 = extractelement <2 x float> %vr2, i32 1 %r4 = extractelement <2 x float> %vr2, i32 1
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_load_int: ;CHECK-LABEL: {{^}}buffer_load_int:
;CHECK: buffer_load_{{dwordx4|b128}} v[0:3], off, s[0:3], 0 ;CHECK-DAG: buffer_load_{{dwordx4|b128}} v[0:3], off, s[0:3], 0
;CHECK: buffer_load_{{dwordx2|b64}} v[4:5], off, s[0:3], 0 glc ;CHECK-DAG: buffer_load_{{dwordx2|b64}} v[4:5], off, s[0:3], 0 glc
;CHECK: buffer_load_{{dword|b32}} v6, off, s[0:3], 0 slc ;CHECK-DAG: buffer_load_{{dword|b32}} v6, off, s[0:3], 0 slc
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> inreg) { define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> inreg) {
main_body: main_body:
%data = call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0) %data = call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0)
%data_glc = call <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32> %0, i32 0, i32 0, i32 1) %data_glc = call <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32> %0, i32 0, i32 0, i32 1)
%data_slc = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %0, i32 0, i32 0, i32 2) %data_slc = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %0, i32 0, i32 0, i32 2)
%fdata = bitcast <4 x i32> %data to <4 x float> %fdata = bitcast <4 x i32> %data to <4 x float>
%fdata_glc = bitcast <2 x i32> %data_glc to <2 x float> %fdata_glc = bitcast <2 x i32> %data_glc to <2 x float>
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll

Show All 12 Lines
; GFX10-NEXT: v_readfirstlane_b32 s5, v1 ; GFX10-NEXT: v_readfirstlane_b32 s5, v1
; GFX10-NEXT: v_readfirstlane_b32 s6, v2 ; GFX10-NEXT: v_readfirstlane_b32 s6, v2
; GFX10-NEXT: v_readfirstlane_b32 s7, v3 ; GFX10-NEXT: v_readfirstlane_b32 s7, v3
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1] ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX10-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3] ; GFX10-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX10-NEXT: s_and_b32 s0, vcc_lo, s0 ; GFX10-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX10-NEXT: s_and_saveexec_b32 s0, s0 ; GFX10-NEXT: s_and_saveexec_b32 s0, s0
; GFX10-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen ; GFX10-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr4 ; GFX10-NEXT: ; implicit-def: $vgpr4
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: s_cbranch_execnz .LBB0_1 ; GFX10-NEXT: s_cbranch_execnz .LBB0_1
; GFX10-NEXT: ; %bb.2: ; GFX10-NEXT: ; %bb.2:
; GFX10-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-NEXT: s_mov_b32 exec_lo, s1
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v5 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v5
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v6 ; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v6
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llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll

; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx704 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7SELDAG,GFX7CHECK %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx704 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7SELDAG,GFX7CHECK %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx704 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7GLISEL,GFX7CHECK %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx704 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7GLISEL,GFX7CHECK %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX8SELDAG,GFX8CHECK %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX8SELDAG,GFX8CHECK %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX8GLISEL,GFX8CHECK %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX8GLISEL,GFX8CHECK %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX9CHECK %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX9CHECK %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX9CHECK %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX9CHECK %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10CHECK %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10CHECK %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10CHECK %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-GISEL-CHECK %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX11CHECK %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX11CHECK %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX11CHECK %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX11CHECK %s
define amdgpu_kernel void @sgpr_isnan_f32(ptr addrspace(1) %out, float %x) { define amdgpu_kernel void @sgpr_isnan_f32(ptr addrspace(1) %out, float %x) {
; GFX7SELDAG-LABEL: sgpr_isnan_f32: ; GFX7SELDAG-LABEL: sgpr_isnan_f32:
; GFX7SELDAG: ; %bb.0: ; GFX7SELDAG: ; %bb.0:
; GFX7SELDAG-NEXT: s_load_dword s4, s[0:1], 0xb ; GFX7SELDAG-NEXT: s_load_dword s4, s[0:1], 0xb
; GFX7SELDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX7SELDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
▲ Show 20 Lines • Show All 894 Lines • ▼ Show 20 Lines
; GFX9CHECK-NEXT: v_cmp_class_f32_e64 s[4:5], v15, 3 ; GFX9CHECK-NEXT: v_cmp_class_f32_e64 s[4:5], v15, 3
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31] ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10CHECK-LABEL: isnan_v16f32: ; GFX10CHECK-LABEL: isnan_v16f32:
; GFX10CHECK: ; %bb.0: ; GFX10CHECK: ; %bb.0:
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10CHECK-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v0, 3 ; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s8, v0, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v1, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v2, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v3, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v4, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v5, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v6, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v7, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v8, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v9, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v10, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v11, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v12, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v13, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v14, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, s4
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v15, 3 ; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s4, v15, 3
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s5, v14, 3
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s6, v13, 3
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s7, v12, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s8
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s8, v1, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, s5
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, s6
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, s7
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, s4 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, s4
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s8
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s8, v2, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s8
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s8, v3, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, s8
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s8, v4, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, s8
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s8, v5, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s8
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s8, v6, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s8
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s8, v7, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s8
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s8, v8, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s8
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s8, v9, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s8
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s8, v10, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s8
; GFX10CHECK-NEXT: v_cmp_class_f32_e64 s8, v11, 3
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s8
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31] ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-GISEL-CHECK-LABEL: isnan_v16f32:
; GFX10-GISEL-CHECK: ; %bb.0:
; GFX10-GISEL-CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s8, v0, 3
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s4, v12, 3
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s5, v13, 3
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s6, v14, 3
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s7, v15, 3
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s8
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s8, v1, 3
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, s4
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, s5
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, s6
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, s7
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s8
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s8, v2, 3
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s8
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s8, v3, 3
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, s8
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s8, v4, 3
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, s8
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s8, v5, 3
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s8
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s8, v6, 3
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s8
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s8, v7, 3
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s8
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s8, v8, 3
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s8
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s8, v9, 3
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s8
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s8, v10, 3
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s8
; GFX10-GISEL-CHECK-NEXT: v_cmp_class_f32_e64 s8, v11, 3
; GFX10-GISEL-CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s8
; GFX10-GISEL-CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX11CHECK-LABEL: isnan_v16f32: ; GFX11CHECK-LABEL: isnan_v16f32:
; GFX11CHECK: ; %bb.0: ; GFX11CHECK: ; %bb.0:
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f32_e64 s0, v0, 3 ; GFX11CHECK-NEXT: v_cmp_class_f32_e64 s0, v0, 3
; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: v_cmp_class_f32_e64 s0, v1, 3 ; GFX11CHECK-NEXT: v_cmp_class_f32_e64 s0, v1, 3
▲ Show 20 Lines • Show All 548 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.mulo.ll

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; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v4, v0 ; GFX10-NEXT: v_mov_b32_e32 v4, v0
; GFX10-NEXT: v_mov_b32_e32 v5, v1 ; GFX10-NEXT: v_mov_b32_e32 v5, v1
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v2, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v2, 0
; GFX10-NEXT: v_mad_u64_u32 v[6:7], s4, v4, v3, 0 ; GFX10-NEXT: v_mad_u64_u32 v[6:7], s4, v4, v3, 0
; GFX10-NEXT: v_mad_u64_u32 v[8:9], s4, v5, v2, 0 ; GFX10-NEXT: v_mad_u64_u32 v[8:9], s4, v5, v2, 0
; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, v5, v3, 0
; GFX10-NEXT: v_mov_b32_e32 v4, v1 ; GFX10-NEXT: v_mov_b32_e32 v4, v1
; GFX10-NEXT: v_add3_u32 v1, v1, v6, v8 ; GFX10-NEXT: v_add3_u32 v1, v1, v6, v8
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v4, v6 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v4, v6
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v7, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v7, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v4, v8 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v4, v8
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v5, v9, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v2, v9, vcc_lo
; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, v5, v3, 0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v4, v2 ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v4, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3] ; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: umulo_i64_v_v: ; GFX11-LABEL: umulo_i64_v_v:
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; GFX10-LABEL: smulo_i64_v_v: ; GFX10-LABEL: smulo_i64_v_v:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v4, v0 ; GFX10-NEXT: v_mov_b32_e32 v4, v0
; GFX10-NEXT: v_mov_b32_e32 v5, v1 ; GFX10-NEXT: v_mov_b32_e32 v5, v1
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v2, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v2, 0
; GFX10-NEXT: v_mad_u64_u32 v[6:7], s4, v4, v3, 0 ; GFX10-NEXT: v_mad_u64_u32 v[6:7], s4, v4, v3, 0
; GFX10-NEXT: v_mad_u64_u32 v[9:10], s4, v5, v2, 0
; GFX10-NEXT: v_mad_i64_i32 v[11:12], s4, v5, v3, 0
; GFX10-NEXT: v_mov_b32_e32 v8, v1 ; GFX10-NEXT: v_mov_b32_e32 v8, v1
; GFX10-NEXT: v_add3_u32 v1, v1, v6, v9 ; GFX10-NEXT: v_add_co_u32 v9, vcc_lo, v8, v6
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v8, v6 ; GFX10-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, 0, v7, vcc_lo
; GFX10-NEXT: v_mad_u64_u32 v[7:8], s4, v5, v2, 0
; GFX10-NEXT: v_add3_u32 v1, v1, v6, v7
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v9, v7
; GFX10-NEXT: v_mad_i64_i32 v[6:7], s4, v5, v3, 0
; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, v10, v8, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v8, v6
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v8, v9 ; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v6, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v7, v10, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v7, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v7, v11
; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v7, v2
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5 ; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v2, v4
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v6, v4 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v5, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3
; GFX10-NEXT: v_mov_b32_e32 v3, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo ; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[2:3] ; GFX10-NEXT: v_mov_b32_e32 v5, v4
; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: smulo_i64_v_v: ; GFX11-LABEL: smulo_i64_v_v:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v1 ; GFX11-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v1
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; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, v3 ; GFX9-NEXT: v_mov_b32_e32 v1, v3
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: smulo_i64_v_4: ; GFX10-LABEL: smulo_i64_v_4:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[3:4], 2, v[0:1]
; GFX10-NEXT: v_alignbit_b32 v3, v1, v0, 30 ; GFX10-NEXT: v_ashrrev_i64 v[4:5], 2, v[3:4]
; GFX10-NEXT: v_ashrrev_i64 v[5:6], 2, v[4:5] ; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[0:1]
; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[0:1] ; GFX10-NEXT: v_alignbit_b32 v1, v1, v0, 30
; GFX10-NEXT: v_mov_b32_e32 v0, v4 ; GFX10-NEXT: v_mov_b32_e32 v0, v3
; GFX10-NEXT: v_mov_b32_e32 v1, v3
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: smulo_i64_v_4: ; GFX11-LABEL: smulo_i64_v_4:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]
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; GFX9-NEXT: v_mov_b32_e32 v0, v4 ; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: v_mov_b32_e32 v1, v3 ; GFX9-NEXT: v_mov_b32_e32 v1, v3
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: umulo_i64_v_4: ; GFX10-LABEL: umulo_i64_v_4:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_and_b32_e32 v7, 0x3fffffff, v1 ; GFX10-NEXT: v_and_b32_e32 v3, 0x3fffffff, v1
; GFX10-NEXT: v_mov_b32_e32 v6, v0 ; GFX10-NEXT: v_mov_b32_e32 v2, v0
; GFX10-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1] ; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[0:1]
; GFX10-NEXT: v_alignbit_b32 v3, v1, v0, 30 ; GFX10-NEXT: v_lshlrev_b64 v[3:4], 2, v[0:1]
; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[0:1] ; GFX10-NEXT: v_alignbit_b32 v1, v1, v0, 30
; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v3
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: umulo_i64_v_4: ; GFX11-LABEL: umulo_i64_v_4:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_and_b32 v7, 0x3fffffff, v1 ; GFX11-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_and_b32 v7, 0x3fffffff, v1
; GFX11-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]
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llvm/test/CodeGen/AMDGPU/load-local.128.ll

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; GFX10-NEXT: ds_read_u8 v1, v0 ; GFX10-NEXT: ds_read_u8 v1, v0
; GFX10-NEXT: ds_read_u8 v2, v0 offset:1 ; GFX10-NEXT: ds_read_u8 v2, v0 offset:1
; GFX10-NEXT: ds_read_u8 v3, v0 offset:2 ; GFX10-NEXT: ds_read_u8 v3, v0 offset:2
; GFX10-NEXT: ds_read_u8 v4, v0 offset:3 ; GFX10-NEXT: ds_read_u8 v4, v0 offset:3
; GFX10-NEXT: ds_read_u8 v5, v0 offset:4 ; GFX10-NEXT: ds_read_u8 v5, v0 offset:4
; GFX10-NEXT: ds_read_u8 v6, v0 offset:5 ; GFX10-NEXT: ds_read_u8 v6, v0 offset:5
; GFX10-NEXT: ds_read_u8 v7, v0 offset:6 ; GFX10-NEXT: ds_read_u8 v7, v0 offset:6
; GFX10-NEXT: ds_read_u8 v8, v0 offset:7 ; GFX10-NEXT: ds_read_u8 v8, v0 offset:7
; GFX10-NEXT: ds_read_u8 v9, v0 offset:8 ; GFX10-NEXT: s_waitcnt lgkmcnt(6)
; GFX10-NEXT: ds_read_u8 v10, v0 offset:9
; GFX10-NEXT: ds_read_u8 v11, v0 offset:10
; GFX10-NEXT: ds_read_u8 v12, v0 offset:11
; GFX10-NEXT: ds_read_u8 v13, v0 offset:12
; GFX10-NEXT: ds_read_u8 v14, v0 offset:13
; GFX10-NEXT: ds_read_u8 v15, v0 offset:14
; GFX10-NEXT: ds_read_u8 v0, v0 offset:15
; GFX10-NEXT: s_waitcnt lgkmcnt(14)
; GFX10-NEXT: v_lshl_or_b32 v1, v2, 8, v1 ; GFX10-NEXT: v_lshl_or_b32 v1, v2, 8, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(12) ; GFX10-NEXT: s_waitcnt lgkmcnt(4)
; GFX10-NEXT: v_lshl_or_b32 v2, v4, 8, v3 ; GFX10-NEXT: v_lshl_or_b32 v2, v4, 8, v3
; GFX10-NEXT: s_waitcnt lgkmcnt(10) ; GFX10-NEXT: s_waitcnt lgkmcnt(2)
; GFX10-NEXT: v_lshl_or_b32 v3, v6, 8, v5 ; GFX10-NEXT: v_lshl_or_b32 v3, v6, 8, v5
; GFX10-NEXT: s_waitcnt lgkmcnt(8) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_lshl_or_b32 v4, v8, 8, v7 ; GFX10-NEXT: v_lshl_or_b32 v4, v8, 8, v7
; GFX10-NEXT: ds_read_u8 v5, v0 offset:8
; GFX10-NEXT: ds_read_u8 v6, v0 offset:9
; GFX10-NEXT: ds_read_u8 v7, v0 offset:10
; GFX10-NEXT: ds_read_u8 v8, v0 offset:11
; GFX10-NEXT: ds_read_u8 v9, v0 offset:12
; GFX10-NEXT: ds_read_u8 v10, v0 offset:13
; GFX10-NEXT: ds_read_u8 v11, v0 offset:14
; GFX10-NEXT: ds_read_u8 v0, v0 offset:15
; GFX10-NEXT: s_waitcnt lgkmcnt(6) ; GFX10-NEXT: s_waitcnt lgkmcnt(6)
; GFX10-NEXT: v_lshl_or_b32 v5, v10, 8, v9 ; GFX10-NEXT: v_lshl_or_b32 v5, v6, 8, v5
; GFX10-NEXT: s_waitcnt lgkmcnt(4) ; GFX10-NEXT: s_waitcnt lgkmcnt(4)
; GFX10-NEXT: v_lshl_or_b32 v6, v12, 8, v11 ; GFX10-NEXT: v_lshl_or_b32 v6, v8, 8, v7
; GFX10-NEXT: s_waitcnt lgkmcnt(2) ; GFX10-NEXT: s_waitcnt lgkmcnt(2)
; GFX10-NEXT: v_lshl_or_b32 v7, v14, 8, v13 ; GFX10-NEXT: v_lshl_or_b32 v7, v10, 8, v9
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_lshl_or_b32 v8, v0, 8, v15 ; GFX10-NEXT: v_lshl_or_b32 v8, v0, 8, v11
; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v1 ; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX10-NEXT: v_lshl_or_b32 v1, v4, 16, v3 ; GFX10-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX10-NEXT: v_lshl_or_b32 v2, v6, 16, v5 ; GFX10-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX10-NEXT: v_lshl_or_b32 v3, v8, 16, v7 ; GFX10-NEXT: v_lshl_or_b32 v3, v8, 16, v7
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: load_lds_v4i32_align1: ; GFX11-LABEL: load_lds_v4i32_align1:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
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llvm/test/CodeGen/AMDGPU/load-local.96.ll

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; GFX10-NEXT: ds_read_u8 v1, v0 ; GFX10-NEXT: ds_read_u8 v1, v0
; GFX10-NEXT: ds_read_u8 v2, v0 offset:1 ; GFX10-NEXT: ds_read_u8 v2, v0 offset:1
; GFX10-NEXT: ds_read_u8 v3, v0 offset:2 ; GFX10-NEXT: ds_read_u8 v3, v0 offset:2
; GFX10-NEXT: ds_read_u8 v4, v0 offset:3 ; GFX10-NEXT: ds_read_u8 v4, v0 offset:3
; GFX10-NEXT: ds_read_u8 v5, v0 offset:4 ; GFX10-NEXT: ds_read_u8 v5, v0 offset:4
; GFX10-NEXT: ds_read_u8 v6, v0 offset:5 ; GFX10-NEXT: ds_read_u8 v6, v0 offset:5
; GFX10-NEXT: ds_read_u8 v7, v0 offset:6 ; GFX10-NEXT: ds_read_u8 v7, v0 offset:6
; GFX10-NEXT: ds_read_u8 v8, v0 offset:7 ; GFX10-NEXT: ds_read_u8 v8, v0 offset:7
; GFX10-NEXT: ds_read_u8 v9, v0 offset:8 ; GFX10-NEXT: s_waitcnt lgkmcnt(6)
; GFX10-NEXT: ds_read_u8 v10, v0 offset:9
; GFX10-NEXT: ds_read_u8 v11, v0 offset:10
; GFX10-NEXT: ds_read_u8 v0, v0 offset:11
; GFX10-NEXT: s_waitcnt lgkmcnt(10)
; GFX10-NEXT: v_lshl_or_b32 v1, v2, 8, v1 ; GFX10-NEXT: v_lshl_or_b32 v1, v2, 8, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(8) ; GFX10-NEXT: s_waitcnt lgkmcnt(4)
; GFX10-NEXT: v_lshl_or_b32 v2, v4, 8, v3 ; GFX10-NEXT: v_lshl_or_b32 v2, v4, 8, v3
; GFX10-NEXT: s_waitcnt lgkmcnt(6) ; GFX10-NEXT: s_waitcnt lgkmcnt(2)
; GFX10-NEXT: v_lshl_or_b32 v3, v6, 8, v5 ; GFX10-NEXT: v_lshl_or_b32 v3, v6, 8, v5
; GFX10-NEXT: s_waitcnt lgkmcnt(4) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_lshl_or_b32 v4, v8, 8, v7 ; GFX10-NEXT: v_lshl_or_b32 v4, v8, 8, v7
; GFX10-NEXT: ds_read_u8 v5, v0 offset:8
; GFX10-NEXT: ds_read_u8 v6, v0 offset:9
; GFX10-NEXT: ds_read_u8 v7, v0 offset:10
; GFX10-NEXT: ds_read_u8 v0, v0 offset:11
; GFX10-NEXT: s_waitcnt lgkmcnt(2) ; GFX10-NEXT: s_waitcnt lgkmcnt(2)
; GFX10-NEXT: v_lshl_or_b32 v5, v10, 8, v9 ; GFX10-NEXT: v_lshl_or_b32 v5, v6, 8, v5
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_lshl_or_b32 v6, v0, 8, v11 ; GFX10-NEXT: v_lshl_or_b32 v6, v0, 8, v7
; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v1 ; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX10-NEXT: v_lshl_or_b32 v1, v4, 16, v3 ; GFX10-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX10-NEXT: v_lshl_or_b32 v2, v6, 16, v5 ; GFX10-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: load_lds_v3i32_align1: ; GFX11-LABEL: load_lds_v3i32_align1:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
▲ Show 20 Lines • Show All 295 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/memcpy-scoped-aa.ll

Show All 14 Lines
; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.add.ptr, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.add.ptr, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
define i32 @test_memcpy(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocapture readonly %q) { define i32 @test_memcpy(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocapture readonly %q) {
; Check loads of %q are scheduled ahead of that store of the memcpy on %p. ; Check loads of %q are scheduled ahead of that store of the memcpy on %p.
; CHECK-LABEL: test_memcpy: ; CHECK-LABEL: test_memcpy:
; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off ; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off
; CHECK-DAG: global_load_dwordx4 [[PVAL:v\[[0-9]+:[0-9]+\]]], v[0:1], off offset:16 ; CHECK-DAG: global_load_dwordx4 [[PVAL:v\[[0-9]+:[0-9]+\]]], v[0:1], off offset:16
; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]] ; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]]
; CHECK: global_store_dwordx4 v[0:1], [[PVAL]], off ; CHECK-DAG: global_store_dwordx4 v[0:1], [[PVAL]], off
; CHECK: s_setpc_b64 s[30:31] ; CHECK: s_setpc_b64 s[30:31]
%add.ptr = getelementptr inbounds i32, ptr addrspace(1) %p, i64 4 %add.ptr = getelementptr inbounds i32, ptr addrspace(1) %p, i64 4
tail call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %p, ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %add.ptr, i64 16, i1 false), !alias.scope !2, !noalias !4 tail call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %p, ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %add.ptr, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, ptr addrspace(1) %q, align 4, !alias.scope !4, !noalias !2 %v0 = load i32, ptr addrspace(1) %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, ptr addrspace(1) %q, i64 1 %q1 = getelementptr inbounds i32, ptr addrspace(1) %q, i64 1
%v1 = load i32, ptr addrspace(1) %q1, align 4, !alias.scope !4, !noalias !2 %v1 = load i32, ptr addrspace(1) %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1 %add = add i32 %v0, %v1
ret i32 %add ret i32 %add
} }
; MIR-LABEL: name: test_memcpy_inline ; MIR-LABEL: name: test_memcpy_inline
; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.add.ptr, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.add.ptr, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
define i32 @test_memcpy_inline(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocapture readonly %q) { define i32 @test_memcpy_inline(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocapture readonly %q) {
; Check loads of %q are scheduled ahead of that store of the memcpy on %p. ; Check loads of %q are scheduled ahead of that store of the memcpy on %p.
; CHECK-LABEL: test_memcpy_inline: ; CHECK-LABEL: test_memcpy_inline:
; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off ; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off
; CHECK-DAG: global_load_dwordx4 [[PVAL:v\[[0-9]+:[0-9]+\]]], v[0:1], off offset:16 ; CHECK-DAG: global_load_dwordx4 [[PVAL:v\[[0-9]+:[0-9]+\]]], v[0:1], off offset:16
; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]] ; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]]
; CHECK: global_store_dwordx4 v[0:1], [[PVAL]], off ; CHECK-DAG: global_store_dwordx4 v[0:1], [[PVAL]], off
; CHECK: s_setpc_b64 s[30:31] ; CHECK: s_setpc_b64 s[30:31]
%add.ptr = getelementptr inbounds i32, ptr addrspace(1) %p, i64 4 %add.ptr = getelementptr inbounds i32, ptr addrspace(1) %p, i64 4
tail call void @llvm.memcpy.inline.p1.p1.i64(ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %p, ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %add.ptr, i64 16, i1 false), !alias.scope !2, !noalias !4 tail call void @llvm.memcpy.inline.p1.p1.i64(ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %p, ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %add.ptr, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, ptr addrspace(1) %q, align 4, !alias.scope !4, !noalias !2 %v0 = load i32, ptr addrspace(1) %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, ptr addrspace(1) %q, i64 1 %q1 = getelementptr inbounds i32, ptr addrspace(1) %q, i64 1
%v1 = load i32, ptr addrspace(1) %q1, align 4, !alias.scope !4, !noalias !2 %v1 = load i32, ptr addrspace(1) %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1 %add = add i32 %v0, %v1
ret i32 %add ret i32 %add
} }
; MIR-LABEL: name: test_memmove ; MIR-LABEL: name: test_memmove
; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.add.ptr, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.add.ptr, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
define i32 @test_memmove(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocapture readonly %q) { define i32 @test_memmove(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocapture readonly %q) {
; Check loads of %q are scheduled ahead of that store of the memmove on %p. ; Check loads of %q are scheduled ahead of that store of the memmove on %p.
; CHECK-LABEL: test_memmove: ; CHECK-LABEL: test_memmove:
; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off ; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off
; CHECK-DAG: global_load_dwordx4 [[PVAL:v\[[0-9]+:[0-9]+\]]], v[0:1], off offset:16 ; CHECK-DAG: global_load_dwordx4 [[PVAL:v\[[0-9]+:[0-9]+\]]], v[0:1], off offset:16
; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]] ; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]]
; CHECK: global_store_dwordx4 v[0:1], [[PVAL]] ; CHECK-DAG: global_store_dwordx4 v[0:1], [[PVAL]]
; CHECK: s_setpc_b64 s[30:31] ; CHECK: s_setpc_b64 s[30:31]
%add.ptr = getelementptr inbounds i32, ptr addrspace(1) %p, i64 4 %add.ptr = getelementptr inbounds i32, ptr addrspace(1) %p, i64 4
tail call void @llvm.memmove.p1.p1.i64(ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %p, ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %add.ptr, i64 16, i1 false), !alias.scope !2, !noalias !4 tail call void @llvm.memmove.p1.p1.i64(ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %p, ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %add.ptr, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, ptr addrspace(1) %q, align 4, !alias.scope !4, !noalias !2 %v0 = load i32, ptr addrspace(1) %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, ptr addrspace(1) %q, i64 1 %q1 = getelementptr inbounds i32, ptr addrspace(1) %q, i64 1
%v1 = load i32, ptr addrspace(1) %q1, align 4, !alias.scope !4, !noalias !2 %v1 = load i32, ptr addrspace(1) %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1 %add = add i32 %v0, %v1
ret i32 %add ret i32 %add
} }
; MIR-LABEL: name: test_memset ; MIR-LABEL: name: test_memset
; MIR: GLOBAL_STORE_DWORDX4 killed %{{[0-9]+}}, killed %{{[0-9]+}}, 0, 0, implicit $exec :: (store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: GLOBAL_STORE_DWORDX4 killed %{{[0-9]+}}, killed %{{[0-9]+}}, 0, 0, implicit $exec :: (store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
define i32 @test_memset(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocapture readonly %q) { define i32 @test_memset(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocapture readonly %q) {
; Check loads of %q are scheduled ahead of that store of the memset on %p. ; Check loads of %q are scheduled ahead of that store of the memset on %p.
; CHECK-LABEL: test_memset: ; CHECK-LABEL: test_memset:
; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off ; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off
; CHECK-DAG: v_mov_b32_e32 v[[PVAL:[0-9]+]], 0xaaaaaaaa ; CHECK-DAG: v_mov_b32_e32 v[[PVAL:[0-9]+]], 0xaaaaaaaa
; CHECK: global_store_dwordx4 v[0:1], v[[[PVAL]]{{:[0-9]+\]}}, off ; CHECK-DAG: global_store_dwordx4 v[0:1], v[[[PVAL]]{{:[0-9]+\]}}, off
; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]] ; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]]
; CHECK: s_setpc_b64 s[30:31] ; CHECK: s_setpc_b64 s[30:31]
tail call void @llvm.memset.p1.i64(ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %p, i8 170, i64 16, i1 false), !alias.scope !2, !noalias !4 tail call void @llvm.memset.p1.i64(ptr addrspace(1) noundef nonnull align 4 dereferenceable(16) %p, i8 170, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, ptr addrspace(1) %q, align 4, !alias.scope !4, !noalias !2 %v0 = load i32, ptr addrspace(1) %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, ptr addrspace(1) %q, i64 1 %q1 = getelementptr inbounds i32, ptr addrspace(1) %q, i64 1
%v1 = load i32, ptr addrspace(1) %q1, align 4, !alias.scope !4, !noalias !2 %v1 = load i32, ptr addrspace(1) %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1 %add = add i32 %v0, %v1
ret i32 %add ret i32 %add
Show All 12 Lines

llvm/test/CodeGen/AMDGPU/memory_clause.ll

Show All 19 Lines
; GCN-NEXT: global_store_dwordx4 v16, v[8:11], s[2:3] offset:32 ; GCN-NEXT: global_store_dwordx4 v16, v[8:11], s[2:3] offset:32
; GCN-NEXT: s_waitcnt vmcnt(3) ; GCN-NEXT: s_waitcnt vmcnt(3)
; GCN-NEXT: global_store_dwordx4 v16, v[12:15], s[2:3] offset:48 ; GCN-NEXT: global_store_dwordx4 v16, v[12:15], s[2:3] offset:48
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-SCRATCH-LABEL: vector_clause: ; GCN-SCRATCH-LABEL: vector_clause:
; GCN-SCRATCH: ; %bb.0: ; %bb ; GCN-SCRATCH: ; %bb.0: ; %bb
; GCN-SCRATCH-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GCN-SCRATCH-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-SCRATCH-NEXT: v_lshlrev_b32_e32 v16, 4, v0 ; GCN-SCRATCH-NEXT: v_lshlrev_b32_e32 v8, 4, v0
; GCN-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GCN-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GCN-SCRATCH-NEXT: s_clause 0x3 ; GCN-SCRATCH-NEXT: s_clause 0x1
; GCN-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v16, s[0:1] ; GCN-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v8, s[0:1]
; GCN-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v16, s[0:1] offset:16 ; GCN-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v8, s[0:1] offset:16
; GCN-SCRATCH-NEXT: global_load_dwordx4 v[8:11], v16, s[0:1] offset:32 ; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(1)
; GCN-SCRATCH-NEXT: global_load_dwordx4 v[12:15], v16, s[0:1] offset:48 ; GCN-SCRATCH-NEXT: global_store_dwordx4 v8, v[0:3], s[2:3]
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(3) ; GCN-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v8, s[0:1] offset:32
; GCN-SCRATCH-NEXT: global_store_dwordx4 v16, v[0:3], s[2:3]
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(2)
; GCN-SCRATCH-NEXT: global_store_dwordx4 v16, v[4:7], s[2:3] offset:16
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(1) ; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(1)
; GCN-SCRATCH-NEXT: global_store_dwordx4 v16, v[8:11], s[2:3] offset:32 ; GCN-SCRATCH-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3] offset:16
; GCN-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v8, s[0:1] offset:48
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(1)
; GCN-SCRATCH-NEXT: global_store_dwordx4 v8, v[0:3], s[2:3] offset:32
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GCN-SCRATCH-NEXT: global_store_dwordx4 v16, v[12:15], s[2:3] offset:48 ; GCN-SCRATCH-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3] offset:48
; GCN-SCRATCH-NEXT: s_endpgm ; GCN-SCRATCH-NEXT: s_endpgm
bb: bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = zext i32 %tmp to i64 %tmp2 = zext i32 %tmp to i64
%tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp2 %tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp2
%tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 16 %tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 16
%tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp2 %tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp2
%tmp6 = add nuw nsw i64 %tmp2, 1 %tmp6 = add nuw nsw i64 %tmp2, 1
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; GCN-NEXT: global_store_dwordx4 v16, v[4:7], s[18:19] offset:16 ; GCN-NEXT: global_store_dwordx4 v16, v[4:7], s[18:19] offset:16
; GCN-NEXT: global_store_dwordx4 v16, v[8:11], s[18:19] offset:32 ; GCN-NEXT: global_store_dwordx4 v16, v[8:11], s[18:19] offset:32
; GCN-NEXT: global_store_dwordx4 v16, v[12:15], s[18:19] offset:48 ; GCN-NEXT: global_store_dwordx4 v16, v[12:15], s[18:19] offset:48
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-SCRATCH-LABEL: scalar_clause: ; GCN-SCRATCH-LABEL: scalar_clause:
; GCN-SCRATCH: ; %bb.0: ; %bb ; GCN-SCRATCH: ; %bb.0: ; %bb
; GCN-SCRATCH-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24 ; GCN-SCRATCH-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v16, 0 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v8, 0
; GCN-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GCN-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GCN-SCRATCH-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0 ; GCN-SCRATCH-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
; GCN-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GCN-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v0, s0 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v0, s0
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v1, s1 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v1, s1
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v2, s2 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v2, s2
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v3, s3 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v3, s3
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v4, s4 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v4, s4
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v5, s5 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v5, s5
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v6, s6 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v6, s6
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v7, s7 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v7, s7
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v8, s8 ; GCN-SCRATCH-NEXT: global_store_dwordx4 v8, v[0:3], s[18:19]
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v9, s9 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v0, s8
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v10, s10 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v1, s9
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v11, s11 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v2, s10
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v12, s12 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v3, s11
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v13, s13 ; GCN-SCRATCH-NEXT: global_store_dwordx4 v8, v[4:7], s[18:19] offset:16
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v14, s14 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v4, s12
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v15, s15 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v5, s13
; GCN-SCRATCH-NEXT: global_store_dwordx4 v16, v[0:3], s[18:19] ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v6, s14
; GCN-SCRATCH-NEXT: global_store_dwordx4 v16, v[4:7], s[18:19] offset:16 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v7, s15
; GCN-SCRATCH-NEXT: global_store_dwordx4 v16, v[8:11], s[18:19] offset:32 ; GCN-SCRATCH-NEXT: global_store_dwordx4 v8, v[0:3], s[18:19] offset:32
; GCN-SCRATCH-NEXT: global_store_dwordx4 v16, v[12:15], s[18:19] offset:48 ; GCN-SCRATCH-NEXT: global_store_dwordx4 v8, v[4:7], s[18:19] offset:48
; GCN-SCRATCH-NEXT: s_endpgm ; GCN-SCRATCH-NEXT: s_endpgm
bb: bb:
%tmp = load <4 x i32>, ptr addrspace(1) %arg, align 16 %tmp = load <4 x i32>, ptr addrspace(1) %arg, align 16
%tmp2 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 1 %tmp2 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 1
%tmp3 = load <4 x i32>, ptr addrspace(1) %tmp2, align 16 %tmp3 = load <4 x i32>, ptr addrspace(1) %tmp2, align 16
%tmp4 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 1 %tmp4 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 1
%tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 2 %tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 2
%tmp6 = load <4 x i32>, ptr addrspace(1) %tmp5, align 16 %tmp6 = load <4 x i32>, ptr addrspace(1) %tmp5, align 16
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; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-SCRATCH-LABEL: mubuf_clause: ; GCN-SCRATCH-LABEL: mubuf_clause:
; GCN-SCRATCH: ; %bb.0: ; %bb ; GCN-SCRATCH: ; %bb.0: ; %bb
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-SCRATCH-NEXT: s_waitcnt_vscnt null, 0x0 ; GCN-SCRATCH-NEXT: s_waitcnt_vscnt null, 0x0
; GCN-SCRATCH-NEXT: v_lshlrev_b32_e32 v2, 4, v31 ; GCN-SCRATCH-NEXT: v_lshlrev_b32_e32 v2, 4, v31
; GCN-SCRATCH-NEXT: v_and_b32_e32 v18, 0x3ff0, v2 ; GCN-SCRATCH-NEXT: v_and_b32_e32 v10, 0x3ff0, v2
; GCN-SCRATCH-NEXT: v_add_nc_u32_e32 v0, v0, v18 ; GCN-SCRATCH-NEXT: v_add_nc_u32_e32 v11, v0, v10
; GCN-SCRATCH-NEXT: s_clause 0x3 ; GCN-SCRATCH-NEXT: v_add_nc_u32_e32 v10, v1, v10
; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[2:5], v0, off ; GCN-SCRATCH-NEXT: s_clause 0x1
; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[6:9], v0, off offset:16 ; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[2:5], v11, off
; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[10:13], v0, off offset:32 ; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[6:9], v11, off offset:16
; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[14:17], v0, off offset:48 ; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(1)
; GCN-SCRATCH-NEXT: v_add_nc_u32_e32 v0, v1, v18 ; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v10, v[2:5], off
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(3) ; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v0, v[2:5], off ; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v10, v[6:9], off offset:16
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(2) ; GCN-SCRATCH-NEXT: s_clause 0x1
; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v0, v[6:9], off offset:16 ; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[0:3], v11, off offset:32
; GCN-SCRATCH-NEXT: scratch_load_dwordx4 v[4:7], v11, off offset:48
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(1) ; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(1)
; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v0, v[10:13], off offset:32 ; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v10, v[0:3], off offset:32
; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v0, v[14:17], off offset:48 ; GCN-SCRATCH-NEXT: scratch_store_dwordx4 v10, v[4:7], off offset:48
; GCN-SCRATCH-NEXT: s_waitcnt_vscnt null, 0x0 ; GCN-SCRATCH-NEXT: s_waitcnt_vscnt null, 0x0
; GCN-SCRATCH-NEXT: s_setpc_b64 s[30:31] ; GCN-SCRATCH-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg, i32 %tmp %tmp2 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg, i32 %tmp
%tmp3 = load <4 x i32>, ptr addrspace(5) %tmp2, align 16 %tmp3 = load <4 x i32>, ptr addrspace(5) %tmp2, align 16
%tmp4 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg1, i32 %tmp %tmp4 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg1, i32 %tmp
%tmp5 = add nuw nsw i32 %tmp, 1 %tmp5 = add nuw nsw i32 %tmp, 1
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llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; GFX1010_W32-NEXT: v_readfirstlane_b32 s9, v1 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s9, v1
; GFX1010_W32-NEXT: v_readfirstlane_b32 s10, v2 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s10, v2
; GFX1010_W32-NEXT: v_readfirstlane_b32 s11, v3 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s11, v3
; GFX1010_W32-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[0:1] ; GFX1010_W32-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[0:1]
; GFX1010_W32-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[2:3] ; GFX1010_W32-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[2:3]
; GFX1010_W32-NEXT: s_and_b32 s4, vcc_lo, s4 ; GFX1010_W32-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX1010_W32-NEXT: s_and_saveexec_b32 s4, s4 ; GFX1010_W32-NEXT: s_and_saveexec_b32 s4, s4
; GFX1010_W32-NEXT: buffer_load_format_x v5, v4, s[8:11], 0 idxen ; GFX1010_W32-NEXT: buffer_load_format_x v5, v4, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1010_W32-NEXT: ; implicit-def: $vgpr4 ; GFX1010_W32-NEXT: ; implicit-def: $vgpr4
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4 ; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB0_1 ; GFX1010_W32-NEXT: s_cbranch_execnz .LBB0_1
; GFX1010_W32-NEXT: ; %bb.2: ; GFX1010_W32-NEXT: ; %bb.2:
; GFX1010_W32-NEXT: s_mov_b32 exec_lo, s5 ; GFX1010_W32-NEXT: s_mov_b32 exec_lo, s5
; GFX1010_W32-NEXT: s_waitcnt vmcnt(0) ; GFX1010_W32-NEXT: s_waitcnt vmcnt(0)
; GFX1010_W32-NEXT: v_mov_b32_e32 v0, v5 ; GFX1010_W32-NEXT: v_mov_b32_e32 v0, v5
; GFX1010_W32-NEXT: s_setpc_b64 s[30:31] ; GFX1010_W32-NEXT: s_setpc_b64 s[30:31]
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; GFX1010_W32-NEXT: v_readfirstlane_b32 s9, v5 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s9, v5
; GFX1010_W32-NEXT: v_readfirstlane_b32 s10, v6 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s10, v6
; GFX1010_W32-NEXT: v_readfirstlane_b32 s11, v7 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s11, v7
; GFX1010_W32-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[4:5] ; GFX1010_W32-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[4:5]
; GFX1010_W32-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[6:7] ; GFX1010_W32-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[6:7]
; GFX1010_W32-NEXT: s_and_b32 s4, vcc_lo, s4 ; GFX1010_W32-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX1010_W32-NEXT: s_and_saveexec_b32 s4, s4 ; GFX1010_W32-NEXT: s_and_saveexec_b32 s4, s4
; GFX1010_W32-NEXT: buffer_load_format_x v0, v8, s[8:11], 0 idxen ; GFX1010_W32-NEXT: buffer_load_format_x v0, v8, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W32-NEXT: ; implicit-def: $vgpr8 ; GFX1010_W32-NEXT: ; implicit-def: $vgpr8
; GFX1010_W32-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4 ; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB1_3 ; GFX1010_W32-NEXT: s_cbranch_execnz .LBB1_3
; GFX1010_W32-NEXT: ; %bb.4: ; GFX1010_W32-NEXT: ; %bb.4:
; GFX1010_W32-NEXT: s_mov_b32 exec_lo, s5 ; GFX1010_W32-NEXT: s_mov_b32 exec_lo, s5
; GFX1010_W32-NEXT: s_waitcnt vmcnt(1) ; GFX1010_W32-NEXT: s_waitcnt vmcnt(1)
; GFX1010_W32-NEXT: global_store_dword v[9:10], v13, off ; GFX1010_W32-NEXT: global_store_dword v[9:10], v13, off
; GFX1010_W32-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1010_W32-NEXT: s_waitcnt_vscnt null, 0x0
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; ;
; GFX1010_W32-LABEL: mubuf_vgpr_outside_entry: ; GFX1010_W32-LABEL: mubuf_vgpr_outside_entry:
; GFX1010_W32: ; %bb.0: ; %entry ; GFX1010_W32: ; %bb.0: ; %entry
; GFX1010_W32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1010_W32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010_W32-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1010_W32-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010_W32-NEXT: ;;#ASMSTART ; GFX1010_W32-NEXT: ;;#ASMSTART
; GFX1010_W32-NEXT: s_mov_b32 s4, 17 ; GFX1010_W32-NEXT: s_mov_b32 s4, 17
; GFX1010_W32-NEXT: ;;#ASMEND ; GFX1010_W32-NEXT: ;;#ASMEND
; GFX1010_W32-NEXT: v_mov_b32_e32 v8, s4 ; GFX1010_W32-NEXT: v_mov_b32_e32 v9, s4
; GFX1010_W32-NEXT: s_mov_b32 s6, exec_lo ; GFX1010_W32-NEXT: s_mov_b32 s6, exec_lo
; GFX1010_W32-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1 ; GFX1010_W32-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
; GFX1010_W32-NEXT: v_readfirstlane_b32 s8, v0 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s8, v0
; GFX1010_W32-NEXT: v_readfirstlane_b32 s9, v1 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s9, v1
; GFX1010_W32-NEXT: v_readfirstlane_b32 s10, v2 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s10, v2
; GFX1010_W32-NEXT: v_readfirstlane_b32 s11, v3 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s11, v3
; GFX1010_W32-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[0:1] ; GFX1010_W32-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[0:1]
; GFX1010_W32-NEXT: v_cmp_eq_u64_e64 s5, s[10:11], v[2:3] ; GFX1010_W32-NEXT: v_cmp_eq_u64_e64 s5, s[10:11], v[2:3]
; GFX1010_W32-NEXT: s_and_b32 s5, vcc_lo, s5 ; GFX1010_W32-NEXT: s_and_b32 s5, vcc_lo, s5
; GFX1010_W32-NEXT: s_and_saveexec_b32 s5, s5 ; GFX1010_W32-NEXT: s_and_saveexec_b32 s5, s5
; GFX1010_W32-NEXT: buffer_load_format_x v9, v8, s[8:11], 0 idxen ; GFX1010_W32-NEXT: buffer_load_format_x v8, v9, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr9
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX1010_W32-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1010_W32-NEXT: ; implicit-def: $vgpr8
; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s5 ; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s5
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB2_1 ; GFX1010_W32-NEXT: s_cbranch_execnz .LBB2_1
; GFX1010_W32-NEXT: ; %bb.2: ; GFX1010_W32-NEXT: ; %bb.2:
; GFX1010_W32-NEXT: s_mov_b32 exec_lo, s6 ; GFX1010_W32-NEXT: s_mov_b32 exec_lo, s6
; GFX1010_W32-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX1010_W32-NEXT: v_and_b32_e32 v0, 0x3ff, v31
; GFX1010_W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1010_W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1010_W32-NEXT: s_and_saveexec_b32 s5, vcc_lo ; GFX1010_W32-NEXT: s_and_saveexec_b32 s5, vcc_lo
; GFX1010_W32-NEXT: s_cbranch_execz .LBB2_6 ; GFX1010_W32-NEXT: s_cbranch_execz .LBB2_6
; GFX1010_W32-NEXT: ; %bb.3: ; %bb1 ; GFX1010_W32-NEXT: ; %bb.3: ; %bb1
; GFX1010_W32-NEXT: v_mov_b32_e32 v0, s4 ; GFX1010_W32-NEXT: v_mov_b32_e32 v0, s4
; GFX1010_W32-NEXT: s_mov_b32 s6, exec_lo ; GFX1010_W32-NEXT: s_mov_b32 s6, exec_lo
; GFX1010_W32-NEXT: .LBB2_4: ; =>This Inner Loop Header: Depth=1 ; GFX1010_W32-NEXT: .LBB2_4: ; =>This Inner Loop Header: Depth=1
; GFX1010_W32-NEXT: v_readfirstlane_b32 s8, v4 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s8, v4
; GFX1010_W32-NEXT: v_readfirstlane_b32 s9, v5 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s9, v5
; GFX1010_W32-NEXT: v_readfirstlane_b32 s10, v6 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s10, v6
; GFX1010_W32-NEXT: v_readfirstlane_b32 s11, v7 ; GFX1010_W32-NEXT: v_readfirstlane_b32 s11, v7
; GFX1010_W32-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[4:5] ; GFX1010_W32-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[4:5]
; GFX1010_W32-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[6:7] ; GFX1010_W32-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[6:7]
; GFX1010_W32-NEXT: s_and_b32 s4, vcc_lo, s4 ; GFX1010_W32-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX1010_W32-NEXT: s_and_saveexec_b32 s4, s4 ; GFX1010_W32-NEXT: s_and_saveexec_b32 s4, s4
; GFX1010_W32-NEXT: buffer_load_format_x v9, v0, s[8:11], 0 idxen ; GFX1010_W32-NEXT: buffer_load_format_x v8, v0, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0 ; GFX1010_W32-NEXT: ; implicit-def: $vgpr0
; GFX1010_W32-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4 ; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB2_4 ; GFX1010_W32-NEXT: s_cbranch_execnz .LBB2_4
; GFX1010_W32-NEXT: ; %bb.5: ; GFX1010_W32-NEXT: ; %bb.5:
; GFX1010_W32-NEXT: s_mov_b32 exec_lo, s6 ; GFX1010_W32-NEXT: s_mov_b32 exec_lo, s6
; GFX1010_W32-NEXT: .LBB2_6: ; %bb2 ; GFX1010_W32-NEXT: .LBB2_6: ; %bb2
; GFX1010_W32-NEXT: s_or_b32 exec_lo, exec_lo, s5 ; GFX1010_W32-NEXT: s_or_b32 exec_lo, exec_lo, s5
; GFX1010_W32-NEXT: s_waitcnt vmcnt(0) ; GFX1010_W32-NEXT: s_waitcnt vmcnt(0)
; GFX1010_W32-NEXT: global_store_dword v[11:12], v9, off ; GFX1010_W32-NEXT: global_store_dword v[11:12], v8, off
; GFX1010_W32-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1010_W32-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010_W32-NEXT: s_setpc_b64 s[30:31] ; GFX1010_W32-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1010_W64-LABEL: mubuf_vgpr_outside_entry: ; GFX1010_W64-LABEL: mubuf_vgpr_outside_entry:
; GFX1010_W64: ; %bb.0: ; %entry ; GFX1010_W64: ; %bb.0: ; %entry
; GFX1010_W64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1010_W64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010_W64-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1010_W64-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010_W64-NEXT: ;;#ASMSTART ; GFX1010_W64-NEXT: ;;#ASMSTART
; GFX1010_W64-NEXT: s_mov_b32 s4, 17 ; GFX1010_W64-NEXT: s_mov_b32 s4, 17
; GFX1010_W64-NEXT: ;;#ASMEND ; GFX1010_W64-NEXT: ;;#ASMEND
; GFX1010_W64-NEXT: v_mov_b32_e32 v8, s4 ; GFX1010_W64-NEXT: v_mov_b32_e32 v9, s4
; GFX1010_W64-NEXT: s_mov_b64 s[12:13], exec ; GFX1010_W64-NEXT: s_mov_b64 s[12:13], exec
; GFX1010_W64-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1 ; GFX1010_W64-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
; GFX1010_W64-NEXT: v_readfirstlane_b32 s8, v0 ; GFX1010_W64-NEXT: v_readfirstlane_b32 s8, v0
; GFX1010_W64-NEXT: v_readfirstlane_b32 s9, v1 ; GFX1010_W64-NEXT: v_readfirstlane_b32 s9, v1
; GFX1010_W64-NEXT: v_readfirstlane_b32 s10, v2 ; GFX1010_W64-NEXT: v_readfirstlane_b32 s10, v2
; GFX1010_W64-NEXT: v_readfirstlane_b32 s11, v3 ; GFX1010_W64-NEXT: v_readfirstlane_b32 s11, v3
; GFX1010_W64-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[0:1] ; GFX1010_W64-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[0:1]
; GFX1010_W64-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], v[2:3] ; GFX1010_W64-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], v[2:3]
; GFX1010_W64-NEXT: s_and_b64 s[6:7], vcc, s[6:7] ; GFX1010_W64-NEXT: s_and_b64 s[6:7], vcc, s[6:7]
; GFX1010_W64-NEXT: s_and_saveexec_b64 s[6:7], s[6:7] ; GFX1010_W64-NEXT: s_and_saveexec_b64 s[6:7], s[6:7]
; GFX1010_W64-NEXT: buffer_load_format_x v9, v8, s[8:11], 0 idxen ; GFX1010_W64-NEXT: buffer_load_format_x v8, v9, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX1010_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1010_W64-NEXT: ; implicit-def: $vgpr8 ; GFX1010_W64-NEXT: ; implicit-def: $vgpr9
; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[6:7] ; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[6:7]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB2_1 ; GFX1010_W64-NEXT: s_cbranch_execnz .LBB2_1
; GFX1010_W64-NEXT: ; %bb.2: ; GFX1010_W64-NEXT: ; %bb.2:
; GFX1010_W64-NEXT: s_mov_b64 exec, s[12:13] ; GFX1010_W64-NEXT: s_mov_b64 exec, s[12:13]
; GFX1010_W64-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX1010_W64-NEXT: v_and_b32_e32 v0, 0x3ff, v31
; GFX1010_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1010_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1010_W64-NEXT: s_and_saveexec_b64 s[6:7], vcc ; GFX1010_W64-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX1010_W64-NEXT: s_cbranch_execz .LBB2_6 ; GFX1010_W64-NEXT: s_cbranch_execz .LBB2_6
; GFX1010_W64-NEXT: ; %bb.3: ; %bb1 ; GFX1010_W64-NEXT: ; %bb.3: ; %bb1
; GFX1010_W64-NEXT: v_mov_b32_e32 v0, s4 ; GFX1010_W64-NEXT: v_mov_b32_e32 v0, s4
; GFX1010_W64-NEXT: s_mov_b64 s[12:13], exec ; GFX1010_W64-NEXT: s_mov_b64 s[12:13], exec
; GFX1010_W64-NEXT: .LBB2_4: ; =>This Inner Loop Header: Depth=1 ; GFX1010_W64-NEXT: .LBB2_4: ; =>This Inner Loop Header: Depth=1
; GFX1010_W64-NEXT: v_readfirstlane_b32 s8, v4 ; GFX1010_W64-NEXT: v_readfirstlane_b32 s8, v4
; GFX1010_W64-NEXT: v_readfirstlane_b32 s9, v5 ; GFX1010_W64-NEXT: v_readfirstlane_b32 s9, v5
; GFX1010_W64-NEXT: v_readfirstlane_b32 s10, v6 ; GFX1010_W64-NEXT: v_readfirstlane_b32 s10, v6
; GFX1010_W64-NEXT: v_readfirstlane_b32 s11, v7 ; GFX1010_W64-NEXT: v_readfirstlane_b32 s11, v7
; GFX1010_W64-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[4:5] ; GFX1010_W64-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[4:5]
; GFX1010_W64-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], v[6:7] ; GFX1010_W64-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], v[6:7]
; GFX1010_W64-NEXT: s_and_b64 s[4:5], vcc, s[4:5] ; GFX1010_W64-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX1010_W64-NEXT: s_and_saveexec_b64 s[4:5], s[4:5] ; GFX1010_W64-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]
; GFX1010_W64-NEXT: buffer_load_format_x v9, v0, s[8:11], 0 idxen ; GFX1010_W64-NEXT: buffer_load_format_x v8, v0, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7 ; GFX1010_W64-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W64-NEXT: ; implicit-def: $vgpr0 ; GFX1010_W64-NEXT: ; implicit-def: $vgpr0
; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[4:5] ; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB2_4 ; GFX1010_W64-NEXT: s_cbranch_execnz .LBB2_4
; GFX1010_W64-NEXT: ; %bb.5: ; GFX1010_W64-NEXT: ; %bb.5:
; GFX1010_W64-NEXT: s_mov_b64 exec, s[12:13] ; GFX1010_W64-NEXT: s_mov_b64 exec, s[12:13]
; GFX1010_W64-NEXT: .LBB2_6: ; %bb2 ; GFX1010_W64-NEXT: .LBB2_6: ; %bb2
; GFX1010_W64-NEXT: s_or_b64 exec, exec, s[6:7] ; GFX1010_W64-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1010_W64-NEXT: s_waitcnt vmcnt(0) ; GFX1010_W64-NEXT: s_waitcnt vmcnt(0)
; GFX1010_W64-NEXT: global_store_dword v[11:12], v9, off ; GFX1010_W64-NEXT: global_store_dword v[11:12], v8, off
; GFX1010_W64-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1010_W64-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010_W64-NEXT: s_setpc_b64 s[30:31] ; GFX1010_W64-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100_W32-LABEL: mubuf_vgpr_outside_entry: ; GFX1100_W32-LABEL: mubuf_vgpr_outside_entry:
; GFX1100_W32: ; %bb.0: ; %entry ; GFX1100_W32: ; %bb.0: ; %entry
; GFX1100_W32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100_W32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100_W32-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1100_W32-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100_W32-NEXT: ;;#ASMSTART ; GFX1100_W32-NEXT: ;;#ASMSTART
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; ;
; GFX1100_W64-LABEL: mubuf_vgpr_outside_entry: ; GFX1100_W64-LABEL: mubuf_vgpr_outside_entry:
; GFX1100_W64: ; %bb.0: ; %entry ; GFX1100_W64: ; %bb.0: ; %entry
; GFX1100_W64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100_W64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100_W64-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1100_W64-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100_W64-NEXT: ;;#ASMSTART ; GFX1100_W64-NEXT: ;;#ASMSTART
; GFX1100_W64-NEXT: s_mov_b32 s4, 17 ; GFX1100_W64-NEXT: s_mov_b32 s4, 17
; GFX1100_W64-NEXT: ;;#ASMEND ; GFX1100_W64-NEXT: ;;#ASMEND
; GFX1100_W64-NEXT: v_mov_b32_e32 v8, s4 ; GFX1100_W64-NEXT: v_mov_b32_e32 v9, s4
; GFX1100_W64-NEXT: s_mov_b64 s[2:3], exec ; GFX1100_W64-NEXT: s_mov_b64 s[2:3], exec
; GFX1100_W64-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1 ; GFX1100_W64-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
; GFX1100_W64-NEXT: v_readfirstlane_b32 s8, v0 ; GFX1100_W64-NEXT: v_readfirstlane_b32 s8, v0
; GFX1100_W64-NEXT: v_readfirstlane_b32 s9, v1 ; GFX1100_W64-NEXT: v_readfirstlane_b32 s9, v1
; GFX1100_W64-NEXT: v_readfirstlane_b32 s10, v2 ; GFX1100_W64-NEXT: v_readfirstlane_b32 s10, v2
; GFX1100_W64-NEXT: v_readfirstlane_b32 s11, v3 ; GFX1100_W64-NEXT: v_readfirstlane_b32 s11, v3
; GFX1100_W64-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1100_W64-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100_W64-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[0:1] ; GFX1100_W64-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[0:1]
; GFX1100_W64-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], v[2:3] ; GFX1100_W64-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], v[2:3]
; GFX1100_W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX1100_W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1100_W64-NEXT: s_and_b64 s[0:1], vcc, s[0:1] ; GFX1100_W64-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
; GFX1100_W64-NEXT: s_and_saveexec_b64 s[0:1], s[0:1] ; GFX1100_W64-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]
; GFX1100_W64-NEXT: buffer_load_format_x v9, v8, s[8:11], 0 idxen ; GFX1100_W64-NEXT: buffer_load_format_x v8, v9, s[8:11], 0 idxen
; GFX1100_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX1100_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1100_W64-NEXT: ; implicit-def: $vgpr8 ; GFX1100_W64-NEXT: ; implicit-def: $vgpr9
; GFX1100_W64-NEXT: s_xor_b64 exec, exec, s[0:1] ; GFX1100_W64-NEXT: s_xor_b64 exec, exec, s[0:1]
; GFX1100_W64-NEXT: s_cbranch_execnz .LBB2_1 ; GFX1100_W64-NEXT: s_cbranch_execnz .LBB2_1
; GFX1100_W64-NEXT: ; %bb.2: ; GFX1100_W64-NEXT: ; %bb.2:
; GFX1100_W64-NEXT: s_mov_b64 exec, s[2:3] ; GFX1100_W64-NEXT: s_mov_b64 exec, s[2:3]
; GFX1100_W64-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX1100_W64-NEXT: v_and_b32_e32 v0, 0x3ff, v31
; GFX1100_W64-NEXT: s_mov_b64 s[2:3], exec ; GFX1100_W64-NEXT: s_mov_b64 s[2:3], exec
; GFX1100_W64-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100_W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100_W64-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX1100_W64-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1100_W64-NEXT: s_cbranch_execz .LBB2_6 ; GFX1100_W64-NEXT: s_cbranch_execz .LBB2_6
; GFX1100_W64-NEXT: ; %bb.3: ; %bb1 ; GFX1100_W64-NEXT: ; %bb.3: ; %bb1
; GFX1100_W64-NEXT: v_mov_b32_e32 v0, s4 ; GFX1100_W64-NEXT: v_mov_b32_e32 v0, s4
; GFX1100_W64-NEXT: s_mov_b64 s[8:9], exec ; GFX1100_W64-NEXT: s_mov_b64 s[8:9], exec
; GFX1100_W64-NEXT: .LBB2_4: ; =>This Inner Loop Header: Depth=1 ; GFX1100_W64-NEXT: .LBB2_4: ; =>This Inner Loop Header: Depth=1
; GFX1100_W64-NEXT: v_readfirstlane_b32 s4, v4 ; GFX1100_W64-NEXT: v_readfirstlane_b32 s4, v4
; GFX1100_W64-NEXT: v_readfirstlane_b32 s5, v5 ; GFX1100_W64-NEXT: v_readfirstlane_b32 s5, v5
; GFX1100_W64-NEXT: v_readfirstlane_b32 s6, v6 ; GFX1100_W64-NEXT: v_readfirstlane_b32 s6, v6
; GFX1100_W64-NEXT: v_readfirstlane_b32 s7, v7 ; GFX1100_W64-NEXT: v_readfirstlane_b32 s7, v7
; GFX1100_W64-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1100_W64-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100_W64-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[4:5] ; GFX1100_W64-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[4:5]
; GFX1100_W64-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], v[6:7] ; GFX1100_W64-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], v[6:7]
; GFX1100_W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX1100_W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1100_W64-NEXT: s_and_b64 s[0:1], vcc, s[0:1] ; GFX1100_W64-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
; GFX1100_W64-NEXT: s_and_saveexec_b64 s[0:1], s[0:1] ; GFX1100_W64-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]
; GFX1100_W64-NEXT: buffer_load_format_x v9, v0, s[4:7], 0 idxen ; GFX1100_W64-NEXT: buffer_load_format_x v8, v0, s[4:7], 0 idxen
; GFX1100_W64-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7 ; GFX1100_W64-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1100_W64-NEXT: ; implicit-def: $vgpr0 ; GFX1100_W64-NEXT: ; implicit-def: $vgpr0
; GFX1100_W64-NEXT: s_xor_b64 exec, exec, s[0:1] ; GFX1100_W64-NEXT: s_xor_b64 exec, exec, s[0:1]
; GFX1100_W64-NEXT: s_cbranch_execnz .LBB2_4 ; GFX1100_W64-NEXT: s_cbranch_execnz .LBB2_4
; GFX1100_W64-NEXT: ; %bb.5: ; GFX1100_W64-NEXT: ; %bb.5:
; GFX1100_W64-NEXT: s_mov_b64 exec, s[8:9] ; GFX1100_W64-NEXT: s_mov_b64 exec, s[8:9]
; GFX1100_W64-NEXT: .LBB2_6: ; %bb2 ; GFX1100_W64-NEXT: .LBB2_6: ; %bb2
; GFX1100_W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1100_W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1100_W64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1100_W64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1100_W64-NEXT: s_waitcnt vmcnt(0) ; GFX1100_W64-NEXT: s_waitcnt vmcnt(0)
; GFX1100_W64-NEXT: global_store_b32 v[11:12], v9, off dlc ; GFX1100_W64-NEXT: global_store_b32 v[11:12], v8, off dlc
; GFX1100_W64-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1100_W64-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100_W64-NEXT: s_setpc_b64 s[30:31] ; GFX1100_W64-NEXT: s_setpc_b64 s[30:31]
; ;
; W64-O0-LABEL: mubuf_vgpr_outside_entry: ; W64-O0-LABEL: mubuf_vgpr_outside_entry:
; W64-O0: ; %bb.0: ; %entry ; W64-O0: ; %bb.0: ; %entry
; W64-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; W64-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; W64-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; W64-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
; W64-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; W64-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
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llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll

Show First 20 Lines • Show All 186 Lines • ▼ Show 20 Lines
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1]
; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2 ; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x1000 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x1000
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v10, vcc_lo, v0, 0x2000 ; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, 0x3800, v0
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: global_load_dwordx2 v[6:7], v[0:1], off ; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: global_load_dwordx2 v[8:9], v[4:5], off offset:-2048 ; GFX10-NEXT: global_load_dwordx2 v[8:9], v[4:5], off
; GFX10-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: global_load_dwordx2 v[10:11], v[4:5], off offset:-2048
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx2 v[12:13], v[6:7], off
; GFX10-NEXT: global_load_dwordx2 v[12:13], v[4:5], off ; GFX10-NEXT: global_load_dwordx2 v[14:15], v[0:1], off
; GFX10-NEXT: global_load_dwordx2 v[14:15], v[10:11], off offset:-2048 ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x3000 ; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v10, v14
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v11, v15, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x2000
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0x3000
; GFX10-NEXT: global_load_dwordx2 v[16:17], v[10:11], off
; GFX10-NEXT: global_load_dwordx2 v[18:19], v[4:5], off offset:-2048
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x3800, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: v_add_co_u32 v16, vcc_lo, v8, v6
; GFX10-NEXT: global_load_dwordx2 v[10:11], v[4:5], off ; GFX10-NEXT: v_add_co_ci_u32_e32 v17, vcc_lo, v9, v7, vcc_lo
; GFX10-NEXT: global_load_dwordx2 v[20:21], v[0:1], off ; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: s_waitcnt vmcnt(6) ; GFX10-NEXT: global_load_dwordx2 v[6:7], v[4:5], off offset:-2048
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v8, v6 ; GFX10-NEXT: global_load_dwordx2 v[8:9], v[4:5], off
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v9, v7, vcc_lo ; GFX10-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:-2048
; GFX10-NEXT: s_waitcnt vmcnt(5) ; GFX10-NEXT: global_load_dwordx2 v[14:15], v[0:1], off
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v12, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(4)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v14, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v15, v1, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(3) ; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v16, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v6, v16
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v17, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v17, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v18, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v8, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v19, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v10, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v10, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v20, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v14, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v21, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v15, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v12, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX90A-LABEL: clmem_read_simplified: ; GFX90A-LABEL: clmem_read_simplified:
; GFX90A: ; %bb.0: ; %entry ; GFX90A: ; %bb.0: ; %entry
; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 ; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 ; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GFX90A-NEXT: s_mov_b32 s38, -1 ; GFX90A-NEXT: s_mov_b32 s38, -1
▲ Show 20 Lines • Show All 438 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_mov_b64 s[0:1], s[36:37] ; GFX10-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX10-NEXT: s_mov_b64 s[2:3], s[38:39] ; GFX10-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX10-NEXT: s_mov_b32 s32, 0 ; GFX10-NEXT: s_mov_b32 s32, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v0 ; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 17, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 17, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: s_movk_i32 s0, 0x7f
; GFX10-NEXT: s_movk_i32 s1, 0x7f ; GFX10-NEXT: v_mov_b32_e32 v6, 0
; GFX10-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2] ; GFX10-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2]
; GFX10-NEXT: v_and_b32_e32 v0, 0xfe000000, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 0xfe000000, v0
; GFX10-NEXT: v_or_b32_e32 v1, v0, v1 ; GFX10-NEXT: v_or_b32_e32 v1, v0, v1
; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, s34 ; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, s34
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s35, v2, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s35, v2, vcc_lo
; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, 0x5000, v1 ; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, 0x5000, v1
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
; GFX10-NEXT: .LBB1_1: ; %for.cond.preheader ; GFX10-NEXT: .LBB1_1: ; %for.cond.preheader
; GFX10-NEXT: ; =>This Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Loop Header: Depth=1
; GFX10-NEXT: ; Child Loop BB1_2 Depth 2 ; GFX10-NEXT: ; Child Loop BB1_2 Depth 2
; GFX10-NEXT: v_mov_b32_e32 v6, v2 ; GFX10-NEXT: v_mov_b32_e32 v4, v2
; GFX10-NEXT: v_mov_b32_e32 v5, v1 ; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10-NEXT: s_mov_b32 s2, 0 ; GFX10-NEXT: s_mov_b32 s1, 0
; GFX10-NEXT: .LBB1_2: ; %for.body ; GFX10-NEXT: .LBB1_2: ; %for.body
; GFX10-NEXT: ; Parent Loop BB1_1 Depth=1 ; GFX10-NEXT: ; Parent Loop BB1_1 Depth=1
; GFX10-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX10-NEXT: ; => This Inner Loop Header: Depth=2
; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v5, 0xffffb800 ; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v3, 0xffffb800
; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, -1, v6, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, -1, v4, vcc_lo
; GFX10-NEXT: v_add_co_u32 v9, vcc_lo, v5, 0xffffc800 ; GFX10-NEXT: v_add_co_u32 v9, vcc_lo, v3, 0xffffc800
; GFX10-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, -1, v6, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, -1, v4, vcc_lo
; GFX10-NEXT: v_add_co_u32 v13, vcc_lo, v5, 0xffffd800 ; GFX10-NEXT: v_add_co_u32 v11, vcc_lo, 0xfffff000, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v14, vcc_lo, -1, v6, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, -1, v4, vcc_lo
; GFX10-NEXT: v_add_co_u32 v17, vcc_lo, v5, 0xffffe800 ; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: global_load_dwordx2 v[13:14], v[7:8], off offset:-2048
; GFX10-NEXT: global_load_dwordx2 v[11:12], v[7:8], off offset:-2048 ; GFX10-NEXT: global_load_dwordx2 v[15:16], v[7:8], off
; GFX10-NEXT: global_load_dwordx2 v[15:16], v[9:10], off offset:-2048 ; GFX10-NEXT: global_load_dwordx2 v[17:18], v[9:10], off offset:-2048
; GFX10-NEXT: global_load_dwordx2 v[19:20], v[13:14], off offset:-2048 ; GFX10-NEXT: global_load_dwordx2 v[19:20], v[11:12], off
; GFX10-NEXT: v_add_co_ci_u32_e32 v18, vcc_lo, -1, v6, vcc_lo ; GFX10-NEXT: s_addk_i32 s1, 0x2000
; GFX10-NEXT: v_add_co_u32 v21, vcc_lo, 0xfffff000, v5 ; GFX10-NEXT: s_cmp_gt_u32 s1, 0x3fffff
; GFX10-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, -1, v6, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: s_clause 0x7 ; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v13, v5
; GFX10-NEXT: global_load_dwordx2 v[23:24], v[17:18], off offset:-2048 ; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v14, v6, vcc_lo
; GFX10-NEXT: global_load_dwordx2 v[7:8], v[7:8], off ; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: global_load_dwordx2 v[9:10], v[9:10], off ; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v15, v5
; GFX10-NEXT: global_load_dwordx2 v[13:14], v[13:14], off ; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v16, v6, vcc_lo
; GFX10-NEXT: global_load_dwordx2 v[25:26], v[17:18], off ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: global_load_dwordx2 v[27:28], v[21:22], off ; GFX10-NEXT: v_add_co_u32 v21, vcc_lo, v17, v5
; GFX10-NEXT: global_load_dwordx2 v[29:30], v[5:6], off offset:-2048 ; GFX10-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, v18, v6, vcc_lo
; GFX10-NEXT: global_load_dwordx2 v[31:32], v[5:6], off ; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v3, 0xffffd800
; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, 0x10000, v5 ; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, -1, v4, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo ; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v3, 0xffffe800
; GFX10-NEXT: s_addk_i32 s2, 0x2000 ; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, -1, v4, vcc_lo
; GFX10-NEXT: s_cmp_gt_u32 s2, 0x3fffff ; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: s_waitcnt vmcnt(10) ; GFX10-NEXT: global_load_dwordx2 v[11:12], v[9:10], off
; GFX10-NEXT: v_add_co_u32 v3, s0, v11, v3 ; GFX10-NEXT: global_load_dwordx2 v[13:14], v[5:6], off offset:-2048
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v12, v4, s0 ; GFX10-NEXT: global_load_dwordx2 v[15:16], v[5:6], off
; GFX10-NEXT: s_waitcnt vmcnt(6) ; GFX10-NEXT: global_load_dwordx2 v[17:18], v[7:8], off offset:-2048
; GFX10-NEXT: v_add_co_u32 v3, s0, v7, v3
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v8, v4, s0
; GFX10-NEXT: v_add_co_u32 v3, s0, v15, v3
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v16, v4, s0
; GFX10-NEXT: s_waitcnt vmcnt(5)
; GFX10-NEXT: v_add_co_u32 v3, s0, v9, v3
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v10, v4, s0
; GFX10-NEXT: v_add_co_u32 v3, s0, v19, v3
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v20, v4, s0
; GFX10-NEXT: s_waitcnt vmcnt(4)
; GFX10-NEXT: v_add_co_u32 v3, s0, v13, v3
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v14, v4, s0
; GFX10-NEXT: v_add_co_u32 v3, s0, v23, v3
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v24, v4, s0
; GFX10-NEXT: s_waitcnt vmcnt(3) ; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_add_co_u32 v3, s0, v25, v3 ; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v11, v21
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v26, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v12, v22, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: v_add_co_u32 v3, s0, v27, v3 ; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v13, v5
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v28, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v14, v6, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_add_co_u32 v3, s0, v29, v3 ; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v15, v5
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v30, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v16, v6, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v31, v3 ; GFX10-NEXT: v_add_co_u32 v13, vcc_lo, v17, v5
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v32, v4, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v14, vcc_lo, v18, v6, vcc_lo
; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: global_load_dwordx2 v[5:6], v[7:8], off
; GFX10-NEXT: global_load_dwordx2 v[9:10], v[3:4], off offset:-2048
; GFX10-NEXT: global_load_dwordx2 v[11:12], v[3:4], off
; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v5, v13
; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v6, v14, vcc_lo
; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v19, v5
; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v20, v6, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v9, v5
; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v11, v5
; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v12, v6, vcc_lo
; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, 0x10000, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
; GFX10-NEXT: s_cbranch_scc0 .LBB1_2 ; GFX10-NEXT: s_cbranch_scc0 .LBB1_2
; GFX10-NEXT: ; %bb.3: ; %while.cond.loopexit ; GFX10-NEXT: ; %bb.3: ; %while.cond.loopexit
; GFX10-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; GFX10-NEXT: ; in Loop: Header=BB1_1 Depth=1
; GFX10-NEXT: s_add_i32 s0, s1, -1 ; GFX10-NEXT: s_add_i32 s1, s0, -1
; GFX10-NEXT: s_cmp_eq_u32 s1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s0, 0
; GFX10-NEXT: s_cbranch_scc1 .LBB1_5 ; GFX10-NEXT: s_cbranch_scc1 .LBB1_5
; GFX10-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1 ; GFX10-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1
; GFX10-NEXT: s_mov_b32 s1, s0 ; GFX10-NEXT: s_mov_b32 s0, s1
; GFX10-NEXT: s_branch .LBB1_1 ; GFX10-NEXT: s_branch .LBB1_1
; GFX10-NEXT: .LBB1_5: ; %while.end ; GFX10-NEXT: .LBB1_5: ; %while.end
; GFX10-NEXT: v_add_co_u32 v0, s0, s34, v0 ; GFX10-NEXT: v_add_co_u32 v0, s0, s34, v0
; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s35, 0, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s35, 0, s0
; GFX10-NEXT: global_store_dwordx2 v[0:1], v[3:4], off ; GFX10-NEXT: global_store_dwordx2 v[0:1], v[5:6], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX90A-LABEL: clmem_read: ; GFX90A-LABEL: clmem_read:
; GFX90A: ; %bb.0: ; %entry ; GFX90A: ; %bb.0: ; %entry
; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 ; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 ; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GFX90A-NEXT: s_mov_b32 s38, -1 ; GFX90A-NEXT: s_mov_b32 s38, -1
; GFX90A-NEXT: s_mov_b32 s39, 0xe00000 ; GFX90A-NEXT: s_mov_b32 s39, 0xe00000
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; GFX11-NEXT: s_addc_u32 s3, s3, _Z13get_global_idj@gotpcrel32@hi+12 ; GFX11-NEXT: s_addc_u32 s3, s3, _Z13get_global_idj@gotpcrel32@hi+12
; GFX11-NEXT: v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, 0 ; GFX11-NEXT: v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, 0
; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 ; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX11-NEXT: s_load_b64 s[34:35], s[0:1], 0x24 ; GFX11-NEXT: s_load_b64 s[34:35], s[0:1], 0x24
; GFX11-NEXT: s_mov_b32 s32, 0 ; GFX11-NEXT: s_mov_b32 s32, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xff, v0 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xff, v0
; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v0, 17, v0 ; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v0, 17, v0
; GFX11-NEXT: v_mov_b32_e32 v4, 0 ; GFX11-NEXT: v_mov_b32_e32 v6, 0
; GFX11-NEXT: s_movk_i32 s1, 0x7f ; GFX11-NEXT: s_movk_i32 s1, 0x7f
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2] ; GFX11-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2]
; GFX11-NEXT: v_and_b32_e32 v0, 0xfe000000, v0 ; GFX11-NEXT: v_and_b32_e32 v0, 0xfe000000, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v1, v0, v1 ; GFX11-NEXT: v_or_b32_e32 v1, v0, v1
; GFX11-NEXT: v_add_co_u32 v1, vcc_lo, v1, s34 ; GFX11-NEXT: v_add_co_u32 v1, vcc_lo, v1, s34
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s35, v2, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s35, v2, vcc_lo
; GFX11-NEXT: v_add_co_u32 v1, vcc_lo, 0x5000, v1 ; GFX11-NEXT: v_add_co_u32 v1, vcc_lo, 0x5000, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
; GFX11-NEXT: .LBB1_1: ; %for.cond.preheader ; GFX11-NEXT: .LBB1_1: ; %for.cond.preheader
; GFX11-NEXT: ; =>This Loop Header: Depth=1 ; GFX11-NEXT: ; =>This Loop Header: Depth=1
; GFX11-NEXT: ; Child Loop BB1_2 Depth 2 ; GFX11-NEXT: ; Child Loop BB1_2 Depth 2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1 ; GFX11-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
; GFX11-NEXT: s_mov_b32 s2, 0 ; GFX11-NEXT: s_mov_b32 s2, 0
; GFX11-NEXT: .LBB1_2: ; %for.body ; GFX11-NEXT: .LBB1_2: ; %for.body
; GFX11-NEXT: ; Parent Loop BB1_1 Depth=1 ; GFX11-NEXT: ; Parent Loop BB1_1 Depth=1
; GFX11-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX11-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_u32 v7, vcc_lo, v5, 0xffffc000 ; GFX11-NEXT: v_add_co_u32 v7, vcc_lo, v3, 0xffffc000
; GFX11-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, -1, v6, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, -1, v4, vcc_lo
; GFX11-NEXT: v_add_co_u32 v9, vcc_lo, 0xffffc000, v5 ; GFX11-NEXT: v_add_co_u32 v9, vcc_lo, 0xffffc000, v3
; GFX11-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, -1, v6, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, -1, v4, vcc_lo
; GFX11-NEXT: v_add_co_u32 v11, vcc_lo, 0xffffd000, v5 ; GFX11-NEXT: v_add_co_u32 v11, vcc_lo, 0xffffd000, v3
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: global_load_b64 v[13:14], v[7:8], off offset:-4096 ; GFX11-NEXT: global_load_b64 v[17:18], v[7:8], off offset:-4096
; GFX11-NEXT: global_load_b64 v[9:10], v[9:10], off offset:-2048 ; GFX11-NEXT: global_load_b64 v[9:10], v[9:10], off offset:-2048
; GFX11-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, -1, v6, vcc_lo
; GFX11-NEXT: v_add_co_u32 v15, vcc_lo, v5, 0xffffe000
; GFX11-NEXT: v_add_co_ci_u32_e32 v16, vcc_lo, -1, v6, vcc_lo
; GFX11-NEXT: global_load_b64 v[11:12], v[11:12], off offset:-2048
; GFX11-NEXT: v_add_co_u32 v17, vcc_lo, 0xffffe000, v5
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_b64 v[19:20], v[15:16], off offset:-4096
; GFX11-NEXT: global_load_b64 v[7:8], v[7:8], off ; GFX11-NEXT: global_load_b64 v[7:8], v[7:8], off
; GFX11-NEXT: v_add_co_ci_u32_e32 v18, vcc_lo, -1, v6, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, -1, v4, vcc_lo
; GFX11-NEXT: v_add_co_u32 v21, vcc_lo, 0xfffff000, v5 ; GFX11-NEXT: v_add_co_u32 v13, vcc_lo, v3, 0xffffe000
; GFX11-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, -1, v6, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v14, vcc_lo, -1, v4, vcc_lo
; GFX11-NEXT: s_clause 0x5 ; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: global_load_b64 v[17:18], v[17:18], off offset:-2048 ; GFX11-NEXT: global_load_b64 v[11:12], v[11:12], off offset:-2048
; GFX11-NEXT: global_load_b64 v[15:16], v[15:16], off ; GFX11-NEXT: global_load_b64 v[19:20], v[13:14], off offset:-4096
; GFX11-NEXT: global_load_b64 v[21:22], v[21:22], off offset:-2048 ; GFX11-NEXT: global_load_b64 v[13:14], v[13:14], off
; GFX11-NEXT: global_load_b64 v[23:24], v[5:6], off offset:-4096 ; GFX11-NEXT: v_add_co_u32 v15, vcc_lo, 0xffffe000, v3
; GFX11-NEXT: global_load_b64 v[25:26], v[5:6], off offset:-2048 ; GFX11-NEXT: v_add_co_ci_u32_e32 v16, vcc_lo, -1, v4, vcc_lo
; GFX11-NEXT: global_load_b64 v[27:28], v[5:6], off
; GFX11-NEXT: v_add_co_u32 v5, vcc_lo, 0x10000, v5
; GFX11-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
; GFX11-NEXT: s_addk_i32 s2, 0x2000 ; GFX11-NEXT: s_addk_i32 s2, 0x2000
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_cmp_gt_u32 s2, 0x3fffff ; GFX11-NEXT: s_cmp_gt_u32 s2, 0x3fffff
; GFX11-NEXT: s_waitcnt vmcnt(10) ; GFX11-NEXT: global_load_b64 v[15:16], v[15:16], off offset:-2048
; GFX11-NEXT: v_add_co_u32 v3, s0, v13, v3
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v14, v4, s0
; GFX11-NEXT: s_waitcnt vmcnt(9)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v3, s0, v9, v3
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v10, v4, s0
; GFX11-NEXT: s_waitcnt vmcnt(6) ; GFX11-NEXT: s_waitcnt vmcnt(6)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v21, vcc_lo, v17, v5
; GFX11-NEXT: v_add_co_u32 v3, s0, v7, v3 ; GFX11-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, v18, v6, vcc_lo
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v8, v4, s0 ; GFX11-NEXT: v_add_co_u32 v5, vcc_lo, 0xfffff000, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, -1, v4, vcc_lo
; GFX11-NEXT: v_add_co_u32 v3, s0, v11, v3
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v12, v4, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v3, s0, v19, v3
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v20, v4, s0
; GFX11-NEXT: s_waitcnt vmcnt(5) ; GFX11-NEXT: s_waitcnt vmcnt(5)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v21, vcc_lo, v9, v21
; GFX11-NEXT: v_add_co_u32 v3, s0, v17, v3 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v18, v4, s0 ; GFX11-NEXT: global_load_b64 v[5:6], v[5:6], off offset:-2048
; GFX11-NEXT: global_load_b64 v[17:18], v[3:4], off offset:-4096
; GFX11-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, v10, v22, vcc_lo
; GFX11-NEXT: global_load_b64 v[9:10], v[3:4], off offset:-2048
; GFX11-NEXT: s_waitcnt vmcnt(7)
; GFX11-NEXT: v_add_co_u32 v21, vcc_lo, v7, v21
; GFX11-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, v8, v22, vcc_lo
; GFX11-NEXT: global_load_b64 v[7:8], v[3:4], off
; GFX11-NEXT: s_waitcnt vmcnt(7)
; GFX11-NEXT: v_add_co_u32 v11, s0, v11, v21
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_add_co_ci_u32_e64 v12, s0, v12, v22, s0
; GFX11-NEXT: v_add_co_u32 v3, vcc_lo, 0x10000, v3
; GFX11-NEXT: s_waitcnt vmcnt(6)
; GFX11-NEXT: v_add_co_u32 v11, s0, v19, v11
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_add_co_ci_u32_e64 v12, s0, v20, v12, s0
; GFX11-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
; GFX11-NEXT: s_waitcnt vmcnt(4) ; GFX11-NEXT: s_waitcnt vmcnt(4)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v11, s0, v15, v11
; GFX11-NEXT: v_add_co_u32 v3, s0, v15, v3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v16, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v12, s0, v16, v12, s0
; GFX11-NEXT: v_add_co_u32 v11, s0, v13, v11
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e64 v12, s0, v14, v12, s0
; GFX11-NEXT: s_waitcnt vmcnt(3) ; GFX11-NEXT: s_waitcnt vmcnt(3)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v5, s0, v5, v11
; GFX11-NEXT: v_add_co_u32 v3, s0, v21, v3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v22, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s0, v6, v12, s0
; GFX11-NEXT: s_waitcnt vmcnt(2) ; GFX11-NEXT: s_waitcnt vmcnt(2)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v5, s0, v17, v5
; GFX11-NEXT: v_add_co_u32 v3, s0, v23, v3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v24, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s0, v18, v6, s0
; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v5, s0, v9, v5
; GFX11-NEXT: v_add_co_u32 v3, s0, v25, v3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v26, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s0, v10, v6, s0
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_co_u32 v5, vcc_lo, v7, v5
; GFX11-NEXT: v_add_co_u32 v3, vcc_lo, v27, v3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v28, v4, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v8, v6, vcc_lo
; GFX11-NEXT: s_cbranch_scc0 .LBB1_2 ; GFX11-NEXT: s_cbranch_scc0 .LBB1_2
; GFX11-NEXT: ; %bb.3: ; %while.cond.loopexit ; GFX11-NEXT: ; %bb.3: ; %while.cond.loopexit
; GFX11-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; GFX11-NEXT: ; in Loop: Header=BB1_1 Depth=1
; GFX11-NEXT: s_add_i32 s0, s1, -1 ; GFX11-NEXT: s_add_i32 s0, s1, -1
; GFX11-NEXT: s_cmp_eq_u32 s1, 0 ; GFX11-NEXT: s_cmp_eq_u32 s1, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB1_5 ; GFX11-NEXT: s_cbranch_scc1 .LBB1_5
; GFX11-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1 ; GFX11-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1
; GFX11-NEXT: s_mov_b32 s1, s0 ; GFX11-NEXT: s_mov_b32 s1, s0
; GFX11-NEXT: s_branch .LBB1_1 ; GFX11-NEXT: s_branch .LBB1_1
; GFX11-NEXT: .LBB1_5: ; %while.end ; GFX11-NEXT: .LBB1_5: ; %while.end
; GFX11-NEXT: v_add_co_u32 v0, s0, s34, v0 ; GFX11-NEXT: v_add_co_u32 v0, s0, s34, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s35, 0, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s35, 0, s0
; GFX11-NEXT: global_store_b64 v[0:1], v[3:4], off ; GFX11-NEXT: global_store_b64 v[0:1], v[5:6], off
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
entry: entry:
%call = tail call i64 @_Z13get_global_idj(i32 0) %call = tail call i64 @_Z13get_global_idj(i32 0)
%conv = and i64 %call, 255 %conv = and i64 %call, 255
%a0 = shl i64 %call, 17 %a0 = shl i64 %call, 17
%idx.ext11 = and i64 %a0, 4261412864 %idx.ext11 = and i64 %a0, 4261412864
%add.ptr12 = getelementptr inbounds i8, ptr addrspace(1) %buffer, i64 %idx.ext11 %add.ptr12 = getelementptr inbounds i8, ptr addrspace(1) %buffer, i64 %idx.ext11
▲ Show 20 Lines • Show All 260 Lines • ▼ Show 20 Lines
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2 ; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x800, v0 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x800, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v0, 0x1000 ; GFX10-NEXT: global_load_dword v6, v[4:5], off offset:1024
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x1000
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, 0x1000, v0
; GFX10-NEXT: s_clause 0x4
; GFX10-NEXT: global_load_dword v10, v[0:1], off
; GFX10-NEXT: global_load_dword v11, v[0:1], off offset:1024
; GFX10-NEXT: global_load_dword v12, v[4:5], off offset:1024
; GFX10-NEXT: global_load_dword v13, v[6:7], off offset:-2048
; GFX10-NEXT: global_load_dword v14, v[6:7], off
; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x1800, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v0, 0x2000
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dword v15, v[8:9], off offset:1024 ; GFX10-NEXT: global_load_dword v7, v[4:5], off offset:-2048
; GFX10-NEXT: global_load_dword v16, v[4:5], off offset:1024 ; GFX10-NEXT: global_load_dword v8, v[4:5], off
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x1000, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: global_load_dword v9, v[4:5], off offset:1024
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x1800, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: global_load_dword v10, v[4:5], off offset:1024
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x2000, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: global_load_dword v4, v[6:7], off offset:-2048 ; GFX10-NEXT: global_load_dword v11, v[4:5], off offset:1024
; GFX10-NEXT: global_load_dword v5, v[6:7], off ; GFX10-NEXT: global_load_dword v12, v[0:1], off
; GFX10-NEXT: global_load_dword v8, v[0:1], off offset:1024 ; GFX10-NEXT: global_load_dword v13, v[0:1], off offset:1024
; GFX10-NEXT: s_waitcnt vmcnt(8) ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0x2000
; GFX10-NEXT: v_add_nc_u32_e32 v0, v11, v10 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(6) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add3_u32 v0, v13, v0, v12 ; GFX10-NEXT: v_add_nc_u32_e32 v4, v13, v12
; GFX10-NEXT: s_waitcnt vmcnt(4) ; GFX10-NEXT: v_add3_u32 v4, v7, v4, v6
; GFX10-NEXT: v_add3_u32 v0, v14, v0, v15 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: global_load_dword v5, v[0:1], off offset:-2048
; GFX10-NEXT: v_add3_u32 v0, v4, v0, v16 ; GFX10-NEXT: global_load_dword v6, v[0:1], off
; GFX10-NEXT: v_add3_u32 v4, v8, v4, v9
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_add3_u32 v0, v5, v4, v10
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add3_u32 v0, v5, v0, v8 ; GFX10-NEXT: v_add3_u32 v0, v6, v0, v11
; GFX10-NEXT: global_store_dword v[2:3], v0, off ; GFX10-NEXT: global_store_dword v[2:3], v0, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX90A-LABEL: Address32: ; GFX90A-LABEL: Address32:
; GFX90A: ; %bb.0: ; %entry ; GFX90A: ; %bb.0: ; %entry
; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 ; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 ; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GFX90A-NEXT: s_mov_b32 s38, -1 ; GFX90A-NEXT: s_mov_b32 s38, -1
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; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1]
; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2 ; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0xfffff800 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0xfffff800
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, 0, v0
; GFX10-NEXT: global_load_dwordx2 v[6:7], v[0:1], off ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 1, v1, vcc_lo
; GFX10-NEXT: global_load_dwordx2 v[8:9], v[4:5], off offset:-2048 ; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 ; GFX10-NEXT: global_load_dwordx2 v[8:9], v[0:1], off
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 1, v1, vcc_lo ; GFX10-NEXT: global_load_dwordx2 v[10:11], v[4:5], off offset:-2048
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx2 v[12:13], v[4:5], off
; GFX10-NEXT: global_load_dwordx2 v[10:11], v[4:5], off ; GFX10-NEXT: global_load_dwordx2 v[14:15], v[6:7], off
; GFX10-NEXT: global_load_dwordx2 v[12:13], v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v8, v6 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v10, v8
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v9, v7, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v9, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v10, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v12, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v12, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v14, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v15, v1, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX90A-LABEL: Offset64: ; GFX90A-LABEL: Offset64:
; GFX90A: ; %bb.0: ; %entry ; GFX90A: ; %bb.0: ; %entry
; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 ; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 ; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GFX90A-NEXT: s_mov_b32 s38, -1 ; GFX90A-NEXT: s_mov_b32 s38, -1
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; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v2
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2 ; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x80000000 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0x80000000
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: global_load_dword v6, v[0:1], off ; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, 0x7ffff800, v0
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ffff800, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: global_load_dword v8, v[0:1], off
; GFX10-NEXT: global_load_dword v7, v[4:5], off offset:-2048 ; GFX10-NEXT: global_load_dword v9, v[4:5], off offset:-2048
; GFX10-NEXT: global_load_dword v8, v[4:5], off ; GFX10-NEXT: global_load_dword v10, v[4:5], off
; GFX10-NEXT: global_load_dword v9, v[0:1], off offset:1024 ; GFX10-NEXT: global_load_dword v11, v[6:7], off offset:1024
; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: v_add_nc_u32_e32 v0, v7, v6 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v9, v8
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add3_u32 v0, v9, v0, v8 ; GFX10-NEXT: v_add3_u32 v0, v11, v0, v10
; GFX10-NEXT: global_store_dword v[2:3], v0, off ; GFX10-NEXT: global_store_dword v[2:3], v0, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX90A-LABEL: p32Offset64: ; GFX90A-LABEL: p32Offset64:
; GFX90A: ; %bb.0: ; %entry ; GFX90A: ; %bb.0: ; %entry
; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 ; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 ; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GFX90A-NEXT: s_mov_b32 s38, -1 ; GFX90A-NEXT: s_mov_b32 s38, -1
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; GFX10-NEXT: s_load_dwordx4 s[36:39], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[36:39], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_mov_b64 s[0:1], s[40:41] ; GFX10-NEXT: s_mov_b64 s[0:1], s[40:41]
; GFX10-NEXT: s_mov_b64 s[2:3], s[42:43] ; GFX10-NEXT: s_mov_b64 s[2:3], s[42:43]
; GFX10-NEXT: s_mov_b32 s32, 0 ; GFX10-NEXT: s_mov_b32 s32, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 7, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 7, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff8000, v0 ; GFX10-NEXT: v_and_b32_e32 v8, 0xffff8000, v0
; GFX10-NEXT: v_add_co_u32 v0, s0, s36, v2 ; GFX10-NEXT: v_add_co_u32 v0, s0, s36, v8
; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s37, 0, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s37, 0, s0
; GFX10-NEXT: v_add_co_u32 v14, s0, s38, v2 ; GFX10-NEXT: v_add_co_u32 v8, s0, s38, v8
; GFX10-NEXT: v_add_co_ci_u32_e64 v15, s0, s39, 0, s0
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, 0x1800 ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, 0x1800
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v14, 0x3000 ; GFX10-NEXT: v_add_co_ci_u32_e64 v11, s0, s39, 0, s0
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v15, vcc_lo ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx2 v[4:5], v[2:3], off offset:-2048
; GFX10-NEXT: global_load_dwordx2 v[6:7], v[2:3], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_co_u32 v9, vcc_lo, v6, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, v7, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v8, 0x3000
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v11, vcc_lo
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx2 v[6:7], v[2:3], off offset:-2048 ; GFX10-NEXT: global_load_dwordx2 v[4:5], v[2:3], off offset:-2048
; GFX10-NEXT: global_load_dwordx2 v[8:9], v[2:3], off ; GFX10-NEXT: global_load_dwordx2 v[6:7], v[2:3], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v6, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v7, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x2000, v0 ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x2000, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx2 v[2:3], v[2:3], off
; GFX10-NEXT: global_load_dwordx2 v[10:11], v[4:5], off offset:-2048 ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dwordx2 v[12:13], v[4:5], off ; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v2, v9
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x3800, v14 ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v3, v10, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v15, vcc_lo ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x3800, v8
; GFX10-NEXT: global_load_dwordx2 v[14:15], v[2:3], off ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v11, vcc_lo
; GFX10-NEXT: global_load_dwordx2 v[16:17], v[4:5], off ; GFX10-NEXT: global_load_dwordx2 v[2:3], v[2:3], off
; GFX10-NEXT: s_waitcnt vmcnt(4)
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v8, v6
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v9, v7, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v12, v10
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v13, v11, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v14, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v15, v3, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v16, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v17, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v6, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; GFX10-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: DiffBase: ; GFX11-LABEL: DiffBase:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, _Z13get_global_idj@gotpcrel32@lo+4 ; GFX11-NEXT: s_add_u32 s2, s2, _Z13get_global_idj@gotpcrel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, _Z13get_global_idj@gotpcrel32@hi+12 ; GFX11-NEXT: s_addc_u32 s3, s3, _Z13get_global_idj@gotpcrel32@hi+12
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; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2 ; GFX10-NEXT: v_add_co_u32 v2, s0, s34, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, s35, 0, s0
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x3800, v0 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x3800, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, 0x3000, v0 ; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, 0x3000, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, 0x2800, v0
; GFX10-NEXT: global_load_dwordx2 v[8:9], v[0:1], off ; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: global_load_dwordx2 v[10:11], v[4:5], off ; GFX10-NEXT: global_load_dwordx2 v[10:11], v[4:5], off
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x2800, v0 ; GFX10-NEXT: global_load_dwordx2 v[12:13], v[6:7], off
; GFX10-NEXT: global_load_dwordx2 v[14:15], v[8:9], off
; GFX10-NEXT: global_load_dwordx2 v[16:17], v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v10, v16
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v11, v17, vcc_lo
; GFX10-NEXT: v_add_co_u32 v10, vcc_lo, v12, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v13, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x2000, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v12, vcc_lo, 0x2000, v0 ; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, 0x1800, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v14, vcc_lo, 0x1800, v0 ; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, 0x1000, v0
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: global_load_dwordx2 v[6:7], v[6:7], off
; GFX10-NEXT: global_load_dwordx2 v[12:13], v[12:13], off
; GFX10-NEXT: v_add_co_ci_u32_e32 v15, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v16, vcc_lo, 0x1000, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx2 v[14:15], v[14:15], off
; GFX10-NEXT: global_load_dwordx2 v[4:5], v[4:5], off
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: v_add_co_u32 v18, vcc_lo, v14, v10
; GFX10-NEXT: global_load_dwordx2 v[18:19], v[16:17], off ; GFX10-NEXT: v_add_co_ci_u32_e32 v19, vcc_lo, v15, v11, vcc_lo
; GFX10-NEXT: global_load_dwordx2 v[20:21], v[0:1], off ; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: s_waitcnt vmcnt(6) ; GFX10-NEXT: global_load_dwordx2 v[10:11], v[4:5], off
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v10, v8 ; GFX10-NEXT: global_load_dwordx2 v[12:13], v[6:7], off
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v9, vcc_lo ; GFX10-NEXT: global_load_dwordx2 v[14:15], v[8:9], off
; GFX10-NEXT: s_waitcnt vmcnt(5) ; GFX10-NEXT: global_load_dwordx2 v[16:17], v[0:1], off
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v6, v0 ; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v10, v18
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v19, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v12, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v12, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v14, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v14, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v15, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v15, v1, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v18, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v19, v1, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v20, v0 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v16, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v21, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v17, v1, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX90A-LABEL: ReverseOrder: ; GFX90A-LABEL: ReverseOrder:
; GFX90A: ; %bb.0: ; %entry ; GFX90A: ; %bb.0: ; %entry
; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 ; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 ; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GFX90A-NEXT: s_mov_b32 s38, -1 ; GFX90A-NEXT: s_mov_b32 s38, -1
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llvm/test/CodeGen/AMDGPU/saddo.ll

Show First 20 Lines • Show All 666 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: global_store_dwordx2 v6, v[4:5], s[0:1] ; GFX9-NEXT: global_store_dwordx2 v6, v[4:5], s[0:1]
; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[2:3] ; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_saddo_v2i32: ; GFX10-LABEL: v_saddo_v2i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v5, 0 ; GFX10-NEXT: v_mov_b32_e32 v6, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx2 v[0:1], v5, s[4:5] ; GFX10-NEXT: global_load_dwordx2 v[0:1], v6, s[4:5]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v5, s[6:7] ; GFX10-NEXT: global_load_dwordx2 v[2:3], v6, s[6:7]
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_nc_u32_e32 v4, v1, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v1, v3
; GFX10-NEXT: v_add_nc_i32 v1, v1, v3 clamp ; GFX10-NEXT: v_add_nc_u32_e32 v4, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v3, v0, v2
; GFX10-NEXT: v_add_nc_i32 v0, v0, v2 clamp ; GFX10-NEXT: v_add_nc_i32 v0, v0, v2 clamp
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, v4, v1 ; GFX10-NEXT: v_add_nc_i32 v1, v1, v3 clamp
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX10-NEXT: global_store_dwordx2 v6, v[4:5], s[0:1]
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, v4, v0
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, v5, v1
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v5, v[3:4], s[0:1] ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: global_store_dwordx2 v5, v[0:1], s[2:3] ; GFX10-NEXT: global_store_dwordx2 v6, v[0:1], s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_saddo_v2i32: ; GFX11-LABEL: v_saddo_v2i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 ; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24
; GFX11-NEXT: v_mov_b32_e32 v5, 0 ; GFX11-NEXT: v_mov_b32_e32 v5, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
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llvm/test/CodeGen/AMDGPU/saddsat.ll

Show First 20 Lines • Show All 451 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_saddsat_i64: ; GFX10-LABEL: v_saddsat_i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[2:3] ; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[4:5], v[0:1]
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1] ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX10-NEXT: v_xor_b32_e32 v1, 0x80000000, v6 ; GFX10-NEXT: v_xor_b32_e32 v1, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_saddsat_i64: ; GFX11-LABEL: v_saddsat_i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2 ; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
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llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit3.ll

; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=MISCHED %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=MISCHED %s
; RUN: llc -march=amdgcn -mcpu=tonga -misched=gcn-iterative-ilp -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-ILP %s ; RUN: llc -march=amdgcn -mcpu=tonga -misched=gcn-iterative-ilp -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-ILP %s
; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-ILP %s
; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-ILP %s
; Test the scheduler when only one wave is requested. The result should be high register usage and max ILP. ; Test the scheduler when only one wave is requested. The result should be high register usage and max ILP.
; We expect a three digit VGPR usage here since only one wave requested. ; We expect a three digit VGPR usage here since only one wave requested.
; ;
; GCN-ILP: NumVgprs: {{[0-9][0-9][0-9]$}} ; GCN-ILP: NumVgprs: {{[0-9][0-9][0-9]$}}
; FIXME: The machine scheduler is doing a poor job at maximizing ILP here. ; FIXME: The machine scheduler is doing a poor job at maximizing ILP here.
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store float %tmp448, ptr addrspace(1) %tmp511, align 4 store float %tmp448, ptr addrspace(1) %tmp511, align 4
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare float @llvm.fmuladd.f32(float, float, float) #0 declare float @llvm.fmuladd.f32(float, float, float) #0
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="1,256" } attributes #1 = { "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="1,128" }

llvm/test/CodeGen/AMDGPU/scratch-simple.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; GFX10-FLATSCR: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0 ; GFX10-FLATSCR: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0
; GFX10-FLATSCR-PAL: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0 ; GFX10-FLATSCR-PAL: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0
; GFX11-FLATSCR: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0 ; GFX11-FLATSCR: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0
; MUBUF-DAG: v_add{{_|_nc_}}{{i|u}}32_e32 [[HI_OFF:v[0-9]+]],{{.*}} 0x280, [[CLAMP_IDX]] ; MUBUF-DAG: v_add{{_|_nc_}}{{i|u}}32_e32 [[HI_OFF:v[0-9]+]],{{.*}} 0x280, [[CLAMP_IDX]]
; MUBUF-DAG: v_add{{_|_nc_}}{{i|u}}32_e32 [[LO_OFF:v[0-9]+]],{{.*}} {{v2|0x80}}, [[CLAMP_IDX]] ; MUBUF-DAG: v_add{{_|_nc_}}{{i|u}}32_e32 [[LO_OFF:v[0-9]+]],{{.*}} {{v2|0x80}}, [[CLAMP_IDX]]
; FLATSCR: v_add{{_|_nc_}}{{u32|b32}}_e32 [[LO_OFF:v[0-9]+]],{{.*}} {{v2|0x80}}, [[CLAMP_IDX]] ; FLATSCR: v_add{{_|_nc_}}{{u32|b32}}_e32 [[LO_OFF:v[0-9]+]],{{.*}} {{v2|0x80}}, [[CLAMP_IDX]]
; MUBUF: buffer_load_dword {{v[0-9]+}}, [[LO_OFF]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen ; MUBUF-DAG: buffer_load_dword {{v[0-9]+}}, [[LO_OFF]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen
; MUBUF: buffer_load_dword {{v[0-9]+}}, [[HI_OFF]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen ; MUBUF-DAG: buffer_load_dword {{v[0-9]+}}, [[HI_OFF]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen
; FLATSCR: scratch_load_dword {{v[0-9]+}}, [[LO_OFF]], off ; FLATSCR: scratch_load_dword {{v[0-9]+}}, [[LO_OFF]], off
; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, [[CLAMP_IDX]], off offset:128 ; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, [[CLAMP_IDX]], off offset:128
define amdgpu_ps float @ps_main(i32 %idx) { define amdgpu_ps float @ps_main(i32 %idx) {
%v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx %v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
%v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx %v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
%r = fadd float %v1, %v2 %r = fadd float %v1, %v2
ret float %r ret float %r
} }
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llvm/test/CodeGen/AMDGPU/smrd.ll

Show First 20 Lines • Show All 437 Lines • ▼ Show 20 Linesmain_body:
%res.tmp = fadd float %a, %b %res.tmp = fadd float %a, %b
%res = fadd float %res.tmp, %c %res = fadd float %res.tmp, %c
ret float %res ret float %res
} }
; GCN-LABEL: {{^}}smrd_vgpr_merged: ; GCN-LABEL: {{^}}smrd_vgpr_merged:
; GCN-NEXT: %bb. ; GCN-NEXT: %bb.
; GFX10-NEXT: s_clause ; GFX10-NEXT: s_clause
; GCN-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 ; GCN-DAG: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
; GCN-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 ; GCN-DAG: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28
define amdgpu_ps void @smrd_vgpr_merged(<4 x i32> inreg %desc, i32 %a) #0 { define amdgpu_ps void @smrd_vgpr_merged(<4 x i32> inreg %desc, i32 %a) #0 {
main_body: main_body:
%a1 = add i32 %a, 4 %a1 = add i32 %a, 4
%a2 = add i32 %a, 8 %a2 = add i32 %a, 8
%a3 = add i32 %a, 12 %a3 = add i32 %a, 12
%a4 = add i32 %a, 16 %a4 = add i32 %a, 16
%a5 = add i32 %a, 28 %a5 = add i32 %a, 28
%a6 = add i32 %a, 32 %a6 = add i32 %a, 32
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llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll

Show All 24 Linesdefine amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x i32> inreg %userData) {
; CHECK-NEXT: undef %50.sub0:sgpr_64 = COPY $sgpr19 ; CHECK-NEXT: undef %50.sub0:sgpr_64 = COPY $sgpr19
; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_32 = COPY $sgpr20 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_32 = COPY $sgpr20
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_32 = COPY $sgpr21 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_32 = COPY $sgpr21
; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_32 = COPY $sgpr22 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_32 = COPY $sgpr22
; CHECK-NEXT: [[COPY9:%[0-9]+]]:sgpr_32 = COPY $sgpr23 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:sgpr_32 = COPY $sgpr23
; CHECK-NEXT: [[COPY10:%[0-9]+]]:sgpr_32 = COPY $sgpr9 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:sgpr_32 = COPY $sgpr9
; CHECK-NEXT: [[COPY11:%[0-9]+]]:sgpr_32 = COPY $sgpr10 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:sgpr_32 = COPY $sgpr10
; CHECK-NEXT: [[COPY12:%[0-9]+]]:sgpr_32 = COPY $sgpr8 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:sgpr_32 = COPY $sgpr8
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM undef %74:sreg_64, 0, 0 :: (invariant load (s128) from `ptr addrspace(4) undef`, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], undef %89:sgpr_128, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[S_LOAD_DWORDX4_IMM]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: KILL undef %89:sgpr_128
; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM]]
; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -1, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -2, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_ADD_U32_e64_1]], [[V_ADD_U32_e64_]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -3, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_1:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_]], [[V_ADD_U32_e64_2]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -4, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_2:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_1]], [[V_ADD_U32_e64_3]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 27, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_3:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_2]], [[V_SUBREV_U32_e64_]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET undef %118:sgpr_128, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_SUBREV_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 28, [[BUFFER_LOAD_DWORD_OFFSET1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_4:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_3]], [[V_SUBREV_U32_e64_1]], implicit $exec
; CHECK-NEXT: undef %71.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %56, 232, 0 :: (invariant load (s64) from %ir.39, addrspace 4) ; CHECK-NEXT: undef %71.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %56, 232, 0 :: (invariant load (s64) from %ir.39, addrspace 4)
; CHECK-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY4]], 4, implicit-def dead $scc ; CHECK-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY4]], 4, implicit-def dead $scc
; CHECK-NEXT: [[S_LSHL_B32_1:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY3]], 4, implicit-def dead $scc ; CHECK-NEXT: [[S_LSHL_B32_1:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY3]], 4, implicit-def dead $scc
; CHECK-NEXT: [[S_LSHL_B32_2:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY2]], 4, implicit-def dead $scc ; CHECK-NEXT: [[S_LSHL_B32_2:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY2]], 4, implicit-def dead $scc
; CHECK-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_]], 31, implicit-def dead $scc ; CHECK-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_]], 31, implicit-def dead $scc
; CHECK-NEXT: [[S_ASHR_I32_1:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_1]], 31, implicit-def dead $scc ; CHECK-NEXT: [[S_ASHR_I32_1:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_1]], 31, implicit-def dead $scc
; CHECK-NEXT: [[S_ASHR_I32_2:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_2]], 31, implicit-def dead $scc ; CHECK-NEXT: [[S_ASHR_I32_2:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_2]], 31, implicit-def dead $scc
; CHECK-NEXT: %71.sub1:sgpr_128 = S_AND_B32 %71.sub1, 65535, implicit-def dead $scc ; CHECK-NEXT: %71.sub1:sgpr_128 = S_AND_B32 %71.sub1, 65535, implicit-def dead $scc
; CHECK-NEXT: undef %130.sub0:sreg_64 = S_ADD_U32 [[COPY5]], [[S_LSHL_B32_2]], implicit-def $scc ; CHECK-NEXT: undef %130.sub0:sreg_64 = S_ADD_U32 [[COPY5]], [[S_LSHL_B32_2]], implicit-def $scc
; CHECK-NEXT: %130.sub1:sreg_64 = S_ADDC_U32 undef %54:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %130.sub1:sreg_64 = S_ADDC_U32 undef %54:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %130, 16, 0 :: (invariant load (s128) from %ir.81, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM1:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %130, 16, 0 :: (invariant load (s128) from %ir.81, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM1:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM undef %74:sreg_64, 0, 0 :: (invariant load (s128) from `ptr addrspace(4) undef`, addrspace 4)
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %132:sgpr_128, 0, 0 :: (dereferenceable invariant load (s32)) ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %132:sgpr_128, 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: KILL undef %74:sreg_64
; CHECK-NEXT: KILL undef %132:sgpr_128 ; CHECK-NEXT: KILL undef %132:sgpr_128
; CHECK-NEXT: KILL %130.sub0, %130.sub1 ; CHECK-NEXT: KILL %130.sub0, %130.sub1
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_LOAD_DWORDX4_IMM]], 0, 0 :: (dereferenceable invariant load (s32)) ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_LOAD_DWORDX4_IMM1]], 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: undef %302.sub1:sgpr_128 = S_MOV_B32 0
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], undef %89:sgpr_128, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM1]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: KILL undef %89:sgpr_128
; CHECK-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[S_BUFFER_LOAD_DWORD_IMM]], 29, implicit-def dead $scc ; CHECK-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[S_BUFFER_LOAD_DWORD_IMM]], 29, implicit-def dead $scc
; CHECK-NEXT: [[S_SUB_I32_1:%[0-9]+]]:sreg_32 = S_SUB_I32 [[S_BUFFER_LOAD_DWORD_IMM]], 30, implicit-def dead $scc ; CHECK-NEXT: [[S_SUB_I32_1:%[0-9]+]]:sreg_32 = S_SUB_I32 [[S_BUFFER_LOAD_DWORD_IMM]], 30, implicit-def dead $scc
; CHECK-NEXT: [[S_SUB_I32_2:%[0-9]+]]:sreg_32 = S_SUB_I32 [[S_BUFFER_LOAD_DWORD_IMM1]], 31, implicit-def dead $scc ; CHECK-NEXT: [[S_SUB_I32_2:%[0-9]+]]:sreg_32 = S_SUB_I32 [[S_BUFFER_LOAD_DWORD_IMM1]], 31, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY5]], 64, implicit-def $scc ; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY5]], 64, implicit-def $scc
; CHECK-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %54:sreg_32, 0, implicit-def dead $scc, implicit $scc ; CHECK-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %54:sreg_32, 0, implicit-def dead $scc, implicit $scc
; CHECK-NEXT: undef %149.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_]], [[S_LSHL_B32_]], implicit-def $scc ; CHECK-NEXT: undef %149.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_]], [[S_LSHL_B32_]], implicit-def $scc
; CHECK-NEXT: %149.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_]], [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %149.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_]], [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: undef %156.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_]], [[S_LSHL_B32_1]], implicit-def $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM2:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %149, 0, 0 :: (invariant load (s128) from %ir.87, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM2:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %149, 0, 0 :: (invariant load (s128) from %ir.87, addrspace 4)
; CHECK-NEXT: [[V_OR_B32_e64_5:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_SUB_I32_]], [[V_OR_B32_e64_4]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_6:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_SUB_I32_1]], [[V_OR_B32_e64_5]], implicit $exec
; CHECK-NEXT: undef %156.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_]], [[S_LSHL_B32_1]], implicit-def $scc
; CHECK-NEXT: %156.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_]], [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %156.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_]], [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM3:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %156, 0, 0 :: (invariant load (s128) from %ir.92, addrspace 4)
; CHECK-NEXT: [[V_OR_B32_e64_7:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_SUB_I32_2]], [[V_OR_B32_e64_6]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN2:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM2]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_SUBREV_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 32, [[BUFFER_LOAD_FORMAT_X_IDXEN2]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_8:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_7]], [[V_SUBREV_U32_e64_2]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN3:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM3]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_SUBREV_U32_e64_3:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 33, [[BUFFER_LOAD_FORMAT_X_IDXEN3]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_9:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_8]], [[V_SUBREV_U32_e64_3]], implicit $exec
; CHECK-NEXT: undef %163.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_]], [[S_LSHL_B32_2]], implicit-def $scc ; CHECK-NEXT: undef %163.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_]], [[S_LSHL_B32_2]], implicit-def $scc
; CHECK-NEXT: %163.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_]], [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %163.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_]], [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM4:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %163, 0, 0 :: (invariant load (s128) from %ir.97, addrspace 4)
; CHECK-NEXT: [[S_ASHR_I32_3:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 undef %171:sreg_32, 31, implicit-def dead $scc ; CHECK-NEXT: [[S_ASHR_I32_3:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 undef %171:sreg_32, 31, implicit-def dead $scc
; CHECK-NEXT: undef %176.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_]], undef %171:sreg_32, implicit-def $scc ; CHECK-NEXT: undef %176.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_]], undef %171:sreg_32, implicit-def $scc
; CHECK-NEXT: %176.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_]], [[S_ASHR_I32_3]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %176.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_]], [[S_ASHR_I32_3]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM5:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %176, 0, 0 :: (invariant load (s128) from %ir.104, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN4:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM4]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_SUBREV_U32_e64_4:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 34, [[BUFFER_LOAD_FORMAT_X_IDXEN4]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_10:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_9]], [[V_SUBREV_U32_e64_4]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN5:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM5]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_SUBREV_U32_e64_5:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 36, [[BUFFER_LOAD_FORMAT_X_IDXEN5]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_11:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_10]], [[V_SUBREV_U32_e64_5]], implicit $exec
; CHECK-NEXT: undef %183.sub0:sreg_64 = S_ADD_U32 %50.sub0, [[S_LSHL_B32_]], implicit-def $scc ; CHECK-NEXT: undef %183.sub0:sreg_64 = S_ADD_U32 %50.sub0, [[S_LSHL_B32_]], implicit-def $scc
; CHECK-NEXT: %183.sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %183.sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM6:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %183, 0, 0 :: (invariant load (s128) from %ir.109, addrspace 4)
; CHECK-NEXT: undef %190.sub0:sreg_64 = S_ADD_U32 %50.sub0, [[S_LSHL_B32_1]], implicit-def $scc ; CHECK-NEXT: undef %190.sub0:sreg_64 = S_ADD_U32 %50.sub0, [[S_LSHL_B32_1]], implicit-def $scc
; CHECK-NEXT: %190.sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %190.sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM7:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %190, 0, 0 :: (invariant load (s128) from %ir.114, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN6:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM6]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_SUBREV_U32_e64_6:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 37, [[BUFFER_LOAD_FORMAT_X_IDXEN6]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_12:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_11]], [[V_SUBREV_U32_e64_6]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN7:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM7]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_SUBREV_U32_e64_7:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 38, [[BUFFER_LOAD_FORMAT_X_IDXEN7]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_13:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_12]], [[V_SUBREV_U32_e64_7]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_8:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 39, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_14:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_13]], [[V_SUBREV_U32_e64_8]], implicit $exec
; CHECK-NEXT: undef %200.sub0:sreg_64 = S_ADD_U32 %50.sub0, undef %171:sreg_32, implicit-def $scc ; CHECK-NEXT: undef %200.sub0:sreg_64 = S_ADD_U32 %50.sub0, undef %171:sreg_32, implicit-def $scc
; CHECK-NEXT: %200.sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_3]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %200.sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_3]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM8:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %200, 0, 0 :: (invariant load (s128) from %ir.121, addrspace 4)
; CHECK-NEXT: [[S_ADD_U32_1:%[0-9]+]]:sreg_32 = S_ADD_U32 %50.sub0, 224, implicit-def $scc ; CHECK-NEXT: [[S_ADD_U32_1:%[0-9]+]]:sreg_32 = S_ADD_U32 %50.sub0, 224, implicit-def $scc
; CHECK-NEXT: [[S_ADDC_U32_1:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %51:sreg_32, 0, implicit-def dead $scc, implicit $scc ; CHECK-NEXT: [[S_ADDC_U32_1:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %51:sreg_32, 0, implicit-def dead $scc, implicit $scc
; CHECK-NEXT: undef %210.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_1]], [[S_LSHL_B32_]], implicit-def $scc ; CHECK-NEXT: undef %210.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_1]], [[S_LSHL_B32_]], implicit-def $scc
; CHECK-NEXT: %210.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_1]], [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %210.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_1]], [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM9:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %210, 0, 0 :: (invariant load (s128) from %ir.127, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN8:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM8]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_SUBREV_U32_e64_9:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 50, [[BUFFER_LOAD_FORMAT_X_IDXEN8]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_15:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_14]], [[V_SUBREV_U32_e64_9]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN9:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM9]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_SUBREV_U32_e64_10:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 51, [[BUFFER_LOAD_FORMAT_X_IDXEN9]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_16:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_15]], [[V_SUBREV_U32_e64_10]], implicit $exec
; CHECK-NEXT: undef %217.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_1]], [[S_LSHL_B32_1]], implicit-def $scc ; CHECK-NEXT: undef %217.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_1]], [[S_LSHL_B32_1]], implicit-def $scc
; CHECK-NEXT: %217.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_1]], [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %217.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_1]], [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM10:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %217, 0, 0 :: (invariant load (s128) from %ir.132, addrspace 4)
; CHECK-NEXT: undef %224.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_1]], [[S_LSHL_B32_2]], implicit-def $scc ; CHECK-NEXT: undef %224.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_1]], [[S_LSHL_B32_2]], implicit-def $scc
; CHECK-NEXT: %224.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_1]], [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %224.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_1]], [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM11:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %224, 0, 0 :: (invariant load (s128) from %ir.137, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN10:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM10]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_SUBREV_U32_e64_11:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 52, [[BUFFER_LOAD_FORMAT_X_IDXEN10]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_17:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_16]], [[V_SUBREV_U32_e64_11]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN11:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM11]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_SUBREV_U32_e64_12:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 53, [[BUFFER_LOAD_FORMAT_X_IDXEN11]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_18:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_17]], [[V_SUBREV_U32_e64_12]], implicit $exec
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM12:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %50, 224, 0 :: (invariant load (s128) from %ir.126, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN12:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM12]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_ADD_U32_e64_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -72, [[BUFFER_LOAD_FORMAT_X_IDXEN12]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_19:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_18]], [[V_ADD_U32_e64_4]], implicit $exec
; CHECK-NEXT: [[S_ADD_U32_2:%[0-9]+]]:sreg_32 = S_ADD_U32 %50.sub0, 576, implicit-def $scc ; CHECK-NEXT: [[S_ADD_U32_2:%[0-9]+]]:sreg_32 = S_ADD_U32 %50.sub0, 576, implicit-def $scc
; CHECK-NEXT: [[S_ADDC_U32_2:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %51:sreg_32, 0, implicit-def dead $scc, implicit $scc ; CHECK-NEXT: [[S_ADDC_U32_2:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %51:sreg_32, 0, implicit-def dead $scc, implicit $scc
; CHECK-NEXT: undef %241.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_2]], [[S_LSHL_B32_]], implicit-def $scc ; CHECK-NEXT: undef %241.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_2]], [[S_LSHL_B32_]], implicit-def $scc
; CHECK-NEXT: %241.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_2]], [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %241.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_2]], [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM13:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %241, 0, 0 :: (invariant load (s128) from %ir.147, addrspace 4)
; CHECK-NEXT: undef %253.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_2]], [[S_LSHL_B32_2]], implicit-def $scc ; CHECK-NEXT: undef %253.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_2]], [[S_LSHL_B32_2]], implicit-def $scc
; CHECK-NEXT: %253.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_2]], [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %253.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_2]], [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM14:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %253, 0, 0 :: (invariant load (s128) from %ir.154, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN13:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM13]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_ADD_U32_e64_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -73, [[BUFFER_LOAD_FORMAT_X_IDXEN13]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_20:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_19]], [[V_ADD_U32_e64_5]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_6:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -74, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_21:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_20]], [[V_ADD_U32_e64_6]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN14:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM14]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_ADD_U32_e64_7:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -75, [[BUFFER_LOAD_FORMAT_X_IDXEN14]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_22:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_21]], [[V_ADD_U32_e64_7]], implicit $exec
; CHECK-NEXT: undef %261.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_2]], undef %171:sreg_32, implicit-def $scc ; CHECK-NEXT: undef %261.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_2]], undef %171:sreg_32, implicit-def $scc
; CHECK-NEXT: %261.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_2]], [[S_ASHR_I32_3]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %261.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_2]], [[S_ASHR_I32_3]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM15:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %261, 0, 0 :: (invariant load (s128) from %ir.159, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN15:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM15]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_ADD_U32_e64_8:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -77, [[BUFFER_LOAD_FORMAT_X_IDXEN15]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_23:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_22]], [[V_ADD_U32_e64_8]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_9:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -93, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_24:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_23]], [[V_ADD_U32_e64_9]], implicit $exec
; CHECK-NEXT: undef %273.sub0:sreg_64 = S_ADD_U32 [[COPY6]], [[S_LSHL_B32_]], implicit-def $scc ; CHECK-NEXT: undef %273.sub0:sreg_64 = S_ADD_U32 [[COPY6]], [[S_LSHL_B32_]], implicit-def $scc
; CHECK-NEXT: %273.sub1:sreg_64 = S_ADDC_U32 undef %48:sreg_32, [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %273.sub1:sreg_64 = S_ADDC_U32 undef %48:sreg_32, [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM16:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %273, 0, 0 :: (invariant load (s128) from %ir.167, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN16:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM16]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_ADD_U32_e64_10:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -94, [[BUFFER_LOAD_FORMAT_X_IDXEN16]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_25:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_24]], [[V_ADD_U32_e64_10]], implicit $exec
; CHECK-NEXT: undef %286.sub0:sreg_64 = S_ADD_U32 [[COPY7]], [[S_LSHL_B32_1]], implicit-def $scc ; CHECK-NEXT: undef %286.sub0:sreg_64 = S_ADD_U32 [[COPY7]], [[S_LSHL_B32_1]], implicit-def $scc
; CHECK-NEXT: %286.sub1:sreg_64 = S_ADDC_U32 undef %45:sreg_32, [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %286.sub1:sreg_64 = S_ADDC_U32 undef %45:sreg_32, [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM17:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %286, 0, 0 :: (invariant load (s128) from %ir.175, addrspace 4)
; CHECK-NEXT: [[V_ADD_U32_e64_11:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -95, [[BUFFER_LOAD_DWORD_OFFSET]], 0, implicit $exec
; CHECK-NEXT: undef %293.sub0:sreg_64 = S_ADD_U32 [[COPY7]], [[S_LSHL_B32_2]], implicit-def $scc ; CHECK-NEXT: undef %293.sub0:sreg_64 = S_ADD_U32 [[COPY7]], [[S_LSHL_B32_2]], implicit-def $scc
; CHECK-NEXT: %293.sub1:sreg_64 = S_ADDC_U32 undef %45:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %293.sub1:sreg_64 = S_ADDC_U32 undef %45:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM18:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %293, 0, 0 :: (invariant load (s128) from %ir.180, addrspace 4)
; CHECK-NEXT: [[V_OR_B32_e64_26:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_25]], [[V_ADD_U32_e64_11]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET2:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[S_LOAD_DWORDX4_IMM17]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_ADD_U32_e64_12:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -96, [[BUFFER_LOAD_DWORD_OFFSET2]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_27:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_26]], [[V_ADD_U32_e64_12]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET3:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[S_LOAD_DWORDX4_IMM18]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: undef %302.sub1:sgpr_128 = S_MOV_B32 0
; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_LSHL_B32_]], 16, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_LSHL_B32_]], 16, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_LSHL_B32_2]], 16, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_LSHL_B32_2]], 16, implicit-def dead $scc
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %302, [[S_ADD_I32_]], 0 :: (dereferenceable invariant load (s32)) ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %302, [[S_ADD_I32_]], 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR1:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %302, undef %314:sreg_32, 0 :: (dereferenceable invariant load (s32)) ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR1:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %302, undef %314:sreg_32, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR2:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %302, [[S_ADD_I32_1]], 0 :: (dereferenceable invariant load (s32)) ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR2:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %302, [[S_ADD_I32_1]], 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM2:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %302, 16, 0 :: (dereferenceable invariant load (s32)) ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM2:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %302, 16, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET undef %118:sgpr_128, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7) ; CHECK-NEXT: KILL undef %314:sreg_32
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR3:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR undef %369:sgpr_128, undef %370:sreg_32, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM3:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %380:sgpr_128, 16, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM3:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %156, 0, 0 :: (invariant load (s128) from %ir.92, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM4:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %163, 0, 0 :: (invariant load (s128) from %ir.97, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM5:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %176, 0, 0 :: (invariant load (s128) from %ir.104, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM6:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %183, 0, 0 :: (invariant load (s128) from %ir.109, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM7:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %190, 0, 0 :: (invariant load (s128) from %ir.114, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN2:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM2]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR4:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR undef %364:sgpr_128, [[S_ADD_I32_]], 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR5:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR undef %375:sgpr_128, [[S_ADD_I32_1]], 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_ADD_I32_2:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR]], -98, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_2:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR]], -98, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_3:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR1]], -114, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_3:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR1]], -114, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_4:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR2]], -130, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_4:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR2]], -130, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_5:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM2]], -178, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_5:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM2]], -178, implicit-def dead $scc
; CHECK-NEXT: undef %327.sub0:sreg_64 = S_ADD_U32 [[COPY8]], [[S_LSHL_B32_]], implicit-def $scc ; CHECK-NEXT: undef %327.sub0:sreg_64 = S_ADD_U32 [[COPY8]], [[S_LSHL_B32_]], implicit-def $scc
; CHECK-NEXT: %327.sub1:sreg_64 = S_ADDC_U32 undef %42:sreg_32, [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %327.sub1:sreg_64 = S_ADDC_U32 undef %42:sreg_32, [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM19:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %327, 0, 0 :: (invariant load (s128) from %ir.202, addrspace 4)
; CHECK-NEXT: [[V_ADD_U32_e64_13:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -97, [[BUFFER_LOAD_DWORD_OFFSET3]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_28:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_27]], [[V_ADD_U32_e64_13]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN17:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM19]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: undef %335.sub0:sreg_64 = S_ADD_U32 [[COPY9]], [[S_LSHL_B32_]], implicit-def $scc ; CHECK-NEXT: undef %335.sub0:sreg_64 = S_ADD_U32 [[COPY9]], [[S_LSHL_B32_]], implicit-def $scc
; CHECK-NEXT: %335.sub1:sreg_64 = S_ADDC_U32 undef %39:sreg_32, [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %335.sub1:sreg_64 = S_ADDC_U32 undef %39:sreg_32, [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[V_OR_B32_e64_29:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_2]], [[V_OR_B32_e64_28]], implicit $exec
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM20:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %335, 0, 0 :: (invariant load (s128) from %ir.208, addrspace 4)
; CHECK-NEXT: [[V_OR_B32_e64_30:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_3]], [[V_OR_B32_e64_29]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_31:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_4]], [[V_OR_B32_e64_30]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_14:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -194, [[BUFFER_LOAD_FORMAT_X_IDXEN17]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_32:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_5]], [[V_OR_B32_e64_31]], implicit $exec
; CHECK-NEXT: undef %343.sub0:sreg_64 = S_ADD_U32 [[COPY9]], [[S_LSHL_B32_1]], implicit-def $scc ; CHECK-NEXT: undef %343.sub0:sreg_64 = S_ADD_U32 [[COPY9]], [[S_LSHL_B32_1]], implicit-def $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM8:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %200, 0, 0 :: (invariant load (s128) from %ir.121, addrspace 4)
; CHECK-NEXT: %343.sub1:sreg_64 = S_ADDC_U32 undef %39:sreg_32, [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %343.sub1:sreg_64 = S_ADDC_U32 undef %39:sreg_32, [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM21:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %343, 0, 0 :: (invariant load (s128) from %ir.213, addrspace 4)
; CHECK-NEXT: [[V_OR_B32_e64_33:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_32]], [[V_ADD_U32_e64_14]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN18:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM20]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_ADD_U32_e64_15:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -195, [[BUFFER_LOAD_FORMAT_X_IDXEN18]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_34:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_33]], [[V_ADD_U32_e64_15]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN19:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM21]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: undef %351.sub0:sreg_64 = S_ADD_U32 [[COPY9]], [[S_LSHL_B32_2]], implicit-def $scc ; CHECK-NEXT: undef %351.sub0:sreg_64 = S_ADD_U32 [[COPY9]], [[S_LSHL_B32_2]], implicit-def $scc
; CHECK-NEXT: %351.sub1:sreg_64 = S_ADDC_U32 undef %39:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %351.sub1:sreg_64 = S_ADDC_U32 undef %39:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM22:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %351, 0, 0 :: (invariant load (s128) from %ir.218, addrspace 4)
; CHECK-NEXT: [[V_ADD_U32_e64_16:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -196, [[BUFFER_LOAD_FORMAT_X_IDXEN19]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_35:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_34]], [[V_ADD_U32_e64_16]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN20:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM22]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR3:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR undef %364:sgpr_128, [[S_ADD_I32_]], 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR4:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR undef %369:sgpr_128, undef %370:sreg_32, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: KILL undef %370:sreg_32
; CHECK-NEXT: KILL undef %364:sgpr_128
; CHECK-NEXT: KILL undef %369:sgpr_128
; CHECK-NEXT: KILL [[S_ADD_I32_]]
; CHECK-NEXT: [[V_ADD_U32_e64_17:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -197, [[BUFFER_LOAD_FORMAT_X_IDXEN20]], 0, implicit $exec
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR5:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR undef %375:sgpr_128, [[S_ADD_I32_1]], 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[V_OR_B32_e64_36:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_35]], [[V_ADD_U32_e64_17]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_18:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -216, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM3:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %380:sgpr_128, 16, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_LSHL_B32_3:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY10]], 4, implicit-def dead $scc ; CHECK-NEXT: [[S_LSHL_B32_3:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY10]], 4, implicit-def dead $scc
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN3:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM3]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7) ; CHECK-NEXT: [[V_OR_B32_e64_37:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_36]], [[V_ADD_U32_e64_18]], implicit $exec
; CHECK-NEXT: [[S_ADD_I32_6:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_LSHL_B32_3]], 16, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_6:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_LSHL_B32_3]], 16, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_7:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR3]], -217, implicit-def dead $scc
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR6:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR undef %396:sgpr_128, [[S_ADD_I32_6]], 0 :: (dereferenceable invariant load (s32)) ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR6:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR undef %396:sgpr_128, [[S_ADD_I32_6]], 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN4:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM4]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7) ; CHECK-NEXT: [[V_OR_B32_e64_38:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_7]], [[V_OR_B32_e64_37]], implicit $exec
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM9:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %50, 224, 0 :: (invariant load (s128) from %ir.126, addrspace 4) ; CHECK-NEXT: [[S_ADD_I32_8:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR4]], -233, implicit-def dead $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM10:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %210, 0, 0 :: (invariant load (s128) from %ir.127, addrspace 4) ; CHECK-NEXT: [[V_OR_B32_e64_39:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_8]], [[V_OR_B32_e64_38]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN5:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM5]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM11:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %217, 0, 0 :: (invariant load (s128) from %ir.132, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM12:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %224, 0, 0 :: (invariant load (s128) from %ir.137, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN6:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM6]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN7:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM7]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN8:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM8]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_ADD_I32_7:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR4]], -217, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_8:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR3]], -233, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_9:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR5]], -249, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_9:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR5]], -249, implicit-def dead $scc
; CHECK-NEXT: [[V_OR_B32_e64_40:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_9]], [[V_OR_B32_e64_39]], implicit $exec
; CHECK-NEXT: [[S_ADD_I32_10:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM3]], -297, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_10:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM3]], -297, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_11:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR3]], -313, implicit-def dead $scc ; CHECK-NEXT: [[V_OR_B32_e64_41:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_10]], [[V_OR_B32_e64_40]], implicit $exec
; CHECK-NEXT: [[S_ADD_I32_12:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR3]], -329, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_11:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR4]], -313, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_13:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR3]], -345, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_12:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR4]], -329, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_13:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR4]], -345, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_14:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR6]], -441, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_14:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR6]], -441, implicit-def dead $scc
; CHECK-NEXT: [[V_OR_B32_e64_42:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_11]], [[V_OR_B32_e64_41]], implicit $exec
; CHECK-NEXT: [[S_ADD_U32_3:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], 160, implicit-def $scc ; CHECK-NEXT: [[S_ADD_U32_3:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], 160, implicit-def $scc
; CHECK-NEXT: [[S_ADDC_U32_3:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %36:sreg_32, 0, implicit-def dead $scc, implicit $scc ; CHECK-NEXT: [[S_ADDC_U32_3:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %36:sreg_32, 0, implicit-def dead $scc, implicit $scc
; CHECK-NEXT: undef %411.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_3]], [[S_LSHL_B32_2]], implicit-def $scc ; CHECK-NEXT: undef %411.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_3]], [[S_LSHL_B32_2]], implicit-def $scc
; CHECK-NEXT: %411.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_3]], [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %411.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_3]], [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[V_OR_B32_e64_43:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_12]], [[V_OR_B32_e64_42]], implicit $exec
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM23:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %411, 0, 0 :: (invariant load (s128) from %ir.253, addrspace 4)
; CHECK-NEXT: [[V_OR_B32_e64_44:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_13]], [[V_OR_B32_e64_43]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_19:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -457, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_45:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_14]], [[V_OR_B32_e64_44]], implicit $exec
; CHECK-NEXT: [[S_LSHL_B32_4:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY11]], 4, implicit-def dead $scc ; CHECK-NEXT: [[S_LSHL_B32_4:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY11]], 4, implicit-def dead $scc
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN9:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM10]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_ASHR_I32_4:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_4]], 31, implicit-def dead $scc ; CHECK-NEXT: [[S_ASHR_I32_4:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_4]], 31, implicit-def dead $scc
; CHECK-NEXT: [[V_OR_B32_e64_46:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_45]], [[V_ADD_U32_e64_19]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_20:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -458, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: undef %425.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_3]], [[S_LSHL_B32_4]], implicit-def $scc ; CHECK-NEXT: undef %425.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_3]], [[S_LSHL_B32_4]], implicit-def $scc
; CHECK-NEXT: %425.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_3]], [[S_ASHR_I32_4]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %425.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_3]], [[S_ASHR_I32_4]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM24:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %425, 0, 0 :: (invariant load (s128) from %ir.261, addrspace 4)
; CHECK-NEXT: [[V_OR_B32_e64_47:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_46]], [[V_ADD_U32_e64_20]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN21:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM23]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_ADD_U32_e64_21:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -459, [[BUFFER_LOAD_FORMAT_X_IDXEN21]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_48:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_47]], [[V_ADD_U32_e64_21]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN22:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM24]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_ADD_U32_4:%[0-9]+]]:sreg_32 = S_ADD_U32 %56.sub0, 168, implicit-def $scc ; CHECK-NEXT: [[S_ADD_U32_4:%[0-9]+]]:sreg_32 = S_ADD_U32 %56.sub0, 168, implicit-def $scc
; CHECK-NEXT: [[S_ADDC_U32_4:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %57:sreg_32, 0, implicit-def dead $scc, implicit $scc ; CHECK-NEXT: [[S_ADDC_U32_4:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %57:sreg_32, 0, implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM13:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %241, 0, 0 :: (invariant load (s128) from %ir.147, addrspace 4)
; CHECK-NEXT: [[S_LSHL_B32_5:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY4]], 3, implicit-def dead $scc ; CHECK-NEXT: [[S_LSHL_B32_5:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY4]], 3, implicit-def dead $scc
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN10:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM11]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_ASHR_I32_5:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_5]], 31, implicit-def dead $scc ; CHECK-NEXT: [[S_ASHR_I32_5:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_5]], 31, implicit-def dead $scc
; CHECK-NEXT: undef %441.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_4]], [[S_LSHL_B32_5]], implicit-def $scc ; CHECK-NEXT: undef %441.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_4]], [[S_LSHL_B32_5]], implicit-def $scc
; CHECK-NEXT: %441.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_4]], [[S_ASHR_I32_5]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %441.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_4]], [[S_ASHR_I32_5]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %441, 0, 0 :: (invariant load (s32) from %ir.269, align 8, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %441, 0, 0 :: (invariant load (s32) from %ir.269, align 8, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM14:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %253, 0, 0 :: (invariant load (s128) from %ir.154, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN11:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM12]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM15:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %261, 0, 0 :: (invariant load (s128) from %ir.159, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN12:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM9]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN13:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM13]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: %71.sub3:sgpr_128 = S_MOV_B32 553734060 ; CHECK-NEXT: %71.sub3:sgpr_128 = S_MOV_B32 553734060
; CHECK-NEXT: %71.sub2:sgpr_128 = S_MOV_B32 -1 ; CHECK-NEXT: %71.sub2:sgpr_128 = S_MOV_B32 -1
; CHECK-NEXT: [[COPY13:%[0-9]+]]:sgpr_128 = COPY %71 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:sgpr_128 = COPY %71
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM16:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %273, 0, 0 :: (invariant load (s128) from %ir.167, addrspace 4)
; CHECK-NEXT: [[COPY13]].sub1:sgpr_128 = COPY %302.sub1 ; CHECK-NEXT: [[COPY13]].sub1:sgpr_128 = COPY %302.sub1
; CHECK-NEXT: [[COPY13]].sub0:sgpr_128 = COPY [[S_LOAD_DWORD_IMM]] ; CHECK-NEXT: [[COPY13]].sub0:sgpr_128 = COPY [[S_LOAD_DWORD_IMM]]
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM4:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY13]], 0, 0 :: (dereferenceable invariant load (s32)) ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM4:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY13]], 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN14:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM14]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN15:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM15]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM17:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %286, 0, 0 :: (invariant load (s128) from %ir.175, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM18:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %293, 0, 0 :: (invariant load (s128) from %ir.180, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN16:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM16]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_LSHL_B32_6:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY3]], 3, implicit-def dead $scc ; CHECK-NEXT: [[S_LSHL_B32_6:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY3]], 3, implicit-def dead $scc
; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[S_LOAD_DWORDX4_IMM1]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_ASHR_I32_6:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_6]], 31, implicit-def dead $scc ; CHECK-NEXT: [[S_ASHR_I32_6:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_6]], 31, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_15:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM4]], -467, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_15:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM4]], -467, implicit-def dead $scc
; CHECK-NEXT: undef %453.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_4]], [[S_LSHL_B32_6]], implicit-def $scc ; CHECK-NEXT: undef %453.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_4]], [[S_LSHL_B32_6]], implicit-def $scc
; CHECK-NEXT: %453.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_4]], [[S_ASHR_I32_6]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %453.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_4]], [[S_ASHR_I32_6]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %453, 0, 0 :: (invariant load (s64) from %ir.277, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %453, 0, 0 :: (invariant load (s64) from %ir.277, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET2:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[S_LOAD_DWORDX4_IMM17]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET3:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[S_LOAD_DWORDX4_IMM18]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM19:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %327, 0, 0 :: (invariant load (s128) from %ir.202, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM20:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %335, 0, 0 :: (invariant load (s128) from %ir.208, addrspace 4)
; CHECK-NEXT: [[COPY14:%[0-9]+]]:sgpr_128 = COPY %71 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:sgpr_128 = COPY %71
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM21:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %343, 0, 0 :: (invariant load (s128) from %ir.213, addrspace 4)
; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_LOAD_DWORDX2_IMM]].sub1, 65535, implicit-def dead $scc ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_LOAD_DWORDX2_IMM]].sub1, 65535, implicit-def dead $scc
; CHECK-NEXT: [[COPY14]].sub0:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM]].sub0 ; CHECK-NEXT: [[COPY14]].sub0:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM]].sub0
; CHECK-NEXT: [[COPY14]].sub1:sgpr_128 = COPY [[S_AND_B32_]] ; CHECK-NEXT: [[COPY14]].sub1:sgpr_128 = COPY [[S_AND_B32_]]
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM5:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY14]], 0, 0 :: (dereferenceable invariant load (s32)) ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM5:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY14]], 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM22:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %351, 0, 0 :: (invariant load (s128) from %ir.218, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN17:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM19]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN18:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM20]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_LSHL_B32_7:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY2]], 3, implicit-def dead $scc ; CHECK-NEXT: [[S_LSHL_B32_7:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY2]], 3, implicit-def dead $scc
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN19:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM21]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_ASHR_I32_7:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_7]], 31, implicit-def dead $scc ; CHECK-NEXT: [[S_ASHR_I32_7:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_7]], 31, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_16:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM5]], -468, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_16:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM5]], -468, implicit-def dead $scc
; CHECK-NEXT: undef %468.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_4]], [[S_LSHL_B32_7]], implicit-def $scc ; CHECK-NEXT: undef %468.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_4]], [[S_LSHL_B32_7]], implicit-def $scc
; CHECK-NEXT: %468.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_4]], [[S_ASHR_I32_7]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %468.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_4]], [[S_ASHR_I32_7]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN20:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM22]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %468, 0, 0 :: (invariant load (s64) from %ir.287, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %468, 0, 0 :: (invariant load (s64) from %ir.287, addrspace 4)
; CHECK-NEXT: [[COPY15:%[0-9]+]]:sgpr_128 = COPY %71 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:sgpr_128 = COPY %71
; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_LOAD_DWORDX2_IMM1]].sub1, 65535, implicit-def dead $scc ; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_LOAD_DWORDX2_IMM1]].sub1, 65535, implicit-def dead $scc
; CHECK-NEXT: [[COPY15]].sub0:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM1]].sub0 ; CHECK-NEXT: [[COPY15]].sub0:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM1]].sub0
; CHECK-NEXT: [[COPY15]].sub1:sgpr_128 = COPY [[S_AND_B32_1]] ; CHECK-NEXT: [[COPY15]].sub1:sgpr_128 = COPY [[S_AND_B32_1]]
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM6:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY15]], 0, 0 :: (dereferenceable invariant load (s32)) ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM6:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY15]], 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM23:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %411, 0, 0 :: (invariant load (s128) from %ir.253, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef %488:sreg_64, 0, 0 :: (invariant load (s32) from `ptr addrspace(4) undef`, addrspace 4)
; CHECK-NEXT: KILL %411.sub0, %411.sub1
; CHECK-NEXT: KILL undef %488:sreg_64
; CHECK-NEXT: KILL [[COPY15]].sub0_sub1, [[COPY15]].sub2_sub3
; CHECK-NEXT: [[S_LSHL_B32_8:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY12]], 3, implicit-def dead $scc ; CHECK-NEXT: [[S_LSHL_B32_8:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY12]], 3, implicit-def dead $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM24:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %425, 0, 0 :: (invariant load (s128) from %ir.261, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef %488:sreg_64, 0, 0 :: (invariant load (s32) from `ptr addrspace(4) undef`, addrspace 4)
; CHECK-NEXT: [[S_ASHR_I32_8:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_8]], 31, implicit-def dead $scc ; CHECK-NEXT: [[S_ASHR_I32_8:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_8]], 31, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_17:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM6]], -469, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_17:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM6]], -469, implicit-def dead $scc
; CHECK-NEXT: undef %485.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_4]], [[S_LSHL_B32_8]], implicit-def $scc ; CHECK-NEXT: undef %485.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_4]], [[S_LSHL_B32_8]], implicit-def $scc
; CHECK-NEXT: %485.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_4]], [[S_ASHR_I32_8]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %485.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_4]], [[S_ASHR_I32_8]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORD_IMM2:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %485, 0, 0 :: (invariant load (s32) from %ir.298, align 8, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORD_IMM2:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %485, 0, 0 :: (invariant load (s32) from %ir.298, align 8, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN21:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM23]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN22:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM24]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM24]]
; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM23]]
; CHECK-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_LOAD_DWORD_IMM1]], 65535, implicit-def dead $scc ; CHECK-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_LOAD_DWORD_IMM1]], 65535, implicit-def dead $scc
; CHECK-NEXT: [[COPY16:%[0-9]+]]:sgpr_128 = COPY %71 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:sgpr_128 = COPY %71
; CHECK-NEXT: [[COPY16]].sub1:sgpr_128 = COPY [[S_AND_B32_2]] ; CHECK-NEXT: [[COPY16]].sub1:sgpr_128 = COPY [[S_AND_B32_2]]
; CHECK-NEXT: [[COPY16]].sub0:sgpr_128 = COPY [[S_LOAD_DWORD_IMM2]] ; CHECK-NEXT: [[COPY16]].sub0:sgpr_128 = COPY [[S_LOAD_DWORD_IMM2]]
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM7:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY16]], 0, 0 :: (dereferenceable invariant load (s32)) ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM7:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY16]], 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_ADD_I32_18:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM]], -474, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_18:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM]], -474, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_19:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR3]], -475, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_19:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR4]], -475, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_20:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR3]], -491, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_20:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR4]], -491, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_21:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR3]], -507, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_21:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR4]], -507, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_22:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR3]], -539, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_22:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR4]], -539, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_23:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM7]], -473, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_23:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM7]], -473, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_U32_5:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], 96, implicit-def $scc ; CHECK-NEXT: [[S_ADD_U32_5:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], 96, implicit-def $scc
; CHECK-NEXT: [[S_ADDC_U32_5:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %33:sreg_32, 0, implicit-def dead $scc, implicit $scc ; CHECK-NEXT: [[S_ADDC_U32_5:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %33:sreg_32, 0, implicit-def dead $scc, implicit $scc
; CHECK-NEXT: undef %514.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_5]], [[S_LSHL_B32_]], implicit-def $scc ; CHECK-NEXT: undef %514.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_5]], [[S_LSHL_B32_]], implicit-def $scc
; CHECK-NEXT: %514.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_5]], [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %514.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_5]], [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM25:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %514, 0, 0 :: (invariant load (s128) from %ir.316, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM25:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %514, 0, 0 :: (invariant load (s128) from %ir.316, addrspace 4)
; CHECK-NEXT: [[V_ADD_U32_e64_22:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -466, [[BUFFER_LOAD_FORMAT_X_IDXEN22]], 0, implicit $exec
; CHECK-NEXT: undef %522.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_5]], [[S_LSHL_B32_1]], implicit-def $scc ; CHECK-NEXT: undef %522.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_5]], [[S_LSHL_B32_1]], implicit-def $scc
; CHECK-NEXT: %522.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_5]], [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: %522.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_5]], [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM26:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %522, 0, 0 :: (invariant load (s128) from %ir.321, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM26:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %522, 0, 0 :: (invariant load (s128) from %ir.321, addrspace 4)
; CHECK-NEXT: undef %530.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_5]], [[S_LSHL_B32_2]], implicit-def $scc
; CHECK-NEXT: %530.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_5]], [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM27:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %530, 0, 0 :: (invariant load (s128) from %ir.326, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN23:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM25]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN24:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM26]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN25:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM27]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM27]]
; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM25]]
; CHECK-NEXT: KILL [[V_MOV_B32_e32_]]
; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM26]]
; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -2, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -1, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -3, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_ADD_U32_e64_]], [[V_ADD_U32_e64_1]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -4, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_1:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_]], [[V_ADD_U32_e64_2]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 27, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_2:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_1]], [[V_ADD_U32_e64_3]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 28, [[BUFFER_LOAD_DWORD_OFFSET]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_3:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_2]], [[V_SUBREV_U32_e64_]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_4:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_3]], [[V_SUBREV_U32_e64_1]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_5:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_SUB_I32_]], [[V_OR_B32_e64_4]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_6:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_SUB_I32_1]], [[V_OR_B32_e64_5]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_7:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_SUB_I32_2]], [[V_OR_B32_e64_6]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 32, [[BUFFER_LOAD_FORMAT_X_IDXEN2]], 0, implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_3:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 33, [[BUFFER_LOAD_FORMAT_X_IDXEN3]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_8:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_7]], [[V_SUBREV_U32_e64_2]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_4:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 34, [[BUFFER_LOAD_FORMAT_X_IDXEN4]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_9:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_8]], [[V_SUBREV_U32_e64_3]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_5:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 36, [[BUFFER_LOAD_FORMAT_X_IDXEN5]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_10:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_9]], [[V_SUBREV_U32_e64_4]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_6:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 37, [[BUFFER_LOAD_FORMAT_X_IDXEN6]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_11:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_10]], [[V_SUBREV_U32_e64_5]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_7:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 38, [[BUFFER_LOAD_FORMAT_X_IDXEN7]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_12:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_11]], [[V_SUBREV_U32_e64_6]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_8:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 39, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_13:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_12]], [[V_SUBREV_U32_e64_7]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_9:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 50, [[BUFFER_LOAD_FORMAT_X_IDXEN8]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_14:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_13]], [[V_SUBREV_U32_e64_8]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_10:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 51, [[BUFFER_LOAD_FORMAT_X_IDXEN9]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_15:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_14]], [[V_SUBREV_U32_e64_9]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_11:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 52, [[BUFFER_LOAD_FORMAT_X_IDXEN10]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_16:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_15]], [[V_SUBREV_U32_e64_10]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_12:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 53, [[BUFFER_LOAD_FORMAT_X_IDXEN11]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_17:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_16]], [[V_SUBREV_U32_e64_11]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -72, [[BUFFER_LOAD_FORMAT_X_IDXEN12]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_18:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_17]], [[V_SUBREV_U32_e64_12]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -73, [[BUFFER_LOAD_FORMAT_X_IDXEN13]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_19:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_18]], [[V_ADD_U32_e64_4]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_6:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -74, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_20:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_19]], [[V_ADD_U32_e64_5]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_7:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -75, [[BUFFER_LOAD_FORMAT_X_IDXEN14]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_21:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_20]], [[V_ADD_U32_e64_6]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_8:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -77, [[BUFFER_LOAD_FORMAT_X_IDXEN15]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_22:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_21]], [[V_ADD_U32_e64_7]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_9:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -93, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_23:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_22]], [[V_ADD_U32_e64_8]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_10:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -94, [[BUFFER_LOAD_FORMAT_X_IDXEN16]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_24:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_23]], [[V_ADD_U32_e64_9]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_11:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -95, [[BUFFER_LOAD_DWORD_OFFSET1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_25:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_24]], [[V_ADD_U32_e64_10]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_12:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -96, [[BUFFER_LOAD_DWORD_OFFSET2]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_26:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_25]], [[V_ADD_U32_e64_11]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_13:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -97, [[BUFFER_LOAD_DWORD_OFFSET3]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_27:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_26]], [[V_ADD_U32_e64_12]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_28:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_27]], [[V_ADD_U32_e64_13]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_29:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_2]], [[V_OR_B32_e64_28]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_30:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_3]], [[V_OR_B32_e64_29]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_31:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_4]], [[V_OR_B32_e64_30]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_14:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -194, [[BUFFER_LOAD_FORMAT_X_IDXEN17]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_32:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_5]], [[V_OR_B32_e64_31]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_15:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -195, [[BUFFER_LOAD_FORMAT_X_IDXEN18]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_33:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_32]], [[V_ADD_U32_e64_14]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_16:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -196, [[BUFFER_LOAD_FORMAT_X_IDXEN19]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_34:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_33]], [[V_ADD_U32_e64_15]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_17:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -197, [[BUFFER_LOAD_FORMAT_X_IDXEN20]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_35:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_34]], [[V_ADD_U32_e64_16]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_18:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -216, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_36:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_35]], [[V_ADD_U32_e64_17]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_37:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_36]], [[V_ADD_U32_e64_18]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_38:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_7]], [[V_OR_B32_e64_37]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_39:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_8]], [[V_OR_B32_e64_38]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_40:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_9]], [[V_OR_B32_e64_39]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_41:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_10]], [[V_OR_B32_e64_40]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_42:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_11]], [[V_OR_B32_e64_41]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_43:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_12]], [[V_OR_B32_e64_42]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_44:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_13]], [[V_OR_B32_e64_43]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_19:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -457, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_45:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_14]], [[V_OR_B32_e64_44]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_20:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -458, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_46:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_45]], [[V_ADD_U32_e64_19]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_21:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -459, [[BUFFER_LOAD_FORMAT_X_IDXEN21]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_47:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_46]], [[V_ADD_U32_e64_20]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_22:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -466, [[BUFFER_LOAD_FORMAT_X_IDXEN22]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_48:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_47]], [[V_ADD_U32_e64_21]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_49:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_48]], [[V_ADD_U32_e64_22]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_49:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_48]], [[V_ADD_U32_e64_22]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN23:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM25]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[V_OR_B32_e64_50:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_15]], [[V_OR_B32_e64_49]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_50:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_15]], [[V_OR_B32_e64_49]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_51:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_16]], [[V_OR_B32_e64_50]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_51:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_16]], [[V_OR_B32_e64_50]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_52:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_17]], [[V_OR_B32_e64_51]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_52:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_17]], [[V_OR_B32_e64_51]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_53:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_23]], [[V_OR_B32_e64_52]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_53:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_23]], [[V_OR_B32_e64_52]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_54:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_18]], [[V_OR_B32_e64_53]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_54:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_18]], [[V_OR_B32_e64_53]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_55:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_19]], [[V_OR_B32_e64_54]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_55:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_19]], [[V_OR_B32_e64_54]], implicit $exec
; CHECK-NEXT: undef %530.sub0:sreg_64 = S_ADD_U32 [[S_ADD_U32_5]], [[S_LSHL_B32_2]], implicit-def $scc
; CHECK-NEXT: %530.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_5]], [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[V_OR_B32_e64_56:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_20]], [[V_OR_B32_e64_55]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_56:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_20]], [[V_OR_B32_e64_55]], implicit $exec
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM27:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM %530, 0, 0 :: (invariant load (s128) from %ir.326, addrspace 4)
; CHECK-NEXT: [[V_OR_B32_e64_57:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_21]], [[V_OR_B32_e64_56]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_57:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_21]], [[V_OR_B32_e64_56]], implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_58:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_22]], [[V_OR_B32_e64_57]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_58:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_22]], [[V_OR_B32_e64_57]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_23:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -555, [[BUFFER_LOAD_FORMAT_X_IDXEN23]], 0, implicit $exec ; CHECK-NEXT: [[V_ADD_U32_e64_23:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -555, [[BUFFER_LOAD_FORMAT_X_IDXEN23]], 0, implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_24:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -556, [[BUFFER_LOAD_FORMAT_X_IDXEN24]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_59:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_58]], [[V_ADD_U32_e64_23]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_59:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_58]], [[V_ADD_U32_e64_23]], implicit $exec
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN24:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM26]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN25:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM27]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 7)
; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM27]]
; CHECK-NEXT: KILL [[V_MOV_B32_e32_]]
; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM26]]
; CHECK-NEXT: [[V_ADD_U32_e64_24:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -556, [[BUFFER_LOAD_FORMAT_X_IDXEN24]], 0, implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_25:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -557, [[BUFFER_LOAD_FORMAT_X_IDXEN25]], 0, implicit $exec ; CHECK-NEXT: [[V_ADD_U32_e64_25:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -557, [[BUFFER_LOAD_FORMAT_X_IDXEN25]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_60:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_59]], [[V_ADD_U32_e64_24]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_60:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_59]], [[V_ADD_U32_e64_24]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_26:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -574, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec ; CHECK-NEXT: [[V_ADD_U32_e64_26:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -574, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_61:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_60]], [[V_ADD_U32_e64_25]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_61:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_60]], [[V_ADD_U32_e64_25]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_27:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -575, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec ; CHECK-NEXT: [[V_ADD_U32_e64_27:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -575, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_62:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_61]], [[V_ADD_U32_e64_26]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_62:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_61]], [[V_ADD_U32_e64_26]], implicit $exec
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM8:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %71, 0, 0 :: (dereferenceable invariant load (s32)) ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM8:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %71, 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[V_ADD_U32_e64_28:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -576, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec ; CHECK-NEXT: [[V_ADD_U32_e64_28:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -576, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_63:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_62]], [[V_ADD_U32_e64_27]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_63:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_62]], [[V_ADD_U32_e64_27]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_29:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -577, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec ; CHECK-NEXT: [[V_ADD_U32_e64_29:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -577, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_64:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_63]], [[V_ADD_U32_e64_28]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_64:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_63]], [[V_ADD_U32_e64_28]], implicit $exec
; CHECK-NEXT: [[V_ADD_U32_e64_30:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -593, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec ; CHECK-NEXT: [[V_ADD_U32_e64_30:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -593, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_65:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_64]], [[V_ADD_U32_e64_29]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_65:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_64]], [[V_ADD_U32_e64_29]], implicit $exec
; CHECK-NEXT: [[S_LOAD_DWORDX8_IMM:%[0-9]+]]:sgpr_256 = S_LOAD_DWORDX8_IMM undef %564:sreg_64, 0, 0 :: (invariant load (s256) from `ptr addrspace(4) undef`, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORDX8_IMM:%[0-9]+]]:sgpr_256 = S_LOAD_DWORDX8_IMM undef %564:sreg_64, 0, 0 :: (invariant load (s256) from `ptr addrspace(4) undef`, addrspace 4)
; CHECK-NEXT: [[V_OR_B32_e64_66:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_65]], [[V_ADD_U32_e64_30]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_66:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_65]], [[V_ADD_U32_e64_30]], implicit $exec
; CHECK-NEXT: [[S_ADD_I32_24:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM8]], -594, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_24:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM8]], -594, implicit-def dead $scc
; CHECK-NEXT: [[V_OR_B32_e64_67:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_24]], [[V_OR_B32_e64_66]], implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_67:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_24]], [[V_OR_B32_e64_66]], implicit $exec
; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 0, [[V_OR_B32_e64_67]], implicit $exec ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 0, [[V_OR_B32_e64_67]], implicit $exec
; CHECK-NEXT: undef %693.sub3:vreg_128 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U32_e64_]], implicit $exec ; CHECK-NEXT: undef %693.sub3:vreg_128 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U32_e64_]], implicit $exec
; CHECK-NEXT: IMAGE_STORE_V4_V2_gfx10 %693, undef %578:vreg_64, [[S_LOAD_DWORDX8_IMM]], 15, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), addrspace 7) ; CHECK-NEXT: IMAGE_STORE_V4_V2_gfx10 %693, undef %578:vreg_64, [[S_LOAD_DWORDX8_IMM]], 15, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), addrspace 7)
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llvm/test/CodeGen/AMDGPU/ssubsat.ll

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; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_i32 v15, v15, v16 clamp ; GFX9-NEXT: v_sub_i32 v15, v15, v16 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_ssubsat_v16i32: ; GFX10-LABEL: v_ssubsat_v16i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_sub_nc_i32 v0, v0, v16 clamp ; GFX10-NEXT: v_sub_nc_i32 v0, v0, v16 clamp
; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GFX10-NEXT: v_sub_nc_i32 v1, v1, v17 clamp ; GFX10-NEXT: v_sub_nc_i32 v1, v1, v17 clamp
; GFX10-NEXT: v_sub_nc_i32 v2, v2, v18 clamp ; GFX10-NEXT: v_sub_nc_i32 v2, v2, v18 clamp
; GFX10-NEXT: v_sub_nc_i32 v3, v3, v19 clamp ; GFX10-NEXT: v_sub_nc_i32 v3, v3, v19 clamp
; GFX10-NEXT: v_sub_nc_i32 v4, v4, v20 clamp ; GFX10-NEXT: v_sub_nc_i32 v4, v4, v20 clamp
; GFX10-NEXT: v_sub_nc_i32 v5, v5, v21 clamp ; GFX10-NEXT: v_sub_nc_i32 v5, v5, v21 clamp
; GFX10-NEXT: v_sub_nc_i32 v6, v6, v22 clamp ; GFX10-NEXT: v_sub_nc_i32 v6, v6, v22 clamp
; GFX10-NEXT: v_sub_nc_i32 v7, v7, v23 clamp ; GFX10-NEXT: v_sub_nc_i32 v7, v7, v23 clamp
; GFX10-NEXT: v_sub_nc_i32 v8, v8, v24 clamp ; GFX10-NEXT: v_sub_nc_i32 v8, v8, v24 clamp
; GFX10-NEXT: v_sub_nc_i32 v9, v9, v25 clamp ; GFX10-NEXT: v_sub_nc_i32 v9, v9, v25 clamp
; GFX10-NEXT: v_sub_nc_i32 v10, v10, v26 clamp ; GFX10-NEXT: v_sub_nc_i32 v10, v10, v26 clamp
; GFX10-NEXT: v_sub_nc_i32 v11, v11, v27 clamp ; GFX10-NEXT: v_sub_nc_i32 v11, v11, v27 clamp
; GFX10-NEXT: v_sub_nc_i32 v12, v12, v28 clamp ; GFX10-NEXT: v_sub_nc_i32 v12, v12, v28 clamp
; GFX10-NEXT: v_sub_nc_i32 v13, v13, v29 clamp ; GFX10-NEXT: v_sub_nc_i32 v13, v13, v29 clamp
; GFX10-NEXT: v_sub_nc_i32 v14, v14, v30 clamp ; GFX10-NEXT: v_sub_nc_i32 v14, v14, v30 clamp
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_sub_nc_i32 v15, v15, v31 clamp ; GFX10-NEXT: v_sub_nc_i32 v15, v15, v16 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_ssubsat_v16i32: ; GFX11-LABEL: v_ssubsat_v16i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_sub_nc_i32 v0, v0, v16 clamp ; GFX11-NEXT: v_sub_nc_i32 v0, v0, v16 clamp
; GFX11-NEXT: scratch_load_b32 v16, off, s32
; GFX11-NEXT: v_sub_nc_i32 v1, v1, v17 clamp ; GFX11-NEXT: v_sub_nc_i32 v1, v1, v17 clamp
; GFX11-NEXT: v_sub_nc_i32 v2, v2, v18 clamp ; GFX11-NEXT: v_sub_nc_i32 v2, v2, v18 clamp
; GFX11-NEXT: v_sub_nc_i32 v3, v3, v19 clamp ; GFX11-NEXT: v_sub_nc_i32 v3, v3, v19 clamp
; GFX11-NEXT: v_sub_nc_i32 v4, v4, v20 clamp ; GFX11-NEXT: v_sub_nc_i32 v4, v4, v20 clamp
; GFX11-NEXT: v_sub_nc_i32 v5, v5, v21 clamp ; GFX11-NEXT: v_sub_nc_i32 v5, v5, v21 clamp
; GFX11-NEXT: v_sub_nc_i32 v6, v6, v22 clamp ; GFX11-NEXT: v_sub_nc_i32 v6, v6, v22 clamp
; GFX11-NEXT: v_sub_nc_i32 v7, v7, v23 clamp ; GFX11-NEXT: v_sub_nc_i32 v7, v7, v23 clamp
; GFX11-NEXT: v_sub_nc_i32 v8, v8, v24 clamp ; GFX11-NEXT: v_sub_nc_i32 v8, v8, v24 clamp
; GFX11-NEXT: v_sub_nc_i32 v9, v9, v25 clamp ; GFX11-NEXT: v_sub_nc_i32 v9, v9, v25 clamp
; GFX11-NEXT: v_sub_nc_i32 v10, v10, v26 clamp ; GFX11-NEXT: v_sub_nc_i32 v10, v10, v26 clamp
; GFX11-NEXT: v_sub_nc_i32 v11, v11, v27 clamp ; GFX11-NEXT: v_sub_nc_i32 v11, v11, v27 clamp
; GFX11-NEXT: v_sub_nc_i32 v12, v12, v28 clamp ; GFX11-NEXT: v_sub_nc_i32 v12, v12, v28 clamp
; GFX11-NEXT: v_sub_nc_i32 v13, v13, v29 clamp ; GFX11-NEXT: v_sub_nc_i32 v13, v13, v29 clamp
; GFX11-NEXT: v_sub_nc_i32 v14, v14, v30 clamp ; GFX11-NEXT: v_sub_nc_i32 v14, v14, v30 clamp
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_sub_nc_i32 v15, v15, v31 clamp ; GFX11-NEXT: v_sub_nc_i32 v15, v15, v16 clamp
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) { define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) {
; GFX6-LABEL: v_ssubsat_i64: ; GFX6-LABEL: v_ssubsat_i64:
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; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_ssubsat_i64: ; GFX10-LABEL: v_ssubsat_i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2 ; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[2:3] ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[4:5], v[0:1]
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1] ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX10-NEXT: v_xor_b32_e32 v1, 0x80000000, v6 ; GFX10-NEXT: v_xor_b32_e32 v1, 0x80000000, v0
; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_ssubsat_i64: ; GFX11-LABEL: v_ssubsat_i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2 ; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
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llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=MUBUF %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=MUBUF %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -mattr=+enable-flat-scratch -verify-machineinstrs | FileCheck -check-prefix=FLATSCR %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -mattr=+enable-flat-scratch -verify-machineinstrs | FileCheck -check-prefix=FLATSCR %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefix=MUBUF11 %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefix=MUBUF11 %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+enable-flat-scratch -verify-machineinstrs | FileCheck -check-prefix=FLATSCR11 %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+enable-flat-scratch -verify-machineinstrs | FileCheck -check-prefix=FLATSCR11 %s
; During instruction selection, we use immediate const zero for soffset in ; During instruction selection, we use immediate const zero for soffset in
; MUBUF stack accesses and let eliminateFrameIndex to fix up this field to use ; MUBUF stack accesses and let eliminateFrameIndex to fix up this field to use
; the correct frame register whenever required. ; the correct frame register whenever required.
define amdgpu_kernel void @kernel_background_evaluate(ptr addrspace(5) %kg, ptr addrspace(1) %input, ptr addrspace(1) %output, i32 %i) { define amdgpu_kernel void @kernel_background_evaluate(ptr addrspace(5) %kg, ptr addrspace(1) %input, ptr addrspace(1) %output, i32 %i) {
; MUBUF-LABEL: kernel_background_evaluate: ; MUBUF-LABEL: kernel_background_evaluate:
; MUBUF: ; %bb.0: ; %entry ; MUBUF: ; %bb.0: ; %entry
; MUBUF-NEXT: s_load_dword s0, s[0:1], 0x24 ; MUBUF-NEXT: s_load_dword s6, s[0:1], 0x24
; MUBUF-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 ; MUBUF-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; MUBUF-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 ; MUBUF-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; MUBUF-NEXT: s_mov_b32 s38, -1 ; MUBUF-NEXT: s_mov_b32 s38, -1
; MUBUF-NEXT: s_mov_b32 s39, 0x31c16000 ; MUBUF-NEXT: s_mov_b32 s39, 0x31c16000
; MUBUF-NEXT: s_add_u32 s36, s36, s3 ; MUBUF-NEXT: s_add_u32 s36, s36, s3
; MUBUF-NEXT: s_addc_u32 s37, s37, 0 ; MUBUF-NEXT: s_addc_u32 s37, s37, 0
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x2000 ; MUBUF-NEXT: v_mov_b32_e32 v1, 0x2000
; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000 ; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000
; MUBUF-NEXT: v_mov_b32_e32 v3, 0 ; MUBUF-NEXT: v_mov_b32_e32 v3, 0
; MUBUF-NEXT: v_mov_b32_e32 v4, 0x400000 ; MUBUF-NEXT: v_mov_b32_e32 v4, 0x400000
; MUBUF-NEXT: s_mov_b64 s[0:1], s[36:37]
; MUBUF-NEXT: s_mov_b64 s[2:3], s[38:39]
; MUBUF-NEXT: s_mov_b32 s32, 0xc0000 ; MUBUF-NEXT: s_mov_b32 s32, 0xc0000
; MUBUF-NEXT: s_getpc_b64 s[4:5] ; MUBUF-NEXT: s_getpc_b64 s[4:5]
; MUBUF-NEXT: s_add_u32 s4, s4, svm_eval_nodes@rel32@lo+4 ; MUBUF-NEXT: s_add_u32 s4, s4, svm_eval_nodes@rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+12 ; MUBUF-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+12
; MUBUF-NEXT: s_waitcnt lgkmcnt(0) ; MUBUF-NEXT: s_waitcnt lgkmcnt(0)
; MUBUF-NEXT: v_mov_b32_e32 v0, s0 ; MUBUF-NEXT: v_mov_b32_e32 v0, s6
; MUBUF-NEXT: s_mov_b64 s[0:1], s[36:37]
; MUBUF-NEXT: s_mov_b64 s[2:3], s[38:39]
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5] ; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5]
; MUBUF-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; MUBUF-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; MUBUF-NEXT: s_and_saveexec_b32 s0, vcc_lo ; MUBUF-NEXT: s_and_saveexec_b32 s0, vcc_lo
; MUBUF-NEXT: s_cbranch_execz .LBB0_2 ; MUBUF-NEXT: s_cbranch_execz .LBB0_2
; MUBUF-NEXT: ; %bb.1: ; %if.then4.i ; MUBUF-NEXT: ; %bb.1: ; %if.then4.i
; MUBUF-NEXT: v_add_nc_u32_e64 v0, 4, 0x4000 ; MUBUF-NEXT: v_add_nc_u32_e64 v0, 4, 0x4000
; MUBUF-NEXT: s_mov_b32 s0, 0x41c64e6d ; MUBUF-NEXT: s_mov_b32 s0, 0x41c64e6d
; MUBUF-NEXT: s_clause 0x1 ; MUBUF-NEXT: s_clause 0x1
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llvm/test/CodeGen/AMDGPU/store-local.128.ll

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; GFX10-LABEL: store_lds_v4i32_align1: ; GFX10-LABEL: store_lds_v4i32_align1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-NEXT: v_mov_b32_e32 v1, s6
; GFX10-NEXT: s_lshr_b32 s3, s7, 24
; GFX10-NEXT: v_mov_b32_e32 v2, s7 ; GFX10-NEXT: v_mov_b32_e32 v2, s7
; GFX10-NEXT: v_mov_b32_e32 v3, s4
; GFX10-NEXT: s_lshr_b32 s0, s6, 8 ; GFX10-NEXT: s_lshr_b32 s0, s6, 8
; GFX10-NEXT: s_lshr_b32 s1, s6, 24 ; GFX10-NEXT: s_lshr_b32 s1, s6, 24
; GFX10-NEXT: s_lshr_b32 s6, s4, 8
; GFX10-NEXT: v_mov_b32_e32 v3, s4
; GFX10-NEXT: s_lshr_b32 s2, s7, 8
; GFX10-NEXT: s_lshr_b32 s4, s4, 24
; GFX10-NEXT: v_mov_b32_e32 v8, s3
; GFX10-NEXT: v_mov_b32_e32 v5, s0
; GFX10-NEXT: v_mov_b32_e32 v9, s6
; GFX10-NEXT: s_lshr_b32 s0, s5, 8
; GFX10-NEXT: v_mov_b32_e32 v4, s5
; GFX10-NEXT: v_mov_b32_e32 v6, s1
; GFX10-NEXT: v_mov_b32_e32 v7, s2
; GFX10-NEXT: ds_write_b8 v0, v1 offset:8 ; GFX10-NEXT: ds_write_b8 v0, v1 offset:8
; GFX10-NEXT: ds_write_b8_d16_hi v0, v1 offset:10 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v1 offset:10
; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: ds_write_b8 v0, v2 offset:12 ; GFX10-NEXT: ds_write_b8 v0, v2 offset:12
; GFX10-NEXT: ds_write_b8_d16_hi v0, v2 offset:14 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v2 offset:14
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_lshr_b32 s2, s7, 8
; GFX10-NEXT: ds_write_b8 v0, v3 ; GFX10-NEXT: ds_write_b8 v0, v3
; GFX10-NEXT: ds_write_b8_d16_hi v0, v3 offset:2 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v3 offset:2
; GFX10-NEXT: ds_write_b8 v0, v4 offset:4 ; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: ds_write_b8_d16_hi v0, v4 offset:6 ; GFX10-NEXT: s_lshr_b32 s3, s7, 24
; GFX10-NEXT: ds_write_b8 v0, v5 offset:9 ; GFX10-NEXT: ds_write_b8 v0, v1 offset:4
; GFX10-NEXT: ds_write_b8 v0, v6 offset:11 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v1 offset:6
; GFX10-NEXT: ds_write_b8 v0, v7 offset:13 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s4 ; GFX10-NEXT: s_lshr_b32 s6, s4, 8
; GFX10-NEXT: ds_write_b8 v0, v2 offset:9
; GFX10-NEXT: v_mov_b32_e32 v2, s3
; GFX10-NEXT: ds_write_b8 v0, v3 offset:11
; GFX10-NEXT: v_mov_b32_e32 v3, s6
; GFX10-NEXT: s_lshr_b32 s0, s4, 24
; GFX10-NEXT: ds_write_b8 v0, v1 offset:13
; GFX10-NEXT: ds_write_b8 v0, v2 offset:15
; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: s_lshr_b32 s0, s5, 8
; GFX10-NEXT: s_lshr_b32 s1, s5, 24 ; GFX10-NEXT: s_lshr_b32 s1, s5, 24
; GFX10-NEXT: v_mov_b32_e32 v2, s0 ; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: ds_write_b8 v0, v3 offset:1
; GFX10-NEXT: v_mov_b32_e32 v3, s1 ; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: ds_write_b8 v0, v8 offset:15
; GFX10-NEXT: ds_write_b8 v0, v9 offset:1
; GFX10-NEXT: ds_write_b8 v0, v1 offset:3 ; GFX10-NEXT: ds_write_b8 v0, v1 offset:3
; GFX10-NEXT: ds_write_b8 v0, v2 offset:5 ; GFX10-NEXT: ds_write_b8 v0, v2 offset:5
; GFX10-NEXT: ds_write_b8 v0, v3 offset:7 ; GFX10-NEXT: ds_write_b8 v0, v3 offset:7
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: store_lds_v4i32_align1: ; GFX11-LABEL: store_lds_v4i32_align1:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
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; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-NEXT: v_mov_b32_e32 v1, s6
; GFX10-NEXT: v_mov_b32_e32 v2, s7 ; GFX10-NEXT: v_mov_b32_e32 v2, s7
; GFX10-NEXT: v_mov_b32_e32 v3, s4 ; GFX10-NEXT: v_mov_b32_e32 v3, s4
; GFX10-NEXT: v_mov_b32_e32 v4, s5
; GFX10-NEXT: ds_write_b16 v0, v1 offset:8 ; GFX10-NEXT: ds_write_b16 v0, v1 offset:8
; GFX10-NEXT: ds_write_b16_d16_hi v0, v1 offset:10 ; GFX10-NEXT: ds_write_b16_d16_hi v0, v1 offset:10
; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: ds_write_b16 v0, v2 offset:12 ; GFX10-NEXT: ds_write_b16 v0, v2 offset:12
; GFX10-NEXT: ds_write_b16_d16_hi v0, v2 offset:14 ; GFX10-NEXT: ds_write_b16_d16_hi v0, v2 offset:14
; GFX10-NEXT: ds_write_b16 v0, v3 ; GFX10-NEXT: ds_write_b16 v0, v3
; GFX10-NEXT: ds_write_b16_d16_hi v0, v3 offset:2 ; GFX10-NEXT: ds_write_b16_d16_hi v0, v3 offset:2
; GFX10-NEXT: ds_write_b16 v0, v4 offset:4 ; GFX10-NEXT: ds_write_b16 v0, v1 offset:4
; GFX10-NEXT: ds_write_b16_d16_hi v0, v4 offset:6 ; GFX10-NEXT: ds_write_b16_d16_hi v0, v1 offset:6
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: store_lds_v4i32_align2: ; GFX11-LABEL: store_lds_v4i32_align2:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x10 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x10
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-NEXT: v_mov_b32_e32 v1, s6
; GFX10-NEXT: v_mov_b32_e32 v2, s7 ; GFX10-NEXT: v_mov_b32_e32 v2, s7
; GFX10-NEXT: v_mov_b32_e32 v3, s4 ; GFX10-NEXT: v_mov_b32_e32 v3, s4
; GFX10-NEXT: v_mov_b32_e32 v4, s5
; GFX10-NEXT: ds_write2_b32 v0, v1, v2 offset0:2 offset1:3 ; GFX10-NEXT: ds_write2_b32 v0, v1, v2 offset0:2 offset1:3
; GFX10-NEXT: ds_write2_b32 v0, v3, v4 offset1:1 ; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: ds_write2_b32 v0, v3, v1 offset1:1
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: store_lds_v4i32_align4: ; GFX11-LABEL: store_lds_v4i32_align4:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x10 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x10
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-LABEL: store_lds_v4i32_align8: ; GFX10-LABEL: store_lds_v4i32_align8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: v_mov_b32_e32 v4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, s6 ; GFX10-NEXT: v_mov_b32_e32 v2, s6
; GFX10-NEXT: v_mov_b32_e32 v3, s7 ; GFX10-NEXT: v_mov_b32_e32 v3, s7
; GFX10-NEXT: v_mov_b32_e32 v4, s2
; GFX10-NEXT: ds_write2_b64 v4, v[0:1], v[2:3] offset1:1 ; GFX10-NEXT: ds_write2_b64 v4, v[0:1], v[2:3] offset1:1
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: store_lds_v4i32_align8: ; GFX11-LABEL: store_lds_v4i32_align8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x10 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x10
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llvm/test/CodeGen/AMDGPU/store-local.96.ll

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; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-NEXT: v_mov_b32_e32 v1, s6
; GFX10-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: v_mov_b32_e32 v3, s5 ; GFX10-NEXT: v_mov_b32_e32 v3, s5
; GFX10-NEXT: s_lshr_b32 s0, s6, 8 ; GFX10-NEXT: s_lshr_b32 s0, s6, 8
; GFX10-NEXT: s_lshr_b32 s1, s6, 24 ; GFX10-NEXT: s_lshr_b32 s1, s6, 24
; GFX10-NEXT: s_lshr_b32 s2, s4, 8 ; GFX10-NEXT: s_lshr_b32 s2, s4, 8
; GFX10-NEXT: s_lshr_b32 s3, s4, 24
; GFX10-NEXT: s_lshr_b32 s4, s5, 8
; GFX10-NEXT: s_lshr_b32 s5, s5, 24
; GFX10-NEXT: v_mov_b32_e32 v4, s0
; GFX10-NEXT: v_mov_b32_e32 v5, s1
; GFX10-NEXT: v_mov_b32_e32 v6, s2
; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: v_mov_b32_e32 v8, s4
; GFX10-NEXT: v_mov_b32_e32 v9, s5
; GFX10-NEXT: ds_write_b8 v0, v1 offset:8 ; GFX10-NEXT: ds_write_b8 v0, v1 offset:8
; GFX10-NEXT: ds_write_b8_d16_hi v0, v1 offset:10 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v1 offset:10
; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: ds_write_b8 v0, v2 ; GFX10-NEXT: ds_write_b8 v0, v2
; GFX10-NEXT: ds_write_b8_d16_hi v0, v2 offset:2 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v2 offset:2
; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: ds_write_b8 v0, v3 offset:4 ; GFX10-NEXT: ds_write_b8 v0, v3 offset:4
; GFX10-NEXT: ds_write_b8_d16_hi v0, v3 offset:6 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v3 offset:6
; GFX10-NEXT: ds_write_b8 v0, v4 offset:9 ; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: ds_write_b8 v0, v5 offset:11 ; GFX10-NEXT: s_lshr_b32 s3, s4, 24
; GFX10-NEXT: ds_write_b8 v0, v6 offset:1 ; GFX10-NEXT: s_lshr_b32 s4, s5, 8
; GFX10-NEXT: ds_write_b8 v0, v7 offset:3 ; GFX10-NEXT: s_lshr_b32 s5, s5, 24
; GFX10-NEXT: ds_write_b8 v0, v8 offset:5 ; GFX10-NEXT: ds_write_b8 v0, v1 offset:9
; GFX10-NEXT: ds_write_b8 v0, v9 offset:7 ; GFX10-NEXT: v_mov_b32_e32 v1, s3
; GFX10-NEXT: ds_write_b8 v0, v2 offset:11
; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: ds_write_b8 v0, v3 offset:1
; GFX10-NEXT: v_mov_b32_e32 v3, s5
; GFX10-NEXT: ds_write_b8 v0, v1 offset:3
; GFX10-NEXT: ds_write_b8 v0, v2 offset:5
; GFX10-NEXT: ds_write_b8 v0, v3 offset:7
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: store_lds_v3i32_align1: ; GFX11-LABEL: store_lds_v3i32_align1:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0 ; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x10 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x10
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll

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; GFX8-NEXT: v_or_b32_e32 v0, v0, v5 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v5
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_constained_fadd_v4f16_fpexcept_strict: ; GFX10-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX10-NEXT: v_add_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_add_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX10-NEXT: v_add_f16_e32 v0, v0, v2
; GFX10-NEXT: v_add_f16_sdwa v2, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-NEXT: v_add_f16_e32 v1, v1, v3 ; GFX10-NEXT: v_add_f16_e32 v1, v1, v3
; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x5040100 ; GFX10-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
; GFX10-NEXT: v_perm_b32 v1, v4, v1, 0x5040100 ; GFX10-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_constained_fadd_v4f16_fpexcept_strict: ; GFX11-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v3 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v2
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llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll

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; ;
; GFX10-LABEL: v_constained_fma_v4f16_fpexcept_strict: ; GFX10-LABEL: v_constained_fma_v4f16_fpexcept_strict:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v5 ; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v5
; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v3 ; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1 ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v4 ; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v0
; GFX10-NEXT: v_fmac_f16_e32 v4, v0, v2
; GFX10-NEXT: v_fmac_f16_e32 v6, v8, v7
; GFX10-NEXT: v_fmac_f16_e32 v5, v1, v3 ; GFX10-NEXT: v_fmac_f16_e32 v5, v1, v3
; GFX10-NEXT: v_fmac_f16_e32 v9, v11, v10 ; GFX10-NEXT: v_fmac_f16_e32 v6, v8, v7
; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX10-NEXT: v_fmac_f16_e32 v4, v0, v2
; GFX10-NEXT: v_perm_b32 v1, v6, v5, 0x5040100 ; GFX10-NEXT: v_perm_b32 v1, v6, v5, 0x5040100
; GFX10-NEXT: v_perm_b32 v0, v9, v4, 0x5040100 ; GFX10-NEXT: v_fmac_f16_e32 v7, v9, v8
; GFX10-NEXT: v_perm_b32 v0, v7, v4, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_constained_fma_v4f16_fpexcept_strict: ; GFX11-LABEL: v_constained_fma_v4f16_fpexcept_strict:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v5 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v5
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v3 ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v3
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llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll

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; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-GISEL-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-SDAG-LABEL: v_constained_fmul_v4f16_fpexcept_strict: ; GFX10-SDAG-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
; GFX10-SDAG: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-SDAG-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX10-SDAG-NEXT: v_mul_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-SDAG-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-SDAG-NEXT: v_mul_f16_e32 v0, v0, v2 ; GFX10-SDAG-NEXT: v_mul_f16_e32 v0, v0, v2
; GFX10-SDAG-NEXT: v_mul_f16_sdwa v2, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3 ; GFX10-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3
; GFX10-SDAG-NEXT: v_perm_b32 v0, v5, v0, 0x5040100 ; GFX10-SDAG-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
; GFX10-SDAG-NEXT: v_perm_b32 v1, v4, v1, 0x5040100 ; GFX10-SDAG-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-GISEL-LABEL: v_constained_fmul_v4f16_fpexcept_strict: ; GFX10-GISEL-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2 ; GFX10-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
; GFX10-GISEL-NEXT: v_pk_mul_f16 v1, v1, v3 ; GFX10-GISEL-NEXT: v_pk_mul_f16 v1, v1, v3
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llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll

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; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-GISEL-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-SDAG-LABEL: v_constained_fsub_v4f16_fpexcept_strict: ; GFX10-SDAG-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
; GFX10-SDAG: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-SDAG-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX10-SDAG-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-SDAG-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2 ; GFX10-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
; GFX10-SDAG-NEXT: v_sub_f16_sdwa v2, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3 ; GFX10-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
; GFX10-SDAG-NEXT: v_perm_b32 v0, v5, v0, 0x5040100 ; GFX10-SDAG-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
; GFX10-SDAG-NEXT: v_perm_b32 v1, v4, v1, 0x5040100 ; GFX10-SDAG-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-GISEL-LABEL: v_constained_fsub_v4f16_fpexcept_strict: ; GFX10-GISEL-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-GISEL-NEXT: v_sub_f16_e32 v4, v0, v2 ; GFX10-GISEL-NEXT: v_sub_f16_e32 v4, v0, v2
; GFX10-GISEL-NEXT: v_sub_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX10-GISEL-NEXT: v_sub_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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llvm/test/CodeGen/AMDGPU/uaddsat.ll

Show First 20 Lines • Show All 551 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e64 v15, v15, v16 clamp ; GFX9-NEXT: v_add_u32_e64 v15, v15, v16 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_uaddsat_v16i32: ; GFX10-LABEL: v_uaddsat_v16i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v16 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v16 clamp
; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v17 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v17 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v18 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v18 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v19 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v19 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v4, v4, v20 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v4, v4, v20 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v5, v5, v21 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v5, v5, v21 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v6, v6, v22 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v6, v6, v22 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v7, v7, v23 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v7, v7, v23 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v8, v8, v24 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v8, v8, v24 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v9, v9, v25 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v9, v9, v25 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v10, v10, v26 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v10, v10, v26 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v11, v11, v27 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v11, v11, v27 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v12, v12, v28 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v12, v12, v28 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v13, v13, v29 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v13, v13, v29 clamp
; GFX10-NEXT: v_add_nc_u32_e64 v14, v14, v30 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v14, v14, v30 clamp
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_nc_u32_e64 v15, v15, v31 clamp ; GFX10-NEXT: v_add_nc_u32_e64 v15, v15, v16 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) { define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) {
; GFX6-LABEL: v_uaddsat_i64: ; GFX6-LABEL: v_uaddsat_i64:
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llvm/test/CodeGen/AMDGPU/usubsat.ll

Show First 20 Lines • Show All 623 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_u32_e64 v15, v15, v16 clamp ; GFX9-NEXT: v_sub_u32_e64 v15, v15, v16 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_usubsat_v16i32: ; GFX10-LABEL: v_usubsat_v16i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp
; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp
; GFX10-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_sub_nc_u32_e64 v15, v15, v31 clamp ; GFX10-NEXT: v_sub_nc_u32_e64 v15, v15, v16 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_usubsat_v16i32: ; GFX11-LABEL: v_usubsat_v16i32:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp
; GFX11-NEXT: scratch_load_b32 v16, off, s32
; GFX11-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp
; GFX11-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_sub_nc_u32_e64 v15, v15, v31 clamp ; GFX11-NEXT: v_sub_nc_u32_e64 v15, v15, v16 clamp
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) { define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {
; GFX6-LABEL: v_usubsat_i64: ; GFX6-LABEL: v_usubsat_i64:
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llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll

Show First 20 Lines • Show All 991 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, v7 ; GFX9-NEXT: v_mov_b32_e32 v2, v7
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: shuffle_v6f16_452367: ; GFX10-LABEL: shuffle_v6f16_452367:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v6, v1
; GFX10-NEXT: v_mov_b32_e32 v5, v0
; GFX10-NEXT: v_mov_b32_e32 v4, v3 ; GFX10-NEXT: v_mov_b32_e32 v4, v3
; GFX10-NEXT: v_mov_b32_e32 v3, v2 ; GFX10-NEXT: v_mov_b32_e32 v3, v2
; GFX10-NEXT: global_load_dwordx3 v[0:2], v[5:6], off ; GFX10-NEXT: v_mov_b32_e32 v6, v1
; GFX10-NEXT: v_mov_b32_e32 v5, v0
; GFX10-NEXT: global_load_dword v7, v[3:4], off ; GFX10-NEXT: global_load_dword v7, v[3:4], off
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: global_load_dwordx3 v[0:2], v[5:6], off
; GFX10-NEXT: v_mov_b32_e32 v0, v2
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, v2
; GFX10-NEXT: v_mov_b32_e32 v2, v7 ; GFX10-NEXT: v_mov_b32_e32 v2, v7
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: shuffle_v6f16_452367: ; GFX11-LABEL: shuffle_v6f16_452367:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_load_b96 v[4:6], v[0:1], off ; GFX11-NEXT: global_load_b96 v[4:6], v[0:1], off
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llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll

Show First 20 Lines • Show All 155 Lines • ▼ Show 20 Linesfor.end:
%r = fadd float %x_float, %v.endif %r = fadd float %x_float, %v.endif
ret float %r ret float %r
} }
; a loop inside an if-else ; a loop inside an if-else
define amdgpu_ps float @loop(i32 %z, float %v, i32 inreg %bound, ptr %extern_func, ptr %extern_func2) #0 { define amdgpu_ps float @loop(i32 %z, float %v, i32 inreg %bound, ptr %extern_func, ptr %extern_func2) #0 {
; SI-LABEL: loop: ; SI-LABEL: loop:
; SI: ; %bb.0: ; %main_body ; SI: ; %bb.0: ; %main_body
; SI-NEXT: v_mov_b32_e32 v6, v0
; SI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 ; SI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; SI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 ; SI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; SI-NEXT: s_mov_b32 s14, -1 ; SI-NEXT: s_mov_b32 s14, -1
; SI-NEXT: v_mov_b32_e32 v0, v1 ; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v0
; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v6
; SI-NEXT: s_mov_b32 s15, 0x31c16000 ; SI-NEXT: s_mov_b32 s15, 0x31c16000
; SI-NEXT: s_add_u32 s12, s12, s1 ; SI-NEXT: s_add_u32 s12, s12, s1
; SI-NEXT: s_addc_u32 s13, s13, 0 ; SI-NEXT: s_addc_u32 s13, s13, 0
; SI-NEXT: s_mov_b32 s32, 0 ; SI-NEXT: s_mov_b32 s32, 0
; SI-NEXT: ; implicit-def: $vgpr1 ; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b32 s0, vcc_lo ; SI-NEXT: s_and_saveexec_b32 s0, vcc_lo
; SI-NEXT: s_xor_b32 s6, exec_lo, s0 ; SI-NEXT: s_xor_b32 s6, exec_lo, s0
; SI-NEXT: s_cbranch_execz .LBB3_4 ; SI-NEXT: s_cbranch_execnz .LBB3_3
; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: ; %bb.1: ; %Flow
; SI-NEXT: s_andn2_saveexec_b32 s6, s6
; SI-NEXT: s_cbranch_execnz .LBB3_6
; SI-NEXT: .LBB3_2: ; %end
; SI-NEXT: s_or_b32 exec_lo, exec_lo, s6
; SI-NEXT: s_branch .LBB3_9
; SI-NEXT: .LBB3_3: ; %else
; SI-NEXT: s_mov_b32 s7, exec_lo ; SI-NEXT: s_mov_b32 s7, exec_lo
; SI-NEXT: .LBB3_2: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: .LBB3_4: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_readfirstlane_b32 s4, v4 ; SI-NEXT: v_readfirstlane_b32 s4, v4
; SI-NEXT: v_readfirstlane_b32 s5, v5 ; SI-NEXT: v_readfirstlane_b32 s5, v5
; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[4:5] ; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[4:5]
; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo ; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo
; SI-NEXT: v_mov_b32_e32 v0, v1
; SI-NEXT: s_mov_b64 s[0:1], s[12:13] ; SI-NEXT: s_mov_b64 s[0:1], s[12:13]
; SI-NEXT: s_mov_b64 s[2:3], s[14:15] ; SI-NEXT: s_mov_b64 s[2:3], s[14:15]
; SI-NEXT: s_swappc_b64 s[30:31], s[4:5] ; SI-NEXT: s_swappc_b64 s[30:31], s[4:5]
; SI-NEXT: v_mov_b32_e32 v1, v0
; SI-NEXT: ; implicit-def: $vgpr4_vgpr5 ; SI-NEXT: ; implicit-def: $vgpr4_vgpr5
; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8 ; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8
; SI-NEXT: s_cbranch_execnz .LBB3_2 ; SI-NEXT: s_cbranch_execnz .LBB3_4
; SI-NEXT: ; %bb.3: ; SI-NEXT: ; %bb.5:
; SI-NEXT: s_mov_b32 exec_lo, s7 ; SI-NEXT: s_mov_b32 exec_lo, s7
; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2 ; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: .LBB3_4: ; %Flow
; SI-NEXT: s_andn2_saveexec_b32 s6, s6 ; SI-NEXT: s_andn2_saveexec_b32 s6, s6
; SI-NEXT: s_cbranch_execz .LBB3_8 ; SI-NEXT: s_cbranch_execz .LBB3_2
; SI-NEXT: ; %bb.5: ; %if ; SI-NEXT: .LBB3_6: ; %if
; SI-NEXT: s_mov_b32 s7, exec_lo ; SI-NEXT: s_mov_b32 s7, exec_lo
; SI-NEXT: .LBB3_6: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: .LBB3_7: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_readfirstlane_b32 s4, v2 ; SI-NEXT: v_readfirstlane_b32 s4, v2
; SI-NEXT: v_readfirstlane_b32 s5, v3 ; SI-NEXT: v_readfirstlane_b32 s5, v3
; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[2:3] ; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[2:3]
; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo ; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo
; SI-NEXT: v_mov_b32_e32 v0, v1
; SI-NEXT: s_mov_b64 s[0:1], s[12:13] ; SI-NEXT: s_mov_b64 s[0:1], s[12:13]
; SI-NEXT: s_mov_b64 s[2:3], s[14:15] ; SI-NEXT: s_mov_b64 s[2:3], s[14:15]
; SI-NEXT: s_swappc_b64 s[30:31], s[4:5] ; SI-NEXT: s_swappc_b64 s[30:31], s[4:5]
; SI-NEXT: v_mov_b32_e32 v1, v0
; SI-NEXT: ; implicit-def: $vgpr2_vgpr3 ; SI-NEXT: ; implicit-def: $vgpr2_vgpr3
; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8 ; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8
; SI-NEXT: s_cbranch_execnz .LBB3_6 ; SI-NEXT: s_cbranch_execnz .LBB3_7
; SI-NEXT: ; %bb.7: ; SI-NEXT: ; %bb.8:
; SI-NEXT: s_mov_b32 exec_lo, s7 ; SI-NEXT: s_mov_b32 exec_lo, s7
; SI-NEXT: .LBB3_8: ; %end
; SI-NEXT: s_or_b32 exec_lo, exec_lo, s6 ; SI-NEXT: s_or_b32 exec_lo, exec_lo, s6
; SI-NEXT: v_mov_b32_e32 v0, v1 ; SI-NEXT: s_branch .LBB3_9
; SI-NEXT: ; return to shader part epilog ; SI-NEXT: .LBB3_9:
main_body: main_body:
%cc = icmp sgt i32 %z, 5 %cc = icmp sgt i32 %z, 5
br i1 %cc, label %if, label %else br i1 %cc, label %if, label %else
if: if:
%v.if = call amdgpu_gfx float %extern_func(float %v) %v.if = call amdgpu_gfx float %extern_func(float %v)
br label %end br label %end
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