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Differential D141689

[AArch64] Update 2 RME MEC instruction encodings
ClosedPublic

Authored by keith.walker.arm on Jan 13 2023, 6:46 AM.

Details

Reviewers
lenary
vhscampos
Commits
rGd86f1a982e84: [AArch64] Update 2 RME MEC instruction encodings
Summary

The encodings of these 2 RME MEC instructions are
incorrect and need swapping:

  • DC CIPAE
  • DC CIGDPAE

The correct encoding is:

Operation op0 op1 CRn CRm op2
DC CIPAE, Xt 0b01 0b100 0b0111 0b1110 0b000
DC CIGDPAE, Xt 0b01 0b100 0b0111 0b1110 0b111

Diff Detail

Unit TestsFailed

TimeTest
60,270 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded::vloxseg.c
60,220 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded::vluxseg.c
60,310 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded::vloxseg.c
60,220 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded::vluxseg.c
20 msx64 debian > SanitizerCommon-asan-x86_64-Linux.SanitizerCommon-asan-x86_64-Linux::printf-ldbl.c
View Full Test Results (9 Failed)

Event Timeline

keith.walker.arm created this revision.Jan 13 2023, 6:46 AM
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lenary accepted this revision.Jan 13 2023, 7:04 AM
This revision is now accepted and ready to land.Jan 13 2023, 7:04 AM
This revision was landed with ongoing or failed builds.Jan 13 2023, 7:20 AM
Closed by commit rGd86f1a982e84: [AArch64] Update 2 RME MEC instruction encodings (authored by keith.walker.arm). · Explain Why
This revision was automatically updated to reflect the committed changes.
keith.walker.arm added a commit: rGd86f1a982e84: [AArch64] Update 2 RME MEC instruction encodings.
Harbormaster completed remote builds in B207631: Diff 488986.Jan 13 2023, 8:01 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
4 lines
test/
MC/
AArch64/
4 lines
Disassembler/
AArch64/
8 lines

Diff 488986

llvm/lib/Target/AArch64/AArch64SystemOperands.td

Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
def : DC<"CGDVAC", 0b011, 0b0111, 0b1010, 0b101>; def : DC<"CGDVAC", 0b011, 0b0111, 0b1010, 0b101>;
def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>; def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>;
def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>; def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>;
def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>; def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>;
def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>; def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>;
} }
let Requires = [{ {AArch64::FeatureMEC} }] in { let Requires = [{ {AArch64::FeatureMEC} }] in {
def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b000>; def : DC<"CIPAE", 0b100, 0b0111, 0b1110, 0b000>;
def : DC<"CIPAE", 0b100, 0b0111, 0b1110, 0b111>; def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b111>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// IC (instruction cache maintenance) instruction options. // IC (instruction cache maintenance) instruction options.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2,
bit needsreg> : SearchableTable { bit needsreg> : SearchableTable {
▲ Show 20 Lines • Show All 1,730 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/armv9a-mec.s

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
msr VMECID_A_EL2, x0 msr VMECID_A_EL2, x0
// CHECK: msr VMECID_A_EL2, x0 // encoding: [0x20,0xa9,0x1c,0xd5] // CHECK: msr VMECID_A_EL2, x0 // encoding: [0x20,0xa9,0x1c,0xd5]
// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate // CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
msr MECID_RL_A_EL3, x0 msr MECID_RL_A_EL3, x0
// CHECK: msr MECID_RL_A_EL3, x0 // encoding: [0x20,0xaa,0x1e,0xd5] // CHECK: msr MECID_RL_A_EL3, x0 // encoding: [0x20,0xaa,0x1e,0xd5]
// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate // CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
dc cigdpae, x0 dc cigdpae, x0
// CHECK: dc cigdpae, x0 // encoding: [0x00,0x7e,0x0c,0xd5] // CHECK: dc cigdpae, x0 // encoding: [0xe0,0x7e,0x0c,0xd5]
// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIGDPAE requires: mec // CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIGDPAE requires: mec
dc cipae, x0 dc cipae, x0
// CHECK: dc cipae, x0 // encoding: [0xe0,0x7e,0x0c,0xd5] // CHECK: dc cipae, x0 // encoding: [0x00,0x7e,0x0c,0xd5]
// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIPAE requires: mec // CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIPAE requires: mec

llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
# CHECK: msr VMECID_P_EL2, x0 # CHECK: msr VMECID_P_EL2, x0
# CHECK-NO-MEC: msr S3_4_C10_C9_0, x0 # CHECK-NO-MEC: msr S3_4_C10_C9_0, x0
[0x20,0xa9,0x1c,0xd5] [0x20,0xa9,0x1c,0xd5]
# CHECK: msr VMECID_A_EL2, x0 # CHECK: msr VMECID_A_EL2, x0
# CHECK-NO-MEC: msr S3_4_C10_C9_1, x0 # CHECK-NO-MEC: msr S3_4_C10_C9_1, x0
[0x20,0xaa,0x1e,0xd5] [0x20,0xaa,0x1e,0xd5]
# CHECK: msr MECID_RL_A_EL3, x0 # CHECK: msr MECID_RL_A_EL3, x0
# CHECK-NO-MEC: msr S3_6_C10_C10_1, x0 # CHECK-NO-MEC: msr S3_6_C10_C10_1, x0
[0x00,0x7e,0x0c,0xd5]
# CHECK: dc cigdpae, x0
# CHECK-NO-MEC: sys #4, c7, c14, #0, x0
[0xe0,0x7e,0x0c,0xd5] [0xe0,0x7e,0x0c,0xd5]
# CHECK: dc cipae, x0 # CHECK: dc cigdpae, x0
# CHECK-NO-MEC: sys #4, c7, c14, #7, x0 # CHECK-NO-MEC: sys #4, c7, c14, #7, x0
[0x00,0x7e,0x0c,0xd5]
# CHECK: dc cipae, x0
# CHECK-NO-MEC: sys #4, c7, c14, #0, x0