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Differential D141405

[ARM] Accept two-register form of vnmul
ClosedPublic

Authored by JiruiWu on Jan 10 2023, 9:12 AM.

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lenary
olista01
Commits
rG75d43d383450: [ARM] Accept two-register form of vnmul
Summary

The previous vnmul only accepts three registers. It should accept either
two or three registers as vmul does.

Diff Detail

Event Timeline

JiruiWu created this revision.Jan 10 2023, 9:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 10 2023, 9:12 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
JiruiWu requested review of this revision.Jan 10 2023, 9:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 10 2023, 9:12 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B206822: Diff 487839.Jan 10 2023, 11:17 AM
olista01 added inline comments.Jan 12 2023, 2:58 AM
llvm/test/MC/Disassembler/ARM/fp-encoding.txt
31

Please add tests for the .f32 and .f16 versions of the instruction too.

JiruiWu updated this revision to Diff 488616.Jan 12 2023, 5:19 AM

Added tests for the .f32 and .f16 versions of the vnmul instruction.

JiruiWu marked an inline comment as done.Jan 12 2023, 5:22 AM
Harbormaster completed remote builds in B207377: Diff 488616.Jan 12 2023, 8:14 AM
olista01 accepted this revision.Jan 13 2023, 6:28 AM

LGTM

This revision is now accepted and ready to land.Jan 13 2023, 6:28 AM
Closed by commit rG75d43d383450: [ARM] Accept two-register form of vnmul (authored by JiruiWu, committed by ostannard). · Explain WhyJan 13 2023, 7:17 AM
This revision was automatically updated to reflect the committed changes.
ostannard added a commit: rG75d43d383450: [ARM] Accept two-register form of vnmul.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
3 lines
test/
MC/
ARM/
4 lines
4 lines
Disassembler/
ARM/
6 lines
3 lines
3 lines

Diff 488997

llvm/lib/Target/ARM/ARMInstrVFP.td

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let TwoOperandAliasConstraint = "$Sn = $Sd" in let TwoOperandAliasConstraint = "$Sn = $Sd" in
def VMULH : AHbI<0b11100, 0b10, 0, 0, def VMULH : AHbI<0b11100, 0b10, 0, 0,
(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm", IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm",
[(set (f16 HPR:$Sd), (fmul (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, [(set (f16 HPR:$Sd), (fmul (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>; Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>;
let TwoOperandAliasConstraint = "$Dn = $Dd" in
def VNMULD : ADbI<0b11100, 0b10, 1, 0, def VNMULD : ADbI<0b11100, 0b10, 1, 0,
(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
[(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>, [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>,
Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>; Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>;
let TwoOperandAliasConstraint = "$Sn = $Sd" in
def VNMULS : ASbI<0b11100, 0b10, 1, 0, def VNMULS : ASbI<0b11100, 0b10, 1, 0,
(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
[(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>, [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>,
Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> { Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> {
// Some single precision VFP instructions may be executed on both NEON and // Some single precision VFP instructions may be executed on both NEON and
// VFP pipelines on A8. // VFP pipelines on A8.
let D = VFPNeonA8Domain; let D = VFPNeonA8Domain;
} }
let TwoOperandAliasConstraint = "$Sn = $Sd" in
def VNMULH : AHbI<0b11100, 0b10, 1, 0, def VNMULH : AHbI<0b11100, 0b10, 1, 0,
(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm", IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",
[(set (f16 HPR:$Sd), (fneg (fmul (f16 HPR:$Sn), (f16 HPR:$Sm))))]>, [(set (f16 HPR:$Sd), (fneg (fmul (f16 HPR:$Sn), (f16 HPR:$Sm))))]>,
Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>; Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>;
multiclass vsel_inst<string op, bits<2> opc, int CC> { multiclass vsel_inst<string op, bits<2> opc, int CC> {
let DecoderNamespace = "VFPV8", PostEncoderMethod = "", let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
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llvm/test/MC/ARM/fullfp16.s

Show All 17 Lines@ THUMB: vdiv.f16 s0, s1, s0 @ encoding: [0x80,0xee,0x80,0x09]
vmul.f16 s0, s1, s0 vmul.f16 s0, s1, s0
@ ARM: vmul.f16 s0, s1, s0 @ encoding: [0x80,0x09,0x20,0xee] @ ARM: vmul.f16 s0, s1, s0 @ encoding: [0x80,0x09,0x20,0xee]
@ THUMB: vmul.f16 s0, s1, s0 @ encoding: [0x20,0xee,0x80,0x09] @ THUMB: vmul.f16 s0, s1, s0 @ encoding: [0x20,0xee,0x80,0x09]
vnmul.f16 s0, s1, s0 vnmul.f16 s0, s1, s0
@ ARM: vnmul.f16 s0, s1, s0 @ encoding: [0xc0,0x09,0x20,0xee] @ ARM: vnmul.f16 s0, s1, s0 @ encoding: [0xc0,0x09,0x20,0xee]
@ THUMB: vnmul.f16 s0, s1, s0 @ encoding: [0x20,0xee,0xc0,0x09] @ THUMB: vnmul.f16 s0, s1, s0 @ encoding: [0x20,0xee,0xc0,0x09]
vnmul.f16 s0, s1
@ ARM: vnmul.f16 s0, s0, s1 @ encoding: [0x60,0x09,0x20,0xee]
@ THUMB: vnmul.f16 s0, s0, s1 @ encoding: [0x20,0xee,0x60,0x09]
vmla.f16 s1, s2, s0 vmla.f16 s1, s2, s0
@ ARM: vmla.f16 s1, s2, s0 @ encoding: [0x00,0x09,0x41,0xee] @ ARM: vmla.f16 s1, s2, s0 @ encoding: [0x00,0x09,0x41,0xee]
@ THUMB: vmla.f16 s1, s2, s0 @ encoding: [0x41,0xee,0x00,0x09] @ THUMB: vmla.f16 s1, s2, s0 @ encoding: [0x41,0xee,0x00,0x09]
vmls.f16 s1, s2, s0 vmls.f16 s1, s2, s0
@ ARM: vmls.f16 s1, s2, s0 @ encoding: [0x40,0x09,0x41,0xee] @ ARM: vmls.f16 s1, s2, s0 @ encoding: [0x40,0x09,0x41,0xee]
@ THUMB: vmls.f16 s1, s2, s0 @ encoding: [0x41,0xee,0x40,0x09] @ THUMB: vmls.f16 s1, s2, s0 @ encoding: [0x41,0xee,0x40,0x09]
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llvm/test/MC/ARM/simple-fp-encoding.s

Show All 28 Lines
@ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee] @ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
@ CHECK: vmul.f64 d20, d20, d17 @ encoding: [0xa1,0x4b,0x64,0xee] @ CHECK: vmul.f64 d20, d20, d17 @ encoding: [0xa1,0x4b,0x64,0xee]
@ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee] @ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
@ CHECK: vmul.f32 s11, s11, s21 @ encoding: [0xaa,0x5a,0x65,0xee] @ CHECK: vmul.f32 s11, s11, s21 @ encoding: [0xaa,0x5a,0x65,0xee]
vnmul.f64 d16, d17, d16 vnmul.f64 d16, d17, d16
vnmul.f32 s0, s1, s0 vnmul.f32 s0, s1, s0
vnmul.f64 d0, d1
vnmul.f32 s0, s1
@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee] @ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
@ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee] @ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
@ CHECK: vnmul.f64 d0, d0, d1 @ encoding: [0x41,0x0b,0x20,0xee]
@ CHECK: vnmul.f32 s0, s0, s1 @ encoding: [0x60,0x0a,0x20,0xee]
vcmp.f64 d17, d16 vcmp.f64 d17, d16
vcmp.f32 s1, s0 vcmp.f32 s1, s0
@ CHECK: vcmp.f64 d17, d16 @ encoding: [0x60,0x1b,0xf4,0xee] @ CHECK: vcmp.f64 d17, d16 @ encoding: [0x60,0x1b,0xf4,0xee]
@ CHECK: vcmp.f32 s1, s0 @ encoding: [0x40,0x0a,0xf4,0xee] @ CHECK: vcmp.f32 s1, s0 @ encoding: [0x40,0x0a,0xf4,0xee]
vcmp.f64 d17, #0.0 vcmp.f64 d17, #0.0
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llvm/test/MC/Disassembler/ARM/fp-encoding.txt

Show All 21 Lines
# CHECK: vmul.f64 d16, d17, d16 # CHECK: vmul.f64 d16, d17, d16
0x80 0x0a 0x20 0xee 0x80 0x0a 0x20 0xee
# CHECK: vmul.f32 s0, s1, s0 # CHECK: vmul.f32 s0, s1, s0
0xe0 0x0b 0x61 0xee 0xe0 0x0b 0x61 0xee
# CHECK: vnmul.f64 d16, d17, d16 # CHECK: vnmul.f64 d16, d17, d16
0x41 0x0b 0x20 0xee
# CHECK: vnmul.f64 d0, d0, d1
olista01Unsubmitted
Done
ReplyInline Actions

Please add tests for the .f32 and .f16 versions of the instruction too.

olista01: Please add tests for the .f32 and .f16 versions of the instruction too.
0xc0 0x0a 0x20 0xee 0xc0 0x0a 0x20 0xee
# CHECK: vnmul.f32 s0, s1, s0 # CHECK: vnmul.f32 s0, s1, s0
0x60 0x0a 0x20 0xee
# CHECK: vnmul.f32 s0, s0, s1
0xe0 0x1b 0xf4 0xee 0xe0 0x1b 0xf4 0xee
# CHECK: vcmpe.f64 d17, d16 # CHECK: vcmpe.f64 d17, d16
0xc0 0x0a 0xf4 0xee 0xc0 0x0a 0xf4 0xee
# CHECK: vcmpe.f32 s1, s0 # CHECK: vcmpe.f32 s1, s0
0xe0 0x0b 0xf0 0xee 0xe0 0x0b 0xf0 0xee
# CHECK: vabs.f64 d16, d16 # CHECK: vabs.f64 d16, d16
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llvm/test/MC/Disassembler/ARM/fullfp16-arm.txt

Show All 9 Lines
[0x80,0x09,0x80,0xee] [0x80,0x09,0x80,0xee]
# CHECK: vmul.f16 s0, s1, s0 # CHECK: vmul.f16 s0, s1, s0
[0x80,0x09,0x20,0xee] [0x80,0x09,0x20,0xee]
# CHECK: vnmul.f16 s0, s1, s0 # CHECK: vnmul.f16 s0, s1, s0
[0xc0,0x09,0x20,0xee] [0xc0,0x09,0x20,0xee]
# CHECK: vnmul.f16 s0, s0, s1
[0x60,0x09,0x20,0xee]
# CHECK: vmla.f16 s1, s2, s0 # CHECK: vmla.f16 s1, s2, s0
[0x00,0x09,0x41,0xee] [0x00,0x09,0x41,0xee]
# CHECK: vmls.f16 s1, s2, s0 # CHECK: vmls.f16 s1, s2, s0
[0x40,0x09,0x41,0xee] [0x40,0x09,0x41,0xee]
# CHECK: vnmla.f16 s1, s2, s0 # CHECK: vnmla.f16 s1, s2, s0
[0x40,0x09,0x51,0xee] [0x40,0x09,0x51,0xee]
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llvm/test/MC/Disassembler/ARM/fullfp16-thumb.txt

Show All 9 Lines
[0x80,0xee,0x80,0x09] [0x80,0xee,0x80,0x09]
# CHECK: vmul.f16 s0, s1, s0 # CHECK: vmul.f16 s0, s1, s0
[0x20,0xee,0x80,0x09] [0x20,0xee,0x80,0x09]
# CHECK: vnmul.f16 s0, s1, s0 # CHECK: vnmul.f16 s0, s1, s0
[0x20,0xee,0xc0,0x09] [0x20,0xee,0xc0,0x09]
# CHECK: vnmul.f16 s0, s0, s1
[0x20,0xee,0x60,0x09]
# CHECK: vmla.f16 s1, s2, s0 # CHECK: vmla.f16 s1, s2, s0
[0x41,0xee,0x00,0x09] [0x41,0xee,0x00,0x09]
# CHECK: vmls.f16 s1, s2, s0 # CHECK: vmls.f16 s1, s2, s0
[0x41,0xee,0x40,0x09] [0x41,0xee,0x40,0x09]
# CHECK: vnmla.f16 s1, s2, s0 # CHECK: vnmla.f16 s1, s2, s0
[0x51,0xee,0x40,0x09] [0x51,0xee,0x40,0x09]
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