[AArch64] Make CNTPCTSS_EL0 and CNTVCTSS_EL0 system registers read-only

[pratlucas]

Summary

The CNTPCTSS_EL0 and CNTVCTSS_EL0 system registers, part of
Armv8.6-A's Enhanced Counter Virtualization extension (FEAT_ECV), are
described as read-only in the Arm ARM. This updates their implementation
to match the spec.

Original patch by Simon Tatham.

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 
 // v8.6a Enhanced Counter Virtualization
 //                                 Op0   Op1    CRn     CRm     Op2
 let Requires = [{ {AArch64::FeatureEnhancedCounterVirtualization} }] in {
 def : RWSysReg<"CNTSCALE_EL2",     0b11, 0b100, 0b1110, 0b0000, 0b100>;
 def : RWSysReg<"CNTISCALE_EL2",    0b11, 0b100, 0b1110, 0b0000, 0b101>;
 def : RWSysReg<"CNTPOFF_EL2",      0b11, 0b100, 0b1110, 0b0000, 0b110>;
 def : RWSysReg<"CNTVFRQ_EL2",      0b11, 0b100, 0b1110, 0b0000, 0b111>;
-def : RWSysReg<"CNTPCTSS_EL0",     0b11, 0b011, 0b1110, 0b0000, 0b101>;
-def : RWSysReg<"CNTVCTSS_EL0",     0b11, 0b011, 0b1110, 0b0000, 0b110>;
+def : ROSysReg<"CNTPCTSS_EL0",     0b11, 0b011, 0b1110, 0b0000, 0b101>;
+def : ROSysReg<"CNTVCTSS_EL0",     0b11, 0b011, 0b1110, 0b0000, 0b110>;
 }
 
 // v8.7a LD64B/ST64B Accelerator Extension system register
 let Requires = [{ {AArch64::FeatureLS64} }] in
 def : RWSysReg<"ACCDATA_EL1",       0b11, 0b000, 0b1101, 0b0000, 0b101>;
 
 // Branch Record Buffer system registers
 let Requires = [{ {AArch64::FeatureBRBE} }] in {

llvm/test/MC/AArch64/armv8.6a-ecv.s

-// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+ecv   < %s | FileCheck %s
-// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding  < %s 2>&1         | FileCheck %s --check-prefix=NOECV
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+ecv   < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64 -show-encoding               < %s 2> %t | FileCheck --check-prefix=NOECV-OUT %s
+// RUN: FileCheck --check-prefix=NOECV %s < %t
 
+// Expect no successful code generation at all with ECV disabled
+// NOECV-OUT-NOT: {{msr|mrs}}
+
+// Writable system registers
 msr CNTSCALE_EL2, x1
 msr CNTISCALE_EL2, x11
 msr CNTPOFF_EL2, x22
 msr CNTVFRQ_EL2, x3
-msr CNTPCTSS_EL0, x13
-msr CNTVCTSS_EL0, x23
 // CHECK: msr     CNTSCALE_EL2, x1        // encoding: [0x81,0xe0,0x1c,0xd5]
 // CHECK: msr     CNTISCALE_EL2, x11      // encoding: [0xab,0xe0,0x1c,0xd5]
 // CHECK: msr     CNTPOFF_EL2, x22        // encoding: [0xd6,0xe0,0x1c,0xd5]
 // CHECK: msr     CNTVFRQ_EL2, x3         // encoding: [0xe3,0xe0,0x1c,0xd5]
-// CHECK: msr     CNTPCTSS_EL0, x13       // encoding: [0xad,0xe0,0x1b,0xd5]
-// CHECK: msr     CNTVCTSS_EL0, x23       // encoding: [0xd7,0xe0,0x1b,0xd5]
-// NOECV: error: expected writable system register or pstate
-// NOECV: error: expected writable system register or pstate
-// NOECV: error: expected writable system register or pstate
-// NOECV: error: expected writable system register or pstate
-// NOECV: error: expected writable system register or pstate
-// NOECV: error: expected writable system register or pstate
+// NOECV: :[[@LINE-8]]:5: error: expected writable system register or pstate
+// NOECV: :[[@LINE-8]]:5: error: expected writable system register or pstate
+// NOECV: :[[@LINE-8]]:5: error: expected writable system register or pstate
+// NOECV: :[[@LINE-8]]:5: error: expected writable system register or pstate
+
+// Readonly system registers: writing them gives an error even with
+// ECV enabled
+msr CNTPCTSS_EL0, x13
+msr CNTVCTSS_EL0, x23
+// ERROR: :[[@LINE-2]]:5: error: expected writable system register or pstate
+// ERROR: :[[@LINE-2]]:5: error: expected writable system register or pstate
+// NOECV: :[[@LINE-4]]:5: error: expected writable system register or pstate
+// NOECV: :[[@LINE-4]]:5: error: expected writable system register or pstate
 
 mrs x0, CNTSCALE_EL2
 mrs x5, CNTISCALE_EL2
 mrs x10, CNTPOFF_EL2
 mrs x15, CNTVFRQ_EL2
 mrs x20, CNTPCTSS_EL0
 mrs x30, CNTVCTSS_EL0
 // CHECK: mrs     x0, CNTSCALE_EL2        // encoding: [0x80,0xe0,0x3c,0xd5]
 // CHECK: mrs     x5, CNTISCALE_EL2       // encoding: [0xa5,0xe0,0x3c,0xd5]
 // CHECK: mrs     x10, CNTPOFF_EL2        // encoding: [0xca,0xe0,0x3c,0xd5]
 // CHECK: mrs     x15, CNTVFRQ_EL2        // encoding: [0xef,0xe0,0x3c,0xd5]
 // CHECK: mrs     x20, CNTPCTSS_EL0       // encoding: [0xb4,0xe0,0x3b,0xd5]
 // CHECK: mrs     x30, CNTVCTSS_EL0       // encoding: [0xde,0xe0,0x3b,0xd5]
-// NOECV: error: expected readable system register
-// NOECV: error: expected readable system register
-// NOECV: error: expected readable system register
-// NOECV: error: expected readable system register
-// NOECV: error: expected readable system register
-// NOECV: error: expected readable system register
+// NOECV: :[[@LINE-12]]:9: error: expected readable system register
+// NOECV: :[[@LINE-12]]:9: error: expected readable system register
+// NOECV: :[[@LINE-12]]:10: error: expected readable system register
+// NOECV: :[[@LINE-12]]:10: error: expected readable system register
+// NOECV: :[[@LINE-12]]:10: error: expected readable system register
+// NOECV: :[[@LINE-12]]:10: error: expected readable system register

llvm/test/MC/Disassembler/AArch64/armv8.6a-ecv.txt

 # RUN: llvm-mc -triple=aarch64  -mattr=+ecv -disassemble < %s      | FileCheck %s
 # RUN: llvm-mc -triple=aarch64              -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOFGT
 
 [0x81,0xe0,0x1c,0xd5]
 [0xab,0xe0,0x1c,0xd5]
 [0xd6,0xe0,0x1c,0xd5]
 [0xe3,0xe0,0x1c,0xd5]
 [0xad,0xe0,0x1b,0xd5]
 [0xd7,0xe0,0x1b,0xd5]
 # CHECK: msr CNTSCALE_EL2, x1
 # CHECK: msr CNTISCALE_EL2, x11
 # CHECK: msr CNTPOFF_EL2, x22
 # CHECK: msr CNTVFRQ_EL2, x3
-# CHECK: msr CNTPCTSS_EL0, x13
-# CHECK: msr CNTVCTSS_EL0, x23
+# CHECK: msr S3_3_C14_C0_5, x13
+# CHECK: msr S3_3_C14_C0_6, x23
 # NOFGT: msr S3_4_C14_C0_4, x1
 # NOFGT: msr S3_4_C14_C0_5, x11
 # NOFGT: msr S3_4_C14_C0_6, x22
 # NOFGT: msr S3_4_C14_C0_7, x3
 # NOFGT: msr S3_3_C14_C0_5, x13
 # NOFGT: msr S3_3_C14_C0_6, x23
 
 [0x80,0xe0,0x3c,0xd5]