[DirectX backend] Remove unused bitcode block for dxil

[python3kgae]

Summary

DXIL doesn't need uselist strtab and symtab blocks which are not supported by llvm3.7 bitcode.

[beanz]

LGTM

llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.h

class BitcodeWriter {
   std::unique_ptr<BitstreamWriter> Stream;
 
   StringTableBuilder StrtabBuilder{StringTableBuilder::RAW};
 
   // Owns any strings created by the irsymtab writer until we create the
   // string table.
   BumpPtrAllocator Alloc;
 
-  bool WroteStrtab = false, WroteSymtab = false;
-
   void writeBlob(unsigned Block, unsigned Record, StringRef Blob);
 
   std::vector<Module *> Mods;
 
 public:
   /// Create a BitcodeWriter that writes to Buffer.
   BitcodeWriter(SmallVectorImpl<char> &Buffer, raw_fd_stream *FS = nullptr);
 
   ~BitcodeWriter();
 
-  /// Attempt to write a symbol table to the bitcode file. This must be called
-  /// at most once after all modules have been written.
-  ///
-  /// A reader does not require a symbol table to interpret a bitcode file;
-  /// the symbol table is needed only to improve link-time performance. So
-  /// this function may decide not to write a symbol table. It may so decide
-  /// if, for example, the target is unregistered or the IR is malformed.
-  void writeSymtab();
-
-  /// Write the bitcode file's string table. This must be called exactly once
-  /// after all modules and the optional symbol table have been written.
-  void writeStrtab();
-
-  /// Copy the string table for another module into this bitcode file. This
-  /// should be called after copying the module itself into the bitcode file.
-  void copyStrtab(StringRef Strtab);
-
   /// Write the specified module to the buffer specified at construction time.
   void writeModule(const Module &M);
 };
 
 /// Write the specified module to the specified raw output stream.
 ///
 /// For streams where it matters, the given stream should be in "binary"
 /// mode.
 void WriteDXILToFile(const Module &M, raw_ostream &Out);
 
 } // namespace dxil
 
 } // namespace llvm

llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp

void pushValue(const Value *V, unsigned InstID,
                  SmallVectorImpl<unsigned> &Vals);
   void pushValueSigned(const Value *V, unsigned InstID,
                        SmallVectorImpl<uint64_t> &Vals);
   void writeInstruction(const Instruction &I, unsigned InstID,
                         SmallVectorImpl<unsigned> &Vals);
   void writeFunctionLevelValueSymbolTable(const ValueSymbolTable &VST);
   void writeGlobalValueSymbolTable(
       DenseMap<const Function *, uint64_t> &FunctionToBitcodeIndex);
-  void writeUseList(UseListOrder &&Order);
-  void writeUseListBlock(const Function *F);
   void writeFunction(const Function &F);
   void writeBlockInfo();
 
   unsigned getEncodedSyncScopeID(SyncScope::ID SSID) { return unsigned(SSID); }
 
   unsigned getEncodedAlign(MaybeAlign Alignment) { return encode(Alignment); }
 
   unsigned getTypeID(Type *T, const Value *V = nullptr);
dxil::BitcodeWriter::BitcodeWriter(SmallVectorImpl<char> &Buffer,
   Stream->Emit((unsigned)'B', 8);
   Stream->Emit((unsigned)'C', 8);
   Stream->Emit(0x0, 4);
   Stream->Emit(0xC, 4);
   Stream->Emit(0xE, 4);
   Stream->Emit(0xD, 4);
 }
 
-dxil::BitcodeWriter::~BitcodeWriter() { assert(WroteStrtab); }
+dxil::BitcodeWriter::~BitcodeWriter() { }
 
 /// Write the specified module to the specified output stream.
 void dxil::WriteDXILToFile(const Module &M, raw_ostream &Out) {
   SmallVector<char, 0> Buffer;
   Buffer.reserve(256 * 1024);
 
   // If this is darwin or another generic macho target, reserve space for the
   // header.
   Triple TT(M.getTargetTriple());
   if (TT.isOSDarwin() || TT.isOSBinFormatMachO())
     Buffer.insert(Buffer.begin(), BWH_HeaderSize, 0);
 
   BitcodeWriter Writer(Buffer, dyn_cast<raw_fd_stream>(&Out));
   Writer.writeModule(M);
-  Writer.writeSymtab();
-  Writer.writeStrtab();
 
   // Write the generated bitstream to "Out".
   if (!Buffer.empty())
     Out.write((char *)&Buffer.front(), Buffer.size());
 }
 
 void BitcodeWriter::writeBlob(unsigned Block, unsigned Record, StringRef Blob) {
   Stream->EnterSubblock(Block, 3);
 
   auto Abbv = std::make_shared<BitCodeAbbrev>();
   Abbv->Add(BitCodeAbbrevOp(Record));
   Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Blob));
   auto AbbrevNo = Stream->EmitAbbrev(std::move(Abbv));
 
   Stream->EmitRecordWithBlob(AbbrevNo, ArrayRef<uint64_t>{Record}, Blob);
 
   Stream->ExitBlock();
 }
 
-void BitcodeWriter::writeSymtab() {
-  assert(!WroteStrtab && !WroteSymtab);
-
-  // If any module has module-level inline asm, we will require a registered asm
-  // parser for the target so that we can create an accurate symbol table for
-  // the module.
-  for (Module *M : Mods) {
-    if (M->getModuleInlineAsm().empty())
-      continue;
-  }
-
-  WroteSymtab = true;
-  SmallVector<char, 0> Symtab;
-  // The irsymtab::build function may be unable to create a symbol table if the
-  // module is malformed (e.g. it contains an invalid alias). Writing a symbol
-  // table is not required for correctness, but we still want to be able to
-  // write malformed modules to bitcode files, so swallow the error.
-  if (Error E = irsymtab::build(Mods, Symtab, StrtabBuilder, Alloc)) {
-    consumeError(std::move(E));
-    return;
-  }
-
-  writeBlob(bitc::SYMTAB_BLOCK_ID, bitc::SYMTAB_BLOB,
-            {Symtab.data(), Symtab.size()});
-}
-
-void BitcodeWriter::writeStrtab() {
-  assert(!WroteStrtab);
-
-  std::vector<char> Strtab;
-  StrtabBuilder.finalizeInOrder();
-  Strtab.resize(StrtabBuilder.getSize());
-  StrtabBuilder.write((uint8_t *)Strtab.data());
-
-  writeBlob(bitc::STRTAB_BLOCK_ID, bitc::STRTAB_BLOB,
-            {Strtab.data(), Strtab.size()});
-
-  WroteStrtab = true;
-}
-
-void BitcodeWriter::copyStrtab(StringRef Strtab) {
-  writeBlob(bitc::STRTAB_BLOCK_ID, bitc::STRTAB_BLOB, Strtab);
-  WroteStrtab = true;
-}
-
 void BitcodeWriter::writeModule(const Module &M) {
-  assert(!WroteStrtab);
 
   // The Mods vector is used by irsymtab::build, which requires non-const
   // Modules in case it needs to materialize metadata. But the bitcode writer
   // requires that the module is materialized, so we can cast to non-const here,
   // after checking that it is in fact materialized.
   assert(M.isMaterialized());
   Mods.push_back(const_cast<Module *>(&M));
 
for (const ValueName *SI : SortedTable) {
 
     // Emit the finished record.
     Stream.EmitRecord(Code, NameVals, AbbrevToUse);
     NameVals.clear();
   }
   Stream.ExitBlock();
 }
 
-void DXILBitcodeWriter::writeUseList(UseListOrder &&Order) {
-  assert(Order.Shuffle.size() >= 2 && "Shuffle too small");
-  unsigned Code;
-  if (isa<BasicBlock>(Order.V))
-    Code = bitc::USELIST_CODE_BB;
-  else
-    Code = bitc::USELIST_CODE_DEFAULT;
-
-  SmallVector<uint64_t, 64> Record(Order.Shuffle.begin(), Order.Shuffle.end());
-  Record.push_back(VE.getValueID(Order.V));
-  Stream.EmitRecord(Code, Record);
-}
-
-void DXILBitcodeWriter::writeUseListBlock(const Function *F) {
-  auto hasMore = [&]() {
-    return !VE.UseListOrders.empty() && VE.UseListOrders.back().F == F;
-  };
-  if (!hasMore())
-    // Nothing to do.
-    return;
-
-  Stream.EnterSubblock(bitc::USELIST_BLOCK_ID, 3);
-  while (hasMore()) {
-    writeUseList(std::move(VE.UseListOrders.back()));
-    VE.UseListOrders.pop_back();
-  }
-  Stream.ExitBlock();
-}
-
 /// Emit a function body to the module stream.
 void DXILBitcodeWriter::writeFunction(const Function &F) {
   Stream.EnterSubblock(bitc::FUNCTION_BLOCK_ID, 4);
   VE.incorporateFunction(F);
 
   SmallVector<unsigned, 64> Vals;
 
   // Emit the number of basic blocks, so the reader can create them ahead of
void DXILBitcodeWriter::writeFunction(const Function &F) {
 
   // Emit names for all the instructions etc.
   if (auto *Symtab = F.getValueSymbolTable())
     writeFunctionLevelValueSymbolTable(*Symtab);
 
   if (NeedsMetadataAttachment)
     writeFunctionMetadataAttachment(F);
 
-  writeUseListBlock(&F);
   VE.purgeFunction();
   Stream.ExitBlock();
 }
 
 // Emit blockinfo, which defines the standard abbreviations etc.
 void DXILBitcodeWriter::writeBlockInfo() {
   // We only want to emit block info records for blocks that have multiple
   // instances: CONSTANTS_BLOCK, FUNCTION_BLOCK and VALUE_SYMTAB_BLOCK.
void DXILBitcodeWriter::write() {
   // Emit metadata.
   writeModuleMetadata();
 
   // Emit names for globals/functions etc.
   // DXIL uses the same format for module-level value symbol table as for the
   // function level table.
   writeFunctionLevelValueSymbolTable(M.getValueSymbolTable());
 
-  // Emit module-level use-lists.
-  writeUseListBlock(nullptr);
-
   // Emit function bodies.
   for (const Function &F : M)
     if (!F.isDeclaration())
       writeFunction(F);
 
   Stream.ExitBlock();
 }

llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp

public:
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesAll();
   }
 };
 } // namespace
 
 char WriteDXILPass::ID = 0;
-INITIALIZE_PASS_BEGIN(WriteDXILPass, "write-bitcode", "Write Bitcode", false,
-                      true)
+INITIALIZE_PASS_BEGIN(WriteDXILPass, "dxil-write-bitcode", "Write Bitcode",
+                      false, true)
 INITIALIZE_PASS_DEPENDENCY(ModuleSummaryIndexWrapperPass)
-INITIALIZE_PASS_END(WriteDXILPass, "write-bitcode", "Write Bitcode", false,
+INITIALIZE_PASS_END(WriteDXILPass, "dxil-write-bitcode", "Write Bitcode", false,
                     true)
 
 ModulePass *llvm::createDXILWriterPass(raw_ostream &Str) {
   return new WriteDXILPass(Str);
 }
 
 char EmbedDXILPass::ID = 0;
 INITIALIZE_PASS(EmbedDXILPass, "dxil-embed", "Embed DXIL", false, true)
 
 ModulePass *llvm::createDXILEmbedderPass() { return new EmbedDXILPass(); }

llvm/lib/Target/DirectX/DirectXTargetMachine.cpp

 
 using namespace llvm;
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeDirectXTarget() {
   RegisterTargetMachine<DirectXTargetMachine> X(getTheDirectXTarget());
   auto *PR = PassRegistry::getPassRegistry();
   initializeDXILPrepareModulePass(*PR);
   initializeEmbedDXILPassPass(*PR);
+  initializeWriteDXILPassPass(*PR);
   initializeDXILOpLoweringLegacyPass(*PR);
   initializeDXILTranslateMetadataPass(*PR);
   initializeDXILResourceWrapperPass(*PR);
   initializeShaderFlagsAnalysisWrapperPass(*PR);
 }
 
 class DXILTargetObjectFile : public TargetLoweringObjectFile {
 public:

llvm/test/tools/dxil-dis/BasicIR.ll

 ; RUN: llc --filetype=obj %s -o - | dxil-dis -o - | FileCheck %s
 
+; RUN: llc --filetype=obj %s --stop-after=dxil-write-bitcode -o %t | llvm-bcanalyzer --dump-blockinfo %t | FileCheck %s  --check-prefix=BLOCK_INFO
+
 ; CHECK: define i32 @foo(i32 %X, i32 %Y) {
 ; CHECK:   %Z = sub i32 %X, %Y
 ; CHECK:   %Q = add i32 %Z, %Y
 ; CHECK:   ret i32 %Q
 ; CHECK: }
 
+; BLOCK_INFO:Stream type: LLVM IR
+; Make sure uselist strtab and symtab is not in dxil.
+; BLOCK_INFO-NOT:USELIST_BLOCK_ID
+; BLOCK_INFO-NOT:STRTAB_BLOCK
+; BLOCK_INFO-NOT:SYMTAB_BLOCK
+
+
 target triple = "dxil-unknown-shadermodel6.7-library"
 
 define i32 @foo(i32 %X, i32 %Y) {
   %Z = sub i32 %X, %Y
   %Q = add i32 %Z, %Y
   ret i32 %Q
 }