[mlir][spirv] Fix MLIR code snippet marker in TD files

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td

let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     atomic-compare-exchange-op ::=
         `spirv.AtomicCompareExchange` scope memory-semantics memory-semantics
                                     ssa-use `,` ssa-use `,` ssa-use
                                     `:` spv-pointer-type
-    ```mlir
+    ```
 
     #### Example:
 
     ```
     %0 = spirv.AtomicCompareExchange "Workgroup" "Acquire" "None"
                                     %pointer, %value, %comparator
                                     : !spirv.ptr<i32, WorkGroup>
     ```
let description = [{
     Memory is a memory Scope.
 
     <!-- End of AutoGen section -->
 
      ```
     atomic-exchange-op ::=
         `spirv.AtomicCompareExchange` scope memory-semantics
                                     ssa-use `,` ssa-use `:` spv-pointer-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.AtomicExchange "Workgroup" "Acquire" %pointer, %value,
                             : !spirv.ptr<i32, WorkGroup>
     ```
   }];
 
   let arguments = (ins
     SPIRV_AnyPtr:$pointer,
     SPIRV_ScopeAttr:$memory_scope,
atomic-fadd-op ::=
                             ssa-use `,` ssa-use `:` spv-pointer-type
     ```
 
     #### Example:
 
     ```mlir
     %0 = spirv.EXT.AtomicFAdd "Device" "None" %pointer, %value :
                            !spirv.ptr<f32, StorageBuffer>
-    ```mlir
+    ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[SPV_EXT_shader_atomic_float_add]>,
     Capability<[SPIRV_C_AtomicFloat16AddEXT, SPIRV_C_AtomicFloat32AddEXT, SPIRV_C_AtomicFloat64AddEXT]>
   ];

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td

let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     float-scalar-vector-type ::= float-type |
                                  `vector<` integer-literal `x` float-type `>`
     ceil-op ::= ssa-id `=` `spirv.CL.ceil` ssa-use `:`
                float-scalar-vector-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %2 = spirv.CL.ceil %0 : f32
     %3 = spirv.CL.ceil %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     float-scalar-vector-type ::= float-type |
                                  `vector<` integer-literal `x` float-type `>`
     cos-op ::= ssa-id `=` `spirv.CL.cos` ssa-use `:`
                float-scalar-vector-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %2 = spirv.CL.cos %0 : f32
     %3 = spirv.CL.cos %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     float-scalar-vector-type ::= float-type |
                                  `vector<` integer-literal `x` float-type `>`
     erf-op ::= ssa-id `=` `spirv.CL.erf` ssa-use `:`
                float-scalar-vector-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %2 = spirv.CL.erf %0 : f32
     %3 = spirv.CL.erf %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     float-scalar-vector-type ::= float-type |
                                  `vector<` integer-literal `x` float-type `>`
     floor-op ::= ssa-id `=` `spirv.CL.floor` ssa-use `:`
                float-scalar-vector-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %2 = spirv.CL.floor %0 : f32
     %3 = spirv.CL.ceifloorl %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
let description = [{
     All of the operands, including the Result Type operand, must be of the
     same type.
 
     <!-- End of AutoGen section -->
 
     ```
     fma-op ::= ssa-id `=` `spirv.CL.fma` ssa-use, ssa-use, ssa-use `:`
                float-scalar-vector-type
-    ```mlir
-
     ```
+
+    #### Example:
+
+    ```mlir
     %0 = spirv.CL.fma %a, %b, %c : f32
     %1 = spirv.CL.fma %a, %b, %c : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     float-scalar-vector-type ::= float-type |
                                  `vector<` integer-literal `x` float-type `>`
     log-op ::= ssa-id `=` `spirv.CL.log` ssa-use `:`
                float-scalar-vector-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %2 = spirv.CL.log %0 : f32
     %3 = spirv.CL.log %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     float-scalar-vector-type ::= float-type |
                                  `vector<` integer-literal `x` float-type `>`
     rsqrt-op ::= ssa-id `=` `spirv.CL.rsqrt` ssa-use `:`
                float-scalar-vector-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %2 = spirv.CL.rsqrt %0 : f32
     %3 = spirv.CL.rsqrt %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     float-scalar-vector-type ::= float-type |
                                  `vector<` integer-literal `x` float-type `>`
     sin-op ::= ssa-id `=` `spirv.CL.sin` ssa-use `:`
                float-scalar-vector-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %2 = spirv.CL.sin %0 : f32
     %3 = spirv.CL.sin %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     float-scalar-vector-type ::= float-type |
                                  `vector<` integer-literal `x` float-type `>`
     sqrt-op ::= ssa-id `=` `spirv.CL.sqrt` ssa-use `:`
                float-scalar-vector-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %2 = spirv.CL.sqrt %0 : f32
     %3 = spirv.CL.sqrt %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     float-scalar-vector-type ::= float-type |
                                  `vector<` integer-literal `x` float-type `>`
     tanh-op ::= ssa-id `=` `spirv.CL.tanh` ssa-use `:`
                float-scalar-vector-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %2 = spirv.CL.tanh %0 : f32
     %3 = spirv.CL.tanh %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td

let description = [{
     the cast fails, the instruction result is an OpConstantNull pointer in
     the Storage Storage Class.
 
     Storage must be one of the following literal values from Storage Class:
     Workgroup, CrossWorkgroup, or Function.
 
     <!-- End of AutoGen section -->
 
-    ```
-    [TODO]
-    ```mlir
-
     #### Example:
 
     ```mlir
        %1 = spirv.GenericCastToPtrExplicitOp %0 : !spirv.ptr<f32, Generic> to
        !spirv.ptr<f32, CrossWorkGroup>
     ```
   }];
 

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td

let description = [{
     <!-- End of AutoGen section -->
 
     ```
     scalar-type ::= integer-type | float-type | boolean-type
     vector-insert-dynamic-op ::= `spirv.VectorInsertDynamic ` ssa-use `,`
                                   ssa-use `[` ssa-use `]`
                                   `:` `vector<` integer-literal `x` scalar-type `>` `,`
                                   integer-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %scalar = ... : f32
     %2 = spirv.VectorInsertDynamic %scalar %0[%1] : f32, vector<8xf32>, i32
     ```
   }];
 
   let arguments = (ins
     SPIRV_Vector:$vector,
     SPIRV_Scalar:$component,

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td

let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     scope ::= `"Workgroup"` | `"Subgroup"`
     operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
     op ::= ssa-id `=` `spirv.KHR.GroupFMul` scope operation ssa-use
                             `:` float-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.KHR.GroupFMul <Workgroup> <Reduce> %value : f32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
let description = [{
     scope ::= `"Workgroup"` | `"Subgroup"`
     integer-float-scalar-vector-type ::= integer-type | float-type |
                                `vector<` integer-literal `x` integer-type `>` |
                                `vector<` integer-literal `x` float-type `>`
     localid-type ::= integer-type |
                    `vector<` integer-literal `x` integer-type `>`
     group-broadcast-op ::= ssa-id `=` `spirv.GroupBroadcast` scope ssa_use,
                    ssa_use `:` integer-float-scalar-vector-type `,` localid-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %scalar_value = ... : f32
     %vector_value = ... : vector<4xf32>
     %scalar_localid = ... : i32
     %vector_localid = ... : vector<3xi32>
     %0 = spirv.GroupBroadcast "Subgroup" %scalar_value, %scalar_localid : f32, i32
     %1 = spirv.GroupBroadcast "Workgroup" %vector_value, %vector_localid :
       vector<4xf32>, vector<3xi32>
     ```
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     scope ::= `"Workgroup"` | `"Subgroup"`
     operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
     op ::= ssa-id `=` `spirv.GroupFAdd` scope operation ssa-use
                             `:` float-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.GroupFAdd <Workgroup> <Reduce> %value : f32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     scope ::= `"Workgroup"` | `"Subgroup"`
     operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
     op ::= ssa-id `=` `spirv.GroupFMax` scope operation ssa-use
                             `:` float-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.GroupFMax <Workgroup> <Reduce> %value : f32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     scope ::= `"Workgroup"` | `"Subgroup"`
     operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
     op ::= ssa-id `=` `spirv.GroupFMin` scope operation ssa-use
                             `:` float-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.GroupFMin <Workgroup> <Reduce> %value : f32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     scope ::= `"Workgroup"` | `"Subgroup"`
     operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
     op ::= ssa-id `=` `spirv.GroupIAdd` scope operation ssa-use
                             `:` integer-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.GroupIAdd <Workgroup> <Reduce> %value : i32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     scope ::= `"Workgroup"` | `"Subgroup"`
     operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
     op ::= ssa-id `=` `spirv.KHR.GroupIMul` scope operation ssa-use
                             `:` integer-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.KHR.GroupIMul <Workgroup> <Reduce> %value : i32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     scope ::= `"Workgroup"` | `"Subgroup"`
     operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
     op ::= ssa-id `=` `spirv.GroupSMax` scope operation ssa-use
                             `:` integer-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.GroupSMax <Workgroup> <Reduce> %value : i32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     scope ::= `"Workgroup"` | `"Subgroup"`
     operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
     op ::= ssa-id `=` `spirv.GroupSMin` scope operation ssa-use
                             `:` integer-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.GroupSMin <Workgroup> <Reduce> %value : i32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     scope ::= `"Workgroup"` | `"Subgroup"`
     operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
     op ::= ssa-id `=` `spirv.GroupUMax` scope operation ssa-use
                             `:` integer-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.GroupUMax <Workgroup> <Reduce> %value : i32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     scope ::= `"Workgroup"` | `"Subgroup"`
     operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
     op ::= ssa-id `=` `spirv.GroupUMin` scope operation ssa-use
                             `:` integer-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.GroupUMin <Workgroup> <Reduce> %value : i32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
let description = [{
 
     The type of Ptr must be a pointer type, and must point to a scalar type.
 
     <!-- End of AutoGen section -->
 
     ```
     subgroup-block-read-INTEL-op ::= ssa-id `=` `spirv.INTEL.SubgroupBlockRead`
                                 storage-class ssa_use `:` spirv-element-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.INTEL.SubgroupBlockRead "StorageBuffer" %ptr : i32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[SPV_INTEL_subgroups]>,
let description = [{
 
     The component type of Data must be equal to the type pointed to by Ptr.
 
     <!-- End of AutoGen section -->
 
     ```
     subgroup-block-write-INTEL-op ::= ssa-id `=` `spirv.INTEL.SubgroupBlockWrite`
                       storage-class ssa_use `,` ssa-use `:` spirv-element-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %ptr, %value : i32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[SPV_INTEL_subgroups]>,

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td

let description = [{
      Results are computed per component.
 
     <!-- End of AutoGen section -->
 
     ```
     float-scalar-vector-type ::= float-type |
                                  `vector<` integer-literal `x` float-type `>`
     ordered-op ::= ssa-id `=` `spirv.Ordered` ssa-use, ssa-use
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %4 = spirv.Ordered %0, %1 : f32
     %5 = spirv.Ordered %2, %3 : vector<4xf32>
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
let description = [{
     ```
     integer-scalar-vector-type ::= integer-type |
                                  `vector<` integer-literal `x` integer-type `>`
     sgreater-than-equal-op ::= ssa-id `=` `spirv.SGreaterThanEqual` ssa-use, ssa-use
                                           `:` integer-scalar-vector-type
     ```
     #### Example:
 
-    ```
+    ```mlir
     %4 = spirv.SGreaterThanEqual %0, %1 : i32
     %5 = spirv.SGreaterThanEqual %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
let description = [{
      Results are computed per component.
 
     <!-- End of AutoGen section -->
 
     ```
     float-scalar-vector-type ::= float-type |
                                  `vector<` integer-literal `x` float-type `>`
     unordered-op ::= ssa-id `=` `spirv.Unordered` ssa-use, ssa-use
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %4 = spirv.Unordered %0, %1 : f32
     %5 = spirv.Unordered %2, %3 : vector<4xf32>
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td

let description = [{
     number of columns in Result Type. Its columns must have the same number
     of components as the number of columns in LeftMatrix.
 
     <!-- End of AutoGen section -->
 
     ```
     matrix-times-matrix-op ::= ssa-id `=` `spirv.MatrixTimesMatrix` ssa-use,
     ssa-use `:` matrix-type `,` matrix-type `->` matrix-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.MatrixTimesMatrix %matrix_1, %matrix_2 :
         !spirv.matrix<4 x vector<3xf32>>, !spirv.matrix<3 x vector<4xf32>> ->
         !spirv.matrix<4 x vector<4xf32>>
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
let description = [{
     matrix-times-scalar-op ::= ssa-id `=` `spirv.MatrixTimesScalar` ssa-use,
     ssa-use `:` matrix-type `,` float-type `->` matrix-type
 
     ```
 
     #### Example:
 
     ```mlir
-
     %0 = spirv.MatrixTimesScalar %matrix, %scalar :
     !spirv.matrix<3 x vector<3xf32>>, f32 -> !spirv.matrix<3 x vector<3xf32>>
 
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
let description = [{
 
     Matrix must have of type of OpTypeMatrix.
 
     <!-- End of AutoGen section -->
 
     ```
     transpose-op ::= ssa-id `=` `spirv.Transpose` ssa-use `:` matrix-type `->`
     matrix-type
+    ```
 
-    ```mlir
 
     #### Example:
 
-    ```
+    ```mlir
     %0 = spirv.Transpose %matrix: !spirv.matrix<2 x vector<3xf32>> ->
     !spirv.matrix<3 x vector<2xf32>>
 
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td

let description = [{
 
 
     <!-- End of AutoGen section -->
 
     ```
     access-chain-op ::= ssa-id `=` `spirv.InBoundsPtrAccessChain` ssa-use
                         `[` ssa-use (',' ssa-use)* `]`
                         `:` pointer-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     func @inbounds_ptr_access_chain(%arg0: !spirv.ptr<f32, CrossWorkgroup>, %arg1 : i64) -> () {
       %0 = spirv.InBoundsPtrAccessChain %arg0[%arg1] : !spirv.ptr<f32, CrossWorkgroup>, i64
       ...
     }
     ```
   }];
 
   let availability = [
let description = [{
     directly used, as its first Index selects the array element.
 
     <!-- End of AutoGen section -->
 
     ```
     [access-chain-op ::= ssa-id `=` `spirv.PtrAccessChain` ssa-use
                         `[` ssa-use (',' ssa-use)* `]`
                         `:` pointer-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     func @ptr_access_chain(%arg0: !spirv.ptr<f32, CrossWorkgroup>, %arg1 : i64) -> () {
       %0 = spirv.PtrAccessChain %arg0[%arg1] : !spirv.ptr<f32, CrossWorkgroup>, i64
       ...
     }
     ```
   }];
 
   let availability = [

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td

def SPIRV_KHRAssumeTrueOp : SPIRV_KhrVendorOp<"AssumeTrue", []> {
 
   let description = [{
 
 
     <!-- End of AutoGen section -->
 
     ```
     assumetruekhr-op ::= `spirv.KHR.AssumeTrue` ssa-use
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     spirv.KHR.AssumeTrue %arg
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
     Extension<[SPV_KHR_expect_assume]>,

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td

let description = [{
     ```
     scope ::= `"Workgroup"` | `"Subgroup"`
     integer-float-scalar-vector-type ::= integer-type | float-type |
                                `vector<` integer-literal `x` integer-type `>` |
                                `vector<` integer-literal `x` float-type `>`
     group-non-uniform-broadcast-op ::= ssa-id `=`
         `spirv.GroupNonUniformBroadcast` scope ssa_use, ssa_use
         `:` integer-float-scalar-vector-type `,` integer-type
-    ```mlir
+    ```
 
     #### Example:
 
-    ```
+    ```mlir
     %scalar_value = ... : f32
     %vector_value = ... : vector<4xf32>
     %id = ... : i32
     %0 = spirv.GroupNonUniformBroadcast "Subgroup" %scalar_value, %id : f32, i32
     %1 = spirv.GroupNonUniformBroadcast "Workgroup" %vector_value, %id :
       vector<4xf32>, i32
     ```
   }];

mlir/utils/spirv/gen_spirv_dialect.py

if arguments is None:
     if arguments:
       # Prepend and append whitespace for formatting
       arguments = '\n    {}\n  '.format(arguments)
 
   description = existing_info.get('description', None)
   if description is None:
     assembly = '\n    ```\n'\
                '    [TODO]\n'\
-               '    ```mlir\n\n'\
+               '    ```\n\n'\
                '    #### Example:\n\n'\
-               '    ```\n'\
+               '    ```mlir\n'\
                '    [TODO]\n' \
                '    ```'
     description = get_description(text, assembly)
 
   return fmt_str.format(
       opname=opname,
       opname_src=opname_src,
       opcode=instruction['opcode'],