[MIScheduler] Print top/down cycle in the SUnit dump.

[fpetrogalli]

Summary

Add an extra command line option to llc that allows checking at what cycle an instruction has been scheduled by the machine scheduler.

[fhahn]

llvm/test/CodeGen/AArch64/sched-print-cycle.mir

19

Should this not check for the expected cycles?

[fpetrogalli]

llvm/test/CodeGen/AArch64/sched-print-cycle.mir

19

I could, but what I am really interested in checking is the fact that we get 2 extra numbers with the option, not their values (for now). The scheduler tests will take care of checking the actual values. Is it OK if I live it as it is?

[fpetrogalli]

llvm/test/CodeGen/AArch64/sched-print-cycle.mir

19

To be more precise, I do not want to check for specific value because I do not want to bother updating the test in case they change. All I care is that the two extra numbers are there when -sched-print-cycles=true

[fhahn]

llvm/lib/CodeGen/ScheduleDAG.cpp

366 ↗

(On Diff #487446)

Hmm, is there a reason for including it in the name and not including them among the attributes (SUnit::dumpAttributes)? There it would also be possible to print a name associated with the values.

llvm/test/CodeGen/AArch64/sched-print-cycle.mir

19

If you fix the CPU (-mcpu=xxx) to an older one, it's unlikely that the latencies for ADD will change? It seems better to check that the correct values are printed IMO , rather than matching any value.

[fpetrogalli]

I have specified -mcpu in the test and the resulting values printed in the SUnit dump.

[fpetrogalli]

llvm/test/CodeGen/AArch64/sched-print-cycle.mir

19

You win :)

[fpetrogalli]

llvm/lib/CodeGen/ScheduleDAG.cpp

366 ↗

(On Diff #487446)

It is because we want the information to be printed by void ScheduleDAGMI::dumpSchedule() const, so that we can check the last bits of the debug info of the machine scheduler right after the string *** Final schedule for %bb.0 ***.

As far as I understand SUnit::dumpAttributes is printed before the scheduler does its job. We need to check the two extra values when the scheduler has finished.

[fpetrogalli]

Specify -mtriple in the invocation of llc in the test to prevent it fail on targets that do not support the cpu specified.

[fpetrogalli]

Based on offline feedback from @fhahn, I have:

1. moved the implementation out of dumpNodeName into ScheduleDAGInstrs::dumpNode(const SUnit &SU)
2. printed the meaning of the values.

[fpetrogalli]

Update the example in the test to have non-zero values printed for both TopReadyCycle and BottomReadyCycle.

[fhahn]

LGTM, thanks!

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

cl::init(1000), cl::desc("The limit to use while constructing the DAG "
                              "prior to scheduling, at which point a trade-off "
                              "is made to avoid excessive compile time."));
 
 static cl::opt<unsigned> ReductionSize(
     "dag-maps-reduction-size", cl::Hidden,
     cl::desc("A huge scheduling region will have maps reduced by this many "
              "nodes at a time. Defaults to HugeRegion / 2."));
 
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
+static cl::opt<bool> SchedPrintCycles(
+    "sched-print-cycles", cl::Hidden, cl::init(false),
+    cl::desc("Report top/bottom cycles when dumping SUnit instances"));
+#endif
+
 static unsigned getReductionSize() {
   // Always reduce a huge region with half of the elements, except
   // when user sets this number explicitly.
   if (ReductionSize.getNumOccurrences() == 0)
     return HugeRegion / 2;
   return ReductionSize;
 }
 
if (!MI.isBundled()) {
       } while (I != Bundle);
     }
   }
 }
 
 void ScheduleDAGInstrs::dumpNode(const SUnit &SU) const {
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
   dumpNodeName(SU);
+  if (SchedPrintCycles)
+    dbgs() << " [TopReadyCycle = " << SU.TopReadyCycle
+           << ", BottomReadyCycle = " << SU.BotReadyCycle << "]";
   dbgs() << ": ";
   SU.getInstr()->dump();
 #endif
 }
 
 void ScheduleDAGInstrs::dump() const {
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
   if (EntrySU.getInstr() != nullptr)

llvm/test/CodeGen/AArch64/sched-print-cycle.mir

+# RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=true \
+# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
+
+# RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=false \
+# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=NOCYCLES
+
+# REQUIRES: asserts
+---
+name: mul_mul
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0
+    $x1 = ADDXrr $x0, $x0
+    $x2 = ADDXrr $x1, $x1
+    $x3 = ADDXrr $x2, $x2
+    $x4 = ADDXrr $x2, $x2
+
+# CHECK-LABEL: *** Final schedule for %bb.0 ***
+# CHECK-NEXT: SU(0) [TopReadyCycle = 0, BottomReadyCycle = 0]:   $x1 = ADDXrr $x0, $x0
+# CHECK-NEXT: SU(1) [TopReadyCycle = 0, BottomReadyCycle = 1]:   $x2 = ADDXrr $x1, $x1
+# CHECK-NEXT: SU(2) [TopReadyCycle = 1, BottomReadyCycle = 0]:   $x3 = ADDXrr $x2, $x2
+# CHECK-NEXT: SU(3) [TopReadyCycle = 1, BottomReadyCycle = 0]:   $x4 = ADDXrr $x2, $x2
+
+# NOCYCLES-LABEL: *** Final schedule for %bb.0 ***
+# NOCYCLES-NEXT: SU(0):   $x1 = ADDXrr $x0, $x0
+# NOCYCLES-NEXT: SU(1):   $x2 = ADDXrr $x1, $x1
+# NOCYCLES-NEXT: SU(2):   $x3 = ADDXrr $x2, $x2
+# NOCYCLES-NEXT: SU(3):   $x4 = ADDXrr $x2, $x2