[AVR] Do not select unimplemented pseudo instructions

[benshi001]

Summary

The expansion of pseudo instructions LPMWRdZPi/ELPMBRdZPi/ELPMWRdZPi
have not be implemented, so we should not select them currently.

[benshi001]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

886

LPMWRdZPi is unimplemented.

890

ELPMBRdZPi is unimplemented.

895

ELPMWRdZPi is unimplemented.

[Miss_Grape]

This comment was removed by Miss_Grape.

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

bool AVRExpandPseudo::expand<AVR::ELPMBRdZ>(Block &MBB, BlockIt MBBI) {
   MILB.setMemRefs(MI.memoperands());
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::LPMWRdZPi>(Block &MBB, BlockIt MBBI) {
   llvm_unreachable("16-bit LPMPi is unimplemented");
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::ELPMBRdZPi>(Block &MBB, BlockIt MBBI) {
-  llvm_unreachable("byte ELPMPi is unimplemented");
+  llvm_unreachable("8-bit ELPMPi is unimplemented");
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::ELPMWRdZPi>(Block &MBB, BlockIt MBBI) {
   llvm_unreachable("16-bit ELPMPi is unimplemented");
 }
 
 template <typename Func>
 bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
   MachineInstr &MI = *MBBI;
   const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
 

llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp

unsigned AVRDAGToDAGISel::selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT,
 
   // Feature ELPM is needed for loading from extended program memory.
   assert((Bank == 0 || Subtarget->hasELPM()) &&
          "cannot load from extended program memory on this mcu");
 
   unsigned Opcode = 0;
   int Offs = cast<ConstantSDNode>(LD->getOffset())->getSExtValue();
 
-  switch (VT.SimpleTy) {
-  case MVT::i8:
-    if (Offs == 1)
-      Opcode = Bank > 0 ? AVR::ELPMBRdZPi : AVR::LPMRdZPi;
-    break;
-  case MVT::i16:
-    if (Offs == 2)
-      Opcode = Bank > 0 ? AVR::ELPMWRdZPi : AVR::LPMWRdZPi;
-    break;
-  default:
-    break;
-  }
+  if (VT.SimpleTy == MVT::i8 && Offs == 1 && Bank == 0)
+    Opcode = AVR::LPMRdZPi;
+
+  // TODO: Implements the expansion of the following pseudo instructions.
+  // LPMWRdZPi:  type == MVT::i16, offset == 2, Bank == 0.
+  // ELPMBRdZPi: type == MVT::i8,  offset == 1, Bank >  0.
+  // ELPMWRdZPi: type == MVT::i16, offset == 2, Bank >  0.
 
   return Opcode;
 }
 
 bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(
     const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
   assert((ConstraintCode == InlineAsm::Constraint_m ||
           ConstraintCode == InlineAsm::Constraint_Q) &&