[AVR] Support .reloc directive

[benshi001]

llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp

425

Two suggestions:

1. Put this after the

const static MCFixupKindInfo Infos[AVR::NumTargetFixupKinds]

and before

if (Kind < FirstTargetFixupKind)
  return MCAsmBackend::getFixupKindInfo(Kind);

this code style is common among ARM, AArch64, and RISCV.

2. Add a comment line before, like

// Fixup kinds from .reloc directive are like R_AVR_NONE. They do not require
// any extra processing.

I also see the comment is common in other targets.

[benshi001]

llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp

256

In other targets, I see the piece of code is put in ::applyFixup and right before calling ::adjustFixupValue.

[MaskRay]

comments

[benshi001]

LGTM. Thanks!

llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h

public:
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override;
 
   void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                   const MCValue &Target, MutableArrayRef<char> Data,
                   uint64_t Value, bool IsResolved,
                   const MCSubtargetInfo *STI) const override;
 
+  std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
 
   unsigned getNumFixupKinds() const override {
     return AVR::NumTargetFixupKinds;
   }
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,

llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp

 } // namespace adjust
 
 namespace llvm {
 
 // Prepare value for the target space for it
 void AVRAsmBackend::adjustFixupValue(const MCFixup &Fixup,
                                      const MCValue &Target, uint64_t &Value,
                                      MCContext *Ctx) const {
+  if (Fixup.getKind() >= FirstLiteralRelocationKind)
+    return;
   // The size of the fixup in bits.
   uint64_t Size = AVRAsmBackend::getFixupKindInfo(Fixup.getKind()).TargetSize;
 
   unsigned Kind = Fixup.getKind();
   switch (Kind) {
   default:
     llvm_unreachable("unhandled fixup");
   case AVR::fixup_7_pcrel:
void AVRAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
   // For each byte of the fragment that the fixup touches, mask in the
   // bits from the fixup value.
   for (unsigned i = 0; i < NumBytes; ++i) {
     uint8_t mask = (((Value >> (i * 8)) & 0xff));
     Data[Offset + i] |= mask;
   }
 }
 
+std::optional<MCFixupKind> AVRAsmBackend::getFixupKind(StringRef Name) const {
+  unsigned Type;
+  Type = llvm::StringSwitch<unsigned>(Name)
+#define ELF_RELOC(X, Y) .Case(#X, Y)
+#include "llvm/BinaryFormat/ELFRelocs/AVR.def"
+#undef ELF_RELOC
+             .Case("BFD_RELOC_NONE", ELF::R_AVR_NONE)
+             .Case("BFD_RELOC_16", ELF::R_AVR_16)
+             .Case("BFD_RELOC_32", ELF::R_AVR_32)
+             .Default(-1u);
+  if (Type != -1u)
+    return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
+  return std::nullopt;
+}
+
 MCFixupKindInfo const &AVRAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
+  if (Kind >= FirstLiteralRelocationKind)
+    return MCAsmBackend::getFixupKindInfo(FK_NONE);
   // NOTE: Many AVR fixups work on sets of non-contignous bits. We work around
   // this by saying that the fixup is the size of the entire instruction.
   const static MCFixupKindInfo Infos[AVR::NumTargetFixupKinds] = {
       // This table *must* be in same the order of fixup_* kinds in
       // AVRFixupKinds.h.
       //
       // name                    offset  bits  flags
       {"fixup_32", 0, 32, 0},
bool AVRAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
   return true;
 }
 
 bool AVRAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
                                           const MCFixup &Fixup,
                                           const MCValue &Target) {
   switch ((unsigned)Fixup.getKind()) {
   default:
-    return false;
+    return Fixup.getKind() >= FirstLiteralRelocationKind;
   // Fixups which should always be recorded as relocations.
   case AVR::fixup_7_pcrel:
   case AVR::fixup_13_pcrel:
   case AVR::fixup_call:
     return true;
   }
 }
 
 MCAsmBackend *createAVRAsmBackend(const Target &T, const MCSubtargetInfo &STI,
                                   const MCRegisterInfo &MRI,
                                   const llvm::MCTargetOptions &TO) {
   return new AVRAsmBackend(STI.getTargetTriple().getOS());
 }
 
 } // end of namespace llvm

llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp

 };
 
 AVRELFObjectWriter::AVRELFObjectWriter(uint8_t OSABI)
     : MCELFObjectTargetWriter(false, OSABI, ELF::EM_AVR, true) {}
 
 unsigned AVRELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
                                           const MCFixup &Fixup,
                                           bool IsPCRel) const {
+  const unsigned Kind = Fixup.getTargetKind();
+  if (Kind >= FirstLiteralRelocationKind)
+    return Kind - FirstLiteralRelocationKind;
   MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();
   switch ((unsigned)Fixup.getKind()) {
   case FK_Data_1:
     switch (Modifier) {
     default:
       llvm_unreachable("Unsupported Modifier");
     case MCSymbolRefExpr::VK_None:
       return ELF::R_AVR_8;

llvm/test/MC/AVR/reloc-directive-err.s

+# RUN: llvm-mc -triple=avr %s 2>&1 | FileCheck --check-prefix=PRINT %s
+# RUN: not llvm-mc -filetype=obj -triple=avr %s -o /dev/null 2>&1 | FileCheck %s
+
+# PRINT: .reloc 0, R_INVALID, 0
+# CHECK: {{.*}}.s:[[#@LINE+1]]:11: error: unknown relocation name
+.reloc 0, R_INVALID, 0
+
+# PRINT: .reloc 0, BFD_RELOC_64, 0
+# CHECK: {{.*}}.s:[[#@LINE+1]]:11: error: unknown relocation name
+.reloc 0, BFD_RELOC_64, 0

llvm/test/MC/AVR/reloc-directive.s

+# RUN: llvm-mc -triple=avr %s | FileCheck --check-prefix=PRINT %s
+# RUN: llvm-mc -filetype=obj -triple=avr %s | llvm-readobj -r - | FileCheck %s
+
+# PRINT:      .reloc 4, R_AVR_NONE, .data
+# PRINT-NEXT: .reloc 2, R_AVR_NONE, foo+4
+# PRINT-NEXT: .reloc 0, R_AVR_NONE, 8
+# PRINT:      .reloc 0, R_AVR_32, .data+2
+# PRINT-NEXT: .reloc 0, R_AVR_16, foo+3
+# PRINT:      .reloc 0, BFD_RELOC_NONE, 9
+# PRINT-NEXT: .reloc 0, BFD_RELOC_16, 9
+# PRINT-NEXT: .reloc 0, BFD_RELOC_32, 9
+
+# CHECK:      Section ({{.*}}) .rela.text {
+# CHECK-NEXT:   0x4 R_AVR_NONE .data 0x0
+# CHECK-NEXT:   0x2 R_AVR_NONE foo 0x4
+# CHECK-NEXT:   0x0 R_AVR_NONE - 0x8
+# CHECK-NEXT:   0x0 R_AVR_32 .data 0x2
+# CHECK-NEXT:   0x0 R_AVR_16 foo 0x3
+# CHECK-NEXT:   0x0 R_AVR_NONE - 0x9
+# CHECK-NEXT:   0x0 R_AVR_16 - 0x9
+# CHECK-NEXT:   0x0 R_AVR_32 - 0x9
+# CHECK-NEXT: }
+
+.text
+  ret
+  nop
+  nop
+  .reloc 4, R_AVR_NONE, .data
+  .reloc 2, R_AVR_NONE, foo+4
+  .reloc 0, R_AVR_NONE, 8
+
+  .reloc 0, R_AVR_32, .data+2
+  .reloc 0, R_AVR_16, foo+3
+
+  .reloc 0, BFD_RELOC_NONE, 9
+  .reloc 0, BFD_RELOC_16, 9
+  .reloc 0, BFD_RELOC_32, 9
+
+.data
+.globl foo
+foo:
+  .word 0
+  .word 0